diff --git a/ci/README.md b/ci/README.md
index edd129cadf36d32a62065683ba34da5f479641da..c6fe244562c59a6ff1ab3f89ca7c48e31f2456c7 100644
--- a/ci/README.md
+++ b/ci/README.md
@@ -10,3 +10,33 @@ It runs [make](quad/Makefile) under the quad directory to build the project.
## Test Stage
The test stage is defined by the [`ci-test.sh`](ci/ci-test.sh) file.
It runs [make test](quad/Makefile#L36) under the quad directory to run the tests.
+
+# CI Server
+The CI server for this project is at `microcart.ece.iastate.edu`
+login information should be handed off outside this repo for security reasons.
+The gitlab runner uses docker to launch a container, in which the scripts are run.
+The VM is running Red Hat Enterprise Linux, which as of Oct. 6, 2018 was licensed.
+**Note:** RHEL uses `yum` for package management, but the docker image uses `apt-get`.
+
+## Accessing System Folders
+If you need to access any folders on the VM from within the docker,
+the information [here](https://docs.gitlab.com/runner/configuration/advanced-configuration.html#volumes-in-the-runners-docker-section) should help
+Specifically this part:
+
+### Example 2: mount a host directory as a data volume
+In addition to creating a volume using you can also mount a directory from your
+Docker daemon's host into a container. It's useful when you want to store builds
+outside the container.
+
+ [runners.docker]
+ ... whatever config is already there ...
+ volumes = ["/path/to/persistent/data/in/container", /path/to/bind/from/host:/path/to/bind/in/container:rw"]
+
+## Accessing a remote share on the VM
+To get to the Xilinx tools for hardware simulation, we need access to
+`logic.ece.iastate.edu/export/Xilinx` as a mounted folder. This can be done with NFS.
+NFS is installed and the folder mounted. If it becomes unmounted, then run
+
+ $ sudo mount logic.ece.iastate.edu:/export/Xilinx /remote/Xilinx
+
+on the VM. This may not be doable from within the CI run as it is in a container (Docker image) that may behave differently or have different permissions.
diff --git a/controls/DataAnalysisTool/Tool/GUI.asv b/controls/DataAnalysisTool/Tool/GUI.asv
new file mode 100644
index 0000000000000000000000000000000000000000..831028acb356e56ec500e969d0c4dc1a83f8b775
--- /dev/null
+++ b/controls/DataAnalysisTool/Tool/GUI.asv
@@ -0,0 +1,784 @@
+function varargout = GUI(varargin)
+% GUI MATLAB code for GUI.fig
+% GUI, by itself, creates a new GUI or raises the existing
+% singleton*.
+%
+% H = GUI returns the handle to a new GUI or the handle to
+% the existing singleton*.
+%
+% GUI('CALLBACK',hObject,eventData,handles,...) calls the local
+% function named CALLBACK in GUI.M with the given input arguments.
+%
+% GUI('Property','Value',...) creates a new GUI or raises the
+% existing singleton*. Starting from the left, property value pairs are
+% applied to the GUI before GUI_OpeningFcn gets called. An
+% unrecognized property name or invalid value makes property application
+% stop. All inputs are passed to GUI_OpeningFcn via varargin.
+%
+% *See GUI Options on GUIDE's Tools menu. Choose "GUI allows only one
+% instance to run (singleton)".
+%
+% See also: GUIDE, GUIDATA, GUIHANDLES
+
+% Edit the above text to modify the response to help GUI
+
+% Last Modified by GUIDE v2.5 24-Mar-2015 21:23:27
+
+% Begin initialization code - DO NOT EDIT
+gui_Singleton = 1;
+gui_State = struct('gui_Name', mfilename, ...
+ 'gui_Singleton', gui_Singleton, ...
+ 'gui_OpeningFcn', @GUI_OpeningFcn, ...
+ 'gui_OutputFcn', @GUI_OutputFcn, ...
+ 'gui_LayoutFcn', [] , ...
+ 'gui_Callback', []);
+if nargin && ischar(varargin{1})
+ gui_State.gui_Callback = str2func(varargin{1});
+end
+
+if nargout
+ [varargout{1:nargout}] = gui_mainfcn(gui_State, varargin{:});
+else
+ gui_mainfcn(gui_State, varargin{:});
+end
+% End initialization code - DO NOT EDIT
+
+
+% --- Executes just before GUI is made visible.
+function GUI_OpeningFcn(hObject, eventdata, handles, varargin)
+% This function has no output args, see OutputFcn.
+% hObject handle to figure
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+% varargin command line arguments to GUI (see VARARGIN)
+
+% Choose default command line output for GUI
+handles.output = hObject;
+
+handles.filepath = hObject;
+handles.filepath = mfilename('fullpath');
+handles.filepath = strrep(handles.filepath, 'GUI', '');
+addpath(handles.filepath);
+cd(handles.filepath);
+if (~exist(handles.filepath,'file'))
+ error(strcat(handles.filepath, ' does not exist'))
+end
+
+if(~isfield(handles, 'axes'))
+ for i = 1:12
+ eval(['handles.axes{' num2str(i) '} = handles.axes' num2str(i) ';']);
+ eval(['handles = rmfield(handles,''axes' num2str(i) ''');']);
+ eval(['handles.togglebuttons{' num2str(i) '} = handles.togglebutton' num2str(i) ';']);
+ eval(['handles = rmfield(handles,''togglebutton' num2str(i) ''');']);
+ eval(['handles.radiobutton{' num2str(i) '} = handles.radiobutton' num2str(i) ';']);
+ eval(['handles = rmfield(handles,''radiobutton' num2str(i) ''');']);
+ end
+ for i = 13:16
+ eval(['handles.radiobutton{' num2str(i) '} = handles.radiobutton' num2str(i) ';']);
+ eval(['handles = rmfield(handles,''radiobutton' num2str(i) ''');']);
+ end
+end
+handles.main = hObject;
+handles.main = struct();
+
+if(evalin('base','exist(''main'')'))
+ handles.main = importData(hObject, eventdata, handles);
+ handles = loadOptions(hObject, eventdata, handles);
+ previewPlot(hObject, eventdata, handles);
+ if(~isfield(handles.main.params.file,'pathName'))
+ handles.main.params.file.name = '';
+ handles.main.params.file.path = handles.filepath;
+ handles.main.params.file.pathName = handles.filepath;
+ end
+else
+ handles.main.params.file.name = '';
+ handles.main.params.file.path = handles.filepath;
+ handles.main.params.file.pathName = handles.filepath;
+end
+
+handles.pause_play_timer = timer('BusyMode', 'queue', 'ExecutionMode',...
+ 'fixedRate', 'Period', 5.0);
+set(handles.pause_play_timer, 'TimerFcn', @(hObject, event) pushbutton2_Callback(hObject, eventdata, guidata(hObject)));
+cd(handles.main.params.file.path);
+load_listbox(hObject, eventdata, handles)
+guidata(hObject, handles);
+% Update handles structure
+%findobj('tag', 'figure\*');
+
+
+% UIWAIT makes GUI wait for user response (see UIRESUME)
+% uiwait(handles.figure1);
+
+
+% --- Outputs from this function are returned to the command line.
+function varargout = GUI_OutputFcn(hObject, eventdata, handles)
+% varargout cell array for returning output args (see VARARGOUT);
+% hObject handle to figure
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+
+% Get default command line output from handles structure
+varargout{1} = handles.output;
+
+% --- Executes when user attempts to close figure1.
+function figure1_CloseRequestFcn(hObject, eventdata, handles)
+% hObject handle to figure1 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+
+cd(handles.filepath);
+% Hint: delete(hObject) closes the figure
+delete(hObject);
+
+
+function uipanel1_SelectionChangeFcn(hObject, eventdata, handles)
+if(isfield(handles.main,'expData'))
+previewPlot(hObject, eventdata, handles)
+end
+
+
+% --- Executes when selected object is changed in uipanel3.
+function uipanel3_SelectionChangeFcn(hObject, eventdata, handles)
+% hObject handle to the selected object in uipanel3
+% eventdata structure with the following fields (see UIBUTTONGROUP)
+% EventName: string 'SelectionChanged' (read only)
+% OldValue: handle of the previously selected object or empty if none was selected
+% NewValue: handle of the currently selected object
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+
+handles.main.params.plotting.separatePlot = 0; % to generate separate plots
+handles.main.params.plotting.multiPlot = 0; % to super impose multiple quantities on the same plot
+handles.main.params.plotting.subPlot = 0;
+
+switch get(get(handles.uipanel3,'SelectedObject'),'Tag')
+case 'radiobutton14', handles.main.params.plotting.separatePlot = 1;
+case 'radiobutton15', handles.main.params.plotting.subPlot = 1;
+case 'radiobutton16', handles.main.params.plotting.multiPlot = 1;
+ otherwise
+ error('You must select a radio button to indicate what field''s options you are changing.')
+end
+exportData(hObject, eventdata, handles);
+previewPlot(hObject, eventdata, handles);
+guidata(hObject,handles);
+
+function pause_play_Timer(hObject, eventdata, handles)
+% hObject handle to pushbutton_pause
+% eventdata reserved - to be defeined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);;
+
+if (handles.pause
+
+
+% --- Executes on button press in pushbutton2.
+function pushbutton2_Callback(hObject, eventdata, handles)
+% hObject handle to pushbutton2 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+
+handles = updateOptions(hObject, eventdata, handles);;
+
+if(handles.main.params.plotting.clearFigs)
+ set(handles.figure1, 'HandleVisibility', 'off');
+ close all;
+ set(handles.figure1, 'HandleVisibility', 'on');
+end
+handles.main.params.plotting.toPlot = handles.main.params.plotting.toPlot(~cellfun('isempty',handles.main.params.plotting.toPlot));
+if(~isempty(handles.main.params.plotting.toPlot))
+ if(handles.main.params.plotting.subPlot) %% plot on one figure using multiple subplots
+ counter = 1;
+ x = ceil(sqrt(length(handles.main.params.plotting.toPlot)));
+ y = x - floor((x ^ 2 - length(handles.main.params.plotting.toPlot))/x);
+ figure_handle = figure;
+ else if(handles.main.params.plotting.multiPlot)
+ figure_handle = figure;
+ end
+ end
+
+ tempData{1} = handles.main.expData.data{1};
+ tempParams{1} = handles.main.expData.params{1};
+ tempUnit{1} = handles.main.expData.unit{1};
+ tempName{1} = handles.main.expData.datafields{1};
+ if(isfield(handles.main.params.plotting,'toPlot'))
+ for m = 1:length(handles.main.params.plotting.toPlot)
+ for n = 1:length(handles.main.expData.datafields)
+ if(strcmp(handles.main.expData.datafields{n},handles.main.params.plotting.toPlot{m}))
+ tempData{m+1} = handles.main.expData.data{n};
+ tempParams{m+1} = handles.main.expData.params{n};
+ tempUnit{m+1} = handles.main.expData.unit{n};
+ tempName{m+1} = handles.main.expData.datafields{n};
+ end
+ end
+ end
+ end
+
+
+ for i=1:length(handles.main.params.plotting.toPlot)
+ if(strcmp(tempName{i},'Marker'))
+
+ else
+ if(handles.main.params.plotting.subPlot)
+ subplot(x,y,counter);
+ counter = counter + 1;
+
+ else if(handles.main.params.plotting.separatePlot)
+ figure_handle = figure;
+ whitebg(tempParams{1}.backgnd);
+ else
+ hold on;
+ end
+ whitebg('white');
+ end
+
+
+ if(strcmp(get(get(handles.uipanel1,'SelectedObject'),'Tag'), 'radiobutton13'))
+ whitebg(tempParams{1}.backgnd);
+ plot(tempData{1},tempData{i+1},'LineStyle',tempParams{1}.style,'Marker',tempParams{1}.marker,'Color',tempParams{1}.color);
+ set(gca,'Color',tempParams{1}.backgnd);
+ set(gcf,'Color',tempParams{1}.backgnd);
+ grid ON;
+ title(tempName{i+1})
+ xlabel(strcat(tempName{1},'(', tempUnit{1},')'));
+ ylabel(tempUnit{i+1});
+ else
+ plot(tempData{1},tempData{i+1},'LineStyle',tempParams{i+1}.style,'Marker',tempParams{i+1}.marker,'Color',tempParams{i+1}.color);
+ if(handles.main.params.plotting.subPlot||handles.main.params.plotting.separatePlot)
+ set(gca,'Color',tempParams{i+1}.backgnd);
+ end
+ grid ON;
+ xlabel(strcat(tempName{1},'(', tempUnit{1},')'));
+ if(~handles.main.params.plotting.multiPlot)
+ ylabel(tempUnit{i+1});
+ title(tempName{i+1})
+ else
+ hold off;
+ end
+
+ end
+
+ if(isfield(handles.main.expData,'Marker'))
+ marks = find(handles.main.expData.Marker.data);
+ l = length(marks);
+ for n = 1:l
+ x = handles.main.expData.data{1}(marks(n));
+ line([x x], get(gca,'YLim'),'Color',[rand(1) rand(1) rand(1)]);
+ y = get(gca,'YLim');
+ y = y(1)+(1/l)*n*(y(2)-y(1));
+ text('String',strcat('M',num2str(n),'>'),'Position',[x,y],'HorizontalAlignment','right')
+ end
+ end
+ end
+ end
+ all_ha = findobj( figure_handle, 'type', 'axes', 'tag', '' );
+ linkaxes( all_ha, 'x' );
+else
+ error('You must select fields to plot first.')
+end
+guidata(hObject,handles);
+
+% --- Executes on button press in checkbox1.
+function checkbox1_Callback(hObject, eventdata, handles)
+% hObject handle to checkbox1 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+
+% Hint: get(hObject,'Value') returns toggle state of checkbox1
+handles = guidata(hObject);
+
+button_state = get(hObject,'Value');
+if button_state == get(hObject,'Max')
+ handles.main.params.plotting.clearFigs = 1;
+elseif button_state == get(hObject,'Min')
+ handles.main.params.plotting.clearFigs = 0;
+end
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+
+
+
+% --- Executes on button press in pushbutton3.
+function pushbutton3_Callback(hObject, eventdata, handles)
+% hObject handle to pushbutton3 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+switch get(get(handles.uipanel1,'SelectedObject'),'Tag')
+case 'radiobutton1', i = 2;
+case 'radiobutton2', i = 3;
+case 'radiobutton3', i = 4;
+case 'radiobutton4', i = 5;
+case 'radiobutton5', i = 6;
+case 'radiobutton6', i = 7;
+case 'radiobutton7', i = 8;
+case 'radiobutton8', i = 9;
+case 'radiobutton9', i = 10;
+case 'radiobutton10', i = 11;
+case 'radiobutton11', i = 12;
+case 'radiobutton12', i = 13;
+case 'radiobutton13', i = 1;
+ otherwise
+ error('You must select a radio button to indicate what field''s options you are changing before pressing this button.')
+end
+
+color = get(handles.listbox1,'String');
+color = color{get(handles.listbox1,'Value')};
+style = get(handles.listbox2,'String');
+style = style{get(handles.listbox2,'Value')};
+marker = get(handles.listbox3,'String');
+marker = marker{get(handles.listbox3,'Value')};
+bg = get(handles.listbox4,'String');
+bg = bg{get(handles.listbox4,'Value')};
+handles.main.expData.params{i}.color = color;
+handles.main.expData.params{i}.style = style;
+handles.main.expData.params{i}.marker = marker;
+handles.main.expData.params{i}.backgnd = bg;
+exportData(hObject, eventdata, handles);
+previewPlot(hObject, eventdata, handles);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+
+% --- Executes on button press in pushbutton4.
+function pushbutton4_Callback(hObject, eventdata, handles)
+% hObject handle to pushbutton4 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+if isdir(handles.main.params.file.pathName)
+ cd (handles.main.params.file.pathName);
+ handles.main.params.file.path = cd;
+ handles.main.params.file.pathName = cd;
+ addpath(cd);
+ load_listbox(hObject, eventdata, handles);
+end
+
+% --- Executes on selection change in listbox5.
+function listbox5_Callback(hObject, eventdata, handles)
+% hObject handle to listbox5 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+
+% Hints: contents = cellstr(get(hObject,'String')) returns listbox5 contents as cell array
+% contents{get(hObject,'Value')} returns selected item from listbox5
+handles = guidata(hObject);
+get(handles.figure1,'SelectionType');
+if strcmp(get(handles.figure1,'SelectionType'),'open')
+ index_selected = get(handles.listbox5,'Value');
+ file_list = get(handles.listbox5,'String');
+ [path, handles.main.params.file.name, ext] = fileparts(file_list{index_selected});
+ handles.main.params.file.name = strcat(handles.main.params.file.name,ext);
+ handles.main.params.file.pathName = strcat(handles.main.params.file.path,'/', handles.main.params.file.name);
+ if isdir(handles.main.params.file.pathName)
+ cd (handles.main.params.file.pathName);
+ handles.main.params.file.path = cd;
+ handles.main.params.file.pathName = cd;
+ addpath(cd);
+ load_listbox(hObject, eventdata, handles);
+ else
+ cd(handles.main.params.file.path);
+ switch ext
+ case '.txt'
+
+ if(isfield(handles.main.params,'plotting'))
+ if(isfield(handles.main,'expData'))
+ handles.main.expData = parse_log(handles.main.params.file.pathName,handles.main.params,handles.main.expData);
+ else
+ handles.main.expData = parse_log(handles.main.params.file.pathName,handles.main.params);
+ end
+ else
+ handles.main.params = set_params(hObject, eventdata, handles);
+ handles.main.expData = parse_log(handles.main.params.file.pathName,handles.main.params);
+ end
+ handles.main = generateGuiData(hObject, eventdata, handles);
+ exportData(hObject, eventdata, handles);
+ handles.main = importData(hObject, eventdata, handles);
+ handles = updateOptions(hObject, eventdata, handles);
+ handles = loadOptions(hObject, eventdata, handles);
+ set(handles.text5,'string',strcat('Current Log:', handles.main.params.file.pathName));
+ previewPlot(hObject, eventdata, handles);
+
+ case '.mat'
+ handles.main = importData(hObject, eventdata, handles);
+ handles = updateOptions(hObject, eventdata, handles);
+ handles = loadOptions(hObject, eventdata, handles);
+ set(handles.text5,'string',strcat('Current Log:', handles.main.params.file.pathName));
+ previewPlot(hObject, eventdata, handles);
+
+ otherwise
+ try
+ open(handles.main.params.file.pathName,handles.main.params);
+ catch ex
+ errordlg(ex.getReport('basic'),'File Type Error','modal');
+ end
+
+ end
+ end
+end
+
+guidata(hObject,handles);
+
+
+
+
+%% Extra Functions
+% Used by above
+
+
+function previewPlot(hObject, eventdata, handles)
+%handles.datafields = fieldnames(handles.main.expData);
+if(~isnan(handles.main.expData.Time.data))
+ if(strcmp(get(get(handles.uipanel1,'SelectedObject'),'Tag'), 'radiobutton13'))
+ whitebg(handles.main.expData.params{1}.backgnd);
+ for i = 1:length(handles.main.expData.data)-1
+ if(~isnan(handles.main.expData.data{i}(1,1)) && i<=12)
+ plot(handles.axes{i},handles.main.expData.data{1},handles.main.expData.data{i+1},'LineStyle',handles.main.expData.params{1}.style,'Marker',handles.main.expData.params{1}.marker,'Color',handles.main.expData.params{1}.color);
+ set(handles.axes{i},'Color',handles.main.expData.params{1}.backgnd);
+ set(handles.togglebuttons{i},'string',handles.main.expData.datafields{i+1},'enable','on');
+ grid(handles.axes{i}, 'on');
+ xlabel(handles.axes{i},strcat(handles.main.expData.datafields{1},'(', handles.main.expData.unit{1},')'));
+ ylabel(handles.axes{i},handles.main.expData.unit{i+1});
+ if(isfield(handles.main.expData,'Marker'))
+ marks = find(handles.main.expData.Marker.data);
+ for j = 1:length(marks)
+ line([handles.main.expData.data{1}(marks(j)) handles.main.expData.data{1}(marks(j))], get(handles.axes{i},'YLim'),'Color','red','Parent',handles.axes{i})
+ end
+
+ end
+ end
+ end
+ else
+ whitebg('white');
+ for i = 1:length(handles.main.expData.data)-1
+ if(~isnan(handles.main.expData.data{i}(1,1)) && (i<=12))
+ plot(handles.axes{i},handles.main.expData.data{1},handles.main.expData.data{i+1},'LineStyle',handles.main.expData.params{i+1}.style,'Marker',handles.main.expData.params{i+1}.marker,'Color',handles.main.expData.params{i+1}.color);
+ if(~handles.main.params.plotting.multiPlot)
+ set(handles.axes{i},'Color',handles.main.expData.params{i+1}.backgnd);
+ end
+ set(handles.togglebuttons{i},'string',handles.main.expData.datafields{i+1},'enable','on');
+ grid(handles.axes{i}, 'on');
+ xlabel(handles.axes{i},strcat(handles.main.expData.datafields{1},'(', handles.main.expData.unit{1},')'));
+ ylabel(handles.axes{i},handles.main.expData.unit{i+1});
+ if(isfield(handles.main.expData,'Marker'))
+ marks = find(handles.main.expData.Marker.data);
+ for j = 1:length(marks)
+ line([handles.main.expData.data{1}(marks(j)) handles.main.expData.data{1}(marks(j))], get(handles.axes{i},'YLim'),'Color','red','Parent',handles.axes{i})
+ end
+
+ end
+ end
+ end
+ end
+ for i = length(handles.main.expData.data):12
+ plot(handles.axes{i},0,0);
+ set(handles.axes{i},'Color','white');
+ grid(handles.axes{i}, 'off');
+ set(handles.togglebuttons{i},'string','no data','enable','off');
+ set(handles.togglebuttons{i},'value',0);
+ handles.main.params.plotting.toPlot{i} = [];
+ end
+ setbgcolor(hObject, eventdata, handles);
+end
+guidata(hObject, handles);
+
+
+
+function main = importData(hObject, eventdata, handles)
+
+main = evalin('base' , 'main');
+handles.main = main;
+handles.main = generateGuiData(hObject, eventdata, handles);
+
+if(~isfield(handles.main.params,'plotting'))
+ handles.main.params = set_params(hObject, eventdata, handles);
+end
+if(~isfield(handles.main.params.plotting,'separatePlot'))
+ handles.main.params.plotting.separatePlot = 1; % to generate separate plots
+end
+if(~isfield(handles.main.params.plotting,'multiPlot'))
+ handles.main.params.plotting.multiPlot = 0; % to super impose multiple quantities on the same plot
+end
+if(~isfield(handles.main.params.plotting,'subPlot'))
+ handles.main.params.plotting.subPlot = 0; % to generate sub plots for multiple quantities
+end
+if(~isfield(handles.main.params.plotting,'clearFigs'))
+ handles.main.params.plotting.clearFigs = 1;
+end
+main = handles.main;
+guidata(hObject, handles);
+
+
+
+function main = generateGuiData(hObject, eventdata, handles)
+n = length(fieldnames(handles.main.expData));
+handles.main.expData.datafields = fieldnames(handles.main.expData);
+for i = 1:n
+eval(['handles.main.expData.data{i} = handles.main.expData.', handles.main.expData.datafields{i}, '.data;']); %%
+eval(['handles.main.expData.unit{i} = handles.main.expData.', handles.main.expData.datafields{i}, '.unit;']); %%
+eval(['handles.main.expData.params{i} = handles.main.expData.', handles.main.expData.datafields{i}, '.params;']);
+end
+main = handles.main;
+guidata(hObject, handles);
+
+
+
+function exportData(hObject, eventdata, handles)
+
+handles.main.expData.datafields = fieldnames(handles.main.expData);
+for i = 1:length(handles.main.expData.data)
+eval(['handles.main.expData.', handles.main.expData.datafields{i}, '.data = handles.main.expData.data{i};']); %%
+eval(['handles.main.expData.', handles.main.expData.datafields{i}, '.unit = handles.main.expData.unit{i};']); %%
+eval(['handles.main.expData.', handles.main.expData.datafields{i}, '.params = handles.main.expData.params{i};']);
+end
+handles.main.expData = rmfield(handles.main.expData, 'datafields');
+handles.main.expData = rmfield(handles.main.expData, 'data');
+handles.main.expData = rmfield(handles.main.expData, 'unit');
+handles.main.expData = rmfield(handles.main.expData, 'params');
+
+assignin('base', 'main', handles.main);
+
+
+
+function setbgcolor(hObject, eventdata, handles)
+
+bgcolor = get(handles.figure1,'color');
+set(handles.uipanel1,'BackgroundColor', bgcolor);
+set(handles.uipanel2,'BackgroundColor', bgcolor);
+set(handles.uipanel3,'BackgroundColor', bgcolor);
+for i = 1:16
+ set(handles.radiobutton{i},'BackgroundColor', bgcolor);
+end
+for i = 1:6
+ eval(['set(handles.text', num2str(i) , ',''BackgroundColor'', bgcolor);'])
+end
+set(handles.checkbox1,'BackgroundColor', bgcolor);
+guidata(hObject, handles);
+
+
+
+function load_listbox(hObject, eventdata, handles)
+dir_struct = dir(cd);
+[sorted_names,sorted_index] = sortrows({dir_struct.name}');
+handles.file_names = sorted_names;
+handles.is_dir = [dir_struct.isdir];
+handles.sorted_index = sorted_index;
+guidata(handles.figure1,handles)
+set(handles.listbox5,'String',handles.file_names,'Value',1)
+set(handles.text5,'string',strcat('Current Log:', handles.main.params.file.pathName))
+cd(handles.filepath);
+guidata(hObject, handles);
+
+
+
+function params = set_params(hObject, eventdata, handles)
+handles.main.params.plotting.plot = 1; % switch to choose plotting
+handles.main.params.plotting.separatePlot = 1; % to generate separate plots
+handles.main.params.plotting.multiPlot = 0; % to super impose multiple quantities on the same plot
+handles.main.params.plotting.subPlot = 0; % to generate sub plots for multiple quantities
+handles.main.params.plotting.clearFigs = 1;
+handles.main.params.plotting.separateData = {}; % column numbers to plot on separate figures
+handles.main.params.plotting.toPlot = {};
+ % if empty & plot = 1, all the columns will be plotted
+handles.main.params.plotting.multiData = {}; % if empty but switch is on, use separateData values
+handles.main.params.plotting.subData = {}; % if empty but switch is on, use multiData values
+handles.main.params.plotting.color = 'black'; % one character for color of the plotting line
+handles.main.params.plotting.marker = 'none'; % one character for the maker of the plotting line
+handles.main.params.plotting.style = '-'; % one character for the style of the plotting line
+handles.main.params.plotting.backgnd = 'white'; % rgb array for background color of the plot
+params = handles.main.params;
+
+
+
+function handles = loadOptions(hObject, eventdata, handles)
+handles = guidata(hObject);
+set(handles.radiobutton{14},'Value',0)
+set(handles.radiobutton{15},'Value',0)
+set(handles.radiobutton{16},'Value',0)
+if(handles.main.params.plotting.separatePlot)
+ set(handles.radiobutton{14},'Value',1)
+else if(handles.main.params.plotting.subPlot)
+ set(handles.radiobutton{15},'Value',1)
+ else if(handles.main.params.plotting.multiPlot)
+ set(handles.radiobutton{16},'Value',1)
+ else
+ set(handles.radiobutton{14},'Value',1);
+ handles.main.params.plotting.separatePlot = 1;
+ end
+ end
+end
+if(handles.main.params.plotting.clearFigs)
+ set(handles.checkbox1,'Value',1)
+else
+ set(handles.checkbox1,'Value',0)
+end
+
+for n = 2:length(handles.main.expData.datafields)
+ if(n<=13)
+ set(handles.togglebuttons{n-1}, 'Value', 0);
+ end
+end
+if(isfield(handles.main.params.plotting,'toPlot'))
+ for m = 1:length(handles.main.params.plotting.toPlot)
+ for n = 2:length(handles.main.expData.datafields)
+ if(strcmp(handles.main.expData.datafields{n},handles.main.params.plotting.toPlot{m}))
+ set(handles.togglebuttons{n-1}, 'Value', 1);
+ end
+ end
+ end
+end
+exportData(hObject, eventdata, handles);
+guidata(hObject, handles);
+
+
+
+function handles = updateOptions(hObject, eventdata, handles)
+
+handles = guidata(hObject);
+
+uipanel3_SelectionChangeFcn(hObject, eventdata, handles);
+
+if(get(handles.checkbox1,'Value'))
+ handles.main.params.plotting.clearFigs = 1;
+else
+ handles.main.params.plotting.clearFigs = 0;
+end
+
+handles.main.params.plotting.toPlot = {};
+for i = 1:length(handles.main.expData.datafields)-1
+ if(i<=12)
+ button_state = get(handles.togglebuttons{i},'Value');
+ end
+ if button_state == 1
+ handles.main.params.plotting.toPlot = {handles.main.params.plotting.toPlot{:}, handles.main.expData.datafields{i+1}};
+ else
+ handles.main.params.plotting.toPlot(strcmp(handles.main.expData.datafields{i+1},handles.main.params.plotting.toPlot)) = [];
+ end
+end
+handles.main.params.plotting.toPlot = handles.main.params.plotting.toPlot(~cellfun('isempty',handles.main.params.plotting.toPlot));
+
+exportData(hObject, eventdata, handles);
+guidata(hObject, handles);
+
+
+
+%% unused functions
+function uipanel1_ButtonDownFcn(hObject, eventdata, handles)
+function togglebutton7_CreateFcn(hObject, eventdata, handles)
+function listbox5_CreateFcn(hObject, eventdata, handles)
+function listbox1_Callback(hObject, eventdata, handles)
+function listbox1_CreateFcn(hObject, eventdata, handles)
+if ispc && isequal(get(hObject,'BackgroundColor'), get(0,'defaultUicontrolBackgroundColor'))
+ set(hObject,'BackgroundColor','white');
+end
+function listbox2_Callback(hObject, eventdata, handles)
+function listbox2_CreateFcn(hObject, eventdata, handles)
+function listbox3_Callback(hObject, eventdata, handles)
+function listbox3_CreateFcn(hObject, eventdata, handles)
+if ispc && isequal(get(hObject,'BackgroundColor'), get(0,'defaultUicontrolBackgroundColor'))
+ set(hObject,'BackgroundColor','white');
+end
+function listbox4_Callback(hObject, eventdata, handles)
+function listbox4_CreateFcn(hObject, eventdata, handles)
+if ispc && isequal(get(hObject,'BackgroundColor'), get(0,'defaultUicontrolBackgroundColor'))
+ set(hObject,'BackgroundColor','white');
+end
+
+
+%% bulky functions (repetative)
+
+%--- Executes on button press in togglebutton1.
+function togglebutton1_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton1 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton2.
+function togglebutton2_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton2 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton3.
+function togglebutton3_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton3 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton4.
+function togglebutton4_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton4 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton5.
+function togglebutton5_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton5 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton6.
+function togglebutton6_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton6 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton7.
+function togglebutton7_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton7 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton8.
+function togglebutton8_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton8 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)clc
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton9.
+function togglebutton9_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton9 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton10.
+function togglebutton10_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton10 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton11.
+function togglebutton11_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton11 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
+% --- Executes on button press in togglebutton12.
+function togglebutton12_Callback(hObject, eventdata, handles)
+% hObject handle to togglebutton12 (see GCBO)
+% eventdata reserved - to be defined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);
+guidata(hObject,handles);
diff --git a/controls/DataAnalysisTool/Tool/GUI.fig b/controls/DataAnalysisTool/Tool/GUI.fig
index 0e62ff281260cd9f294eff1374daa9c160bab03e..cbbcff33b682e326691c4bffc93b94c4dde630a0 100644
Binary files a/controls/DataAnalysisTool/Tool/GUI.fig and b/controls/DataAnalysisTool/Tool/GUI.fig differ
diff --git a/controls/DataAnalysisTool/Tool/GUI.m b/controls/DataAnalysisTool/Tool/GUI.m
index 3794047e00cc08f8ad91d60cbe691a2839368fa4..95016c85f4251c7337a1c7b9b799a0bb79b8d0ae 100644
--- a/controls/DataAnalysisTool/Tool/GUI.m
+++ b/controls/DataAnalysisTool/Tool/GUI.m
@@ -95,6 +95,11 @@ else
handles.main.params.file.path = handles.filepath;
handles.main.params.file.pathName = handles.filepath;
end
+
+handles.pause_or_play = 0;
+handles.pause_play_timer = timer('BusyMode', 'queue', 'ExecutionMode',...
+ 'fixedRate', 'Period', 5.0);
+set(handles.pause_play_timer, 'TimerFcn', @(hObject, event) pushbutton2_Callback(hObject, eventdata, guidata(hObject)));
cd(handles.main.params.file.path);
load_listbox(hObject, eventdata, handles)
guidata(hObject, handles);
@@ -158,6 +163,22 @@ exportData(hObject, eventdata, handles);
previewPlot(hObject, eventdata, handles);
guidata(hObject,handles);
+function pause_play_timer(hObject, eventdata, handles)
+% hObject handle to pushbutton_pause
+% eventdata reserved - to be defeined in a future version of MATLAB
+% handles structure with handles and user data (see GUIDATA)
+handles = guidata(hObject);
+handles = updateOptions(hObject, eventdata, handles);;
+
+if (handles.pause_or_play == 0)
+ handles.pause_or_play = 1;
+ start(handles.pause_play_timer);
+else
+ handles.pause_or_play = 0;
+ stop(handles.pause_play_timer);
+end
+guidata(hObject, handles);
+
% --- Executes on button press in pushbutton2.
function pushbutton2_Callback(hObject, eventdata, handles)
diff --git a/controls/DataAnalysisTool/Tool/gen b/controls/DataAnalysisTool/Tool/gen
new file mode 100755
index 0000000000000000000000000000000000000000..92ae91f76d291217c66a37c880ae548b1c1aea58
Binary files /dev/null and b/controls/DataAnalysisTool/Tool/gen differ
diff --git a/controls/DataAnalysisTool/Tool/gen_script.c b/controls/DataAnalysisTool/Tool/gen_script.c
new file mode 100644
index 0000000000000000000000000000000000000000..0e666217c3068070d6b38e1eecd53ed4fef69f74
--- /dev/null
+++ b/controls/DataAnalysisTool/Tool/gen_script.c
@@ -0,0 +1,39 @@
+/*
+ * This basic script will populate a .txt file (gui_testLogFile) with junk
+ * (but viable) data. This is for the purpose of testing the real time
+ * data logging feature on the groundstation side.
+ *
+ */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+static int NUM_OPERATIONS = 50;
+
+int main(){
+
+ FILE * f = fopen("gui_testLogFile.txt", "a");
+ FILE * to_write = fopen("junk_data.txt", "r");
+ char buffer[1048];
+
+ int i = 0;
+
+ if (f == NULL){
+ perror("Error opening file");
+ }
+ if (to_write == NULL){
+ perror("Error opening junk file");
+ }
+ while(i < NUM_OPERATIONS){
+ FILE * f = fopen("gui_testLogFile.txt", "a");
+ fgets(buffer, 746, to_write);
+ fprintf(f, buffer);
+ fclose(f);
+ i++;
+ sleep(1);
+ }
+ fclose(to_write);
+ return 0;
+}
diff --git a/controls/DataAnalysisTool/Tool/gui_testLogFile.txt b/controls/DataAnalysisTool/Tool/gui_testLogFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..aaaecc9d7f35670c3ff0549fd32990e709a486b4
--- /dev/null
+++ b/controls/DataAnalysisTool/Tool/gui_testLogFile.txt
@@ -0,0 +1,21 @@
+# MicroCART On-board Quad Log
+# Sample size: 1408
+# IMU IIC failures: 0
+# LiDAR IIC failures: 0
+# Optical Flow IIC failures: 0
+# Roll PID : Kp = 35.000000 Ki = 0.000000 Kd = 1.000000 Alpha = 0.880000
+# Pitch PID : Kp = 35.000000 Ki = 0.000000 Kd = 1.000000 Alpha = 0.880000
+# Yaw PID : Kp = 2.600000 Ki = 0.000000 Kd = 0.000000 Alpha = 0.000000
+# Roll Rate PID : Kp = 0.030000 Ki = 0.000000 Kd = 0.005000 Alpha = 0.880000
+# Pitch Rate PID : Kp = 0.030000 Ki = 0.000000 Kd = 0.005000 Alpha = 0.880000
+# Yaw Rate PID : Kp = 0.297000 Ki = 0.000000 Kd = 0.000000 Alpha = 0.000000
+# X pos PID : Kp = 0.550000 Ki = 0.007500 Kd = 0.000000 Alpha = 0.000000
+# Y pos PID : Kp = 0.550000 Ki = 0.007500 Kd = 0.000000 Alpha = 0.000000
+# Altitude PID : Kp = -0.098040 Ki = -0.008170 Kd = -0.073530 Alpha = 0.880000
+# X Vel PID : Kp = -0.100000 Ki = 0.000000 Kd = -0.020000 Alpha = 0.000000
+# Y Vel PID : Kp = 0.100000 Ki = 0.000000 Kd = 0.020000 Alpha = 0.000000
+# X Vel : Kp = 0.000000 Ki = 0.000000 Kd = -1.000000 Alpha = 0.880000
+# Y Vel : Kp = 0.000000 Ki = 0.000000 Kd = -1.000000 Alpha = 0.880000
+%Time accel_x accel_y accel_z gyro_x gyro_y gyro_z mag_x mag_y mag_z Roll_Constant Yaw_Constant X Setpoint_Constant Y Setpoint_Constant Alt Setpoint_Constant Yaw Setpoint_Constant Lidar_Constant VRPN X_Constant VRPN Y_Constant VRPN Alt_Constant Flow Vel X_Constant Flow Vel Y_Constant Flow Quality_Constant Altitude PID_Correction X pos PID_Correction Y pos PID_Correction Pitch PID_Correction Roll PID_Correction Yaw PID_Correction Pitch Rate PID_Correction Roll Rate PID_Correction Yaw Rate PID_Correction Pitch trim add_Sum Signal Mixer_MOTOR 0 Signal Mixer_MOTOR 1 Signal Mixer_MOTOR 2 Signal Mixer_MOTOR 3 X Vel PID_Correction Y Vel PID_Correction X Vel_Correction Y Vel_Correction OF Offset Angle_Rotated X OF Offset Angle_Rotated Y OF Integrate X_Integrated OF Integrate Y_Integrated PSI Sum_Sum Mag Yaw_Constant
+&s G G G rad/s rad/s rad/s uT uT uT 10ns_dutycycle rad rad rad/s rad/s rad/s 10ns_dutycycle 10ns_dutycycle 10ns_dutycycle rad 10ns_dutycycle 10ns_dutycycle 10ns_dutycycle 10ns_dutycycle rad rad m/s m/s m/s m/s m m rad rad rad rad m m m m m m m m m/s m/s none
+453.017395 0.001541 0.004752 -0.944339 -0.005257 0.000335 0.007330 -38.648438 144.703125 -341.859375 -0.010841 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.110840 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.684479 0.460010 0.000000 -0.020490 0.014007 -0.036237 0.047361 0.123941 0.010486 0.079480 0.110974 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
diff --git a/controls/DataAnalysisTool/Tool/junk_data.txt b/controls/DataAnalysisTool/Tool/junk_data.txt
new file mode 100644
index 0000000000000000000000000000000000000000..efd0d580a1eaf8bee0908571295e461ac8c895c8
--- /dev/null
+++ b/controls/DataAnalysisTool/Tool/junk_data.txt
@@ -0,0 +1,1407 @@
+453.022400 -0.000656 0.004752 -0.942142 -0.005257 0.001399 0.007330 -38.648438 140.109375 -344.250000 -0.010823 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.114607 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.681461 0.452479 0.000000 -0.020566 0.013775 -0.036237 0.047364 0.124248 0.010642 0.079323 0.110666 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.027405 0.000809 0.007437 -0.942630 -0.004193 0.001399 0.006266 -38.648438 140.109375 -344.250000 -0.010798 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.118300 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.678663 0.445392 0.000000 -0.020472 0.013398 -0.035921 0.047364 0.124216 0.011429 0.079169 0.110066 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.032410 -0.000900 0.005973 -0.941410 -0.005257 0.001399 0.006266 -43.195312 140.109375 -339.468750 -0.010779 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.121921 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.676027 0.439047 0.000000 -0.020385 0.013378 -0.035921 0.047362 0.124138 0.011526 0.079051 0.110124 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.037415 0.002273 0.006461 -0.944095 -0.005257 0.000335 0.006266 -43.195312 140.109375 -339.468750 -0.010760 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.125470 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.673227 0.433665 0.000000 -0.020134 0.013210 -0.035921 0.047351 0.124055 0.011945 0.078633 0.110208 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.042419 -0.001633 0.004020 -0.943363 -0.005257 0.001399 0.007330 -44.332031 138.960938 -347.835938 -0.010741 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.128950 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.670908 0.428856 0.000000 -0.020233 0.013061 -0.036237 0.047344 0.124619 0.011679 0.078266 0.110276 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.047424 0.000076 0.006705 -0.943607 -0.004193 0.001399 0.005202 -44.332031 138.960938 -347.835938 -0.010716 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.132362 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.668697 0.424213 0.000000 -0.020159 0.012758 -0.035605 0.047334 0.124216 0.012689 0.078521 0.109414 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.052429 0.000564 0.004996 -0.943363 -0.004193 0.001399 0.005202 -44.332031 138.960938 -347.835938 -0.010691 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.135707 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.666587 0.420004 0.000000 -0.020089 0.012643 -0.035605 0.047322 0.124261 0.012874 0.078336 0.109369 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.057434 0.004227 0.006705 -0.939457 -0.006321 0.002463 0.005202 -37.511719 145.851562 -345.445312 -0.010677 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.138986 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.664962 0.417113 0.000000 -0.020194 0.012885 -0.035605 0.047315 0.124134 0.012536 0.078693 0.109517 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.062439 0.002518 0.005729 -0.941410 -0.004193 0.001399 0.005202 -37.511719 145.851562 -345.445312 -0.010652 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.142201 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.663300 0.413633 0.000000 -0.019964 0.012440 -0.035605 0.047305 0.124349 0.013212 0.078018 0.109301 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.067444 0.002273 0.006217 -0.940921 -0.004193 0.001399 0.006266 -40.921875 142.406250 -341.859375 -0.010627 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.145353 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.661989 0.410497 0.000000 -0.019922 0.012357 -0.035921 0.047297 0.124706 0.013020 0.077577 0.109577 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.072449 0.001541 0.005729 -0.944339 -0.006321 -0.000729 0.006266 -40.921875 142.406250 -341.859375 -0.010614 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.148443 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.660375 0.408294 0.000000 -0.019552 0.012620 -0.035921 0.047283 0.124073 0.013127 0.077470 0.110210 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.077454 0.002273 0.005729 -0.946048 -0.003128 0.000335 0.006266 -48.878906 143.554688 -338.273438 -0.010586 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.151473 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.659373 0.405087 0.000000 -0.019710 0.012023 -0.035921 0.047277 0.124818 0.013556 0.077022 0.109445 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.082458 0.001053 0.007437 -0.946781 -0.004193 0.000335 0.005202 -48.878906 143.554688 -338.273438 -0.010563 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.154443 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.658589 0.402761 0.000000 -0.019696 0.012140 -0.035605 0.047272 0.124371 0.013769 0.077441 0.109259 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.087463 0.000076 0.007682 -0.942630 -0.004193 0.000335 0.005202 -35.238281 143.554688 -343.054688 -0.010542 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.157355 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.657939 0.400706 0.000000 -0.019685 0.012086 -0.035605 0.047269 0.124414 0.013833 0.077376 0.109217 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.092468 0.001053 0.006217 -0.943119 -0.005257 0.000335 0.005202 -35.238281 143.554688 -343.054688 -0.010528 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.160210 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.657336 0.399241 0.000000 -0.019675 0.012209 -0.035605 0.047266 0.124280 0.013721 0.077489 0.109350 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.097473 -0.002121 0.005729 -0.943363 -0.006321 0.002463 0.007330 -39.785156 138.960938 -345.445312 -0.010521 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.162406 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.657329 0.398594 0.000000 -0.020000 0.012341 -0.036237 0.047271 0.125117 0.012642 0.077323 0.109798 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.102478 -0.001877 0.007682 -0.944339 -0.005257 0.001399 0.007330 -39.785156 138.960938 -345.445312 -0.010509 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.164560 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.656834 0.397480 0.000000 -0.019801 0.012124 -0.036237 0.047268 0.125134 0.013057 0.076908 0.109781 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.107483 -0.000168 0.009879 -0.944584 -0.005257 0.001399 0.006266 -39.785156 138.960938 -345.445312 -0.010500 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.166672 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.656123 0.396561 0.000000 -0.019773 0.012092 -0.035921 0.047261 0.124823 0.013434 0.077164 0.109460 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.112488 0.000076 0.004752 -0.942875 -0.005257 0.001399 0.007330 -39.785156 138.960938 -345.445312 -0.010493 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.168743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.655242 0.395856 0.000000 -0.019741 0.012066 -0.036237 0.047249 0.125132 0.013175 0.076790 0.109782 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.117493 -0.000412 0.007926 -0.941654 -0.005257 0.001399 0.007330 -35.238281 141.257812 -335.882812 -0.010487 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.170774 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.654254 0.395302 0.000000 -0.019706 0.012046 -0.036237 0.047235 0.125118 0.013231 0.076735 0.109796 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.122498 0.000809 0.007193 -0.940677 -0.005257 0.001399 0.006266 -35.238281 141.257812 -335.882812 -0.010483 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.172766 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.652854 0.394855 0.000000 -0.019660 0.012029 -0.035906 0.047219 0.124757 0.013625 0.077003 0.109495 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.127502 0.000076 0.006705 -0.942142 -0.005257 0.002463 0.006266 -36.375000 137.812500 -344.250000 -0.010480 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.174719 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.652139 0.394495 0.000000 -0.019794 0.012015 -0.035906 0.047208 0.124905 0.013505 0.077123 0.109347 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.132507 0.003494 0.004020 -0.946537 -0.004193 0.002463 0.006266 -36.375000 137.812500 -344.250000 -0.010471 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.176634 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651500 0.393840 0.000000 -0.019756 0.011833 -0.035906 0.047197 0.125049 0.013725 0.076903 0.109203 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.137512 0.001785 0.003531 -0.944095 -0.005257 0.002463 0.006266 -39.785156 145.851562 -340.664062 -0.010465 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.178512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651034 0.393405 0.000000 -0.019726 0.011992 -0.035906 0.047188 0.124859 0.013596 0.077032 0.109393 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.142517 0.000809 0.004996 -0.944095 -0.004193 0.002463 0.006266 -39.785156 145.851562 -340.664062 -0.010450 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.180353 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651137 0.392158 0.000000 -0.019714 0.011792 -0.035921 0.047183 0.125054 0.013783 0.076795 0.109208 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.147522 0.002518 0.005240 -0.942142 -0.004193 0.001399 0.007330 -43.195312 142.406250 -344.250000 -0.010431 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.182159 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650755 0.391030 0.000000 -0.019531 0.011770 -0.036237 0.047176 0.125208 0.013672 0.076273 0.109686 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.152527 0.003982 0.005729 -0.945072 -0.003128 0.001399 0.007330 -43.195312 142.406250 -344.250000 -0.010403 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.183930 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650591 0.389464 0.000000 -0.019530 0.011573 -0.036237 0.047171 0.125404 0.013869 0.076076 0.109491 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.157532 0.001297 0.005240 -0.939945 -0.004193 0.000335 0.006266 -43.195312 142.406250 -344.250000 -0.010379 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.185666 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650345 0.388157 0.000000 -0.019366 0.011718 -0.035921 0.047166 0.124779 0.014204 0.076374 0.109483 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.162537 0.002273 0.006949 -0.938724 -0.004193 0.000335 0.005202 -39.785156 143.554688 -345.445312 -0.010354 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.187369 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650295 0.386842 0.000000 -0.019383 0.011685 -0.035605 0.047164 0.124513 0.014536 0.076673 0.109117 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.167542 0.003982 0.005973 -0.941166 -0.005257 -0.000729 0.007330 -39.785156 143.554688 -345.445312 -0.010334 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.189038 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650101 0.385895 0.000000 -0.019234 0.011822 -0.036237 0.047159 0.124860 0.013917 0.076029 0.110035 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.172546 0.001297 0.005484 -0.941654 -0.005257 0.000335 0.007330 -43.195312 137.812500 -344.250000 -0.010315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.190675 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650378 0.385017 0.000000 -0.019432 0.011785 -0.036237 0.047162 0.125094 0.013756 0.076190 0.109801 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.177551 0.000076 0.004264 -0.944828 -0.005257 0.001399 0.007330 -43.195312 137.812500 -344.250000 -0.010296 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.192280 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651019 0.384185 0.000000 -0.019621 0.011751 -0.036237 0.047172 0.125318 0.013601 0.076345 0.109577 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.182556 0.000320 0.006705 -0.946293 -0.004193 0.000335 0.006266 -39.785156 141.257812 -340.664062 -0.010272 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.193853 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651259 0.383065 0.000000 -0.019463 0.011550 -0.035921 0.047176 0.125045 0.014276 0.076302 0.109218 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.187561 -0.000656 0.003531 -0.944584 -0.005257 0.001399 0.006266 -39.785156 141.257812 -340.664062 -0.010253 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.195396 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651655 0.382285 0.000000 -0.019645 0.011694 -0.035921 0.047182 0.125082 0.013950 0.076628 0.109180 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.192566 -0.001633 0.005973 -0.940189 -0.006321 0.002463 0.005202 -38.648438 142.406250 -344.250000 -0.010239 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.196908 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.652114 0.381805 0.000000 -0.019812 0.011831 -0.035605 0.047190 0.124796 0.013962 0.077248 0.108834 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.197571 0.000564 0.005484 -0.944339 -0.004193 0.002463 0.005202 -38.648438 142.406250 -344.250000 -0.010214 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.198391 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.652280 0.380679 0.000000 -0.019796 0.011456 -0.035605 0.047193 0.125155 0.014353 0.076856 0.108475 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.202576 0.001297 0.007193 -0.950199 -0.005257 0.001399 0.006266 -44.332031 138.960938 -340.664062 -0.010195 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.199645 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651909 0.379923 0.000000 -0.019607 0.011603 -0.035921 0.047188 0.125135 0.014079 0.076499 0.109128 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.207581 0.003982 0.006217 -0.947269 -0.005257 0.000335 0.006266 -44.332031 138.960938 -340.664062 -0.010177 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.200874 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650796 0.379552 0.000000 -0.019413 0.011586 -0.035906 0.047175 0.124952 0.014315 0.076313 0.109300 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.212585 0.001297 0.004752 -0.947269 -0.004193 0.001399 0.005202 -42.058594 145.851562 -340.664062 -0.010155 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.202080 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650434 0.378660 0.000000 -0.019576 0.011395 -0.035590 0.047168 0.124991 0.014659 0.076601 0.108629 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.217590 0.002273 0.004752 -0.943363 -0.005257 0.001399 0.005202 -42.058594 145.851562 -340.664062 -0.010139 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.203262 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650187 0.378127 0.000000 -0.019566 0.011550 -0.035590 0.047164 0.124826 0.014514 0.076746 0.108793 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.222595 0.001785 0.006461 -0.942630 -0.005257 0.001399 0.007330 -45.468750 135.515625 -341.859375 -0.010123 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.204423 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650072 0.377591 0.000000 -0.019560 0.011528 -0.036222 0.047161 0.125475 0.013910 0.076086 0.109409 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.227600 0.000564 0.006217 -0.942875 -0.006321 0.001399 0.007330 -45.468750 135.515625 -341.859375 -0.010113 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.205562 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650057 0.377385 0.000000 -0.019558 0.011676 -0.036222 0.047160 0.125324 0.013764 0.076232 0.109560 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.232605 0.003006 0.005729 -0.943607 -0.005257 0.001399 0.006266 -45.468750 133.218750 -346.640625 -0.010098 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.206679 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650111 0.376891 0.000000 -0.019558 0.011482 -0.035906 0.047160 0.125202 0.014274 0.076354 0.109050 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.237610 0.002029 0.005729 -0.943607 -0.004193 0.000335 0.006266 -45.468750 133.218750 -346.640625 -0.010078 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.207774 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649936 0.376122 0.000000 -0.019392 0.011297 -0.035906 0.047156 0.125220 0.014625 0.076003 0.109032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.242615 -0.000168 0.006461 -0.948490 -0.004193 0.000335 0.006266 -43.195312 142.406250 -344.250000 -0.010059 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.208849 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649835 0.375403 0.000000 -0.019403 0.011289 -0.035906 0.047154 0.125240 0.014622 0.076006 0.109012 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.247620 0.000564 0.007193 -0.945316 -0.004193 0.001399 0.006266 -43.195312 142.406250 -344.250000 -0.010042 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.209903 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650038 0.374754 0.000000 -0.019581 0.011281 -0.035906 0.047156 0.125425 0.014452 0.076176 0.108827 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.252625 0.000809 0.005973 -0.943851 -0.004193 0.001399 0.006266 -47.742188 142.406250 -351.421875 -0.010025 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.210938 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650524 0.373893 0.000000 -0.019591 0.011266 -0.035921 0.047158 0.125456 0.014432 0.076145 0.108807 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.257629 -0.001633 0.005240 -0.942142 -0.003128 0.001399 0.006266 -47.742188 142.406250 -351.421875 -0.010005 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.211953 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650529 0.373082 0.000000 -0.019587 0.011091 -0.035921 0.047157 0.125627 0.014611 0.075967 0.108636 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.262634 0.001297 0.005729 -0.943119 -0.003128 -0.000729 0.006266 -47.742188 142.406250 -351.421875 -0.009984 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.212948 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649760 0.372303 0.000000 -0.019241 0.011091 -0.035921 0.047144 0.125281 0.014956 0.075621 0.108981 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.267639 0.002029 0.005484 -0.943363 -0.004193 0.000335 0.006266 -44.332031 141.257812 -345.445312 -0.009969 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.213924 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649232 0.371834 0.000000 -0.019412 0.011257 -0.035921 0.047134 0.125286 0.014619 0.075959 0.108976 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.272644 0.002029 0.004752 -0.944095 -0.004193 0.000335 0.007330 -44.332031 141.257812 -345.445312 -0.009954 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.214882 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648710 0.371319 0.000000 -0.019406 0.011245 -0.036237 0.047124 0.125608 0.014322 0.075623 0.109286 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.277649 -0.000168 0.003775 -0.944584 -0.004193 0.001399 0.007330 -42.058594 138.960938 -345.445312 -0.009936 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.215821 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648179 0.371014 0.000000 -0.019557 0.011238 -0.036237 0.047119 0.125776 0.014187 0.075778 0.109138 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.282654 0.000564 0.001822 -0.943607 -0.005257 0.001399 0.007330 -42.058594 138.960938 -345.445312 -0.009922 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.216743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648007 0.370554 0.000000 -0.019544 0.011386 -0.036237 0.047114 0.125615 0.014053 0.075912 0.109300 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.287659 0.001541 0.004752 -0.944828 -0.005257 -0.000729 0.008394 -38.648438 142.406250 -341.859375 -0.009903 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.217646 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.647203 0.369857 0.000000 -0.019193 0.011352 -0.036553 0.047099 0.125615 0.014122 0.075211 0.109932 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.292664 0.001785 0.005973 -0.940677 -0.004193 0.000335 0.006266 -38.648438 142.406250 -341.859375 -0.009876 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.218532 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646761 0.368672 0.000000 -0.019363 0.011145 -0.035921 0.047089 0.125360 0.014791 0.075807 0.108923 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.297668 0.001053 0.004996 -0.943851 -0.005257 0.000335 0.006266 -39.785156 141.257812 -343.054688 -0.009853 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.219401 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646379 0.367748 0.000000 -0.019358 0.011282 -0.035906 0.047080 0.125202 0.014674 0.075954 0.109050 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.302673 0.001541 0.006217 -0.948002 -0.004193 0.000335 0.006266 -39.785156 141.257812 -343.054688 -0.009825 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.220454 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646060 0.366522 0.000000 -0.019354 0.011074 -0.035906 0.047072 0.125405 0.014886 0.075742 0.108847 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.307678 0.000320 0.007193 -0.943851 -0.003128 0.000335 0.006266 -36.375000 140.109375 -344.250000 -0.009792 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.221487 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645786 0.365093 0.000000 -0.019350 0.010877 -0.035906 0.047065 0.125598 0.015087 0.075541 0.108654 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.312683 0.002273 0.005240 -0.943851 -0.005257 0.000335 0.006266 -36.375000 140.109375 -344.250000 -0.009773 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.222500 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645544 0.364465 0.000000 -0.019347 0.011198 -0.035906 0.047058 0.125275 0.014769 0.075859 0.108977 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.317688 0.000076 0.006705 -0.945804 -0.004193 0.000335 0.006266 -40.921875 137.812500 -339.468750 -0.009751 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.223493 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645328 0.363668 0.000000 -0.019344 0.011002 -0.035921 0.047051 0.125483 0.014953 0.075645 0.108799 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.322693 0.000809 0.005973 -0.947513 -0.005257 0.001399 0.005202 -40.921875 137.812500 -339.468750 -0.009736 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.224467 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645419 0.363335 0.000000 -0.019509 0.011156 -0.035605 0.047050 0.125179 0.014950 0.076280 0.108471 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.327698 -0.000656 0.002066 -0.943607 -0.005257 0.001399 0.006266 -40.921875 135.515625 -346.640625 -0.009724 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.225422 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645451 0.363065 0.000000 -0.019498 0.011136 -0.035921 0.047048 0.125503 0.014665 0.075932 0.108779 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.332703 0.003250 0.003775 -0.943119 -0.004193 0.000335 0.006266 -40.921875 135.515625 -346.640625 -0.009705 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.226359 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645113 0.362415 0.000000 -0.019317 0.010946 -0.035921 0.047040 0.125512 0.015036 0.075562 0.108771 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.337708 0.001297 0.005484 -0.941898 -0.005257 0.001399 0.005202 -40.921875 135.515625 -344.250000 -0.009689 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.227278 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645102 0.361968 0.000000 -0.019482 0.011099 -0.035605 0.047038 0.125208 0.015034 0.076195 0.108442 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.342712 0.001297 0.007193 -0.942142 -0.006321 0.001399 0.006266 -40.921875 135.515625 -344.250000 -0.009678 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.228179 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645492 0.361766 0.000000 -0.019483 0.011242 -0.035906 0.047036 0.125367 0.014589 0.076039 0.108885 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.347717 0.000076 0.005240 -0.943851 -0.004193 0.002463 0.005202 -43.195312 144.703125 -346.640625 -0.009657 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.229063 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645843 0.360944 0.000000 -0.019644 0.010875 -0.035590 0.047040 0.125579 0.015111 0.076149 0.108041 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.352722 0.002518 0.007682 -0.943851 -0.004193 0.001399 0.006266 -43.195312 144.703125 -346.640625 -0.009637 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.229929 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645867 0.360212 0.000000 -0.019462 0.010862 -0.035906 0.047039 0.125725 0.014990 0.075638 0.108527 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.357727 0.001053 0.007437 -0.941410 -0.003128 0.000335 0.007330 -35.238281 143.554688 -345.445312 -0.009614 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.230779 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645604 0.359317 0.000000 -0.019289 0.010684 -0.036222 0.047033 0.126047 0.015025 0.074971 0.108837 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.362732 0.000809 0.007926 -0.941410 -0.005257 0.001399 0.006266 -35.238281 143.554688 -345.445312 -0.009605 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.231612 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645684 0.358961 0.000000 -0.019462 0.011015 -0.035921 0.047033 0.125578 0.014812 0.075766 0.108685 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.367737 0.003250 0.008902 -0.943607 -0.005257 0.002463 0.007330 -35.238281 143.554688 -345.445312 -0.009601 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.232429 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646099 0.359116 0.000000 -0.019628 0.011009 -0.036237 0.047038 0.126066 0.014336 0.075610 0.108829 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.372742 0.002029 0.006949 -0.945072 -0.004193 -0.000729 0.006266 -39.785156 145.851562 -345.445312 -0.009595 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.233230 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645621 0.359178 0.000000 -0.019114 0.010842 -0.035921 0.047029 0.125403 0.015332 0.075245 0.108859 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.377747 0.002273 0.009146 -0.943363 -0.006321 0.000335 0.006266 -39.785156 145.851562 -345.445312 -0.009604 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.234015 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645577 0.360066 0.000000 -0.019300 0.011195 -0.035921 0.047027 0.125237 0.014793 0.075784 0.109026 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.382751 0.002029 0.004996 -0.942386 -0.004193 0.000335 0.007330 -38.648438 140.109375 -339.468750 -0.009605 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.234784 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645628 0.360436 0.000000 -0.019311 0.010863 -0.036237 0.047027 0.125896 0.014799 0.075147 0.108999 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.387756 0.001541 0.007682 -0.941166 -0.004193 0.000335 0.007330 -38.648438 140.109375 -339.468750 -0.009608 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.235538 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645745 0.360857 0.000000 -0.019323 0.010884 -0.036237 0.047028 0.125886 0.014765 0.075180 0.109009 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.392761 -0.000656 0.005240 -0.942630 -0.004193 -0.000729 0.006266 -37.511719 138.960938 -340.664062 -0.009611 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.236278 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645551 0.361246 0.000000 -0.019165 0.010904 -0.035921 0.047023 0.125392 0.015220 0.075357 0.108871 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.397766 0.000564 0.006217 -0.942630 -0.006321 0.000335 0.007330 -37.511719 138.960938 -340.664062 -0.009624 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.237003 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645605 0.362161 0.000000 -0.019347 0.011258 -0.036237 0.047023 0.125537 0.014368 0.075578 0.109358 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.402771 0.004959 0.006705 -0.945072 -0.004193 0.000335 0.006266 -40.921875 144.703125 -341.859375 -0.009624 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.237713 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645585 0.362291 0.000000 -0.019350 0.010918 -0.035921 0.047022 0.125563 0.015020 0.075557 0.108699 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.407776 0.000320 0.005973 -0.943607 -0.004193 0.002463 0.006266 -40.921875 144.703125 -341.859375 -0.009622 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.238410 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645836 0.362606 0.000000 -0.019680 0.010937 -0.035921 0.047032 0.125885 0.014682 0.075916 0.108398 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.412781 0.000320 0.005484 -0.941166 -0.006321 0.000335 0.005202 -43.195312 137.812500 -346.640625 -0.009629 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.239092 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645786 0.363123 0.000000 -0.019332 0.011280 -0.035605 0.047030 0.124878 0.015003 0.076226 0.108773 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.417786 0.001053 0.005729 -0.940677 -0.004193 0.000335 0.005202 -43.195312 137.812500 -346.640625 -0.009624 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.239762 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645682 0.362855 0.000000 -0.019335 0.010929 -0.035605 0.047028 0.125231 0.015351 0.075879 0.108419 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.422791 0.002273 0.005484 -0.945560 -0.004193 0.001399 0.005202 -35.238281 141.257812 -345.445312 -0.009616 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.240418 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645840 0.362467 0.000000 -0.019505 0.010927 -0.035605 0.047031 0.125403 0.015183 0.076047 0.108247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.427795 0.000076 0.006949 -0.941410 -0.005257 0.001399 0.005202 -35.238281 141.257812 -345.445312 -0.009611 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.241061 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646313 0.362300 0.000000 -0.019509 0.011090 -0.035605 0.047032 0.125243 0.015016 0.076214 0.108407 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.432800 0.000564 0.005240 -0.937504 -0.004193 0.002463 0.005202 -39.785156 148.148438 -347.835938 -0.009601 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.241691 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646672 0.361754 0.000000 -0.019670 0.010907 -0.035605 0.047038 0.125588 0.015038 0.076191 0.108062 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.437805 -0.000412 0.004508 -0.942630 -0.005257 0.001399 0.007330 -39.785156 148.148438 -347.835938 -0.009594 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.242309 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646613 0.361470 0.000000 -0.019485 0.011066 -0.036237 0.047037 0.125876 0.014431 0.075534 0.109039 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.442810 -0.001389 0.004996 -0.944584 -0.004193 0.001399 0.007330 -37.511719 141.257812 -343.054688 -0.009580 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.242915 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646420 0.360778 0.000000 -0.019474 0.010878 -0.036237 0.047034 0.126053 0.014631 0.075335 0.108862 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.447815 0.000564 0.007682 -0.939945 -0.006321 0.002463 0.007330 -37.511719 141.257812 -343.054688 -0.009576 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.243508 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646382 0.360660 0.000000 -0.019627 0.011202 -0.036237 0.047034 0.125882 0.014153 0.075813 0.109032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.452820 -0.002121 0.005240 -0.944584 -0.004193 0.001399 0.006266 -44.332031 148.148438 -347.835938 -0.009561 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.244090 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645860 0.359904 0.000000 -0.019433 0.010837 -0.035921 0.047025 0.125736 0.015029 0.075569 0.108546 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.457825 0.000320 0.004264 -0.945072 -0.004193 0.000335 0.006266 -44.332031 148.148438 -347.835938 -0.009546 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.244660 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.644886 0.359172 0.000000 -0.019242 0.010826 -0.035921 0.047008 0.125558 0.015231 0.075367 0.108725 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.462830 0.003250 0.005240 -0.942630 -0.003128 0.000335 0.006266 -40.921875 140.109375 -344.250000 -0.009524 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.245218 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.643873 0.358109 0.000000 -0.019225 0.010643 -0.035921 0.046989 0.125723 0.015430 0.075168 0.108559 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.467834 0.002518 0.006949 -0.941654 -0.004193 -0.000729 0.006266 -40.921875 140.109375 -344.250000 -0.009508 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.245765 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.642662 0.357369 0.000000 -0.019042 0.010804 -0.035921 0.046967 0.125379 0.015453 0.075144 0.108904 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.472839 -0.001389 0.007682 -0.944339 -0.004193 0.000335 0.005202 -40.921875 140.109375 -344.250000 -0.009492 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.246302 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641944 0.356395 0.000000 -0.019206 0.010780 -0.035605 0.046952 0.125241 0.015619 0.075590 0.108389 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.477844 0.002029 0.005484 -0.946781 -0.004193 0.001399 0.006266 -40.921875 142.406250 -344.250000 -0.009478 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.246828 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641658 0.355838 0.000000 -0.019364 0.010768 -0.035921 0.046944 0.125728 0.015157 0.075421 0.108535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.482849 0.002273 0.004508 -0.944095 -0.005257 0.000335 0.006266 -40.921875 142.406250 -344.250000 -0.009471 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.247344 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641165 0.355673 0.000000 -0.019181 0.010926 -0.035921 0.046932 0.125386 0.015181 0.075396 0.108876 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.487854 0.002029 0.004752 -0.942142 -0.004193 0.001399 0.006266 -43.195312 140.109375 -344.250000 -0.009458 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.247850 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641142 0.355182 0.000000 -0.019348 0.010740 -0.035921 0.046928 0.125739 0.015201 0.075377 0.108524 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.492859 0.000320 0.005484 -0.944095 -0.003128 0.000335 0.005202 -43.195312 140.109375 -344.250000 -0.009440 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.248346 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640931 0.354343 0.000000 -0.019173 0.010560 -0.035605 0.046921 0.125428 0.015871 0.075338 0.108202 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.497864 -0.001633 0.005729 -0.944095 -0.004193 0.000335 0.006266 -37.511719 141.257812 -340.664062 -0.009425 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.248832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640773 0.353798 0.000000 -0.019176 0.010723 -0.035921 0.046916 0.125584 0.015389 0.075188 0.108678 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.502869 0.000076 0.009146 -0.944339 -0.005257 0.000335 0.007330 -37.511719 141.257812 -340.664062 -0.009417 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249309 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640558 0.353590 0.000000 -0.019177 0.010879 -0.036237 0.046909 0.125745 0.014918 0.075028 0.109149 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.507874 0.000076 0.006461 -0.945072 -0.004193 0.001399 0.006266 -40.921875 140.109375 -349.031250 -0.009405 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249375 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640548 0.353174 0.000000 -0.019342 0.010693 -0.035921 0.046906 0.125780 0.015254 0.075324 0.108482 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.512878 0.000809 0.006217 -0.939945 -0.004193 0.001399 0.007330 -40.921875 140.109375 -349.031250 -0.009396 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249441 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640436 0.352897 0.000000 -0.019329 0.010688 -0.036237 0.046901 0.126088 0.014956 0.074989 0.108807 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.517883 0.001785 0.004264 -0.943363 -0.004193 0.001399 0.006266 -40.921875 144.703125 -349.031250 -0.009387 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249505 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640266 0.352992 0.000000 -0.019315 0.010694 -0.035921 0.046895 0.125762 0.015290 0.075307 0.108520 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.522888 -0.001633 0.006705 -0.943851 -0.005257 0.001399 0.005202 -40.921875 144.703125 -349.031250 -0.009385 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640067 0.353102 0.000000 -0.019301 0.010859 -0.035605 0.046889 0.125267 0.015455 0.075775 0.108384 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.527893 0.000809 0.004752 -0.944828 -0.004193 0.000335 0.005202 -38.648438 140.109375 -349.031250 -0.009377 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249631 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639505 0.352856 0.000000 -0.019118 0.010679 -0.035605 0.046877 0.125263 0.015818 0.075412 0.108387 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.532898 0.001297 0.005729 -0.946048 -0.005257 0.001399 0.005202 -38.648438 140.109375 -349.031250 -0.009373 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249692 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639237 0.352874 0.000000 -0.019278 0.010843 -0.035605 0.046870 0.125260 0.015493 0.075737 0.108390 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.537903 0.000809 0.006217 -0.944584 -0.005257 0.001399 0.006266 -42.058594 141.257812 -340.664062 -0.009368 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249753 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638622 0.352823 0.000000 -0.019253 0.010830 -0.035921 0.046862 0.125564 0.015216 0.075382 0.108718 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.542908 0.001053 0.004752 -0.944095 -0.005257 0.001399 0.007330 -42.058594 141.257812 -340.664062 -0.009363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249812 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638410 0.352715 0.000000 -0.019240 0.010816 -0.036237 0.046856 0.125881 0.014926 0.075039 0.109033 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.547913 -0.000168 0.006705 -0.943851 -0.004193 0.001399 0.006266 -44.332031 141.257812 -340.664062 -0.009352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249871 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638231 0.352247 0.000000 -0.019229 0.010633 -0.035921 0.046850 0.125737 0.015436 0.075161 0.108545 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.552917 -0.000412 0.006949 -0.945560 -0.004193 0.001399 0.005202 -44.332031 141.257812 -340.664062 -0.009340 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249930 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638048 0.351790 0.000000 -0.019219 0.010627 -0.035605 0.046844 0.125417 0.015769 0.075461 0.108233 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.557922 0.000076 0.007193 -0.946781 -0.004193 0.001399 0.005202 -37.511719 141.257812 -343.054688 -0.009330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.249987 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637828 0.351400 0.000000 -0.019208 0.010621 -0.035605 0.046838 0.125412 0.015785 0.075444 0.108238 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.562927 0.000320 0.006461 -0.947513 -0.005257 0.001399 0.006266 -37.511719 141.257812 -343.054688 -0.009327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250044 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637930 0.351118 0.000000 -0.019207 0.010778 -0.035921 0.046830 0.125561 0.015303 0.075274 0.108702 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.567932 0.002518 0.004264 -0.942142 -0.005257 0.001399 0.006266 -36.375000 140.109375 -346.640625 -0.009324 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250100 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637667 0.351178 0.000000 -0.019196 0.010769 -0.035921 0.046823 0.125558 0.015323 0.075254 0.108704 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.572937 0.001785 0.003775 -0.942630 -0.004193 0.002463 0.006266 -36.375000 140.109375 -346.640625 -0.009316 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250156 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637788 0.350876 0.000000 -0.019357 0.010592 -0.035921 0.046822 0.125896 0.015341 0.075237 0.108366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.577942 0.000809 0.006949 -0.943851 -0.003128 0.001399 0.006266 -36.375000 140.109375 -346.640625 -0.009301 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250211 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637686 0.350179 0.000000 -0.019176 0.010418 -0.035921 0.046818 0.125889 0.015694 0.074883 0.108374 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.582947 0.001053 0.005973 -0.942142 -0.005257 -0.000729 0.005202 -40.921875 147.000000 -346.640625 -0.009296 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250266 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637047 0.350374 0.000000 -0.018837 0.010765 -0.035605 0.046805 0.124897 0.016012 0.075217 0.108753 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.587952 0.003494 0.005484 -0.945804 -0.005257 0.001399 0.006266 -40.921875 147.000000 -346.640625 -0.009290 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250320 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637162 0.350239 0.000000 -0.019190 0.010750 -0.035921 0.046804 0.125582 0.015359 0.075238 0.108701 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.592957 0.002762 0.006217 -0.946293 -0.005257 0.001399 0.005202 -40.921875 137.812500 -341.859375 -0.009285 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250373 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637409 0.350083 0.000000 -0.019194 0.010735 -0.035605 0.046806 0.125284 0.015687 0.075543 0.108366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.597961 0.002029 0.005484 -0.948246 -0.005257 0.001399 0.006266 -40.921875 137.812500 -341.859375 -0.009279 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250425 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637812 0.349918 0.000000 -0.019202 0.010721 -0.035921 0.046811 0.125623 0.015376 0.075222 0.108660 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.602966 -0.002121 0.007437 -0.945072 -0.005257 -0.000729 0.007330 -42.058594 138.960938 -347.835938 -0.009273 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.250477 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637663 0.349766 0.000000 -0.018875 0.010708 -0.036237 0.046806 0.125624 0.015399 0.074566 0.109290 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.607971 -0.001389 0.005240 -0.943851 -0.004193 0.001399 0.007330 -42.058594 138.960938 -347.835938 -0.009263 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.251734 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638074 0.349341 0.000000 -0.019235 0.010529 -0.036237 0.046812 0.126163 0.015219 0.074747 0.108752 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.612976 -0.000656 0.005240 -0.940189 -0.004193 0.000335 0.006266 -38.648438 142.406250 -353.812500 -0.009253 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.252967 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637954 0.348954 0.000000 -0.019066 0.010527 -0.035921 0.046809 0.125680 0.015707 0.074891 0.108602 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.617981 0.002029 0.004020 -0.941898 -0.004193 0.000335 0.006266 -38.648438 142.406250 -353.812500 -0.009243 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.254175 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637648 0.348547 0.000000 -0.019066 0.010523 -0.035921 0.046802 0.125685 0.015710 0.074888 0.108598 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.622986 0.000809 0.005729 -0.943363 -0.004193 0.001399 0.005202 -38.648438 140.109375 -344.250000 -0.009232 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.255359 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637548 0.348079 0.000000 -0.019232 0.010516 -0.035605 0.046799 0.125541 0.015867 0.075362 0.108109 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.627991 0.003494 0.006949 -0.944095 -0.004193 0.001399 0.005202 -38.648438 140.109375 -344.250000 -0.009220 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.256520 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637428 0.347575 0.000000 -0.019220 0.010507 -0.035590 0.046796 0.125523 0.015903 0.075357 0.108096 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.632996 -0.000412 0.006949 -0.941898 -0.005257 0.000335 0.005202 -44.332031 141.257812 -343.054688 -0.009214 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.257657 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637043 0.347416 0.000000 -0.019043 0.010667 -0.035590 0.046788 0.125185 0.015920 0.075340 0.108435 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.638000 -0.000412 0.004264 -0.941410 -0.005257 0.000335 0.005202 -44.332031 141.257812 -343.054688 -0.009208 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.258772 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636693 0.347297 0.000000 -0.019042 0.010653 -0.035590 0.046780 0.125198 0.015935 0.075325 0.108422 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.643005 0.000076 0.006705 -0.941898 -0.004193 0.000335 0.006266 -38.648438 144.703125 -346.640625 -0.009198 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.259864 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636318 0.346880 0.000000 -0.019039 0.010472 -0.035906 0.046772 0.125693 0.015803 0.074825 0.108559 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.648010 0.000809 0.007437 -0.942142 -0.004193 0.000335 0.006266 -38.648438 144.703125 -346.640625 -0.009188 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.260934 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635540 0.346515 0.000000 -0.019023 0.010468 -0.034161 0.046763 0.123936 0.017568 0.076550 0.106827 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.653015 0.000809 0.004264 -0.938968 -0.005257 0.000335 0.006266 -39.785156 138.960938 -350.226562 -0.009185 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.261983 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635103 0.346529 0.000000 -0.019016 0.010635 -0.034161 0.046754 0.123763 0.017408 0.076709 0.107000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.658020 0.003006 0.008170 -0.944339 -0.004193 -0.000729 0.005202 -39.785156 138.960938 -350.226562 -0.009177 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.263010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634385 0.346263 0.000000 -0.018840 0.010457 -0.033845 0.046739 0.123448 0.018077 0.076673 0.106682 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.663025 0.000076 0.004996 -0.945560 -0.004193 0.000335 0.005202 -37.511719 141.257812 -345.445312 -0.009170 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.264017 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634077 0.346050 0.000000 -0.019011 0.010458 -0.033845 0.046731 0.123619 0.017906 0.076844 0.106512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.668030 0.001297 0.004996 -0.940189 -0.004193 0.001399 0.006266 -37.511719 141.257812 -345.445312 -0.009164 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.265003 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634154 0.345856 0.000000 -0.019176 0.010458 -0.034161 0.046730 0.124099 0.017425 0.076692 0.106664 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.673035 0.001541 0.005484 -0.940433 -0.004193 0.000335 0.006266 -34.101562 144.703125 -346.640625 -0.009157 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.265969 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634320 0.345626 0.000000 -0.019008 0.010456 -0.028836 0.046724 0.118608 0.022920 0.081848 0.101504 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.678040 0.002762 0.007193 -0.941410 -0.004193 -0.000729 0.005202 -34.101562 144.703125 -346.640625 -0.009149 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.266915 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633891 0.345363 0.000000 -0.018839 0.010453 -0.028520 0.046714 0.118126 0.023408 0.081992 0.101354 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.683044 0.004471 0.006705 -0.944828 -0.005257 0.001399 0.006266 -34.101562 144.703125 -346.640625 -0.009147 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.267843 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634247 0.345428 0.000000 -0.019188 0.010618 -0.028836 0.046717 0.118625 0.022578 0.082190 0.101487 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.688049 0.002273 0.006461 -0.942386 -0.004193 0.000335 0.006266 -35.238281 138.960938 -343.054688 -0.009141 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.268751 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634468 0.345213 0.000000 -0.019021 0.010441 -0.028836 0.046719 0.118636 0.022923 0.081845 0.101476 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.693054 0.002029 0.007926 -0.940433 -0.003128 0.000335 0.006266 -35.238281 138.960938 -343.054688 -0.009130 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.269641 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634858 0.344761 0.000000 -0.019035 0.010273 -0.027061 0.046724 0.117044 0.024851 0.083467 0.099518 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.698059 -0.000412 0.007437 -0.942142 -0.004193 0.000335 0.006266 -40.921875 142.406250 -344.250000 -0.009127 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.270512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635321 0.344746 0.000000 -0.019052 0.010451 -0.027061 0.046730 0.116881 0.024656 0.083662 0.099681 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.703064 -0.000656 0.007682 -0.943119 -0.004193 0.000335 0.006266 -40.921875 142.406250 -344.250000 -0.009126 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.271367 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635722 0.344856 0.000000 -0.019066 0.010457 -0.027061 0.046736 0.116890 0.024637 0.083681 0.099672 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.708069 0.000564 0.005729 -0.941166 -0.004193 0.000335 0.005202 -34.101562 140.109375 -351.421875 -0.009127 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.273007 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635958 0.345065 0.000000 -0.019075 0.010465 -0.026745 0.046739 0.116575 0.024936 0.084015 0.099355 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.713074 0.001053 0.008170 -0.939945 -0.004193 0.001399 0.006266 -34.101562 140.109375 -351.421875 -0.009130 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.274615 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636336 0.345329 0.000000 -0.019247 0.010474 -0.027061 0.046745 0.117054 0.024437 0.083881 0.099508 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.718079 0.000564 0.008902 -0.943363 -0.005257 0.000335 0.006266 -34.101562 140.109375 -346.640625 -0.009139 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.276190 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636242 0.345676 0.000000 -0.019071 0.010646 -0.030611 0.046744 0.120247 0.020882 0.080316 0.103396 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.723083 0.004227 0.005729 -0.944828 -0.003128 -0.000729 0.006266 -34.101562 140.109375 -346.640625 -0.009139 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.277733 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635770 0.345762 0.000000 -0.018901 0.010315 -0.030611 0.046736 0.120407 0.021384 0.079814 0.103235 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.728088 0.002029 0.004996 -0.948246 -0.004193 0.000335 0.006266 -36.375000 144.703125 -339.468750 -0.009145 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.279245 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635668 0.346174 0.000000 -0.019075 0.010505 -0.030611 0.046734 0.120391 0.021019 0.080179 0.103251 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.733093 0.002029 0.006949 -0.942875 -0.004193 0.000335 0.006266 -36.375000 144.703125 -339.468750 -0.009150 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280727 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635657 0.346493 0.000000 -0.019075 0.010515 -0.030611 0.046733 0.120381 0.021008 0.080190 0.103261 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.738098 -0.000412 0.006949 -0.938968 -0.005257 0.001399 0.006266 -43.195312 142.406250 -344.250000 -0.009159 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282178 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636013 0.347027 0.000000 -0.019246 0.010692 -0.034146 0.046738 0.123911 0.017126 0.077002 0.106801 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.743103 0.000809 0.005729 -0.945316 -0.005257 0.002463 0.006266 -43.195312 142.406250 -344.250000 -0.009167 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283601 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636645 0.347463 0.000000 -0.019410 0.010690 -0.034146 0.046749 0.124076 0.016964 0.077164 0.106636 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.748108 0.002273 0.005729 -0.950199 -0.005257 0.001399 0.007330 -34.101562 140.109375 -344.250000 -0.009173 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284996 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636893 0.347786 0.000000 -0.019229 0.010687 -0.034462 0.046754 0.124215 0.016832 0.076664 0.107129 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.753113 0.001053 0.005973 -0.947025 -0.005257 0.001399 0.005202 -34.101562 140.109375 -344.250000 -0.009177 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286362 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637109 0.347987 0.000000 -0.019226 0.010681 -0.033830 0.046758 0.123585 0.017473 0.077287 0.106495 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.758118 0.001785 0.006461 -0.942386 -0.005257 0.001399 0.006266 -43.195312 135.515625 -341.859375 -0.009179 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287702 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637315 0.348081 0.000000 -0.019224 0.010674 -0.034146 0.046762 0.123906 0.017166 0.076962 0.106806 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.763123 0.001053 0.005484 -0.940921 -0.004193 0.001399 0.006266 -43.195312 135.515625 -341.859375 -0.009175 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289015 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637514 0.347782 0.000000 -0.019222 0.010497 -0.034146 0.046766 0.124082 0.017345 0.076783 0.106630 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.768127 0.000076 0.003531 -0.939701 -0.005257 0.000335 0.006266 -37.511719 141.257812 -347.835938 -0.009175 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290302 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637375 0.347710 0.000000 -0.019052 0.010661 -0.034146 0.046765 0.123747 0.017350 0.076777 0.106966 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.773132 0.002762 0.004996 -0.943607 -0.004193 0.001399 0.006266 -37.511719 141.257812 -347.835938 -0.009166 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291563 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637528 0.347179 0.000000 -0.019226 0.010477 -0.034146 0.046768 0.124104 0.017361 0.076767 0.106608 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.778137 0.002273 0.004264 -0.942386 -0.004193 0.000335 0.007330 -40.921875 135.515625 -341.859375 -0.009155 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292800 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637383 0.346509 0.000000 -0.019055 0.010465 -0.034462 0.046767 0.124262 0.017228 0.076267 0.107082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.783142 0.001541 0.006461 -0.944095 -0.004193 0.002463 0.006266 -40.921875 135.515625 -341.859375 -0.009141 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294011 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637921 0.345737 0.000000 -0.019399 0.010448 -0.035921 0.046776 0.126092 0.015451 0.075146 0.108190 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.788147 0.000809 0.005973 -0.941410 -0.005257 0.002463 0.006266 -40.921875 135.515625 -341.859375 -0.009132 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295199 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638471 0.345248 0.000000 -0.019393 0.010599 -0.035921 0.046787 0.125935 0.015306 0.075291 0.108347 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.793152 0.001053 0.004508 -0.945316 -0.004193 0.001399 0.006266 -40.921875 142.406250 -349.031250 -0.009117 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296362 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638688 0.344449 0.000000 -0.019220 0.010406 -0.035921 0.046792 0.125956 0.015673 0.074925 0.108327 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.798157 0.001053 0.006705 -0.945804 -0.004193 0.000335 0.006266 -40.921875 142.406250 -349.031250 -0.009102 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297502 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638564 0.343686 0.000000 -0.019055 0.010389 -0.035921 0.046791 0.125807 0.015855 0.074743 0.108475 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.803162 -0.000412 0.008414 -0.948490 -0.005257 0.000335 0.006266 -44.332031 145.851562 -345.445312 -0.009093 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298620 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638400 0.343634 0.000000 -0.019063 0.010553 -0.034146 0.046790 0.123877 0.017458 0.076690 0.106856 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.808167 -0.001877 0.006461 -0.948002 -0.004193 0.000335 0.006266 -44.332031 145.851562 -345.445312 -0.009082 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299715 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638127 0.343130 0.000000 -0.019067 0.010368 -0.034146 0.046786 0.124065 0.017639 0.076509 0.106667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.813171 -0.000900 0.004996 -0.945560 -0.005257 0.000335 0.006266 -45.468750 142.406250 -344.250000 -0.009079 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300185 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637673 0.343101 0.000000 -0.019064 0.010533 -0.034146 0.046779 0.123897 0.017477 0.076671 0.106835 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.818176 -0.002121 0.006949 -0.941166 -0.004193 0.002463 0.006266 -45.468750 142.406250 -344.250000 -0.009072 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300647 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637626 0.342848 0.000000 -0.019391 0.010356 -0.034146 0.046779 0.124401 0.017327 0.076820 0.106331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.823181 0.001297 0.002799 -0.943851 -0.005257 0.000335 0.006266 -38.648438 135.515625 -344.250000 -0.009071 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301099 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636733 0.342943 0.000000 -0.019022 0.010525 -0.034146 0.046764 0.123863 0.017527 0.076621 0.106869 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.828186 0.001541 0.005240 -0.940433 -0.005257 0.000335 0.006266 -38.648438 135.515625 -344.250000 -0.009069 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301543 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635768 0.342968 0.000000 -0.019004 0.010516 -0.034146 0.046747 0.123854 0.017554 0.076594 0.106878 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.833191 0.000320 0.005729 -0.945072 -0.005257 0.001399 0.006266 -42.058594 138.960938 -340.664062 -0.009065 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301979 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635153 0.342887 0.000000 -0.019155 0.010505 -0.034146 0.046735 0.124015 0.017414 0.076734 0.106717 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.838196 0.001785 0.006705 -0.943851 -0.005257 0.000335 0.005202 -42.058594 138.960938 -340.664062 -0.009061 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302406 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634302 0.342749 0.000000 -0.018963 0.010494 -0.033830 0.046719 0.123519 0.017933 0.076847 0.106581 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.843201 0.001053 0.006217 -0.943607 -0.004193 0.002463 0.006266 -39.785156 138.960938 -345.445312 -0.009051 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302824 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634214 0.342295 0.000000 -0.019288 0.010314 -0.034146 0.046715 0.124340 0.017471 0.076677 0.106392 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.848206 -0.000168 0.007193 -0.942386 -0.005257 0.001399 0.007330 -39.785156 138.960938 -345.445312 -0.009047 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303235 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633557 0.342215 0.000000 -0.019086 0.010481 -0.034462 0.046708 0.124288 0.017190 0.076325 0.107077 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.853210 0.000564 0.008902 -0.944584 -0.006321 0.000335 0.006266 -34.101562 140.109375 -344.250000 -0.009051 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303637 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633026 0.342553 0.000000 -0.018906 0.010644 -0.034146 0.046697 0.123629 0.017523 0.076624 0.107104 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.858215 0.001541 0.006705 -0.945072 -0.004193 0.001399 0.006266 -34.101562 140.109375 -344.250000 -0.009047 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304031 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632886 0.342413 0.000000 -0.019073 0.010299 -0.034146 0.046692 0.124140 0.017701 0.076446 0.106592 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.863220 0.000809 0.004752 -0.947757 -0.004193 0.000335 0.006266 -42.058594 145.851562 -345.445312 -0.009045 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304418 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632505 0.342412 0.000000 -0.018897 0.010311 -0.034146 0.046683 0.123952 0.017866 0.076282 0.106780 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.868225 0.002273 0.007682 -0.942630 -0.005257 0.000335 0.006266 -42.058594 145.851562 -345.445312 -0.009049 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304797 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632221 0.342781 0.000000 -0.018899 0.010492 -0.034146 0.046676 0.142443 0.036353 0.095135 0.125629 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.873230 0.002518 0.007682 -0.939213 -0.004193 0.000335 0.006266 -43.195312 140.109375 -334.687500 -0.009050 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305168 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632061 0.342876 0.000000 -0.018903 0.010329 -0.034146 0.046670 0.142610 0.036511 0.094977 0.125462 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.878235 0.000320 0.007926 -0.943363 -0.005257 0.000335 0.006266 -43.195312 140.109375 -334.687500 -0.009057 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305532 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632028 0.343370 0.000000 -0.018911 0.010514 -0.034146 0.046667 0.142433 0.036320 0.095168 0.125639 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.883240 -0.002121 0.007437 -0.946293 -0.004193 0.000335 0.007330 -39.785156 143.554688 -338.273438 -0.009061 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305889 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632029 0.343631 0.000000 -0.018918 0.010355 -0.034462 0.046665 0.142915 0.036155 0.094701 0.125790 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.888245 0.001053 0.006217 -0.942386 -0.005257 0.000335 0.006266 -39.785156 143.554688 -338.273438 -0.009072 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306239 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631950 0.344272 0.000000 -0.018922 0.010544 -0.034146 0.046661 0.142414 0.036278 0.095209 0.125658 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.893250 -0.000900 0.004996 -0.941898 -0.005257 0.000335 0.005202 -39.785156 143.554688 -338.273438 -0.009082 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306582 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631756 0.344886 0.000000 -0.018922 0.010555 -0.033830 0.046656 0.161917 0.056413 0.115367 0.145183 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.898254 0.000320 0.006705 -0.943119 -0.004193 0.000335 0.006266 -37.511719 143.554688 -345.445312 -0.009086 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306918 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631449 0.345092 0.000000 -0.018917 0.010396 -0.034146 0.046648 0.162388 0.056261 0.114887 0.145344 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.903259 -0.000168 0.007682 -0.944095 -0.005257 -0.000729 0.005202 -37.511719 143.554688 -345.445312 -0.009095 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630724 0.345536 0.000000 -0.018740 0.010578 -0.033830 0.046634 0.161712 0.056571 0.115209 0.145388 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.908264 0.001053 0.005973 -0.942386 -0.005257 0.000335 0.006266 -42.058594 150.445312 -347.835938 -0.009102 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307570 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630260 0.345920 0.000000 -0.018905 0.010583 -0.034146 0.046623 0.162188 0.056085 0.115062 0.145544 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.913269 0.001785 0.007193 -0.941410 -0.004193 0.000335 0.004137 -42.058594 150.445312 -347.835938 -0.009104 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629781 0.345945 0.000000 -0.018892 0.010419 -0.033514 0.046612 0.176877 0.072065 0.130687 0.159930 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.918274 0.001297 0.005240 -0.941166 -0.005257 0.001399 0.006266 -42.058594 138.960938 -340.664062 -0.009111 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306604 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629678 0.346245 0.000000 -0.019050 0.010598 -0.034146 0.046607 0.177489 0.071096 0.130392 0.160584 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.923279 0.001541 0.004264 -0.944339 -0.005257 0.000335 0.006266 -42.058594 138.960938 -340.664062 -0.009116 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306135 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629340 0.346445 0.000000 -0.018866 0.010597 -0.034146 0.046599 0.177305 0.071280 0.130208 0.160767 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.928284 0.000076 0.007193 -0.944828 -0.005257 0.000335 0.006266 -37.511719 138.960938 -347.835938 -0.009118 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629094 0.346513 0.000000 -0.018862 0.010594 -0.034146 0.046591 0.177304 0.071288 0.130200 0.160768 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.933289 0.001541 0.007193 -0.941410 -0.005257 0.000335 0.006266 -37.511719 138.960938 -347.835938 -0.009120 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305226 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628913 0.346505 0.000000 -0.018859 0.010589 -0.034146 0.046585 0.177306 0.071296 0.130191 0.160766 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.938293 0.003250 0.005973 -0.942142 -0.005257 0.001399 0.007330 -40.921875 144.703125 -344.250000 -0.009121 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304784 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629489 0.346185 0.000000 -0.019038 0.010575 -0.034462 0.046586 0.185975 0.078975 0.138201 0.169049 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.943298 0.000076 0.007193 -0.944584 -0.005257 0.000335 0.007330 -40.921875 144.703125 -344.250000 -0.009122 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304352 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629480 0.346176 0.000000 -0.018865 0.010571 -0.034462 0.046583 0.185806 0.079152 0.138023 0.169218 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.948303 0.001297 0.004508 -0.948246 -0.005257 0.000335 0.006266 -39.785156 138.960938 -347.835938 -0.009123 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303928 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629537 0.346173 0.000000 -0.018870 0.010567 -0.034146 0.046582 0.185499 0.079467 0.138341 0.168893 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.953308 0.003494 0.005484 -0.943851 -0.005257 0.001399 0.006266 -39.785156 138.960938 -347.835938 -0.009123 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629960 0.346132 0.000000 -0.019045 0.010563 -0.034146 0.046587 0.185678 0.079295 0.138512 0.168714 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.958313 -0.000656 0.003775 -0.940189 -0.004193 0.002463 0.006266 -34.101562 137.812500 -341.859375 -0.009117 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303105 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630737 0.345990 0.000000 -0.019216 0.010397 -0.034146 0.046598 0.187185 0.080461 0.139686 0.169547 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.963318 0.001297 0.007682 -0.943607 -0.004193 0.001399 0.006266 -34.101562 137.812500 -341.859375 -0.009108 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302707 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631171 0.345473 0.000000 -0.019043 0.010394 -0.034146 0.046605 0.187015 0.080637 0.139511 0.169718 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.968323 0.001541 0.004996 -0.942386 -0.004193 0.001399 0.005202 -42.058594 141.257812 -347.835938 -0.009099 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302316 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631559 0.344930 0.000000 -0.019047 0.010389 -0.033830 0.046611 0.186707 0.080954 0.139826 0.169393 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.973328 0.003250 0.005484 -0.942142 -0.005257 0.001399 0.006266 -42.058594 141.257812 -347.835938 -0.009095 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301933 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631941 0.344693 0.000000 -0.019051 0.010552 -0.034146 0.046617 0.186865 0.080471 0.139677 0.169867 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.978333 0.002518 0.006949 -0.942875 -0.004193 0.000335 0.006266 -40.921875 144.703125 -344.250000 -0.009085 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301558 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632059 0.344136 0.000000 -0.018889 0.010369 -0.034146 0.046620 0.191546 0.085476 0.143992 0.174507 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.983337 0.003006 0.007437 -0.944584 -0.004193 0.001399 0.005202 -40.921875 144.703125 -344.250000 -0.009076 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301191 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632588 0.343646 0.000000 -0.019074 0.010364 -0.033830 0.046629 0.191420 0.085611 0.144489 0.174000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.988342 0.002029 0.004508 -0.944095 -0.005257 0.002463 0.006266 -40.921875 137.812500 -344.250000 -0.009073 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300830 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633516 0.343558 0.000000 -0.019255 0.010530 -0.034146 0.046645 0.191752 0.084949 0.144519 0.174301 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.993347 0.002518 0.004996 -0.945560 -0.003128 0.001399 0.005202 -40.921875 137.812500 -344.250000 -0.009060 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300478 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634177 0.342867 0.000000 -0.019094 0.010182 -0.033830 0.046658 0.191622 0.085774 0.144326 0.173798 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+453.998352 0.002273 0.006461 -0.943363 -0.003128 0.000335 0.005202 -40.921875 137.812500 -344.250000 -0.009046 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300132 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634570 0.342191 0.000000 -0.018943 0.010185 -0.033830 0.046666 0.191468 0.085921 0.144179 0.173952 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.003357 0.000076 0.004752 -0.941166 -0.004193 0.000335 0.006266 -45.468750 140.109375 -339.468750 -0.009038 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299793 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634978 0.341536 0.000000 -0.018968 0.010346 -0.035921 0.046675 0.200423 0.090644 0.149273 0.183180 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.008362 0.000809 0.006217 -0.937504 -0.004193 0.000335 0.007330 -45.468750 140.109375 -339.468750 -0.009030 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299461 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635320 0.341168 0.000000 -0.018989 0.010338 -0.036237 0.046683 0.200768 0.090315 0.148970 0.183466 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.013367 0.000809 0.003775 -0.941166 -0.005257 0.000335 0.006266 -42.058594 145.851562 -343.054688 -0.009026 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299538 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635536 0.341082 0.000000 -0.019005 0.010498 -0.035921 0.046689 0.200309 0.090455 0.149462 0.183294 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.018372 0.003738 0.005240 -0.938236 -0.003128 0.001399 0.007330 -42.058594 145.851562 -343.054688 -0.009010 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299613 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635970 0.340297 0.000000 -0.019186 0.010142 -0.036237 0.046699 0.201161 0.090314 0.148972 0.183073 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.023376 0.002273 0.004508 -0.940189 -0.003128 0.001399 0.006266 -44.332031 143.554688 -345.445312 -0.008993 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299686 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636366 0.339758 0.000000 -0.019190 0.010145 -0.035906 0.046708 0.204341 0.094148 0.152820 0.186251 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.028381 0.000320 0.011832 -0.942875 -0.005257 0.001399 0.005202 -44.332031 143.554688 -345.445312 -0.008987 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299757 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636752 0.339579 0.000000 -0.019195 0.010476 -0.035590 0.046718 0.203699 0.094129 0.153471 0.186261 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.033386 0.002029 0.004752 -0.939701 -0.005257 0.000335 0.007330 -35.238281 148.148438 -340.664062 -0.008983 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299826 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636795 0.339538 0.000000 -0.019031 0.010459 -0.036222 0.046721 0.204184 0.093678 0.152658 0.187040 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.038391 -0.005295 0.010367 -0.947757 -0.007385 0.003528 0.012651 -35.238281 148.148438 -340.664062 -0.008993 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299894 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637676 0.340310 0.000000 -0.019546 0.010788 -0.037802 0.046739 0.205951 0.091254 0.151921 0.188434 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.043396 0.011062 0.000602 -0.959232 -0.005257 0.000335 0.011587 -36.375000 156.187500 -337.078125 -0.008995 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299959 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637456 0.340562 0.000000 -0.019023 0.010433 -0.037486 0.046738 0.205467 0.092447 0.151360 0.188286 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.048401 -0.007492 0.015250 -0.940433 0.002193 0.000335 0.010523 -36.375000 156.187500 -337.078125 -0.008962 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300023 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637226 0.338736 0.000000 -0.019030 0.009255 -0.037186 0.046737 0.212181 0.099750 0.156319 0.192630 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.053406 0.005447 0.009635 -0.924808 -0.010578 -0.001794 0.000945 -30.691406 152.742188 -333.492188 -0.008997 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300086 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636305 0.341014 0.000000 -0.018695 0.011339 -0.034341 0.046724 0.206917 0.100846 0.160913 0.192205 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.058411 0.003494 0.020621 -0.933109 -0.002064 0.002463 -0.012890 -30.691406 152.742188 -333.492188 -0.008999 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300148 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636636 0.341191 0.000000 -0.019384 0.009973 -0.030232 0.046731 0.204863 0.105632 0.164345 0.186041 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.063416 -0.007736 -0.003305 -0.962406 -0.009514 -0.003922 -0.029918 -36.375000 158.484375 -337.078125 -0.009047 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300208 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635030 0.344088 0.000000 -0.018353 0.011216 -0.025175 0.046706 0.197532 0.110477 0.169614 0.183257 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.068420 0.002518 0.020377 -0.949711 -0.002064 -0.006050 -0.043753 -36.375000 158.484375 -337.078125 -0.009064 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300267 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632679 0.344992 0.000000 -0.018033 0.010053 -0.021066 0.046666 0.200096 0.121899 0.178070 0.184136 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.073425 0.006424 0.003775 -0.931400 -0.006321 -0.004986 -0.053331 -35.238281 164.226562 -335.882812 -0.009107 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300324 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630635 0.347378 0.000000 -0.018223 0.010806 -0.018221 0.046629 0.196688 0.123800 0.181858 0.181854 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.078430 -0.003342 0.015738 -0.941166 -0.006321 0.002463 -0.052267 -35.238281 164.226562 -335.882812 -0.009153 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300381 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630925 0.349881 0.000000 -0.019414 0.010857 -0.018537 0.046631 0.198144 0.122241 0.182785 0.181030 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.083435 0.017410 -0.013314 -0.956546 -0.005257 -0.002858 -0.037367 -34.101562 165.375000 -337.078125 -0.009193 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300436 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629874 0.351867 0.000000 -0.018535 0.010737 -0.022962 0.046610 0.201811 0.118815 0.177360 0.186214 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.088440 0.002518 -0.008188 -0.945072 -0.001000 -0.000729 -0.015019 -34.101562 165.375000 -337.078125 -0.009198 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300490 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630059 0.351723 0.000000 -0.018893 0.010091 -0.029600 0.046610 0.211791 0.114806 0.172775 0.194188 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.093445 0.009109 -0.004281 -0.941654 -0.004193 0.000335 0.005202 -35.238281 159.632812 -333.492188 -0.009195 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300544 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631208 0.351174 0.000000 -0.019086 0.010613 -0.035605 0.046626 0.217468 0.108087 0.167483 0.200522 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.098450 0.014725 -0.010141 -0.933109 0.002193 0.007785 0.035000 -35.238281 159.632812 -333.492188 -0.009134 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635234 0.347270 0.000000 -0.020307 0.009544 -0.044455 0.046693 0.228608 0.099084 0.158785 0.207082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.103455 -0.020676 0.006217 -0.956791 -0.008450 0.008849 0.054156 -35.238281 159.632812 -333.492188 -0.009103 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300648 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639850 0.345301 0.000000 -0.020483 0.011177 -0.050145 0.046773 0.232840 0.091585 0.154906 0.214229 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.108459 0.017166 -0.007211 -0.943851 -0.001000 0.002463 0.070119 -34.101562 156.187500 -339.468750 -0.009016 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300699 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.642322 0.340212 0.000000 -0.019477 0.009840 -0.054886 0.046820 0.237913 0.089188 0.147821 0.218639 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.113464 -0.003830 0.004996 -0.935550 -0.004193 0.006720 0.078633 -34.101562 156.187500 -339.468750 -0.008935 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300750 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645784 0.335330 0.000000 -0.020203 0.010220 -0.057414 0.046885 0.243108 0.087873 0.148718 0.223141 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.118469 0.005203 0.004752 -0.940433 -0.003128 0.016298 0.086083 -42.058594 155.039062 -335.882812 -0.008843 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300799 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.651753 0.330375 0.000000 -0.021743 0.009907 -0.059627 0.046996 0.247172 0.084433 0.147733 0.223501 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.123474 -0.006760 0.009146 -0.956791 -0.002064 0.002463 0.086083 -42.058594 155.039062 -335.882812 -0.008750 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300848 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.653061 0.325546 0.000000 -0.019503 0.009615 -0.059627 0.047031 0.245226 0.086965 0.145201 0.225448 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.128479 -0.000900 0.018424 -0.919925 -0.001000 0.001399 0.085019 -37.511719 150.445312 -340.664062 -0.008664 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300896 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.653530 0.321349 0.000000 -0.019377 0.009355 -0.059311 0.047053 0.245043 0.087667 0.145131 0.224998 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.133484 -0.003830 0.007437 -0.922123 -0.006321 0.006720 0.074376 -37.511719 150.445312 -340.664062 -0.008625 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300942 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.654925 0.320340 0.000000 -0.020249 0.010160 -0.056150 0.047090 0.243119 0.090320 0.151140 0.222941 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.138489 -0.007248 0.010367 -0.947025 -0.004193 0.005656 0.061606 -42.058594 148.148438 -333.492188 -0.008597 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300988 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.655246 0.319629 0.000000 -0.020051 0.009776 -0.052357 0.047109 0.239512 0.094695 0.154351 0.218962 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.143494 0.000564 0.017203 -0.953129 -0.010578 0.001399 0.046706 -42.058594 148.148438 -333.492188 -0.008620 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301031 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.653600 0.321940 0.000000 -0.019337 0.010796 -0.047932 0.047093 0.233353 0.098815 0.159081 0.216271 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.148499 0.005936 0.011588 -0.939701 -0.005257 -0.000729 0.024358 -37.511719 155.039062 -331.101562 -0.008637 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301072 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650973 0.323703 0.000000 -0.018976 0.009953 -0.041294 0.047059 0.227198 0.106657 0.164514 0.209151 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.153503 0.004471 0.025992 -0.933841 0.001128 0.003528 0.003073 -37.511719 155.039062 -331.101562 -0.008643 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301112 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649704 0.324692 0.000000 -0.019640 0.009015 -0.034973 0.047045 0.222479 0.113252 0.170562 0.201227 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.158508 -0.001145 0.000846 -0.944339 -0.001000 -0.000729 -0.017147 -30.691406 157.335938 -338.273438 -0.008679 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301150 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.647454 0.327056 0.000000 -0.018929 0.009488 -0.028968 0.047013 0.222289 0.126495 0.183330 0.203406 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.163513 0.003494 0.007682 -0.945316 -0.008450 -0.003922 -0.041624 -30.691406 157.335938 -338.273438 -0.008762 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301187 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.644606 0.332338 0.000000 -0.018422 0.010806 -0.021698 0.046968 0.213194 0.132955 0.191410 0.197962 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.168518 -0.002854 0.004996 -0.941654 -0.005257 -0.006050 -0.055459 -31.828125 156.187500 -339.468750 -0.008830 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301223 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641488 0.336416 0.000000 -0.018105 0.010379 -0.017589 0.046916 0.209195 0.137807 0.194776 0.193743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.173523 -0.001145 0.005240 -0.944339 -0.007385 -0.003922 -0.081001 -31.828125 156.187500 -339.468750 -0.008903 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301257 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639203 0.340596 0.000000 -0.018471 0.010808 -0.010003 0.046876 0.201545 0.144598 0.203156 0.186221 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.178528 0.004715 0.011100 -0.953617 -0.002064 -0.010307 -0.094836 -39.785156 161.929688 -340.664062 -0.008941 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301290 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635188 0.342549 0.000000 -0.017463 0.010025 -0.005894 0.046804 0.206552 0.159838 0.214814 0.191676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.183533 -0.001877 0.004996 -0.935795 -0.004193 -0.011372 -0.103349 -39.785156 161.929688 -340.664062 -0.008983 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301323 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631159 0.344603 0.000000 -0.017337 0.010443 -0.003365 0.046730 0.203479 0.162074 0.217635 0.189692 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.188538 0.007156 0.004020 -0.945072 -0.006321 -0.006050 -0.101221 -36.375000 151.593750 -334.687500 -0.009026 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301354 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629048 0.346703 0.000000 -0.018222 0.010828 -0.003998 0.046684 0.204612 0.160172 0.218272 0.189823 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.193542 0.005203 -0.000375 -0.949711 -0.006321 -0.004986 -0.091643 -36.375000 151.593750 -334.687500 -0.009059 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301386 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627644 0.348076 0.000000 -0.018396 0.010841 -0.006842 0.046650 0.207617 0.157141 0.215614 0.192507 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.198547 0.001053 -0.010385 -0.950199 0.001128 -0.010307 -0.073551 -30.691406 164.226562 -333.492188 -0.009038 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301417 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625139 0.346295 0.000000 -0.017557 0.009645 -0.012216 0.046597 0.218007 0.158463 0.212866 0.202184 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.203552 -0.002854 0.021598 -0.943363 -0.002064 -0.003922 -0.053331 -30.691406 164.226562 -333.492188 -0.009017 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301448 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624864 0.344635 0.000000 -0.018612 0.010159 -0.018221 0.046580 0.224554 0.150887 0.208431 0.207648 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.208557 0.006180 0.008658 -0.940677 -0.004193 0.000335 -0.034175 -30.691406 164.226562 -333.492188 -0.009001 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301479 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625906 0.343350 0.000000 -0.019284 0.010469 -0.023910 0.046586 0.230606 0.144217 0.203722 0.212975 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.213562 -0.002609 0.006461 -0.948490 -0.008450 0.000335 -0.019276 -32.964844 168.820312 -326.320312 -0.009007 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301511 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626900 0.343485 0.000000 -0.019254 0.011106 -0.028335 0.046593 0.234364 0.139184 0.199905 0.218067 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.218567 0.009109 0.013297 -0.957767 -0.007385 0.002463 -0.001184 -32.964844 168.820312 -326.320312 -0.009012 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302547 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628501 0.343541 0.000000 -0.019569 0.010882 -0.033709 0.046612 0.240275 0.133720 0.194623 0.222902 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.223572 0.004471 0.001090 -0.958988 -0.003128 0.003528 0.022229 -27.281250 167.671875 -332.296875 -0.009000 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303563 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630152 0.342952 0.000000 -0.019701 0.010184 -0.040647 0.046640 0.251554 0.130858 0.190628 0.232520 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.228577 -0.007248 0.019645 -0.954593 -0.007385 0.007785 0.045642 -27.281250 167.671875 -332.296875 -0.009015 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304560 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633446 0.343686 0.000000 -0.020355 0.010868 -0.047601 0.046691 0.258478 0.122566 0.185013 0.239503 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.233582 0.002518 -0.007455 -0.936527 -0.006321 0.004592 0.062670 -34.101562 167.671875 -329.906250 -0.009030 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305539 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635495 0.344361 0.000000 -0.019804 0.010688 -0.052658 0.046725 0.263164 0.118240 0.179225 0.244932 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.238586 -0.002121 0.021109 -0.928226 -0.006321 0.006720 0.077569 -34.101562 167.671875 -329.906250 -0.009047 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306499 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637815 0.345161 0.000000 -0.020121 0.010692 -0.057083 0.046764 0.267901 0.113494 0.175120 0.249045 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.243591 0.000320 0.008414 -0.948978 -0.004193 0.009913 0.086083 -34.101562 160.781250 -337.078125 -0.009058 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307441 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641034 0.345287 0.000000 -0.020602 0.010359 -0.059627 0.046815 0.271249 0.110792 0.172714 0.250764 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.248596 0.005447 0.013541 -0.949466 -0.006321 0.004592 0.091404 -34.101562 160.781250 -337.078125 -0.009087 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641986 0.346763 0.000000 -0.019704 0.010738 -0.061207 0.046836 0.271553 0.109731 0.170614 0.253621 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.253601 -0.002121 0.010611 -0.939701 -0.003128 0.010977 0.088211 -31.828125 160.781250 -337.078125 -0.009107 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309272 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.644681 0.347674 0.000000 -0.020705 0.010269 -0.060259 0.046887 0.272076 0.110147 0.172095 0.251202 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.258606 0.001541 0.006949 -0.943363 -0.007385 0.006720 0.082890 -31.828125 160.781250 -337.078125 -0.009154 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310161 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645914 0.350143 0.000000 -0.019980 0.011012 -0.058679 0.046915 0.269026 0.111710 0.173693 0.251091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.263611 0.002762 0.001334 -0.945072 -0.001000 0.008849 0.072248 -34.101562 160.781250 -339.468750 -0.009170 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.647653 0.350691 0.000000 -0.020303 0.010037 -0.055518 0.046952 0.267164 0.115523 0.176202 0.246632 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.268616 0.001541 0.004020 -0.941166 -0.004193 0.004592 0.063734 -34.101562 160.781250 -339.468750 -0.009198 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311885 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648089 0.351890 0.000000 -0.019605 0.010613 -0.052989 0.046967 0.263361 0.118173 0.178608 0.245378 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.273621 0.000564 0.000357 -0.937748 -0.006321 0.004592 0.048835 -34.101562 160.781250 -337.078125 -0.009226 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312722 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648551 0.353151 0.000000 -0.019616 0.010978 -0.048564 0.046983 0.258582 0.122222 0.183410 0.241307 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.278625 0.000320 0.004508 -0.940677 -0.004193 0.005656 0.035000 -34.101562 160.781250 -337.078125 -0.009233 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313542 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649314 0.353107 0.000000 -0.019796 0.010635 -0.044455 0.047004 0.254996 0.126495 0.187355 0.236674 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.283630 0.003738 0.002555 -0.945804 -0.005257 0.001399 0.016908 -34.101562 165.375000 -334.687500 -0.009235 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314345 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648795 0.352777 0.000000 -0.019124 0.010794 -0.039082 0.047003 0.248792 0.132379 0.192217 0.232132 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.288635 0.000320 0.006949 -0.946537 -0.001000 0.001399 -0.002248 -34.101562 165.375000 -334.687500 -0.009207 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315131 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648348 0.350736 0.000000 -0.019157 0.010089 -0.033393 0.047003 0.243841 0.138742 0.197232 0.225705 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.293640 -0.002121 0.008658 -0.939945 -0.007385 -0.002858 -0.020340 -35.238281 159.632812 -340.664062 -0.009206 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315901 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646670 0.350412 0.000000 -0.018508 0.011092 -0.028019 0.046980 0.236816 0.143761 0.202961 0.221983 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.298645 0.003738 0.010367 -0.941166 -0.004193 -0.004986 -0.039496 -35.238281 159.632812 -340.664062 -0.009189 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316656 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.644382 0.349186 0.000000 -0.018217 0.010533 -0.022330 0.046946 0.231394 0.150299 0.207801 0.216026 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.303650 0.003494 0.009879 -0.950687 -0.001000 -0.001794 -0.054395 -30.691406 166.523438 -333.492188 -0.009160 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317395 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.643157 0.347349 0.000000 -0.018775 0.010008 -0.017905 0.046927 0.228052 0.154692 0.212258 0.210518 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.308655 -0.000412 0.012076 -0.947513 -0.006321 -0.006050 -0.065037 -30.691406 166.523438 -333.492188 -0.009165 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318119 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640823 0.347591 0.000000 -0.018122 0.010866 -0.014744 0.046889 0.224551 0.158817 0.216794 0.210038 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.313660 0.005691 0.009879 -0.940921 -0.003128 -0.004986 -0.068230 -30.691406 166.523438 -333.492188 -0.009163 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318829 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639026 0.347391 0.000000 -0.018339 0.010351 -0.013796 0.046857 0.224333 0.160064 0.217444 0.208359 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.318665 0.006424 0.004996 -0.940433 -0.004193 -0.003922 -0.067166 -29.554688 158.484375 -334.687500 -0.009173 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319524 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637851 0.347954 0.000000 -0.018545 0.010548 -0.014112 0.046835 0.224659 0.159345 0.217530 0.208665 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.323669 0.003982 0.008414 -0.947513 -0.004193 -0.003922 -0.059716 -29.554688 158.484375 -334.687500 -0.009187 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320205 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637084 0.348737 0.000000 -0.018579 0.010573 -0.016325 0.046819 0.226880 0.157074 0.215377 0.210869 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.328674 0.003250 0.012320 -0.941410 -0.005257 -0.006050 -0.049074 -35.238281 168.820312 -333.492188 -0.009210 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320873 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636073 0.349973 0.000000 -0.018279 0.010772 -0.019485 0.046798 0.229543 0.154014 0.212115 0.214528 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.333679 0.000320 0.007926 -0.945804 -0.004193 -0.006050 -0.038432 -35.238281 168.820312 -333.492188 -0.009231 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321528 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635335 0.351344 0.000000 -0.018332 0.010639 -0.022646 0.046781 0.237558 0.155603 0.213545 0.222174 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.338684 0.000076 0.010367 -0.929447 -0.006321 -0.001794 -0.023532 -32.964844 159.632812 -326.320312 -0.009265 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322169 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635929 0.353167 0.000000 -0.019053 0.011016 -0.027071 0.046786 0.242328 0.150079 0.210219 0.226254 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.343689 0.000076 0.006217 -0.945804 -0.004193 0.000335 -0.007569 -32.964844 159.632812 -326.320312 -0.009290 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322797 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637001 0.354377 0.000000 -0.019401 0.010706 -0.031812 0.046801 0.247728 0.145301 0.205515 0.230337 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.348694 -0.011887 0.009146 -0.955082 -0.006321 0.003528 0.010523 -28.417969 164.226562 -331.101562 -0.009325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638597 0.356159 0.000000 -0.019894 0.011085 -0.037186 0.046825 0.253215 0.139056 0.201013 0.235596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.353699 -0.002854 -0.005746 -0.944828 -0.001000 0.003528 0.026486 -28.417969 164.226562 -331.101562 -0.009330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324016 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639438 0.356073 0.000000 -0.019844 0.010259 -0.041927 0.046839 0.259891 0.136351 0.196556 0.240722 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.358704 0.007889 0.004508 -0.936039 -0.004193 0.004592 0.043514 -29.554688 167.671875 -332.296875 -0.009341 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324607 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639956 0.356382 0.000000 -0.019952 0.010801 -0.046984 0.046847 0.264515 0.130643 0.192150 0.246213 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.363708 0.003494 -0.001352 -0.939701 -0.006321 0.007785 0.054156 -29.554688 167.671875 -332.296875 -0.009350 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325186 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641198 0.356581 0.000000 -0.020394 0.011128 -0.050145 0.046868 0.267791 0.126713 0.189758 0.249259 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.368713 0.004471 0.003043 -0.942630 -0.004193 0.002463 0.063734 -32.964844 171.117188 -338.273438 -0.009336 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325753 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640956 0.355416 0.000000 -0.019478 0.010745 -0.052989 0.046865 0.270102 0.125167 0.185614 0.252636 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.373718 0.004959 0.007926 -0.950443 -0.002064 0.004592 0.063734 -32.964844 171.117188 -338.273438 -0.009301 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326309 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641645 0.353118 0.000000 -0.019797 0.010362 -0.052989 0.046878 0.270804 0.125232 0.185550 0.251935 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.378723 0.001297 0.012320 -0.947025 -0.005257 0.008849 0.061606 -27.281250 174.562500 -332.296875 -0.009279 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326854 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.643892 0.351380 0.000000 -0.020453 0.010824 -0.052357 0.046917 0.270366 0.124746 0.187300 0.251108 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.383728 -0.013596 -0.003305 -0.952152 -0.005257 0.007785 0.054156 -27.281250 174.562500 -332.296875 -0.009257 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327387 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645777 0.350045 0.000000 -0.020246 0.010769 -0.050145 0.046952 0.268001 0.127221 0.189250 0.249048 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.388733 0.000809 0.001822 -0.939701 -0.001000 0.003528 0.045642 -28.417969 168.820312 -326.320312 -0.009212 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327911 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645981 0.347436 0.000000 -0.019537 0.010039 -0.047616 0.046960 0.265494 0.131188 0.190340 0.246498 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.393738 0.000809 0.010367 -0.930423 -0.006321 0.005656 0.033936 -28.417969 168.820312 -326.320312 -0.009191 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328423 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.646400 0.346397 0.000000 -0.019862 0.010855 -0.044139 0.046972 0.261526 0.133523 0.194959 0.243512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.398743 0.012527 0.010367 -0.938480 -0.006321 0.000335 0.022229 -30.691406 166.523438 -328.710938 -0.009174 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328926 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.644800 0.345844 0.000000 -0.018980 0.010806 -0.040647 0.046955 0.257212 0.137957 0.197529 0.240863 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.403748 0.001297 0.010367 -0.943119 -0.007385 -0.003922 0.009459 -30.691406 166.523438 -328.710938 -0.009168 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329419 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.642671 0.345750 0.000000 -0.018323 0.010934 -0.036854 0.046922 0.252633 0.142279 0.200793 0.237855 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.408752 0.009598 0.015982 -0.943607 -0.004193 -0.002858 -0.005441 -35.238281 164.226562 -333.492188 -0.009158 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329901 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641426 0.345337 0.000000 -0.018546 0.010402 -0.032429 0.046902 0.248963 0.147013 0.204909 0.232675 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.413757 -0.003098 0.008414 -0.943363 -0.003128 0.001399 -0.017147 -35.238281 164.226562 -333.492188 -0.009155 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330373 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641931 0.345378 0.000000 -0.019273 0.010254 -0.028952 0.046911 0.246361 0.149911 0.208964 0.228323 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.418762 -0.006271 0.004752 -0.945316 -0.009514 -0.003922 -0.019276 -35.238281 164.226562 -333.492188 -0.009193 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330836 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641365 0.347874 0.000000 -0.018461 0.011310 -0.028320 0.046895 0.243861 0.150298 0.209841 0.229559 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.423767 0.006424 0.002311 -0.936527 -0.001000 -0.000729 -0.023532 -30.691406 161.929688 -335.882812 -0.009194 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329881 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641285 0.347975 0.000000 -0.019017 0.009966 -0.027056 0.046893 0.244497 0.152351 0.210317 0.226395 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.428772 0.013260 0.014273 -0.948734 -0.009514 -0.000729 -0.022468 -30.691406 161.929688 -335.882812 -0.009238 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328946 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641275 0.350595 0.000000 -0.019041 0.011382 -0.027372 0.046893 0.243421 0.150596 0.211440 0.228103 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.433777 -0.004563 0.012076 -0.938724 -0.009514 -0.006050 -0.022468 -37.511719 157.335938 -333.492188 -0.009283 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328029 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639998 0.353207 0.000000 -0.018225 0.011391 -0.027372 0.046871 0.242597 0.151402 0.210634 0.228927 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.438782 -0.001145 0.010367 -0.944584 -0.005257 0.000335 -0.023532 -37.511719 157.335938 -333.492188 -0.009312 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327131 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640748 0.354707 0.000000 -0.019301 0.010736 -0.027056 0.046882 0.244010 0.151297 0.211371 0.226882 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.443787 -0.005783 0.007682 -0.954105 0.002193 0.001399 -0.020340 -32.964844 157.335938 -333.492188 -0.009307 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326250 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641526 0.354187 0.000000 -0.019475 0.009611 -0.028019 0.046895 0.246263 0.151274 0.209447 0.226535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.448792 -0.008713 -0.004281 -0.934330 -0.007385 -0.000729 -0.010762 -32.964844 157.335938 -333.492188 -0.009349 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325387 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641118 0.356454 0.000000 -0.019121 0.011229 -0.030864 0.046888 0.247136 0.147165 0.207867 0.231352 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.453796 -0.001633 0.004020 -0.924808 -0.005257 -0.000729 -0.009697 -30.691406 155.039062 -338.273438 -0.009373 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324541 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640000 0.357521 0.000000 -0.019099 0.010904 -0.031180 0.046868 0.247754 0.147197 0.207203 0.231366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.458801 0.019119 0.003287 -0.948978 -0.001000 0.002463 -0.008633 -30.691406 155.039062 -338.273438 -0.009364 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323712 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639481 0.356669 0.000000 -0.019571 0.010238 -0.031496 0.046858 0.249210 0.147074 0.206693 0.230543 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.463806 0.002029 0.012809 -0.938236 -0.007385 0.001399 -0.005441 -34.101562 163.078125 -339.468750 -0.009379 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322898 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638931 0.357261 0.000000 -0.019358 0.011272 -0.032444 0.046847 0.247750 0.144146 0.205406 0.231579 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.468811 -0.007492 0.004020 -0.951908 -0.005257 0.001399 0.003073 -34.101562 163.078125 -339.468750 -0.009379 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322101 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638781 0.356968 0.000000 -0.019336 0.010904 -0.034973 0.046843 0.250624 0.142007 0.202487 0.233762 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.473816 -0.001145 0.007437 -0.955326 0.000064 -0.000729 0.006266 -34.101562 156.187500 -329.906250 -0.009350 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321320 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638033 0.355032 0.000000 -0.018978 0.010044 -0.035921 0.046828 0.252076 0.142277 0.200321 0.234207 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.478821 0.008621 -0.006234 -0.938480 0.001128 0.001399 0.015844 -34.101562 156.187500 -329.906250 -0.009312 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320554 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637930 0.352678 0.000000 -0.019311 0.009886 -0.038766 0.046824 0.255411 0.139257 0.197652 0.236561 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.483826 0.003250 0.017936 -0.933109 -0.010578 0.005656 0.025422 -36.375000 163.078125 -334.687500 -0.009328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319803 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639281 0.353607 0.000000 -0.019974 0.011749 -0.041611 0.046845 0.257056 0.133886 0.197333 0.240605 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.488831 0.000320 0.004020 -0.954593 -0.003128 0.005656 0.027550 -36.375000 163.078125 -334.687500 -0.009307 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319068 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640818 0.351981 0.000000 -0.019945 0.010484 -0.042243 0.046870 0.258914 0.134538 0.195397 0.239992 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.493835 0.016434 0.015738 -0.951908 0.001128 -0.002858 0.032872 -38.648438 158.484375 -341.859375 -0.009268 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318347 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640148 0.349728 0.000000 -0.018582 0.009799 -0.043823 0.046858 0.259817 0.135006 0.191768 0.242249 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.498840 0.005203 -0.001840 -0.931888 -0.005257 0.001399 0.042450 -38.648438 158.484375 -341.859375 -0.009267 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317642 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641403 0.349755 0.000000 -0.019323 0.010836 -0.046668 0.046879 0.262365 0.130384 0.190701 0.245391 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.503845 -0.028244 0.006217 -0.946781 -0.018028 0.003528 0.042450 -32.964844 166.523438 -338.273438 -0.009330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316950 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.643437 0.353608 0.000000 -0.019698 0.012844 -0.046668 0.046915 0.260732 0.128000 0.193085 0.247024 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.508850 0.025711 0.003531 -0.952640 0.004321 0.000335 0.042450 -32.964844 166.523438 -338.273438 -0.009281 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316273 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.644086 0.350924 0.000000 -0.019204 0.009209 -0.046668 0.046928 0.263883 0.132139 0.188965 0.243892 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.513855 0.003738 0.010855 -0.950931 -0.003128 0.003528 0.037128 -35.238281 164.226562 -338.273438 -0.009268 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315610 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645607 0.350240 0.000000 -0.019744 0.010448 -0.045087 0.046957 0.261603 0.131940 0.192325 0.243012 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.518860 -0.013352 -0.002572 -0.927982 -0.007385 -0.000729 0.029679 -35.238281 164.226562 -338.273438 -0.009276 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314961 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645888 0.350778 0.000000 -0.019082 0.011121 -0.042875 0.046965 0.258056 0.134142 0.194548 0.242134 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.523865 0.007400 0.035025 -0.938236 -0.001000 0.012041 0.020101 -35.238281 164.226562 -338.273438 -0.009255 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315330 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.649598 0.349590 0.000000 -0.021141 0.010083 -0.040030 0.047032 0.258308 0.135966 0.198413 0.236192 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.528870 0.011551 0.002555 -0.958988 -0.013771 0.002463 0.014780 -35.238281 161.929688 -333.492188 -0.009308 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315692 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.650158 0.352875 0.000000 -0.019567 0.012148 -0.038435 0.047048 0.253073 0.137071 0.200500 0.238236 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.533875 -0.005051 -0.004770 -0.936771 -0.002064 -0.010307 0.014780 -35.238281 161.929688 -333.492188 -0.009312 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316047 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.647100 0.353043 0.000000 -0.017561 0.010260 -0.038435 0.047003 0.252956 0.140964 0.196607 0.238353 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.538879 -0.010666 0.017447 -0.936283 0.004321 0.003528 0.006266 -36.375000 160.781250 -334.687500 -0.009285 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316395 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.648105 0.351388 0.000000 -0.019851 0.009300 -0.035906 0.047023 0.253677 0.142163 0.200465 0.232575 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.543884 -0.010910 0.001578 -0.931644 -0.021220 0.001399 -0.005441 -36.375000 160.781250 -334.687500 -0.009385 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316736 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.647733 0.357317 0.000000 -0.019485 0.013441 -0.032429 0.047021 0.245693 0.141865 0.207717 0.233606 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.548889 0.005447 0.016715 -0.956302 0.000064 -0.001794 -0.017147 -36.375000 158.484375 -334.687500 -0.009380 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317069 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.645603 0.356750 0.000000 -0.018941 0.009983 -0.028952 0.046989 0.245130 0.149344 0.207191 0.227215 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.553894 0.015457 -0.005258 -0.951175 0.010706 0.000335 -0.019276 -36.375000 158.484375 -334.687500 -0.009322 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317396 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.643902 0.352816 0.000000 -0.019254 0.008355 -0.028335 0.046961 0.246454 0.151276 0.206493 0.224657 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.558899 -0.019699 -0.005502 -0.948002 -0.021220 -0.008179 -0.018211 -32.964844 161.929688 -331.101562 -0.009415 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317716 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639862 0.358315 0.000000 -0.017865 0.013537 -0.028651 0.046893 0.240200 0.147167 0.209970 0.231543 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.563904 0.022293 0.016959 -0.929935 0.006450 0.003528 -0.019276 -32.964844 161.929688 -331.101562 -0.009360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318030 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639517 0.354760 0.000000 -0.019740 0.009023 -0.028335 0.046884 0.246272 0.150121 0.207648 0.224839 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.568909 0.000809 -0.002328 -0.941654 -0.002064 0.001399 -0.020340 -30.691406 152.742188 -333.492188 -0.009340 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318337 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638936 0.353501 0.000000 -0.019349 0.010433 -0.028019 0.046871 0.244155 0.149418 0.208983 0.226323 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.573914 -0.007492 0.002066 -0.935550 -0.018028 -0.008179 -0.018211 -30.691406 152.742188 -333.492188 -0.009393 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318638 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636037 0.356595 0.000000 -0.017809 0.012948 -0.028651 0.046818 0.241893 0.148971 0.210486 0.232170 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.578918 -0.007248 0.006949 -0.941898 0.010706 0.003528 -0.018211 -32.964844 155.039062 -333.492188 -0.009297 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318933 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636702 0.350708 0.000000 -0.019708 0.008258 -0.028651 0.046823 0.248482 0.151763 0.207694 0.225581 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.583923 0.014725 0.013541 -0.961185 -0.008450 0.003528 -0.011826 -32.964844 155.039062 -333.492188 -0.009293 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319221 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637191 0.350642 0.000000 -0.019662 0.011361 -0.030548 0.046827 0.247230 0.146809 0.208855 0.230626 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.588928 -0.004074 0.000113 -0.950199 -0.010578 -0.009243 0.000945 -34.101562 160.781250 -334.687500 -0.009303 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319504 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634057 0.351304 0.000000 -0.017601 0.011629 -0.034341 0.046770 0.248692 0.144809 0.203269 0.236749 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.593933 -0.011643 0.005729 -0.944339 0.003257 0.004592 0.008394 -34.101562 160.781250 -334.687500 -0.009245 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319781 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635135 0.347957 0.000000 -0.019845 0.009361 -0.036553 0.046782 0.255417 0.142620 0.201033 0.234450 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.598938 0.006180 0.010611 -0.944828 -0.010578 0.001399 0.013715 -35.238281 161.929688 -335.882812 -0.009257 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320053 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634899 0.348930 0.000000 -0.019281 0.011582 -0.038134 0.046773 0.254212 0.139383 0.201109 0.238816 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.603943 0.001541 0.004264 -0.935795 -0.006321 0.000335 0.016908 -35.238281 161.929688 -335.882812 -0.009252 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320320 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634180 0.348783 0.000000 -0.019076 0.010844 -0.039082 0.046756 0.255694 0.139378 0.199219 0.239230 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.608948 -0.000656 0.009391 -0.940189 0.005385 0.004592 0.025422 -38.648438 153.890625 -332.296875 -0.009192 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320582 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634757 0.345432 0.000000 -0.019727 0.008965 -0.041611 0.046760 0.260753 0.138077 0.195462 0.239229 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.613953 -0.001633 -0.013314 -0.958988 -0.016963 -0.003922 0.035000 -38.648438 153.890625 -332.296875 -0.009243 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320838 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632812 0.348773 0.000000 -0.018327 0.012564 -0.044455 0.046723 0.258598 0.133034 0.194816 0.247073 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.618958 0.012527 0.008414 -0.951664 0.002193 0.001399 0.037128 -38.648438 156.187500 -334.687500 -0.009192 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632638 0.346194 0.000000 -0.019184 0.009423 -0.045087 0.046715 0.263228 0.134685 0.191900 0.243707 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.623962 -0.003830 0.026236 -0.958011 -0.001000 0.010977 0.031807 -38.648438 156.187500 -334.687500 -0.009155 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320937 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635553 0.344272 0.000000 -0.020688 0.009952 -0.043507 0.046759 0.262623 0.134232 0.195514 0.241151 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.628967 -0.006271 0.007682 -0.929935 -0.020156 -0.000729 0.031807 -38.648438 156.187500 -334.687500 -0.009222 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320786 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635017 0.348572 0.000000 -0.018762 0.013002 -0.043507 0.046747 0.257646 0.133109 0.196637 0.246128 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.633972 -0.013840 -0.011117 -0.938724 0.002193 -0.000729 0.025422 -30.691406 157.335938 -335.882812 -0.009186 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320640 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634173 0.346516 0.000000 -0.018768 0.009357 -0.041611 0.046730 0.259402 0.138644 0.194895 0.240579 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.638977 0.007889 -0.002084 -0.948734 -0.006321 0.008849 0.022229 -30.691406 157.335938 -335.882812 -0.009188 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320497 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635616 0.346526 0.000000 -0.020276 0.010751 -0.040662 0.046751 0.258568 0.136691 0.198745 0.239517 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.643982 0.015457 0.005484 -0.956058 -0.010578 -0.000729 0.024358 -35.238281 152.742188 -335.882812 -0.009201 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320358 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634070 0.347475 0.000000 -0.018681 0.011398 -0.041294 0.046723 0.256958 0.137007 0.197164 0.242391 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.648987 0.000564 0.028434 -0.949222 0.006450 0.000335 0.015844 -35.238281 152.742188 -335.882812 -0.009127 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320222 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633364 0.343235 0.000000 -0.018857 0.008638 -0.038766 0.046708 0.257365 0.142118 0.197110 0.236927 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.653992 -0.007492 -0.014047 -0.916263 -0.009514 -0.009243 0.002009 -36.375000 158.484375 -332.296875 -0.009138 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320090 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630268 0.344178 0.000000 -0.017347 0.011236 -0.034657 0.046652 0.249147 0.145140 0.202306 0.236926 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.658997 -0.009934 0.015494 -0.937504 -0.010578 0.004592 -0.009697 -36.375000 158.484375 -332.296875 -0.009156 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319960 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631280 0.345477 0.000000 -0.019606 0.011360 -0.031180 0.046664 0.247806 0.146234 0.208165 0.231314 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.664001 0.023514 0.009879 -0.963627 0.008578 0.007785 -0.011826 -35.238281 157.335938 -340.664062 -0.009081 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319833 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633017 0.341534 0.000000 -0.020073 0.008288 -0.030533 0.046689 0.250708 0.149497 0.206218 0.227137 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.669006 0.005203 -0.005746 -0.940433 -0.012706 -0.012436 -0.010762 -35.238281 157.335938 -340.664062 -0.009116 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319708 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629169 0.343927 0.000000 -0.016824 0.011755 -0.030849 0.046621 0.244308 0.148962 0.206120 0.234169 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.674011 -0.006271 0.016959 -0.931888 -0.007385 -0.004986 -0.011826 -38.648438 156.187500 -334.687500 -0.009124 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319586 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628286 0.344614 0.000000 -0.018116 0.010851 -0.030533 0.046600 0.246188 0.148890 0.206824 0.231657 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.679016 0.009598 0.006949 -0.950931 -0.003128 0.008849 -0.015019 -38.648438 156.187500 -334.687500 -0.009113 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319466 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631766 0.344160 0.000000 -0.020365 0.010164 -0.029585 0.046653 0.248176 0.148277 0.209334 0.227773 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.684021 -0.010422 -0.001107 -0.956546 -0.003128 -0.000729 -0.023532 -32.964844 159.632812 -338.273438 -0.009106 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319348 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632299 0.343590 0.000000 -0.018807 0.010177 -0.027071 0.046659 0.244081 0.152324 0.210294 0.226821 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.689026 0.002762 0.011832 -0.921634 0.008578 -0.002858 -0.020340 -32.964844 159.632812 -338.273438 -0.009040 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319232 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632005 0.339892 0.000000 -0.018496 0.008338 -0.028019 0.046652 0.246558 0.153527 0.207195 0.226241 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.694031 0.012039 -0.001107 -0.925296 -0.011642 -0.001794 -0.009697 -35.238281 155.039062 -340.664062 -0.009074 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319119 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631923 0.342249 0.000000 -0.018699 0.011633 -0.031180 0.046649 0.246626 0.146868 0.207531 0.232494 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.699036 -0.009934 0.026236 -0.944828 -0.005257 -0.003922 -0.008633 -35.238281 155.039062 -340.664062 -0.009078 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319007 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631240 0.342684 0.000000 -0.018384 0.010567 -0.031496 0.046635 0.247693 0.147934 0.205834 0.232059 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.704041 0.015457 0.008414 -0.959720 -0.005257 0.007785 -0.006505 -37.511719 152.742188 -340.664062 -0.009090 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318896 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634017 0.343574 0.000000 -0.020275 0.010578 -0.032128 0.046680 0.250205 0.145399 0.207104 0.230811 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.709045 -0.002365 0.013297 -0.964603 -0.010578 -0.003922 -0.000119 -37.511719 152.742188 -340.664062 -0.009140 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318787 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633345 0.346908 0.000000 -0.018377 0.011462 -0.034025 0.046668 0.249330 0.144526 0.204204 0.235500 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.714050 -0.001877 -0.000619 -0.929691 0.002193 -0.001794 0.008394 -36.375000 160.781250 -329.906250 -0.009133 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318680 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633430 0.346451 0.000000 -0.018759 0.009445 -0.036553 0.046669 0.254258 0.143632 0.200041 0.235629 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.719055 -0.012619 -0.014291 -0.947757 -0.003128 0.006720 0.013715 -36.375000 160.781250 -329.906250 -0.009149 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318575 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635697 0.347371 0.000000 -0.020127 0.010376 -0.038134 0.046707 0.256274 0.139753 0.200759 0.236773 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.724060 0.002762 0.029410 -0.943607 -0.013771 0.005656 0.019037 -37.511719 159.632812 -338.273438 -0.009208 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318472 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636929 0.350781 0.000000 -0.019902 0.012091 -0.039714 0.046729 0.255915 0.136683 0.200668 0.240293 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.729065 0.015213 0.009635 -0.934086 -0.003128 0.002463 0.026486 -37.511719 159.632812 -338.273438 -0.009212 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318372 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636847 0.350511 0.000000 -0.019346 0.010348 -0.041927 0.046730 0.259304 0.136759 0.196147 0.241309 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.734070 -0.000168 0.010367 -0.926517 0.003257 -0.006050 0.028615 -37.511719 159.632812 -338.273438 -0.009190 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318274 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634474 0.349001 0.000000 -0.017978 0.009377 -0.042559 0.046692 0.259540 0.138466 0.193176 0.242338 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.739075 -0.020676 0.008170 -0.943607 -0.015899 0.002463 0.031807 -36.375000 158.484375 -332.296875 -0.009268 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318177 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634747 0.353470 0.000000 -0.019368 0.012503 -0.043507 0.046697 0.258752 0.133002 0.196744 0.245022 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.744080 -0.001877 -0.017465 -0.952640 -0.019092 0.001399 0.032872 -36.375000 158.484375 -332.296875 -0.009358 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634117 0.358480 0.000000 -0.019159 0.012962 -0.043823 0.046687 0.258401 0.132436 0.196678 0.246005 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.749084 0.010086 0.007193 -0.935795 0.008578 0.005656 0.030743 -39.785156 157.335938 -331.101562 -0.009298 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317989 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634218 0.354678 0.000000 -0.019789 0.008503 -0.043191 0.046688 0.262867 0.136907 0.193491 0.240295 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.754089 0.009842 0.013785 -0.944095 0.001128 0.003528 0.026486 -39.785156 157.335938 -331.101562 -0.009263 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317896 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633736 0.352317 0.000000 -0.019384 0.009775 -0.041927 0.046680 0.259926 0.137304 0.195622 0.240707 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.759094 -0.011154 0.021109 -0.949222 -0.021220 -0.008179 0.023294 -32.964844 161.929688 -338.273438 -0.009339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317805 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630173 0.356587 0.000000 -0.017490 0.013345 -0.040978 0.046619 0.253513 0.136576 0.198247 0.245224 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.764099 -0.004318 0.002799 -0.936527 -0.002064 0.006720 0.017972 -32.964844 161.929688 -338.273438 -0.009325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317716 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631172 0.355427 0.000000 -0.019894 0.010197 -0.039398 0.046632 0.257485 0.138901 0.199083 0.238091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.769104 -0.007248 -0.014291 -0.947025 -0.001000 0.004592 0.014780 -34.101562 158.484375 -334.687500 -0.009308 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317628 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631161 0.354132 0.000000 -0.019484 0.010062 -0.038450 0.046629 0.256262 0.140394 0.199486 0.237418 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.774109 0.015945 0.017691 -0.938968 0.000064 0.000335 0.008394 -34.101562 158.484375 -334.687500 -0.009279 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317541 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629693 0.351935 0.000000 -0.018752 0.009908 -0.036553 0.046602 0.253778 0.143167 0.200486 0.236089 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.779114 0.021561 0.006217 -0.940189 -0.002064 -0.000729 0.005202 -35.238281 161.929688 -335.882812 -0.009258 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317456 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628505 0.350575 0.000000 -0.018575 0.010264 -0.035605 0.046579 0.252296 0.143936 0.201613 0.235674 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.784119 -0.006760 0.014273 -0.949711 -0.016963 -0.006050 -0.001184 -35.238281 161.929688 -335.882812 -0.009313 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317372 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626815 0.353790 0.000000 -0.017757 0.012632 -0.033709 0.046546 0.247214 0.144282 0.205060 0.236963 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.789124 -0.004563 0.004752 -0.942875 0.003257 0.007785 -0.005441 -38.648438 151.593750 -332.296875 -0.009272 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317290 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629868 0.351192 0.000000 -0.020027 0.009341 -0.032444 0.046593 0.251511 0.146568 0.205304 0.230138 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.794128 -0.008469 -0.003793 -0.939457 -0.001000 0.004592 -0.009697 -38.648438 151.593750 -332.296875 -0.009254 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317210 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631765 0.350110 0.000000 -0.019498 0.010078 -0.031180 0.046623 0.247810 0.146454 0.205606 0.228971 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.799133 0.012039 0.011832 -0.934330 -0.011642 -0.008179 -0.008633 -32.964844 159.632812 -333.492188 -0.009287 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317131 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629575 0.352054 0.000000 -0.017468 0.011787 -0.031496 0.046585 0.244387 0.146459 0.204969 0.233025 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.804138 0.011307 0.009146 -0.942875 -0.004193 0.004592 -0.009697 -32.964844 159.632812 -333.492188 -0.009282 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317053 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631332 0.351658 0.000000 -0.019577 0.010553 -0.031180 0.046612 0.247414 0.145900 0.206160 0.229366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.809143 -0.004318 0.008170 -0.953129 -0.005257 -0.006050 -0.011826 -30.691406 161.929688 -335.882812 -0.009284 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316977 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630204 0.351736 0.000000 -0.017887 0.010730 -0.030548 0.046593 0.244916 0.148045 0.205279 0.230600 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.814148 -0.005783 0.000113 -0.944095 0.002193 0.002463 -0.010762 -30.691406 161.929688 -335.882812 -0.009250 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316901 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631682 0.349715 0.000000 -0.019308 0.009550 -0.030864 0.046616 0.247833 0.147488 0.205204 0.228315 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.819153 -0.003098 -0.000619 -0.948490 -0.001000 0.003528 -0.007569 -36.375000 165.375000 -329.906250 -0.009230 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316828 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632688 0.348861 0.000000 -0.019464 0.010108 -0.031812 0.046639 0.248389 0.145836 0.204980 0.229676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.824158 -0.007492 0.008902 -0.938480 -0.010578 -0.003922 -0.004376 -36.375000 165.375000 -329.906250 -0.009252 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316756 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631242 0.350228 0.000000 -0.018258 0.011632 -0.032760 0.046615 0.246607 0.144569 0.204350 0.233354 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.829163 0.005936 -0.005990 -0.926517 -0.002064 0.001399 -0.004376 -39.785156 159.632812 -333.492188 -0.009224 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316685 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630866 0.348655 0.000000 -0.019112 0.010211 -0.032760 0.046609 0.248882 0.145136 0.203783 0.231079 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.834167 0.002518 0.016715 -0.958500 -0.007385 -0.001794 -0.002248 -39.785156 159.632812 -333.492188 -0.009218 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316616 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629290 0.348403 0.000000 -0.018569 0.011039 -0.033393 0.046581 0.248143 0.144220 0.203435 0.233082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.839172 0.004959 -0.000131 -0.965091 -0.002064 0.004592 0.003073 -39.785156 159.632812 -333.492188 -0.009184 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316548 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630068 0.346500 0.000000 -0.019581 0.010140 -0.034973 0.046587 0.249294 0.140187 0.199627 0.230412 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.844177 -0.007248 -0.001840 -0.941898 -0.004193 0.000335 0.008394 -27.281250 156.187500 -332.296875 -0.009159 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316482 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629313 0.345210 0.000000 -0.018855 0.010458 -0.036553 0.046572 0.249830 0.139014 0.197640 0.233037 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.849182 -0.013840 0.001090 -0.945072 -0.012706 -0.001794 0.013715 -27.281250 156.187500 -332.296875 -0.009171 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316418 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627755 0.346144 0.000000 -0.018493 0.011766 -0.038134 0.046544 0.249741 0.136488 0.197005 0.236286 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.854187 0.007889 0.001578 -0.949711 -0.005257 0.004592 0.015844 -32.964844 157.335938 -338.273438 -0.009139 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316356 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627685 0.344456 0.000000 -0.019483 0.010478 -0.038766 0.046540 0.252651 0.136154 0.196075 0.234641 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.859192 0.004959 0.013053 -0.940921 0.007514 -0.002858 0.014780 -32.964844 157.335938 -338.273438 -0.009042 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316296 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624912 0.338940 0.000000 -0.018221 0.008399 -0.038435 0.046496 0.253146 0.139836 0.193075 0.233503 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.864197 -0.003098 0.003531 -0.929935 -0.006321 0.001399 0.014780 -30.691406 157.335938 -338.273438 -0.009015 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316238 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624031 0.337901 0.000000 -0.018885 0.010627 -0.038435 0.046476 0.251583 0.136943 0.195968 0.235067 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.869202 0.003250 0.025016 -0.950443 -0.016963 0.005656 0.020101 -30.691406 157.335938 -338.273438 -0.009051 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316182 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624623 0.340489 0.000000 -0.019527 0.012265 -0.040015 0.046481 0.252167 0.133083 0.196667 0.237643 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.874207 0.001297 -0.001596 -0.948002 -0.004193 -0.004986 0.027550 -35.238281 159.632812 -338.273438 -0.009035 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316127 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622294 0.339929 0.000000 -0.017787 0.010148 -0.042228 0.046437 0.254756 0.134727 0.190598 0.239479 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.879211 -0.005295 0.005484 -0.947269 0.013899 0.008849 0.024358 -35.238281 159.632812 -338.273438 -0.008940 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316074 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624292 0.334675 0.000000 -0.020010 0.007299 -0.041279 0.046465 0.258880 0.136302 0.190919 0.233459 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.884216 0.012771 0.003287 -0.942875 -0.007385 0.004592 0.017972 -35.238281 155.039062 -333.492188 -0.008955 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316022 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625420 0.335852 0.000000 -0.019283 0.010805 -0.039398 0.046475 0.250426 0.133064 0.193240 0.233470 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.889221 -0.001633 0.022574 -0.936283 -0.012706 -0.002858 0.014780 -35.238281 155.039062 -333.492188 -0.009001 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315971 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624282 0.339019 0.000000 -0.018086 0.011637 -0.038450 0.046452 0.247449 0.134377 0.193823 0.234550 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.894226 0.005203 0.009146 -0.937992 0.005385 0.003528 0.013715 -34.101562 156.187500 -337.078125 -0.008966 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315922 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625437 0.337232 0.000000 -0.019145 0.008740 -0.038134 0.046468 0.251089 0.136531 0.192301 0.230279 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.899231 0.001785 -0.026010 -0.950199 -0.006321 -0.002858 0.016908 -34.101562 156.187500 -337.078125 -0.008992 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315874 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624969 0.339102 0.000000 -0.018140 0.010697 -0.039082 0.046458 0.249075 0.134630 0.192306 0.234189 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.904236 -0.000656 0.019400 -0.956058 -0.010578 0.004592 0.010523 -36.375000 158.484375 -337.078125 -0.009028 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315826 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626897 0.341489 0.000000 -0.019378 0.011367 -0.037186 0.046488 0.241906 0.128780 0.190269 0.225885 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.909241 0.016189 0.011832 -0.948734 -0.001000 0.010977 0.004137 -36.375000 158.484375 -337.078125 -0.009009 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315780 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630799 0.340496 0.000000 -0.020400 0.009804 -0.035289 0.046553 0.242595 0.131216 0.191626 0.221403 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.914246 0.000564 -0.002084 -0.940433 -0.005257 -0.006050 -0.002248 -29.554688 151.593750 -334.687500 -0.009011 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315734 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629918 0.340723 0.000000 -0.017683 0.010502 -0.033393 0.046541 0.237283 0.135132 0.191503 0.222922 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.919250 -0.011643 0.002066 -0.930668 0.005385 0.000335 -0.006505 -29.554688 151.593750 -334.687500 -0.008956 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315691 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631150 0.337583 0.000000 -0.018801 0.008798 -0.032128 0.046563 0.238842 0.136983 0.192181 0.218834 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.924255 -0.013840 0.011832 -0.938236 -0.013771 0.002463 -0.006505 -36.375000 151.593750 -339.468750 -0.008991 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315647 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632433 0.339951 0.000000 -0.019176 0.011881 -0.032128 0.046587 0.236134 0.133525 0.195639 0.221543 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.929260 0.017654 0.024039 -0.935550 -0.009514 -0.004986 -0.005441 -36.375000 151.593750 -339.468750 -0.009009 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315002 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630389 0.341405 0.000000 -0.017982 0.011134 -0.032444 0.046562 0.219683 0.118829 0.177062 0.205986 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.934265 0.002518 -0.007943 -0.946293 0.006450 0.001399 -0.011826 -35.238281 148.148438 -338.273438 -0.008955 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314370 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630427 0.338312 0.000000 -0.019035 0.008575 -0.030548 0.046565 0.221398 0.122233 0.177451 0.200478 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.939270 -0.007248 0.006217 -0.947025 -0.008450 -0.003922 -0.013954 -35.238281 148.148438 -338.273438 -0.008979 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313749 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628894 0.339922 0.000000 -0.018181 0.011022 -0.029916 0.046540 0.217465 0.121271 0.179678 0.203147 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.944275 -0.007004 0.016227 -0.948246 -0.004193 -0.000729 -0.008633 -35.238281 148.148438 -338.273438 -0.008982 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313141 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628102 0.340207 0.000000 -0.018704 0.010324 -0.031496 0.046527 0.220266 0.119865 0.177922 0.203506 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.949280 0.007156 -0.007455 -0.933597 -0.001000 0.006720 -0.008633 -42.058594 155.039062 -333.492188 -0.008970 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312544 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629494 0.339307 0.000000 -0.019877 0.009819 -0.031496 0.046544 0.209104 0.106357 0.165750 0.188988 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.954285 -0.007004 0.018668 -0.940921 -0.004193 0.000335 -0.003312 -42.058594 155.039062 -333.492188 -0.008973 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311959 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628362 0.339618 0.000000 -0.018791 0.010354 -0.033077 0.046525 0.209063 0.105329 0.163618 0.192190 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.959290 0.012527 -0.000375 -0.941898 0.000064 -0.004986 -0.000119 -34.101562 153.890625 -334.687500 -0.008955 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311386 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625685 0.338658 0.000000 -0.017921 0.009682 -0.034025 0.046479 0.209813 0.105922 0.161128 0.193336 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.964294 0.009354 0.020865 -0.944095 -0.012706 -0.003922 0.000945 -34.101562 153.890625 -334.687500 -0.009003 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310823 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623808 0.341624 0.000000 -0.018108 0.011743 -0.034341 0.046445 0.208256 0.103358 0.163060 0.195526 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.969299 -0.001389 -0.010141 -0.930423 0.000064 0.005656 0.003073 -42.058594 145.851562 -343.054688 -0.008990 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310271 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625425 0.341109 0.000000 -0.019652 0.009679 -0.033198 0.046468 0.202560 0.096862 0.155523 0.182615 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.974304 0.001541 -0.000863 -0.944339 -0.002064 0.002463 0.013715 -42.058594 145.851562 -343.054688 -0.008982 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309730 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626462 0.340678 0.000000 -0.019118 0.010052 -0.036359 0.046483 0.204815 0.093862 0.152200 0.186683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.979309 0.007889 0.013053 -0.945804 -0.011642 0.001399 0.025422 -37.511719 152.742188 -340.664062 -0.009013 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309199 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627468 0.342557 0.000000 -0.018958 0.011572 -0.039835 0.046499 0.206612 0.089024 0.150085 0.191839 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.984314 0.008865 0.009635 -0.939213 0.000064 0.002463 0.029679 -37.511719 152.742188 -340.664062 -0.008983 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308678 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629160 0.340714 0.000000 -0.019157 0.009648 -0.041100 0.046527 0.210000 0.089485 0.147095 0.190980 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.989319 -0.001389 0.007437 -0.950931 0.000064 0.002463 0.030743 -39.785156 145.851562 -343.054688 -0.008954 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308167 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631192 0.339074 0.000000 -0.019193 0.009667 -0.041416 0.046563 0.210332 0.089114 0.146835 0.191279 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.994324 -0.013596 0.005729 -0.927250 -0.014835 0.000335 0.031807 -39.785156 145.851562 -343.054688 -0.009002 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307665 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632499 0.341727 0.000000 -0.018891 0.012041 -0.041732 0.046587 0.198633 0.077386 0.139250 0.184931 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+454.999329 0.002518 0.016227 -0.946781 0.003257 0.009913 0.036064 -35.238281 143.554688 -340.664062 -0.008964 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307174 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636050 0.339444 0.000000 -0.020445 0.009098 -0.042996 0.046651 0.204394 0.077510 0.136597 0.181699 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.004333 -0.002121 -0.013070 -0.955326 -0.006321 0.004592 0.042450 -35.238281 143.554688 -340.664062 -0.008976 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306691 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637277 0.340231 0.000000 -0.019556 0.010677 -0.044893 0.046678 0.203822 0.074924 0.135390 0.186063 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.009338 -0.001389 0.003287 -0.938480 -0.004193 -0.001794 0.042450 -38.648438 144.703125 -341.859375 -0.008972 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306219 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636081 0.340014 0.000000 -0.018527 0.010317 -0.044893 0.046664 0.203152 0.076313 0.134002 0.186733 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.014343 0.011795 0.016471 -0.945072 0.001128 0.008849 0.036064 -38.648438 144.703125 -341.859375 -0.008935 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305755 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637785 0.337861 0.000000 -0.020234 0.009456 -0.042996 0.046699 0.193324 0.066864 0.126244 0.171768 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.019348 -0.017258 -0.007943 -0.940677 -0.009514 -0.003922 0.027550 -29.554688 147.000000 -344.250000 -0.008948 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305301 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635507 0.338770 0.000000 -0.018150 0.011157 -0.040468 0.046666 0.187011 0.069775 0.128389 0.173024 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.024353 -0.008225 0.020133 -0.928714 -0.001000 0.004592 0.015844 -29.554688 147.000000 -344.250000 -0.008917 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304856 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635346 0.337023 0.000000 -0.019518 0.009743 -0.036991 0.046667 0.186316 0.073299 0.131820 0.166765 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.029358 0.005691 0.013785 -0.954838 -0.001000 0.014170 0.009459 -39.785156 148.148438 -340.664062 -0.008890 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304420 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637345 0.335631 0.000000 -0.020975 0.009749 -0.035094 0.046705 0.185871 0.073732 0.135180 0.163417 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.034363 0.001541 -0.008920 -0.963871 -0.006321 -0.007115 0.005202 -39.785156 148.148438 -340.664062 -0.008897 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632735 0.336240 0.000000 -0.017474 0.010607 -0.033830 0.046632 0.180247 0.077639 0.133801 0.166513 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.039368 0.004959 0.009635 -0.940677 0.001128 0.002463 -0.000119 -42.058594 148.148438 -340.664062 -0.008866 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304768 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631295 0.334929 0.000000 -0.019022 0.009411 -0.032250 0.046608 0.169741 0.067197 0.124063 0.150518 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.044373 -0.003098 0.024527 -0.934086 -0.010578 0.005656 -0.009697 -42.058594 148.148438 -340.664062 -0.008897 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304938 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631110 0.336959 0.000000 -0.019494 0.011299 -0.029405 0.046605 0.165480 0.067681 0.129269 0.149090 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.049377 -0.002609 0.002311 -0.933597 -0.005257 -0.002858 -0.020340 -42.058594 148.148438 -340.664062 -0.008909 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305104 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628608 0.337845 0.000000 -0.018096 0.010423 -0.026244 0.046562 0.161797 0.073117 0.130155 0.146452 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.054382 -0.001877 0.006217 -0.939457 0.002193 -0.008179 -0.027789 -36.375000 142.406250 -339.468750 -0.008893 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305267 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624727 0.336933 0.000000 -0.017263 0.009263 -0.024032 0.046493 0.159911 0.077323 0.130374 0.143912 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.059387 0.001053 0.000602 -0.947513 -0.010578 -0.000729 -0.030982 -36.375000 142.406250 -339.468750 -0.008941 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305427 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623249 0.339882 0.000000 -0.018483 0.011360 -0.023083 0.046462 0.149927 0.066793 0.126480 0.135680 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.064392 0.003982 0.014273 -0.949222 -0.003128 0.000335 -0.033110 -38.648438 149.296875 -344.250000 -0.008950 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305583 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622258 0.340397 0.000000 -0.018636 0.010157 -0.022451 0.046439 0.150651 0.068476 0.126062 0.133692 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.069397 0.014236 0.007926 -0.945804 0.003257 -0.002858 -0.029918 -38.648438 149.296875 -344.250000 -0.008928 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305736 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620786 0.339039 0.000000 -0.018118 0.009176 -0.023400 0.046407 0.152061 0.069026 0.123615 0.134178 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.074402 -0.007492 -0.004037 -0.934574 -0.011642 -0.002858 -0.026725 -34.101562 142.406250 -341.859375 -0.008979 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305887 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619968 0.342061 0.000000 -0.018144 0.011608 -0.024348 0.046386 0.150603 0.065620 0.125125 0.137532 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.079407 0.000320 0.019645 -0.933597 0.003257 -0.003922 -0.026725 -34.101562 142.406250 -341.859375 -0.008953 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306034 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619192 0.340373 0.000000 -0.018005 0.009204 -0.024348 0.046365 0.145869 0.061163 0.115582 0.128266 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.084412 0.001053 0.000113 -0.942386 -0.004193 0.000335 -0.021404 -31.828125 147.000000 -339.468750 -0.008963 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306177 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619767 0.340923 0.000000 -0.018715 0.010447 -0.025928 0.046367 0.146917 0.057630 0.115954 0.130379 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.089417 -0.006516 -0.014047 -0.949955 -0.011642 0.000335 -0.013954 -31.828125 147.000000 -339.468750 -0.009004 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306318 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620226 0.343288 0.000000 -0.018716 0.011624 -0.028141 0.046368 0.147953 0.054240 0.114919 0.133769 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.094421 0.008865 0.015982 -0.937992 0.009642 0.001399 -0.003312 -36.375000 142.406250 -341.859375 -0.008927 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306455 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620821 0.338587 0.000000 -0.018881 0.008174 -0.031301 0.046372 0.154729 0.054364 0.108474 0.133314 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.099426 0.008865 0.002799 -0.932865 -0.005257 0.002463 0.004137 -36.375000 142.406250 -341.859375 -0.008917 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306590 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621794 0.338040 0.000000 -0.019044 0.010595 -0.033514 0.046384 0.154683 0.049567 0.108845 0.137785 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.104431 0.002029 0.012809 -0.948490 -0.012706 0.000335 0.015844 -35.238281 138.960938 -338.273438 -0.008942 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306721 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622466 0.339565 0.000000 -0.018707 0.011722 -0.036991 0.046391 0.153196 0.041800 0.102659 0.139226 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.109436 0.008377 -0.000375 -0.936039 0.004321 0.005656 0.022229 -35.238281 138.960938 -338.273438 -0.008882 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306848 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625069 0.336049 0.000000 -0.019580 0.008925 -0.038887 0.046433 0.158762 0.041827 0.098838 0.137452 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.114441 -0.017746 0.003531 -0.949711 -0.007385 0.000335 0.027550 -37.511719 148.148438 -340.664062 -0.008880 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306973 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626120 0.336129 0.000000 -0.018735 0.010806 -0.040468 0.046450 0.157616 0.039211 0.098294 0.141759 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.119446 0.012039 -0.006234 -0.950687 -0.009514 0.000335 0.037128 -37.511719 148.148438 -340.664062 -0.008885 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307095 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626906 0.336557 0.000000 -0.018766 0.011078 -0.043312 0.046463 0.160220 0.036064 0.095751 0.144845 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.124451 -0.002365 -0.005258 -0.938724 -0.002064 0.003528 0.043514 -43.195312 142.406250 -332.296875 -0.008843 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307214 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628381 0.334208 0.000000 -0.019295 0.009807 -0.045209 0.046489 0.160416 0.031409 0.089613 0.141441 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.129456 -0.001877 0.012564 -0.933597 -0.010578 0.002463 0.044578 -43.195312 142.406250 -332.296875 -0.008833 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629295 0.333888 0.000000 -0.019122 0.011108 -0.045525 0.046507 0.159259 0.029965 0.090425 0.143231 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.134460 0.005447 0.004264 -0.934818 -0.001000 0.002463 0.044578 -39.785156 141.257812 -343.054688 -0.008773 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307847 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629959 0.330574 0.000000 -0.019122 0.009479 -0.045525 0.046521 0.160887 0.031594 0.088796 0.141602 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.139465 0.008377 0.010367 -0.944339 -0.008450 0.002463 0.041385 -39.785156 141.257812 -343.054688 -0.008753 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308353 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630604 0.329773 0.000000 -0.019123 0.010629 -0.044577 0.046535 0.158791 0.031392 0.090895 0.141802 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.144470 -0.005783 0.007682 -0.957767 -0.007385 0.003528 0.037128 -42.058594 141.257812 -343.054688 -0.008735 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308847 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631668 0.329075 0.000000 -0.019299 0.010390 -0.043312 0.046556 0.157941 0.032719 0.092097 0.140124 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.149475 -0.008713 -0.001107 -0.941654 0.002193 0.008849 0.029679 -42.058594 141.257812 -343.054688 -0.008676 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309332 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634076 0.325999 0.000000 -0.020140 0.008826 -0.041100 0.046601 0.151134 0.028654 0.086586 0.128506 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.154480 0.001297 0.008658 -0.958744 -0.001000 0.003528 0.027550 -42.058594 141.257812 -343.054688 -0.008638 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309808 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634359 0.324257 0.000000 -0.019248 0.009359 -0.040468 0.046611 0.149077 0.029645 0.086860 0.129299 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.159485 0.015213 0.003043 -0.945072 -0.002064 0.007785 0.019037 -32.964844 145.851562 -340.664062 -0.008608 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310273 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635664 0.323091 0.000000 -0.019912 0.009532 -0.037939 0.046639 0.147040 0.031337 0.090225 0.126278 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.164490 -0.001145 0.015006 -0.929691 -0.003128 0.001399 0.010523 -32.964844 145.851562 -340.664062 -0.008589 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310731 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635257 0.322545 0.000000 -0.018869 0.009702 -0.035410 0.046638 0.143298 0.034739 0.091881 0.124963 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.169495 0.000076 0.013541 -0.937504 -0.005257 -0.000729 0.000945 -44.332031 145.851562 -343.054688 -0.008590 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311179 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634523 0.323139 0.000000 -0.018556 0.010047 -0.032566 0.046631 0.135125 0.032882 0.090087 0.118107 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.174500 -0.001633 0.023062 -0.944095 -0.003128 -0.001794 -0.008633 -44.332031 145.851562 -343.054688 -0.008594 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311619 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633599 0.323911 0.000000 -0.018424 0.009727 -0.029721 0.046620 0.132467 0.036178 0.092480 0.115075 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.179504 -0.010178 0.004752 -0.941654 -0.006321 0.001399 -0.017147 -44.332031 136.664062 -347.835938 -0.008632 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312050 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633472 0.326554 0.000000 -0.018962 0.010296 -0.027192 0.046621 0.129909 0.037600 0.096115 0.112576 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.184509 -0.000168 -0.005746 -0.944828 -0.007385 -0.001794 -0.023532 -44.332031 136.664062 -347.835938 -0.008684 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312473 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631967 0.329878 0.000000 -0.018448 0.010518 -0.025296 0.046599 0.127277 0.039788 0.097720 0.111415 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.189514 0.007645 0.004264 -0.943119 0.003257 0.000335 -0.023532 -43.195312 144.703125 -339.468750 -0.008680 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312887 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630841 0.329722 0.000000 -0.018789 0.008869 -0.025296 0.046581 0.118765 0.030596 0.085912 0.098927 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.194519 -0.000656 -0.003305 -0.936527 -0.009514 -0.008179 -0.024597 -43.195312 144.703125 -339.468750 -0.008729 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313292 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627270 0.332724 0.000000 -0.017422 0.010985 -0.024980 0.046521 0.114967 0.030162 0.086978 0.102093 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.199524 0.008865 0.013785 -0.939213 -0.003128 0.001399 -0.025661 -38.648438 142.406250 -339.468750 -0.008736 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313690 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626892 0.333034 0.000000 -0.018985 0.009951 -0.024664 0.046513 0.117248 0.029950 0.087822 0.099179 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.204529 -0.001389 0.010123 -0.939457 -0.003128 -0.001794 -0.023532 -38.648438 142.406250 -339.468750 -0.008736 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314079 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625915 0.332977 0.000000 -0.018461 0.009965 -0.025296 0.046493 0.117342 0.029828 0.086680 0.100350 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.209534 -0.002609 0.007193 -0.948978 -0.007385 -0.002858 -0.021404 -39.785156 132.070312 -345.445312 -0.008756 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314459 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624898 0.334124 0.000000 -0.018302 0.010652 -0.025928 0.046473 0.117128 0.028667 0.086576 0.101828 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.214539 -0.010666 0.003531 -0.935795 -0.003128 -0.001794 -0.017147 -39.785156 132.070312 -345.445312 -0.008755 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624128 0.333646 0.000000 -0.018482 0.009951 -0.027192 0.046456 0.116934 0.025585 0.082450 0.099871 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.219543 0.008377 -0.008188 -0.937259 -0.009514 0.001399 -0.009697 -36.375000 144.703125 -344.250000 -0.008781 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315197 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624031 0.335078 0.000000 -0.018980 0.010970 -0.029405 0.046450 0.118626 0.021855 0.081755 0.102604 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.224548 -0.000412 -0.001352 -0.945072 -0.001000 -0.000729 -0.001184 -36.375000 144.703125 -344.250000 -0.008754 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315554 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623187 0.333276 0.000000 -0.018610 0.009563 -0.031934 0.046432 0.122190 0.021104 0.077449 0.104097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.229553 0.014725 -0.001107 -0.936039 -0.005257 0.001399 0.008394 -40.921875 140.109375 -337.078125 -0.008733 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315903 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623217 0.331990 0.000000 -0.018937 0.010219 -0.034778 0.046428 0.124707 0.017276 0.075588 0.107269 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.234558 0.008621 0.010123 -0.952396 -0.008450 0.000335 0.015844 -40.921875 140.109375 -337.078125 -0.008717 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315843 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623520 0.331363 0.000000 -0.018763 0.010666 -0.036991 0.046429 0.126308 0.014800 0.073659 0.110114 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.239563 0.003494 0.013053 -0.936283 -0.004193 0.003528 0.020101 -42.058594 143.554688 -345.445312 -0.008678 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315783 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625493 0.329092 0.000000 -0.019295 0.009903 -0.038255 0.046459 0.128867 0.013766 0.072164 0.110083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.244568 0.002029 0.014273 -0.946781 -0.005257 0.001399 0.026486 -42.058594 143.554688 -345.445312 -0.008651 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315725 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627316 0.327668 0.000000 -0.018980 0.010032 -0.040152 0.046488 0.130320 0.012057 0.070080 0.112423 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.249573 -0.011643 0.005484 -0.933597 -0.005257 0.002463 0.028615 -36.375000 144.703125 -344.250000 -0.008636 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629497 0.327009 0.000000 -0.019191 0.010007 -0.040784 0.046525 0.131188 0.011239 0.069634 0.112819 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.254578 -0.005783 0.000846 -0.949955 -0.005257 0.002463 0.031807 -36.375000 144.703125 -344.250000 -0.008631 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315610 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631134 0.326928 0.000000 -0.019212 0.009999 -0.041732 0.046555 0.132164 0.010277 0.068700 0.113739 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.259583 0.000564 0.010611 -0.944095 -0.006321 0.008849 0.031807 -36.375000 144.703125 -344.250000 -0.008637 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315554 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633842 0.327466 0.000000 -0.020226 0.010171 -0.041732 0.046604 0.133007 0.009091 0.069885 0.112897 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.264587 0.005936 0.003287 -0.941166 -0.002064 0.005656 0.033936 -47.742188 137.812500 -341.859375 -0.008625 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315500 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634947 0.326946 0.000000 -0.019667 0.009498 -0.042364 0.046627 0.133753 0.009691 0.068021 0.113415 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.269592 0.014236 0.011344 -0.944584 -0.001000 0.001399 0.036064 -47.742188 137.812500 -341.859375 -0.008611 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315446 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634715 0.326336 0.000000 -0.018968 0.009365 -0.042996 0.046629 0.133819 0.009891 0.066557 0.114613 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.274597 -0.002854 0.000602 -0.940677 -0.007385 0.001399 0.030743 -43.195312 140.109375 -339.468750 -0.008632 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315393 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634823 0.327760 0.000000 -0.018985 0.010420 -0.041416 0.046636 0.131201 0.010399 0.069209 0.114071 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.279602 -0.015305 0.010855 -0.939213 -0.007385 0.003528 0.026486 -43.195312 140.109375 -339.468750 -0.008653 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315342 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635602 0.329140 0.000000 -0.019340 0.010417 -0.041927 0.046654 0.132069 0.009536 0.069050 0.114224 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.284607 0.004227 0.001822 -0.942386 -0.002064 0.005656 0.019037 -44.332031 136.664062 -340.664062 -0.008648 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315292 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636545 0.328879 0.000000 -0.019667 0.009573 -0.039714 0.046675 0.131028 0.012266 0.070746 0.110840 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.289612 0.000564 0.009635 -0.943119 -0.002064 0.003528 0.011587 -44.332031 136.664062 -340.664062 -0.008642 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315242 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636426 0.328600 0.000000 -0.019296 0.009607 -0.037502 0.046678 0.128411 0.014815 0.072622 0.109032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.294617 -0.003586 0.001334 -0.946781 -0.006321 -0.002858 0.005202 -38.648438 140.109375 -346.640625 -0.008657 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315194 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634218 0.329505 0.000000 -0.018261 0.010310 -0.035605 0.046646 0.124776 0.017044 0.074186 0.108874 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.299622 0.003982 0.010123 -0.936771 -0.006321 -0.000729 -0.001184 -38.648438 140.109375 -346.640625 -0.008669 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315147 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632588 0.330259 0.000000 -0.018613 0.010304 -0.033709 0.046621 0.123237 0.018594 0.076429 0.106620 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.304626 -0.004074 0.000113 -0.936039 -0.003128 0.004592 -0.007569 -40.921875 137.812500 -341.859375 -0.008664 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315100 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632517 0.329930 0.000000 -0.019450 0.009791 -0.031812 0.046621 0.122691 0.020167 0.078649 0.103373 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.309631 0.010330 0.000846 -0.943363 -0.002064 0.000335 -0.009697 -40.921875 137.812500 -341.859375 -0.008650 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315054 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631256 0.329071 0.000000 -0.018733 0.009630 -0.031180 0.046601 0.121504 0.021677 0.078403 0.103296 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.314636 0.002029 0.009635 -0.954349 -0.010578 -0.001794 -0.013954 -40.921875 140.109375 -346.640625 -0.008672 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315009 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629733 0.330448 0.000000 -0.018394 0.010984 -0.029916 0.046575 0.118546 0.021926 0.080683 0.103726 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.319641 0.005936 0.000113 -0.935306 -0.007385 -0.003922 -0.018211 -40.921875 140.109375 -346.640625 -0.008675 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314965 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628112 0.330599 0.000000 -0.018080 0.010420 -0.028651 0.046546 0.117532 0.024069 0.081068 0.102211 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.324646 0.000076 0.007682 -0.939701 0.004321 0.001399 -0.022468 -40.921875 135.515625 -346.640625 -0.008618 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314922 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628552 0.327160 0.000000 -0.018968 0.008528 -0.027372 0.046551 0.119032 0.026352 0.081344 0.098151 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.329651 -0.005295 0.011100 -0.946781 -0.005257 -0.000729 -0.020340 -40.921875 135.515625 -346.640625 -0.008608 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314879 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628556 0.326712 0.000000 -0.018641 0.010089 -0.028004 0.046549 0.117776 0.024486 0.081946 0.100673 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.334656 0.001297 0.009391 -0.938968 -0.010578 -0.001794 -0.018211 -40.921875 137.812500 -339.468750 -0.008629 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314837 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628183 0.328086 0.000000 -0.018493 0.010913 -0.028636 0.046541 0.117437 0.023177 0.081990 0.102276 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.339661 -0.002121 0.001822 -0.950443 -0.004193 0.000335 -0.018211 -40.921875 137.812500 -339.468750 -0.008623 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314796 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628266 0.327804 0.000000 -0.018851 0.009857 -0.028636 0.046540 0.118850 0.023876 0.081291 0.100862 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.344666 0.012771 0.006949 -0.940433 0.000064 0.003528 -0.012890 -37.511719 141.257812 -343.054688 -0.008598 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314756 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629223 0.326151 0.000000 -0.019359 0.009181 -0.030232 0.046555 0.121620 0.022438 0.079518 0.101264 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.349670 -0.003586 0.003287 -0.942386 -0.005257 -0.000729 -0.007569 -37.511719 141.257812 -343.054688 -0.008602 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314716 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629038 0.326472 0.000000 -0.018670 0.010061 -0.031812 0.046551 0.121632 0.020667 0.078129 0.104413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.354675 0.017166 0.012320 -0.949711 -0.004193 -0.002858 -0.001184 -35.238281 143.554688 -345.445312 -0.008600 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314678 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628563 0.326507 0.000000 -0.018358 0.009889 -0.033709 0.046542 0.123388 0.019254 0.075749 0.106450 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.359680 0.003250 0.005729 -0.939213 -0.008450 -0.002858 0.004137 -35.238281 143.554688 -345.445312 -0.008623 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314641 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628653 0.327930 0.000000 -0.018410 0.010574 -0.035289 0.046542 0.124335 0.016936 0.074905 0.108663 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.364685 -0.010178 0.012809 -0.942875 0.000064 -0.000729 0.010523 -35.238281 143.554688 -345.445312 -0.008607 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314605 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629737 0.327017 0.000000 -0.018806 0.009212 -0.037186 0.046559 0.127989 0.016007 0.072042 0.108802 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.369690 -0.000412 0.002555 -0.935795 -0.013771 0.001399 0.015844 -44.332031 138.960938 -343.054688 -0.008664 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314569 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631234 0.330742 0.000000 -0.019178 0.011470 -0.038766 0.046585 0.127693 0.011807 0.073102 0.112278 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.374695 -0.007248 0.004508 -0.942875 -0.005257 0.003528 0.021165 -44.332031 138.960938 -343.054688 -0.008679 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632794 0.331560 0.000000 -0.019520 0.010082 -0.040346 0.046612 0.131004 0.011272 0.070475 0.112128 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.379700 0.003738 0.001822 -0.944095 -0.001000 0.000335 0.025422 -43.195312 140.109375 -339.468750 -0.008671 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314501 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632774 0.330953 0.000000 -0.018989 0.009428 -0.041611 0.046614 0.132391 0.011193 0.068026 0.113270 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.384705 -0.006516 -0.005502 -0.952640 -0.006321 0.006720 0.027550 -43.195312 140.109375 -339.468750 -0.008683 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314468 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634116 0.331537 0.000000 -0.019987 0.010307 -0.042243 0.046639 0.133143 0.008684 0.069271 0.113783 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.389709 0.007400 0.011344 -0.950443 0.000064 0.003528 0.028615 -40.921875 142.406250 -346.640625 -0.008653 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314435 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633709 0.329671 0.000000 -0.019405 0.009273 -0.042559 0.046641 0.133910 0.009984 0.067339 0.113647 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.394714 -0.000656 -0.005258 -0.944584 -0.002064 0.004592 0.029679 -40.921875 142.406250 -346.640625 -0.008626 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314404 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633839 0.328064 0.000000 -0.019534 0.009618 -0.042875 0.046646 0.134011 0.009194 0.067496 0.114179 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.399719 0.004715 0.018424 -0.932865 -0.007385 0.002463 0.029679 -39.785156 136.664062 -343.054688 -0.008621 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314374 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633399 0.327806 0.000000 -0.019156 0.010442 -0.042875 0.046642 0.132808 0.008748 0.067943 0.115381 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.404724 0.006668 0.005484 -0.938236 -0.006321 0.000335 0.028615 -39.785156 136.664062 -343.054688 -0.008611 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314344 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632605 0.327311 0.000000 -0.018803 0.010221 -0.042559 0.046630 0.132361 0.009637 0.067685 0.115197 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.409729 0.000320 0.009391 -0.939701 -0.008450 0.000335 0.022229 -38.648438 142.406250 -344.250000 -0.008618 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314316 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632220 0.327779 0.000000 -0.018814 0.010529 -0.040662 0.046625 0.130167 0.011215 0.069900 0.113598 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.414734 -0.000168 0.012320 -0.946781 -0.005257 0.004592 0.017972 -38.648438 142.406250 -344.250000 -0.008615 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314288 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633382 0.327703 0.000000 -0.019506 0.009995 -0.039398 0.046646 0.130130 0.012321 0.071323 0.111107 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.419739 -0.001877 -0.002328 -0.943119 -0.002064 0.001399 0.013715 -39.785156 145.851562 -343.054688 -0.008604 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314261 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633633 0.327090 0.000000 -0.018991 0.009497 -0.038134 0.046652 0.128848 0.014598 0.071575 0.109860 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.424744 0.000076 0.012320 -0.951420 -0.004193 0.001399 0.009459 -39.785156 145.851562 -343.054688 -0.008607 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314234 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633808 0.327329 0.000000 -0.019004 0.009869 -0.036869 0.046657 0.127224 0.015478 0.073223 0.108955 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.429749 -0.001633 -0.003305 -0.937748 -0.007385 0.000335 0.002009 -39.785156 138.960938 -350.226562 -0.008626 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314208 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633503 0.328525 0.000000 -0.018841 0.010393 -0.034657 0.046653 0.124325 0.017329 0.075797 0.107428 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.434753 -0.001877 0.010123 -0.936283 0.002193 -0.001794 -0.002248 -39.785156 138.960938 -350.226562 -0.008596 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314182 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632379 0.326753 0.000000 -0.018509 0.008866 -0.033377 0.046636 0.124241 0.020468 0.075217 0.104954 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.439758 0.005203 0.007682 -0.938236 -0.005257 0.002463 -0.006505 -40.921875 144.703125 -341.859375 -0.008602 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313554 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632384 0.327192 0.000000 -0.019197 0.010100 -0.032113 0.046637 0.122429 0.019810 0.078404 0.104237 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.444763 0.004227 0.005729 -0.947025 -0.006321 -0.003922 -0.011826 -40.921875 144.703125 -341.859375 -0.008613 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312938 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630535 0.327950 0.000000 -0.018166 0.010267 -0.030533 0.046606 0.119651 0.022254 0.079120 0.103855 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.449768 0.005447 0.017936 -0.942386 -0.006321 0.001399 -0.013954 -43.195312 142.406250 -341.859375 -0.008628 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312335 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630575 0.328835 0.000000 -0.019041 0.010265 -0.029901 0.046605 0.119896 0.022013 0.080625 0.102345 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.454773 -0.001633 0.005484 -0.936283 -0.007385 -0.000729 -0.015019 -43.195312 142.406250 -341.859375 -0.008654 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630257 0.330354 0.000000 -0.018702 0.010445 -0.029600 0.046599 0.119077 0.022473 0.080768 0.102563 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.459778 0.001297 0.011344 -0.937259 0.000064 -0.002858 -0.016083 -39.785156 141.257812 -343.054688 -0.008650 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311163 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629484 0.329999 0.000000 -0.018382 0.009280 -0.029284 0.046585 0.119606 0.024275 0.079598 0.101402 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.464783 0.001053 0.007926 -0.947269 -0.006321 0.002463 -0.013954 -39.785156 141.257812 -343.054688 -0.008682 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310595 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630356 0.331849 0.000000 -0.019256 0.010367 -0.029916 0.046598 0.120025 0.021681 0.080927 0.102247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.469788 -0.001633 -0.003305 -0.948002 -0.007385 -0.000729 -0.012890 -39.785156 141.257812 -343.054688 -0.008721 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310037 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630210 0.333992 0.000000 -0.018740 0.010564 -0.030232 0.046594 0.119628 0.021684 0.080293 0.103276 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.474792 -0.003586 0.008414 -0.930912 -0.003128 0.000335 -0.008633 -37.511719 141.257812 -343.054688 -0.008735 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309490 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630219 0.334526 0.000000 -0.018917 0.009903 -0.031496 0.046593 0.121730 0.020903 0.078545 0.103702 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.479797 -0.000900 -0.005746 -0.939945 -0.006321 -0.001794 -0.004376 -37.511719 141.257812 -343.054688 -0.008756 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308954 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629675 0.335514 0.000000 -0.018582 0.010439 -0.032760 0.046577 0.122123 0.019439 0.077480 0.105837 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.484802 -0.000412 0.004996 -0.942630 -0.003128 0.001399 0.000945 -38.648438 142.406250 -349.031250 -0.008750 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308428 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629461 0.334889 0.000000 -0.019085 0.009919 -0.034341 0.046572 0.124726 0.017875 0.075883 0.106395 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.489807 0.002518 -0.000619 -0.954593 -0.003128 0.001399 0.005202 -38.648438 142.406250 -349.031250 -0.008733 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307913 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629061 0.333638 0.000000 -0.019054 0.009908 -0.035605 0.046564 0.125970 0.016653 0.074577 0.107680 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.494812 -0.000168 0.003531 -0.944584 -0.007385 0.000335 0.010523 -40.921875 144.703125 -344.250000 -0.008727 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307408 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628306 0.333110 0.000000 -0.018855 0.010554 -0.037186 0.046549 0.126706 0.014626 0.073443 0.110105 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.499817 0.002762 0.014518 -0.941166 -0.003128 0.001399 0.014780 -40.921875 144.703125 -344.250000 -0.008694 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306912 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627931 0.331043 0.000000 -0.019003 0.009813 -0.038435 0.046540 0.128845 0.013969 0.071602 0.110464 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.504822 0.003250 0.007682 -0.944095 -0.008450 0.002463 0.019037 -40.921875 142.406250 -344.250000 -0.008689 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306427 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628014 0.330762 0.000000 -0.019151 0.010628 -0.039699 0.046539 0.129441 0.011742 0.071300 0.112396 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.509827 -0.001389 0.005729 -0.945072 -0.002064 0.004592 0.020101 -40.921875 142.406250 -344.250000 -0.008659 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305952 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628880 0.328956 0.000000 -0.019468 0.009562 -0.040015 0.046552 0.131140 0.012175 0.070235 0.111330 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.514832 -0.001389 0.006949 -0.944339 -0.002064 0.000335 0.023294 -42.058594 141.257812 -343.054688 -0.008634 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305487 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628531 0.327569 0.000000 -0.018763 0.009565 -0.040963 0.046544 0.131382 0.011929 0.068585 0.112985 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.519836 -0.001389 0.004508 -0.946048 -0.005257 0.001399 0.025422 -42.058594 141.257812 -343.054688 -0.008629 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628467 0.327150 0.000000 -0.018933 0.010070 -0.041611 0.046542 0.131684 0.010596 0.068603 0.113957 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.524841 -0.003342 0.003531 -0.943851 -0.005257 0.004592 0.024358 -39.785156 138.960938 -343.054688 -0.008627 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304586 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629185 0.327175 0.000000 -0.019429 0.010059 -0.041294 0.046552 0.131875 0.010428 0.069404 0.113134 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.529846 0.003250 0.000846 -0.946048 -0.004193 0.002463 0.024358 -39.785156 138.960938 -343.054688 -0.008619 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304150 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629069 0.326852 0.000000 -0.019056 0.009879 -0.041294 0.046550 0.131682 0.010980 0.068851 0.113327 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.534851 -0.002854 0.009146 -0.932621 -0.004193 0.003528 0.024358 -42.058594 138.960938 -345.445312 -0.008610 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303722 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629167 0.326429 0.000000 -0.019206 0.009873 -0.041294 0.046551 0.131837 0.010837 0.068994 0.113172 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.539856 0.000320 -0.001840 -0.936039 -0.007385 0.001399 0.021165 -42.058594 138.960938 -345.445312 -0.008614 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303706 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628547 0.326838 0.000000 -0.018841 0.010369 -0.040346 0.046539 0.130028 0.011653 0.070074 0.113085 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.544861 0.003250 0.013053 -0.947269 -0.008450 0.002463 0.016908 -43.195312 142.406250 -339.468750 -0.008622 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303690 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628238 0.327428 0.000000 -0.018998 0.010506 -0.039082 0.046533 0.128795 0.012634 0.071642 0.111809 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.549866 0.000076 0.007926 -0.946781 -0.002064 0.002463 0.013715 -43.195312 142.406250 -339.468750 -0.008600 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303675 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628026 0.326206 0.000000 -0.018983 0.009460 -0.038134 0.046528 0.128876 0.014644 0.071529 0.109831 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.554871 0.001785 0.012320 -0.940433 -0.002064 -0.000729 0.008394 -40.921875 142.406250 -339.468750 -0.008583 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303659 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627011 0.325374 0.000000 -0.018465 0.009482 -0.036553 0.046509 0.126757 0.016720 0.072614 0.108790 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.559875 -0.002121 0.015738 -0.945804 -0.005257 0.001399 0.002009 -40.921875 142.406250 -339.468750 -0.008592 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303644 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626762 0.326050 0.000000 -0.018816 0.010022 -0.034657 0.046503 0.124671 0.017726 0.075400 0.107083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.564880 0.000320 0.006217 -0.945316 -0.008450 0.001399 -0.003312 -44.332031 143.554688 -335.882812 -0.008627 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303629 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626540 0.328555 0.000000 -0.018813 0.010566 -0.033077 0.046497 0.122543 0.018765 0.077522 0.106050 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.569885 0.004471 0.006461 -0.944828 0.000064 0.000335 -0.006505 -44.332031 143.554688 -335.882812 -0.008628 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303615 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626052 0.328609 0.000000 -0.018641 0.009236 -0.032128 0.046487 0.122754 0.021214 0.076969 0.103943 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.574890 -0.012131 0.003287 -0.942142 -0.003128 0.001399 -0.010762 -44.332031 143.554688 -335.882812 -0.008648 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303601 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625865 0.329762 0.000000 -0.018813 0.009824 -0.030864 0.046481 0.121074 0.021719 0.078993 0.103094 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.579895 0.002518 0.011832 -0.938236 -0.011642 -0.002858 -0.011826 -37.511719 138.960938 -338.273438 -0.008709 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303587 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624190 0.333330 0.000000 -0.018125 0.011227 -0.030548 0.046450 0.118667 0.021320 0.080024 0.104869 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.584900 -0.000168 -0.007211 -0.938480 -0.003128 0.001399 -0.011826 -37.511719 138.960938 -338.273438 -0.008725 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303574 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623609 0.334023 0.000000 -0.018808 0.009866 -0.030548 0.046437 0.120710 0.021998 0.079346 0.102825 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.589905 -0.003098 -0.002572 -0.940189 -0.001000 0.000335 -0.011826 -35.238281 141.257812 -338.273438 -0.008719 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303561 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622597 0.333174 0.000000 -0.018611 0.009551 -0.030548 0.046416 0.120818 0.022500 0.078824 0.102698 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.594910 -0.000656 0.001578 -0.941654 -0.004193 -0.000729 -0.010762 -35.238281 141.257812 -338.273438 -0.008715 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303548 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621181 0.332726 0.000000 -0.018418 0.010073 -0.030864 0.046387 0.120419 0.021855 0.078837 0.103729 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.599915 0.006668 0.005729 -0.946048 -0.008450 -0.000729 -0.007569 -42.058594 148.148438 -345.445312 -0.008719 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303536 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619826 0.332777 0.000000 -0.018401 0.010717 -0.031812 0.046359 0.120706 0.020280 0.078516 0.105338 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.604919 0.002029 -0.003305 -0.948002 -0.003128 -0.001794 -0.004376 -42.058594 148.148438 -345.445312 -0.008686 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303523 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618456 0.330670 0.000000 -0.018221 0.009798 -0.032760 0.046330 0.122393 0.020430 0.076469 0.105548 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.609924 0.007156 0.009146 -0.937259 -0.001000 0.000335 -0.001184 -42.058594 141.257812 -338.273438 -0.008634 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303510 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618175 0.327902 0.000000 -0.018565 0.009422 -0.033693 0.046318 0.124057 0.019539 0.075514 0.105770 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.614929 -0.000656 0.010855 -0.944584 -0.005257 0.001399 0.002009 -42.058594 141.257812 -338.273438 -0.008602 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303498 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618658 0.326138 0.000000 -0.018738 0.010061 -0.034642 0.046320 0.124539 0.017779 0.075377 0.107184 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.619934 0.006180 0.008658 -0.943851 -0.006321 -0.001794 0.005202 -34.101562 144.703125 -349.031250 -0.008581 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303486 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618570 0.325065 0.000000 -0.018240 0.010174 -0.035590 0.046313 0.124876 0.017216 0.074044 0.108743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.624939 -0.006027 0.003531 -0.948246 -0.004193 0.001399 0.008394 -34.101562 144.703125 -349.031250 -0.008556 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303474 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619668 0.323842 0.000000 -0.018784 0.009790 -0.036538 0.046326 0.126752 0.016108 0.073256 0.108765 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.629944 -0.001877 0.012076 -0.943851 -0.006321 0.003528 0.013715 -40.921875 137.812500 -346.640625 -0.008550 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303462 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621296 0.323424 0.000000 -0.019133 0.010103 -0.038134 0.046349 0.128374 0.013840 0.072313 0.110313 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.634949 -0.005295 0.003287 -0.943851 -0.007385 -0.000729 0.014780 -40.921875 137.812500 -346.640625 -0.008556 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303451 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621280 0.324043 0.000000 -0.018448 0.010256 -0.038450 0.046347 0.127852 0.014056 0.071464 0.111467 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.639954 0.002762 0.008170 -0.945804 -0.004193 0.000335 0.020101 -35.238281 141.257812 -343.054688 -0.008552 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303440 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621207 0.324029 0.000000 -0.018626 0.009739 -0.040030 0.046343 0.130127 0.012815 0.069545 0.112354 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.644958 -0.001145 0.003531 -0.948978 -0.004193 0.004592 0.021165 -35.238281 141.257812 -343.054688 -0.008552 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304435 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622089 0.324231 0.000000 -0.019293 0.009758 -0.040346 0.046356 0.131091 0.011813 0.069915 0.112021 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.649963 0.003494 0.002799 -0.944584 -0.006321 0.002463 0.024358 -37.511719 145.851562 -345.445312 -0.008564 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305411 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622151 0.325093 0.000000 -0.018916 0.010114 -0.041294 0.046356 0.131307 0.010885 0.068946 0.113702 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.654968 0.002029 -0.000131 -0.948734 -0.003128 0.003528 0.023294 -37.511719 145.851562 -345.445312 -0.008557 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306367 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622517 0.324801 0.000000 -0.019066 0.009606 -0.040978 0.046361 0.131648 0.011560 0.068904 0.112729 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.659973 0.007156 0.000846 -0.938724 -0.002064 0.002463 0.023294 -43.195312 140.109375 -341.859375 -0.008538 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307305 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622733 0.323848 0.000000 -0.018878 0.009446 -0.040978 0.046364 0.131621 0.011907 0.068556 0.112756 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.664978 -0.002365 0.004996 -0.936771 -0.006321 0.001399 0.022229 -43.195312 140.109375 -341.859375 -0.008534 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308224 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622898 0.323768 0.000000 -0.018709 0.010122 -0.040662 0.046366 0.130460 0.011717 0.069378 0.113285 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.669983 0.002029 0.009391 -0.942142 -0.005257 0.001399 0.019037 -42.058594 136.664062 -343.054688 -0.008521 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309126 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623241 0.323123 0.000000 -0.018722 0.009916 -0.039714 0.046372 0.129729 0.012858 0.070134 0.112119 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.674988 0.000076 -0.000863 -0.948490 -0.005257 0.000335 0.015844 -42.058594 136.664062 -343.054688 -0.008506 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622977 0.322716 0.000000 -0.018556 0.009896 -0.038751 0.046373 0.128631 0.014017 0.070922 0.111311 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.679993 0.001053 0.008170 -0.944339 -0.003128 0.003528 0.010523 -42.058594 136.664062 -343.054688 -0.008479 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310876 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624027 0.321350 0.000000 -0.019084 0.009529 -0.037170 0.046391 0.127945 0.015437 0.072663 0.108836 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.684998 -0.003098 0.001822 -0.938724 -0.003128 0.000335 0.005202 -43.195312 137.812500 -346.640625 -0.008453 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311724 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624018 0.320023 0.000000 -0.018574 0.009514 -0.035590 0.046392 0.125870 0.017542 0.073718 0.107750 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.690002 -0.001877 0.008170 -0.939457 -0.006321 -0.001794 0.000945 -43.195312 137.812500 -346.640625 -0.008443 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312556 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623200 0.319721 0.000000 -0.018249 0.010006 -0.034326 0.046379 0.123789 0.018640 0.075149 0.107302 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.695007 -0.006760 0.004752 -0.943607 -0.006321 0.001399 -0.002248 -37.511719 141.257812 -338.273438 -0.008434 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313371 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623024 0.319523 0.000000 -0.018770 0.009973 -0.033377 0.046376 0.123394 0.019100 0.076585 0.105800 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.700012 0.000809 0.008170 -0.946537 -0.004193 -0.001794 -0.005441 -37.511719 141.257812 -338.273438 -0.008419 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314170 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621862 0.318877 0.000000 -0.018252 0.009610 -0.032444 0.046350 0.122306 0.020914 0.076638 0.105023 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.705017 -0.003098 0.002066 -0.947269 -0.005257 0.000335 -0.008633 -44.332031 141.257812 -345.445312 -0.008411 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314952 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620686 0.318742 0.000000 -0.018578 0.009776 -0.031496 0.046329 0.121518 0.021371 0.078077 0.103914 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.710022 0.001297 0.008414 -0.943119 -0.005257 -0.001794 -0.010762 -44.332031 141.257812 -345.445312 -0.008406 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315719 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618711 0.318730 0.000000 -0.018205 0.009769 -0.030864 0.046293 0.120521 0.022382 0.078330 0.103647 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.715027 0.002762 -0.000619 -0.941166 -0.004193 -0.000729 -0.011826 -39.785156 143.554688 -340.664062 -0.008397 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316470 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617090 0.318454 0.000000 -0.018353 0.009595 -0.030548 0.046262 0.120526 0.022724 0.078620 0.103010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.720032 0.006668 0.005973 -0.943851 -0.001000 0.000335 -0.009697 -39.785156 143.554688 -340.664062 -0.008372 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317207 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616064 0.316894 0.000000 -0.018498 0.009080 -0.031180 0.046240 0.121809 0.022452 0.077608 0.102972 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.725037 0.006668 0.002066 -0.950443 -0.004193 -0.000729 -0.007569 -39.785156 145.851562 -340.664062 -0.008360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317928 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615238 0.316506 0.000000 -0.018313 0.009602 -0.031812 0.046221 0.121734 0.021483 0.077312 0.104311 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.730042 0.006668 0.008170 -0.948246 -0.004193 -0.000729 -0.006505 -39.785156 145.851562 -340.664062 -0.008347 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318636 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615090 0.316032 0.000000 -0.018323 0.009590 -0.032128 0.046213 0.122072 0.021169 0.076995 0.104605 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.735046 0.007156 0.006705 -0.942630 -0.004193 0.002463 -0.003312 -38.648438 142.406250 -344.250000 -0.008335 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319329 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616587 0.315588 0.000000 -0.018860 0.009578 -0.033077 0.046233 0.123568 0.019695 0.076572 0.105005 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.740051 0.000564 0.002066 -0.947513 -0.004193 0.001399 0.000945 -38.648438 142.406250 -344.250000 -0.008323 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618309 0.315221 0.000000 -0.018717 0.009569 -0.034341 0.046258 0.124699 0.018583 0.075156 0.106403 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.745056 -0.000168 0.006217 -0.944584 -0.001000 0.001399 0.004137 -40.921875 137.812500 -341.859375 -0.008297 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620286 0.313941 0.000000 -0.018761 0.009054 -0.035289 0.046290 0.126207 0.018106 0.073736 0.106791 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.750061 -0.003342 0.009146 -0.945072 -0.003128 0.000335 0.006266 -40.921875 137.812500 -341.859375 -0.008282 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621850 0.313401 0.000000 -0.018635 0.009404 -0.035921 0.046316 0.126363 0.017249 0.073328 0.107900 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.755066 -0.000900 0.006705 -0.944584 -0.005257 0.001399 0.011587 -40.921875 140.109375 -341.859375 -0.008281 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321972 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623383 0.313674 0.000000 -0.018845 0.009742 -0.037502 0.046343 0.127814 0.015121 0.072295 0.109609 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.760071 -0.004074 0.003775 -0.940677 -0.008450 0.000335 0.013715 -40.921875 140.109375 -341.859375 -0.008299 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322602 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624085 0.315024 0.000000 -0.018694 0.010241 -0.038134 0.046358 0.127797 0.014142 0.072011 0.110891 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.765076 -0.005295 0.001090 -0.938480 -0.003128 0.000335 0.015844 -37.511719 141.257812 -340.664062 -0.008290 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323219 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624177 0.314753 0.000000 -0.018701 0.009370 -0.038766 0.046362 0.129307 0.014372 0.070516 0.110645 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.770081 -0.005295 0.000846 -0.943607 -0.004193 0.002463 0.019037 -37.511719 141.257812 -340.664062 -0.008284 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323824 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624206 0.314620 0.000000 -0.019025 0.009546 -0.039714 0.046365 0.130404 0.012925 0.070067 0.111444 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.775085 -0.004807 -0.001352 -0.950443 -0.005257 0.001399 0.020101 -36.375000 140.109375 -341.859375 -0.008278 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324416 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623209 0.314431 0.000000 -0.018809 0.009702 -0.040030 0.046350 0.130347 0.012669 0.069691 0.112133 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.780090 0.003250 0.006461 -0.945316 -0.007385 0.002463 0.020101 -36.375000 140.109375 -341.859375 -0.008275 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324998 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622020 0.314449 0.000000 -0.018924 0.010008 -0.040030 0.046332 0.130156 0.012247 0.070112 0.112324 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.785095 0.005447 0.003287 -0.941898 -0.002064 0.002463 0.021165 -36.375000 140.109375 -341.859375 -0.008241 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325567 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620719 0.312914 0.000000 -0.018863 0.009122 -0.040346 0.046310 0.131307 0.012889 0.068858 0.111826 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.790100 0.007156 0.002555 -0.942142 -0.002064 0.001399 0.020101 -40.921875 140.109375 -349.031250 -0.008204 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326125 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619429 0.311009 0.000000 -0.018644 0.009104 -0.040030 0.046287 0.130790 0.013441 0.068938 0.111710 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.795105 0.000809 0.001334 -0.945316 -0.006321 0.001399 0.020101 -40.921875 140.109375 -349.031250 -0.008186 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326673 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618710 0.310288 0.000000 -0.018620 0.009755 -0.040030 0.046273 0.130115 0.012814 0.069566 0.112385 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.800110 0.008377 0.005973 -0.942630 -0.006321 0.001399 0.015844 -40.921875 140.109375 -344.250000 -0.008166 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327209 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618594 0.309476 0.000000 -0.018615 0.009700 -0.038766 0.046269 0.128900 0.014139 0.070769 0.111071 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.805115 0.003982 0.003287 -0.937992 -0.002064 0.001399 0.015844 -40.921875 140.109375 -344.250000 -0.008126 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327735 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619112 0.307435 0.000000 -0.018629 0.008974 -0.038766 0.046276 0.129641 0.014852 0.070056 0.110331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.810120 0.003982 0.012320 -0.938724 -0.002064 0.000335 0.010523 -37.511719 145.851562 -343.054688 -0.008088 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328250 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619876 0.305352 0.000000 -0.018490 0.008948 -0.037186 0.046287 0.127937 0.016586 0.071463 0.108854 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.815125 -0.000656 0.014273 -0.944095 -0.006321 0.001399 0.007330 -37.511719 145.851562 -343.054688 -0.008080 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328754 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621321 0.305365 0.000000 -0.018707 0.009620 -0.036237 0.046311 0.126534 0.016645 0.073300 0.108360 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.820129 -0.001389 0.010855 -0.945804 -0.007385 0.001399 0.003073 -39.785156 143.554688 -340.664062 -0.008090 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329248 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622820 0.306418 0.000000 -0.018749 0.009779 -0.034973 0.046337 0.125153 0.017709 0.074765 0.107213 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.825134 -0.002609 0.008170 -0.943119 -0.003128 0.000335 -0.000119 -39.785156 143.554688 -340.664062 -0.008092 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329732 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623784 0.306922 0.000000 -0.018616 0.009112 -0.034025 0.046355 0.124739 0.019458 0.074913 0.105731 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.830139 -0.003098 0.009635 -0.939213 -0.006321 -0.000729 -0.004376 -42.058594 143.554688 -340.664062 -0.008121 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330206 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624030 0.308951 0.000000 -0.018476 0.009674 -0.032760 0.046361 0.122773 0.020299 0.076600 0.105168 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.835144 -0.005295 0.011344 -0.940189 -0.006321 -0.001794 -0.006505 -42.058594 143.554688 -340.664062 -0.008159 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330670 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623442 0.311372 0.000000 -0.018326 0.009721 -0.032128 0.046354 0.121943 0.021035 0.077129 0.104733 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.840149 -0.001877 0.001090 -0.938968 -0.006321 -0.000729 -0.008633 -37.511719 136.664062 -340.664062 -0.008202 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331125 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622607 0.313985 0.000000 -0.018499 0.009777 -0.031496 0.046341 0.121429 0.021438 0.077990 0.103983 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.845154 -0.004563 -0.000375 -0.941654 -0.003128 -0.000729 -0.009697 -37.511719 136.664062 -340.664062 -0.008228 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331168 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621248 0.315454 0.000000 -0.018477 0.009322 -0.031180 0.046319 0.121546 0.022231 0.077829 0.103235 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.850159 0.001053 0.004020 -0.942630 -0.003128 0.000335 -0.010762 -38.648438 137.812500 -341.859375 -0.008247 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331209 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619806 0.316422 0.000000 -0.018610 0.009379 -0.030864 0.046294 0.121305 0.022357 0.078335 0.102843 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.855164 -0.003342 0.001578 -0.943363 -0.007385 -0.000729 -0.008633 -38.648438 137.812500 -341.859375 -0.008277 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331250 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617827 0.318027 0.000000 -0.018391 0.010090 -0.031496 0.046259 0.121006 0.021233 0.078195 0.104406 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.860168 0.003982 0.001822 -0.938724 -0.006321 0.000335 -0.006505 -39.785156 141.257812 -352.617188 -0.008291 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331289 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616136 0.318632 0.000000 -0.018514 0.009910 -0.032128 0.046227 0.121943 0.020658 0.077505 0.104734 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.865173 0.004227 -0.000375 -0.945560 -0.004193 0.002463 -0.003312 -39.785156 141.257812 -352.617188 -0.008284 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331327 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615285 0.317955 0.000000 -0.018805 0.009551 -0.033077 0.046209 0.123541 0.019777 0.076490 0.105032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.870178 0.009354 0.005729 -0.948002 -0.003128 -0.000729 -0.000119 -39.785156 143.554688 -347.835938 -0.008262 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331363 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.613982 0.316436 0.000000 -0.018255 0.009359 -0.034025 0.046182 0.124130 0.019571 0.074799 0.106339 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.875183 0.006180 0.009879 -0.943119 -0.006321 0.001399 0.004137 -39.785156 143.554688 -347.835938 -0.008250 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331399 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.614070 0.315626 0.000000 -0.018594 0.009841 -0.035289 0.046178 0.125252 0.017486 0.074356 0.107746 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.880188 0.000076 0.004508 -0.940921 -0.007385 0.000335 0.008394 -43.195312 137.812500 -337.078125 -0.008243 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331434 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.614551 0.315160 0.000000 -0.018433 0.009965 -0.036553 0.046182 0.126232 0.016259 0.073054 0.109295 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.885193 0.003738 0.010611 -0.942875 -0.004193 0.001399 0.009459 -43.195312 137.812500 -337.078125 -0.008223 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331468 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615825 0.313967 0.000000 -0.018632 0.009416 -0.036869 0.046199 0.127296 0.016292 0.072389 0.108863 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.890198 0.004715 0.008658 -0.946048 -0.001000 0.003528 0.013715 -43.195312 137.812500 -337.078125 -0.008194 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331502 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618027 0.312255 0.000000 -0.019004 0.008901 -0.038134 0.046234 0.129446 0.015171 0.070981 0.109241 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.895203 0.003982 0.010855 -0.939457 -0.003128 0.001399 0.015844 -44.332031 143.554688 -340.664062 -0.008184 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619440 0.312043 0.000000 -0.018684 0.009273 -0.038751 0.046263 0.129381 0.014512 0.070427 0.110560 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.900208 -0.003342 0.008902 -0.942142 -0.007385 0.002463 0.016908 -44.332031 143.554688 -340.664062 -0.008203 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331567 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621587 0.313334 0.000000 -0.018901 0.009972 -0.039067 0.046300 0.129216 0.013280 0.071027 0.111358 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.905212 -0.003830 0.007437 -0.939213 -0.005257 0.000335 0.017972 -40.921875 142.406250 -346.640625 -0.008221 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331599 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622841 0.314408 0.000000 -0.018598 0.009643 -0.039383 0.046324 0.129558 0.013596 0.070078 0.111648 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.910217 -0.002365 0.010367 -0.947269 -0.002064 0.003528 0.019037 -40.921875 142.406250 -346.640625 -0.008229 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331630 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624540 0.314878 0.000000 -0.019139 0.009172 -0.039699 0.046356 0.130886 0.013210 0.069833 0.110952 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.915222 -0.001877 0.004020 -0.943607 -0.005257 0.001399 0.020101 -43.195312 137.812500 -339.468750 -0.008257 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331660 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624997 0.316531 0.000000 -0.018798 0.009741 -0.040015 0.046368 0.130292 0.012666 0.069744 0.112178 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.920227 -0.003830 0.006217 -0.943851 -0.008450 0.002463 0.017972 -43.195312 137.812500 -339.468750 -0.008303 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331690 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625559 0.319106 0.000000 -0.018974 0.010286 -0.039398 0.046376 0.129306 0.012562 0.071082 0.111930 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.925232 0.001541 0.002799 -0.944339 -0.001000 0.003528 0.016908 -37.511719 138.960938 -335.882812 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331719 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625576 0.319246 0.000000 -0.019118 0.009118 -0.039082 0.046381 0.130302 0.013902 0.070374 0.110302 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.930237 -0.005295 0.003775 -0.941654 -0.002064 0.002463 0.013715 -37.511719 138.960938 -335.882812 -0.008315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331747 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624894 0.319428 0.000000 -0.018909 0.009342 -0.038134 0.046373 0.128920 0.014836 0.071337 0.109787 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.935242 0.001541 0.006217 -0.938968 -0.005257 0.001399 0.011587 -36.375000 135.515625 -346.640625 -0.008332 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331775 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623634 0.320199 0.000000 -0.018701 0.009880 -0.037502 0.046355 0.127542 0.015138 0.072299 0.109901 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.940247 0.004227 0.005240 -0.947269 -0.007385 0.000335 0.008394 -36.375000 135.515625 -346.640625 -0.008354 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331803 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622018 0.320959 0.000000 -0.018499 0.010208 -0.036553 0.046330 0.126064 0.015960 0.073374 0.109483 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.945251 0.004471 0.001090 -0.945316 -0.002064 0.000335 0.006266 -39.785156 141.257812 -345.445312 -0.008344 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331829 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620668 0.320121 0.000000 -0.018479 0.009342 -0.035921 0.046307 0.126278 0.017478 0.073120 0.108005 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.950256 0.004959 0.005729 -0.941898 -0.002064 0.000335 0.003073 -39.785156 141.257812 -345.445312 -0.008329 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330851 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619780 0.319023 0.000000 -0.018470 0.009348 -0.034973 0.046292 0.125315 0.018429 0.074065 0.107071 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.955261 0.005203 0.006949 -0.943119 -0.005257 0.001399 0.000945 -35.238281 145.851562 -335.882812 -0.008326 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329892 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619764 0.318695 0.000000 -0.018645 0.009851 -0.034341 0.046290 0.124355 0.018383 0.075376 0.106767 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.960266 0.007645 0.002799 -0.940677 -0.005257 -0.001794 -0.002248 -35.238281 145.851562 -335.882812 -0.008321 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328953 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619041 0.318568 0.000000 -0.018144 0.009831 -0.033393 0.046283 0.122925 0.019852 0.075803 0.106300 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.965271 -0.003098 0.002799 -0.939457 -0.005257 -0.000729 -0.004376 -36.375000 135.515625 -339.468750 -0.008313 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619536 0.318039 0.000000 -0.018363 0.009802 -0.032760 0.046289 0.122542 0.020295 0.076624 0.105419 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.970276 0.009109 0.006705 -0.942386 -0.005257 0.001399 -0.006505 -36.375000 135.515625 -339.468750 -0.008303 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327130 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620978 0.317415 0.000000 -0.018750 0.009771 -0.032128 0.046313 0.122327 0.020572 0.077612 0.104369 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.975281 0.003006 0.002066 -0.947757 -0.004193 -0.001794 -0.006505 -35.238281 141.257812 -347.835938 -0.008287 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326246 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621720 0.316442 0.000000 -0.018284 0.009571 -0.032128 0.046326 0.122061 0.021237 0.076946 0.104635 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.980286 -0.000900 0.011100 -0.933841 -0.004193 -0.000729 -0.006505 -35.238281 141.257812 -347.835938 -0.008271 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325379 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622948 0.315534 0.000000 -0.018518 0.009549 -0.032128 0.046348 0.122317 0.021024 0.077159 0.104380 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.985291 -0.004074 0.006949 -0.935795 -0.006321 0.000335 -0.006505 -43.195312 140.109375 -339.468750 -0.008269 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324530 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624700 0.315479 0.000000 -0.018748 0.009872 -0.032128 0.046373 0.122224 0.020472 0.077712 0.104473 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.990295 -0.004807 0.008658 -0.940189 -0.006321 0.001399 -0.005441 -43.195312 140.109375 -339.468750 -0.008272 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323697 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625927 0.315728 0.000000 -0.018945 0.009853 -0.032444 0.046397 0.122756 0.019978 0.077574 0.104573 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+455.995300 -0.004318 0.004264 -0.942875 -0.004193 0.000335 -0.003312 -43.195312 140.109375 -339.468750 -0.008270 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322881 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626155 0.315635 0.000000 -0.018777 0.009508 -0.033077 0.046404 0.123565 0.019858 0.076429 0.105028 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.000305 -0.004318 0.002799 -0.944584 -0.004193 0.001399 -0.000119 -42.058594 143.554688 -340.664062 -0.008270 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322080 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625979 0.315704 0.000000 -0.018933 0.009521 -0.034025 0.046405 0.124657 0.018741 0.075649 0.105832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.005310 -0.005539 0.004020 -0.936039 -0.007385 -0.000729 0.000945 -42.058594 143.554688 -340.664062 -0.008286 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321295 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624474 0.316382 0.000000 -0.018556 0.010029 -0.034341 0.046382 0.124077 0.018285 0.075454 0.107024 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.010315 -0.000656 0.004996 -0.936039 -0.006321 0.000335 0.005202 -39.785156 141.257812 -340.664062 -0.008294 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320525 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622739 0.316882 0.000000 -0.018682 0.009847 -0.035605 0.046355 0.125650 0.017076 0.074133 0.107980 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.015320 0.000809 0.001578 -0.944095 -0.002064 0.002463 0.008394 -39.785156 141.257812 -340.664062 -0.008279 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319770 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621322 0.315953 0.000000 -0.018960 0.009162 -0.036553 0.046331 0.127561 0.016535 0.072779 0.107966 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.020325 0.002762 0.001578 -0.944339 -0.004193 0.001399 0.013715 -43.195312 142.406250 -337.078125 -0.008270 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319029 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619577 0.315451 0.000000 -0.018718 0.009512 -0.038134 0.046300 0.128550 0.014846 0.071306 0.110137 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.025330 -0.002365 0.006705 -0.943363 -0.006321 0.001399 0.015844 -43.195312 142.406250 -337.078125 -0.008267 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318303 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618032 0.315329 0.000000 -0.018661 0.009837 -0.038766 0.046272 0.128801 0.013946 0.070942 0.111151 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.030334 0.003738 0.001822 -0.944828 -0.006321 0.002463 0.016908 -36.375000 140.109375 -344.250000 -0.008261 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317591 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617076 0.315019 0.000000 -0.018783 0.009805 -0.039082 0.046252 0.129270 0.013540 0.070716 0.111314 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.035339 0.003982 0.005484 -0.942386 -0.003128 0.003528 0.017972 -36.375000 140.109375 -344.250000 -0.008237 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316893 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616809 0.313651 0.000000 -0.018911 0.009265 -0.039398 0.046244 0.130254 0.013636 0.069988 0.110963 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.040344 0.003738 0.007926 -0.946293 -0.003128 0.001399 0.021165 -40.921875 140.109375 -349.031250 -0.008213 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316208 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616404 0.312325 0.000000 -0.018543 0.009254 -0.040346 0.046233 0.130846 0.013066 0.068661 0.112267 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.045349 0.009354 0.005729 -0.946781 -0.006321 0.001399 0.020101 -40.921875 140.109375 -349.031250 -0.008206 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315538 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616601 0.312119 0.000000 -0.018548 0.009752 -0.040030 0.046232 0.130037 0.012880 0.069480 0.112444 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.050354 0.005936 0.010611 -0.945560 -0.007385 0.002463 0.016908 -43.195312 144.703125 -339.468750 -0.008209 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315685 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617795 0.312767 0.000000 -0.018743 0.009907 -0.039082 0.046249 0.129138 0.013489 0.070788 0.111466 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.055359 0.003982 0.008902 -0.941654 -0.002064 0.002463 0.016908 -43.195312 144.703125 -339.468750 -0.008192 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315829 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619605 0.311902 0.000000 -0.018781 0.009047 -0.039082 0.046277 0.130036 0.014310 0.069966 0.110568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.060364 -0.002609 0.008902 -0.940677 -0.004193 0.000335 0.015844 -36.375000 142.406250 -341.859375 -0.008193 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315971 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621135 0.312150 0.000000 -0.018493 0.009418 -0.038766 0.046302 0.129061 0.014543 0.070366 0.110911 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.065369 0.003006 0.012076 -0.944339 -0.008450 0.000335 0.012651 -36.375000 142.406250 -341.859375 -0.008224 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316111 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622712 0.314095 0.000000 -0.018559 0.010124 -0.037818 0.046330 0.127473 0.014720 0.072085 0.110603 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.070374 -0.006760 0.002555 -0.943851 -0.004193 0.000335 0.008394 -37.511719 136.664062 -345.445312 -0.008240 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623699 0.315094 0.000000 -0.018604 0.009462 -0.036553 0.046354 0.126916 0.016601 0.072732 0.108631 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.075378 0.003006 0.005484 -0.944339 -0.006321 0.002463 0.006266 -37.511719 136.664062 -345.445312 -0.008269 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316382 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625243 0.316840 0.000000 -0.018984 0.009847 -0.035921 0.046383 0.126278 0.016468 0.074130 0.108005 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.080383 -0.000412 0.005729 -0.945072 -0.003128 0.002463 0.003073 -37.511719 138.960938 -343.054688 -0.008283 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316514 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626319 0.317529 0.000000 -0.018998 0.009371 -0.034973 0.046406 0.125820 0.017879 0.074615 0.106566 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.085388 -0.002365 0.001578 -0.945072 -0.005257 -0.002858 -0.000119 -37.511719 138.960938 -343.054688 -0.008304 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316644 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625425 0.318643 0.000000 -0.018157 0.009753 -0.034025 0.046395 0.123648 0.019285 0.075105 0.106841 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.090393 -0.001145 0.010123 -0.947757 -0.006321 0.002463 -0.005441 -37.511719 143.554688 -345.445312 -0.008326 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316771 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625749 0.319777 0.000000 -0.019027 0.009942 -0.032444 0.046404 0.122749 0.019806 0.077745 0.104580 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.095398 -0.008225 0.001578 -0.939457 -0.004193 -0.001794 -0.005441 -37.511719 143.554688 -345.445312 -0.008333 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316896 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624719 0.320025 0.000000 -0.018336 0.009612 -0.032429 0.046384 0.122373 0.020843 0.076738 0.104925 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.100403 -0.004074 0.005240 -0.943851 -0.004193 0.001399 -0.006505 -37.511719 143.554688 -345.445312 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317019 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623768 0.320040 0.000000 -0.018828 0.009626 -0.032113 0.046370 0.122536 0.020653 0.077561 0.104131 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.105408 -0.004318 0.002799 -0.948978 -0.003128 0.000335 -0.006505 -34.101562 142.406250 -344.250000 -0.008331 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317140 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621967 0.319479 0.000000 -0.018606 0.009462 -0.032113 0.046341 0.122477 0.021040 0.077174 0.104189 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.110413 0.004471 0.004020 -0.942875 -0.008450 -0.000729 -0.005441 -34.101562 142.406250 -344.250000 -0.008346 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317259 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619559 0.320234 0.000000 -0.018382 0.010308 -0.032429 0.046299 0.121723 0.020101 0.077481 0.105576 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.115417 0.004715 0.004752 -0.945560 -0.001000 -0.000729 -0.003312 -37.511719 143.554688 -333.492188 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317376 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617265 0.318221 0.000000 -0.018335 0.009077 -0.033077 0.046258 0.123544 0.020722 0.075545 0.105029 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.120422 0.003982 0.002311 -0.939457 -0.004193 -0.000729 -0.002248 -37.511719 143.554688 -333.492188 -0.008306 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317491 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615420 0.317339 0.000000 -0.018299 0.009589 -0.033393 0.046223 0.123312 0.019929 0.075705 0.105893 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.125427 0.007645 0.013297 -0.947757 -0.006321 0.001399 -0.000119 -40.921875 140.109375 -339.468750 -0.008302 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317604 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.614847 0.317051 0.000000 -0.018618 0.009906 -0.034025 0.046208 0.123946 0.018661 0.075709 0.106523 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.130432 0.010086 0.000602 -0.946537 -0.007385 -0.000729 0.003073 -40.921875 140.109375 -339.468750 -0.008305 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317715 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.614442 0.317183 0.000000 -0.018271 0.010045 -0.034973 0.046196 0.124408 0.017921 0.074553 0.107958 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.135437 0.001053 0.006949 -0.943607 -0.005257 0.000335 0.005202 -42.058594 143.554688 -340.664062 -0.008298 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317825 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615196 0.316782 0.000000 -0.018470 0.009677 -0.035605 0.046203 0.125608 0.017458 0.073752 0.108022 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.140442 0.007400 0.009635 -0.941898 -0.003128 0.002463 0.007330 -42.058594 143.554688 -340.664062 -0.008283 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317932 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617213 0.315907 0.000000 -0.018849 0.009330 -0.036237 0.046233 0.126966 0.016794 0.073152 0.107928 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.145447 0.003250 0.008170 -0.945316 -0.006321 0.001399 0.011587 -42.058594 141.257812 -345.445312 -0.008289 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318037 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619346 0.316276 0.000000 -0.018722 0.009849 -0.037502 0.046267 0.127585 0.015137 0.072279 0.109838 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.150452 0.005447 0.009146 -0.947025 -0.003128 0.002463 0.012651 -42.058594 141.257812 -345.445312 -0.008284 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318141 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622071 0.316025 0.000000 -0.018952 0.009342 -0.037818 0.046312 0.128637 0.015099 0.071686 0.109418 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.155457 0.001785 0.008658 -0.943851 -0.004193 0.003528 0.015844 -38.648438 140.109375 -341.859375 -0.008291 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318042 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625199 0.316456 0.000000 -0.019179 0.009542 -0.038766 0.046367 0.129613 0.013723 0.071166 0.110339 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.160461 0.000076 0.007926 -0.947269 -0.005257 0.002463 0.016908 -38.648438 140.109375 -341.859375 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317945 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627878 0.317804 0.000000 -0.019062 0.009752 -0.039082 0.046417 0.129602 0.013314 0.070942 0.110982 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.165466 -0.003342 0.005484 -0.946537 -0.005257 0.000335 0.017972 -37.511719 141.257812 -340.664062 -0.008330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317851 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629561 0.319026 0.000000 -0.018775 0.009781 -0.039398 0.046452 0.129602 0.013256 0.070368 0.111614 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.170471 -0.006271 0.003531 -0.942875 -0.006321 0.000335 0.017972 -37.511719 141.257812 -340.664062 -0.008357 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317759 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630636 0.320549 0.000000 -0.018822 0.009980 -0.039398 0.046477 0.129450 0.013010 0.070614 0.111766 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.175476 -0.008713 0.006217 -0.943119 -0.005257 0.003528 0.017972 -37.511719 143.554688 -343.054688 -0.008378 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317669 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631780 0.321574 0.000000 -0.019348 0.009830 -0.039398 0.046504 0.130126 0.012634 0.070990 0.111091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.180481 -0.001633 0.001822 -0.941654 -0.004193 0.002463 0.015844 -37.511719 143.554688 -343.054688 -0.008389 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317582 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631247 0.322028 0.000000 -0.019138 0.009681 -0.038751 0.046509 0.129427 0.013650 0.071288 0.110514 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.185486 -0.007492 0.005729 -0.943851 -0.005257 0.001399 0.014780 -40.921875 144.703125 -339.468750 -0.008400 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317496 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629907 0.322487 0.000000 -0.018923 0.009867 -0.038435 0.046493 0.128710 0.013995 0.071576 0.110599 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.190491 -0.000412 0.003287 -0.947757 -0.003128 0.002463 0.010523 -40.921875 144.703125 -339.468750 -0.008396 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628223 0.322005 0.000000 -0.019034 0.009530 -0.037170 0.046471 0.127895 0.015486 0.072613 0.108886 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.195496 -0.005539 0.005240 -0.942630 -0.004193 -0.000729 0.010523 -38.648438 142.406250 -344.250000 -0.008392 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625169 0.321594 0.000000 -0.018450 0.009704 -0.037170 0.046423 0.127136 0.015896 0.072203 0.109644 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.200500 0.005447 0.004020 -0.943851 -0.004193 0.001399 0.006266 -38.648438 142.406250 -344.250000 -0.008384 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317251 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622629 0.320981 0.000000 -0.018727 0.009694 -0.035906 0.046381 0.126159 0.016893 0.073735 0.108093 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.205505 0.000564 0.002066 -0.942142 -0.003128 -0.000729 0.005202 -38.648438 142.406250 -344.250000 -0.008367 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317173 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620033 0.319881 0.000000 -0.018329 0.009509 -0.035605 0.046329 0.125646 0.017777 0.073452 0.108005 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.210510 0.005447 0.007682 -0.948734 -0.007385 -0.001794 0.000945 -39.785156 136.664062 -347.835938 -0.008368 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617271 0.319909 0.000000 -0.018117 0.010169 -0.034341 0.046279 0.123508 0.018593 0.075165 0.107614 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.215515 0.005936 0.005240 -0.946781 -0.004193 0.001399 -0.000119 -39.785156 136.664062 -347.835938 -0.008353 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317023 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616163 0.318940 0.000000 -0.018604 0.009620 -0.034025 0.046255 0.124229 0.018972 0.075419 0.106260 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.220520 0.005936 0.009879 -0.942142 -0.004193 -0.000729 -0.001184 -37.511719 143.554688 -352.617188 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316950 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615223 0.318116 0.000000 -0.018247 0.009604 -0.033709 0.046233 0.123572 0.019660 0.075362 0.106285 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.225525 0.005203 0.005240 -0.943363 -0.006321 0.001399 -0.003312 -37.511719 143.554688 -352.617188 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316879 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.615729 0.318166 0.000000 -0.018604 0.009932 -0.033077 0.046235 0.122968 0.019607 0.076680 0.105625 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.230530 0.008133 0.007682 -0.939457 -0.004193 -0.000729 -0.003312 -38.648438 142.406250 -346.640625 -0.008332 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316809 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.616341 0.317824 0.000000 -0.018292 0.009579 -0.033077 0.046240 0.123010 0.020272 0.076015 0.105583 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.235535 0.004471 0.009879 -0.945072 -0.007385 0.001399 -0.003312 -38.648438 142.406250 -346.640625 -0.008346 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316741 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618247 0.318701 0.000000 -0.018690 0.010094 -0.033077 0.046267 0.122893 0.019360 0.076927 0.105701 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.240540 0.008865 0.009879 -0.951664 -0.003128 0.000335 -0.002248 -39.785156 141.257812 -333.492188 -0.008345 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316675 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620349 0.318632 0.000000 -0.018581 0.009416 -0.033393 0.046300 0.123778 0.019830 0.075825 0.105447 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.245544 -0.001389 0.006461 -0.947025 -0.005257 0.001399 -0.001184 -39.785156 141.257812 -333.492188 -0.008360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316610 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623090 0.319549 0.000000 -0.018828 0.009791 -0.033709 0.046346 0.123965 0.018892 0.076130 0.105892 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.250549 0.005691 0.005240 -0.945072 -0.004193 0.001399 0.000945 -37.511719 138.960938 -338.273438 -0.008374 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316547 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625868 0.320338 0.000000 -0.018900 0.009650 -0.034341 0.046394 0.124811 0.018329 0.075429 0.106311 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.255554 -0.003586 0.007926 -0.940677 -0.006321 0.002463 0.003073 -37.511719 138.960938 -338.273438 -0.008400 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315681 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628748 0.321803 0.000000 -0.019136 0.010023 -0.034973 0.046447 0.125306 0.017088 0.075406 0.107080 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.260559 -0.002121 0.009879 -0.942630 -0.005257 0.002463 0.005202 -42.058594 143.554688 -345.445312 -0.008422 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314834 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631141 0.322956 0.000000 -0.019184 0.009877 -0.035605 0.046493 0.126132 0.016554 0.074675 0.107518 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.265564 -0.001877 0.001334 -0.947757 -0.005257 0.000335 0.006266 -42.058594 143.554688 -345.445312 -0.008444 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314003 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632228 0.324087 0.000000 -0.018876 0.009907 -0.035921 0.046519 0.126111 0.016516 0.074082 0.108172 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.270569 -0.006516 0.008170 -0.947269 -0.005257 0.000335 0.009459 -35.238281 138.960938 -338.273438 -0.008465 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313190 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632583 0.324764 0.000000 -0.018899 0.009924 -0.036869 0.046533 0.127054 0.015518 0.073164 0.109104 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.275574 -0.002121 0.003043 -0.947757 -0.004193 0.001399 0.011587 -35.238281 138.960938 -338.273438 -0.008477 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312393 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632468 0.325208 0.000000 -0.019066 0.009775 -0.037502 0.046539 0.128002 0.014868 0.072549 0.109421 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.280579 -0.001389 0.010367 -0.948978 -0.005257 0.002463 0.012651 -39.785156 138.960938 -347.835938 -0.008491 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311612 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631977 0.325785 0.000000 -0.019205 0.009965 -0.037818 0.046537 0.128268 0.014223 0.072562 0.109788 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.285583 -0.003342 0.001090 -0.946048 -0.004193 0.001399 0.012651 -39.785156 138.960938 -347.835938 -0.008497 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310848 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630656 0.325892 0.000000 -0.018985 0.009804 -0.037818 0.046521 0.128208 0.014603 0.072182 0.109847 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.290588 0.003250 0.001334 -0.939701 -0.005257 -0.001794 0.012651 -44.332031 143.554688 -345.445312 -0.008505 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310100 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628115 0.326369 0.000000 -0.018427 0.009990 -0.037818 0.046482 0.127475 0.014985 0.071819 0.110601 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.295593 -0.002609 0.003531 -0.946293 -0.004193 0.001399 0.011587 -44.332031 143.554688 -345.445312 -0.008500 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309367 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626498 0.325857 0.000000 -0.018901 0.009810 -0.037502 0.046457 0.127812 0.015008 0.072429 0.109631 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.300598 0.007645 0.004264 -0.934086 -0.007385 0.001399 0.011587 -42.058594 145.851562 -343.054688 -0.008505 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308649 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625031 0.325953 0.000000 -0.018849 0.010303 -0.037502 0.046432 0.127268 0.014567 0.072870 0.110175 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.305603 -0.002121 0.006461 -0.937992 -0.004193 0.001399 0.011587 -42.058594 145.851562 -343.054688 -0.008490 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307946 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623894 0.324866 0.000000 -0.018808 0.009755 -0.037502 0.046412 0.127775 0.015155 0.072282 0.109668 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.310608 0.010086 0.002799 -0.940433 -0.006321 -0.000729 0.009459 -42.058594 145.851562 -343.054688 -0.008483 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307257 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622582 0.324331 0.000000 -0.018444 0.010072 -0.036869 0.046389 0.126461 0.015835 0.072867 0.109718 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.315613 0.007156 0.009146 -0.945316 -0.004193 0.001399 0.007330 -42.058594 145.851562 -345.445312 -0.008465 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306582 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622554 0.322865 0.000000 -0.018788 0.009691 -0.036237 0.046386 0.126544 0.016494 0.073451 0.108350 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.320618 0.006668 0.006217 -0.942142 -0.005257 0.001399 0.007330 -42.058594 145.851562 -345.445312 -0.008454 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305919 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623275 0.322179 0.000000 -0.018801 0.009844 -0.036237 0.046395 0.126404 0.016328 0.073618 0.108491 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.325623 0.007400 0.006949 -0.940921 -0.004193 0.000335 0.005202 -38.648438 140.109375 -346.640625 -0.008441 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305270 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624388 0.321418 0.000000 -0.018667 0.009659 -0.035605 0.046413 0.125823 0.017278 0.073932 0.107807 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.330627 0.002273 0.012076 -0.939213 -0.004193 0.002463 0.005202 -38.648438 140.109375 -346.640625 -0.008433 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304633 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626697 0.320991 0.000000 -0.019065 0.009660 -0.035605 0.046451 0.126220 0.016881 0.074329 0.107410 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.335632 0.001297 0.005484 -0.945804 -0.005257 0.001399 0.004137 -38.648438 140.109375 -344.250000 -0.008437 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304008 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628946 0.321279 0.000000 -0.018950 0.009839 -0.035289 0.046491 0.125610 0.017132 0.074710 0.107388 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.340637 0.001785 0.010855 -0.946048 -0.003128 0.000335 0.004137 -38.648438 140.109375 -344.250000 -0.008436 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303395 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630868 0.321301 0.000000 -0.018843 0.009516 -0.035289 0.046526 0.125827 0.017562 0.074280 0.107171 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.345642 -0.004074 0.003531 -0.945072 -0.004193 0.001399 0.003073 -32.964844 134.367188 -347.835938 -0.008446 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302795 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632846 0.321932 0.000000 -0.019073 0.009720 -0.034973 0.046564 0.125536 0.017444 0.075031 0.106830 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.350647 -0.002609 0.010855 -0.941654 -0.005257 -0.001794 0.003073 -32.964844 134.367188 -347.835938 -0.008465 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302206 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633362 0.323039 0.000000 -0.018605 0.009921 -0.034973 0.046579 0.124867 0.017712 0.074762 0.107499 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.355652 -0.007980 0.005240 -0.942142 -0.004193 0.001399 0.003073 -40.921875 135.515625 -346.640625 -0.008481 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302231 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634125 0.323918 0.000000 -0.019147 0.009779 -0.034973 0.046598 0.125551 0.017311 0.075163 0.106815 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.360657 -0.004807 0.004020 -0.939701 -0.006321 -0.000729 0.002009 -40.921875 135.515625 -346.640625 -0.008508 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302256 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633021 0.325708 0.000000 -0.018785 0.010159 -0.034642 0.046591 0.124487 0.017634 0.075523 0.107236 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.365662 -0.001389 0.006461 -0.948490 -0.004193 0.000335 0.003073 -39.785156 136.664062 -340.664062 -0.008522 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302280 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631808 0.326386 0.000000 -0.018930 0.009837 -0.034958 0.046576 0.125271 0.017495 0.075029 0.107084 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.370667 -0.003342 0.000846 -0.944095 -0.006321 -0.000729 0.003073 -39.785156 136.664062 -340.664062 -0.008542 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302303 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629698 0.327436 0.000000 -0.018712 0.010197 -0.034958 0.046543 0.124692 0.017354 0.075171 0.107663 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.375671 -0.002121 0.010367 -0.942142 -0.003128 0.000335 0.003073 -38.648438 140.109375 -341.859375 -0.008543 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302326 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627536 0.327240 0.000000 -0.018825 0.009690 -0.034958 0.046508 0.125313 0.017747 0.074778 0.107043 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.380676 -0.003342 -0.002084 -0.944095 -0.003128 0.000335 0.005202 -38.648438 140.109375 -341.859375 -0.008539 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302348 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625518 0.326812 0.000000 -0.018766 0.009704 -0.035605 0.046468 0.125887 0.017145 0.074085 0.107763 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.385681 -0.001877 0.006461 -0.944339 -0.007385 -0.000729 0.005202 -36.375000 140.109375 -341.859375 -0.008550 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302370 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622734 0.327346 0.000000 -0.018524 0.010382 -0.035605 0.046418 0.124968 0.016709 0.074520 0.108683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.390686 0.004227 0.004020 -0.945316 -0.004193 0.001399 0.007330 -36.375000 140.109375 -341.859375 -0.008541 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302392 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620696 0.326620 0.000000 -0.018798 0.009840 -0.036237 0.046379 0.126415 0.016344 0.073621 0.108499 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.395691 0.003006 0.001822 -0.942875 -0.005257 0.001399 0.006266 -35.238281 141.257812 -347.835938 -0.008533 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619008 0.326006 0.000000 -0.018731 0.009992 -0.035921 0.046345 0.125881 0.016576 0.074022 0.108401 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.400696 0.006912 0.012076 -0.945804 -0.004193 0.000335 0.007330 -35.238281 141.257812 -347.835938 -0.008517 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302434 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617596 0.324668 0.000000 -0.018515 0.009785 -0.036237 0.046314 0.126177 0.016672 0.073273 0.108717 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.405701 0.003738 0.000113 -0.943119 -0.005257 0.001399 0.008394 -39.785156 138.960938 -343.054688 -0.008506 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302455 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617230 0.324003 0.000000 -0.018667 0.009935 -0.036553 0.046301 0.126495 0.016055 0.073258 0.109031 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.410706 0.004471 0.009391 -0.947269 -0.004193 0.000335 0.009459 -39.785156 138.960938 -343.054688 -0.008491 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302475 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.617256 0.323109 0.000000 -0.018495 0.009741 -0.036869 0.046294 0.126833 0.016104 0.072577 0.109326 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.415710 0.003494 0.003287 -0.944339 -0.004193 0.003528 0.009459 -39.785156 138.960938 -343.054688 -0.008477 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302495 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.618822 0.322338 0.000000 -0.019025 0.009728 -0.036869 0.046314 0.127376 0.015588 0.073093 0.108783 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.420715 0.005691 0.003043 -0.940677 -0.005257 0.000335 0.010523 -43.195312 144.703125 -344.250000 -0.008469 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302515 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619893 0.321967 0.000000 -0.018535 0.009884 -0.037186 0.046327 0.127047 0.015605 0.072444 0.109744 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.425720 0.005691 0.009879 -0.937015 -0.004193 0.002463 0.010523 -43.195312 144.703125 -344.250000 -0.008457 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622003 0.321630 0.000000 -0.018926 0.009706 -0.037186 0.046359 0.127625 0.015402 0.072667 0.109186 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.430725 0.001053 0.004508 -0.943607 -0.006321 0.001399 0.009459 -36.375000 137.812500 -346.640625 -0.008457 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302554 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624054 0.321767 0.000000 -0.018805 0.010038 -0.036869 0.046392 0.126857 0.015507 0.073194 0.109322 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.435730 0.001541 0.006461 -0.945804 -0.004193 0.001399 0.008394 -36.375000 137.812500 -346.640625 -0.008449 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302573 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626158 0.321407 0.000000 -0.018863 0.009684 -0.036553 0.046428 0.126952 0.016119 0.073215 0.108594 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.440735 -0.000656 0.004996 -0.944339 -0.005257 0.001399 0.008394 -38.648438 140.109375 -339.468750 -0.008448 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302591 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628098 0.321479 0.000000 -0.018917 0.009856 -0.036553 0.046463 0.126834 0.015893 0.073440 0.108712 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.445740 -0.002121 0.004752 -0.948246 -0.003128 0.001399 0.005202 -38.648438 140.109375 -339.468750 -0.008438 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302609 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629675 0.320679 0.000000 -0.018961 0.009507 -0.035605 0.046493 0.126269 0.017138 0.074072 0.107361 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.450745 0.000564 0.011344 -0.947269 -0.006321 0.001399 0.005202 -40.921875 140.109375 -349.031250 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302626 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630778 0.321218 0.000000 -0.018990 0.010026 -0.035605 0.046516 0.125779 0.016588 0.074622 0.107851 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.455750 -0.004807 0.005240 -0.946537 -0.004193 0.001399 0.003073 -40.921875 140.109375 -349.031250 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302644 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631357 0.321274 0.000000 -0.019005 0.009685 -0.034973 0.046531 0.125503 0.017547 0.074927 0.106863 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.460754 -0.001389 0.007926 -0.940921 -0.002064 -0.000729 0.002009 -40.921875 140.109375 -346.640625 -0.008437 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303063 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630753 0.320888 0.000000 -0.018665 0.009364 -0.034657 0.046526 0.125168 0.018525 0.074582 0.106566 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.465759 -0.005539 0.007682 -0.946537 -0.005257 0.001399 0.003073 -40.921875 140.109375 -346.640625 -0.008448 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303474 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630251 0.321617 0.000000 -0.018997 0.009903 -0.034973 0.046522 0.125277 0.017337 0.075138 0.107089 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.470764 -0.003586 0.005729 -0.946293 -0.005257 0.000335 0.002009 -36.375000 144.703125 -344.250000 -0.008461 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303877 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628891 0.322441 0.000000 -0.018791 0.009916 -0.034657 0.046502 0.124752 0.017856 0.075271 0.107002 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.475769 0.001053 0.003531 -0.943363 -0.004193 0.001399 0.002009 -36.375000 144.703125 -344.250000 -0.008469 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304272 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627439 0.322939 0.000000 -0.018917 0.009761 -0.034657 0.046480 0.125033 0.017884 0.075242 0.106721 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.480774 -0.001877 0.003287 -0.945804 -0.004193 0.000335 0.003073 -39.785156 138.960938 -347.835938 -0.008475 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304660 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625480 0.323289 0.000000 -0.018693 0.009778 -0.034973 0.046448 0.125107 0.017776 0.074718 0.107278 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.485779 0.008865 0.006217 -0.946537 -0.006321 -0.000729 0.003073 -39.785156 138.960938 -347.835938 -0.008489 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305040 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623310 0.324038 0.000000 -0.018478 0.010125 -0.034973 0.046410 0.124545 0.017644 0.074850 0.107841 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.490784 0.005936 0.001578 -0.941654 -0.005257 0.001399 0.003073 -44.332031 148.148438 -340.664062 -0.008493 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622242 0.324204 0.000000 -0.018789 0.009945 -0.034973 0.046389 0.125027 0.017503 0.074971 0.107339 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.495789 0.007400 0.002799 -0.938724 -0.004193 0.000335 0.004137 -44.332031 148.148438 -340.664062 -0.008486 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305778 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621563 0.323762 0.000000 -0.018599 0.009765 -0.035289 0.046374 0.125334 0.017557 0.074285 0.107664 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.500793 0.004227 0.006461 -0.944095 -0.003128 0.000335 0.005202 -42.058594 143.554688 -345.445312 -0.008470 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306137 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621656 0.322748 0.000000 -0.018609 0.009584 -0.035605 0.046372 0.125841 0.017412 0.073798 0.107790 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.505798 0.004471 0.002799 -0.943851 -0.005257 0.001399 0.004137 -42.058594 143.554688 -345.445312 -0.008461 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306488 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622721 0.322215 0.000000 -0.018807 0.009910 -0.035289 0.046387 0.125396 0.017204 0.074638 0.107602 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.510803 0.005447 0.004508 -0.937992 -0.003128 0.001399 0.006266 -45.468750 144.703125 -344.250000 -0.008439 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624289 0.321232 0.000000 -0.018844 0.009551 -0.035921 0.046412 0.126424 0.016894 0.073684 0.107838 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.515808 0.000809 0.003775 -0.945072 -0.004193 0.002463 0.007330 -45.468750 144.703125 -344.250000 -0.008420 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307169 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626492 0.320206 0.000000 -0.019061 0.009701 -0.036237 0.046448 0.126807 0.016211 0.073735 0.108088 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.520813 0.002518 0.006949 -0.941410 -0.005257 0.001399 0.008394 -45.468750 144.703125 -344.250000 -0.008405 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307499 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628466 0.319490 0.000000 -0.018937 0.009843 -0.036553 0.046483 0.126857 0.015876 0.073437 0.108669 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.525818 -0.001633 0.005240 -0.940433 -0.005257 0.001399 0.008394 -38.648438 133.218750 -344.250000 -0.008392 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307823 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630318 0.318854 0.000000 -0.018988 0.009812 -0.036553 0.046517 0.126939 0.015857 0.073457 0.108587 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.530823 0.000564 0.006217 -0.942875 -0.005257 0.000335 0.008394 -38.648438 133.218750 -344.250000 -0.008380 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308139 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631555 0.318361 0.000000 -0.018861 0.009787 -0.036553 0.046542 0.126838 0.016009 0.073304 0.108689 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.535828 -0.004563 0.009146 -0.941166 -0.005257 0.001399 0.009459 -46.605469 148.148438 -345.445312 -0.008372 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308448 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632308 0.318076 0.000000 -0.019055 0.009769 -0.036854 0.046566 0.127360 0.015542 0.073189 0.108788 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.540833 -0.003830 0.005240 -0.942386 -0.006321 0.000335 0.010523 -46.605469 148.148438 -345.445312 -0.008374 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308751 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632518 0.318367 0.000000 -0.018896 0.009929 -0.037170 0.046575 0.127358 0.015225 0.072875 0.109423 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.545837 -0.001633 0.005484 -0.938968 -0.005257 0.000335 0.011587 -34.101562 135.515625 -344.250000 -0.008374 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309048 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632106 0.318545 0.000000 -0.018895 0.009752 -0.037486 0.046573 0.127849 0.015087 0.072380 0.109564 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.550842 -0.002854 0.003775 -0.937748 -0.003128 0.002463 0.011587 -34.101562 135.515625 -344.250000 -0.008366 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309337 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631771 0.318204 0.000000 -0.019213 0.009418 -0.037486 0.046571 0.128501 0.015103 0.072365 0.108911 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.555847 -0.003098 0.004996 -0.942630 -0.004193 0.000335 0.011587 -39.785156 138.960938 -340.664062 -0.008363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309621 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630695 0.317905 0.000000 -0.018839 0.009595 -0.037502 0.046551 0.127966 0.015284 0.072153 0.109478 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.560852 -0.000656 0.004752 -0.943119 -0.005257 0.001399 0.009459 -39.785156 138.960938 -340.664062 -0.008365 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309496 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629241 0.318170 0.000000 -0.018966 0.009771 -0.036869 0.046529 0.127285 0.015613 0.073088 0.108894 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.565857 -0.001877 0.002799 -0.943119 -0.003128 0.001399 0.008394 -44.332031 150.445312 -343.054688 -0.008355 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309373 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627596 0.317697 0.000000 -0.018911 0.009429 -0.036553 0.046502 0.127255 0.016326 0.073007 0.108291 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.570862 0.004471 0.006217 -0.943119 -0.005257 0.000335 0.007330 -44.332031 150.445312 -343.054688 -0.008354 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309252 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625648 0.317741 0.000000 -0.018688 0.009773 -0.036237 0.046468 0.126372 0.016521 0.073444 0.108542 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.575867 0.003006 0.008170 -0.943363 -0.005257 0.001399 0.006266 -36.375000 147.000000 -346.640625 -0.008352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309133 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624286 0.317721 0.000000 -0.018818 0.009763 -0.035921 0.046443 0.126196 0.016718 0.073879 0.108086 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.580872 0.003006 0.005484 -0.944339 -0.006321 -0.000729 0.004137 -36.375000 147.000000 -346.640625 -0.008356 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309016 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622730 0.318364 0.000000 -0.018446 0.009933 -0.035289 0.046414 0.125023 0.017552 0.074310 0.107995 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.585876 0.002762 0.004996 -0.938480 -0.004193 0.001399 0.004137 -37.511719 145.851562 -340.664062 -0.008350 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308901 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622308 0.318131 0.000000 -0.018779 0.009584 -0.035289 0.046403 0.125704 0.017569 0.074293 0.107314 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.590881 0.005447 0.005729 -0.944339 -0.004193 0.001399 0.003073 -37.511719 145.851562 -340.664062 -0.008345 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308788 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622368 0.317950 0.000000 -0.018772 0.009588 -0.034973 0.046400 0.125377 0.017886 0.074608 0.107009 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.595886 0.004471 0.007437 -0.941410 -0.005257 -0.000729 0.003073 -37.511719 141.257812 -345.445312 -0.008347 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308677 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622299 0.318136 0.000000 -0.018444 0.009763 -0.034973 0.046395 0.124874 0.018040 0.074454 0.107512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.600891 0.005936 0.006705 -0.939945 -0.003128 0.001399 0.002009 -37.511719 141.257812 -345.445312 -0.008340 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623366 0.317482 0.000000 -0.018819 0.009417 -0.034657 0.046409 0.125270 0.018317 0.074789 0.106464 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.605896 0.001785 0.006949 -0.939457 -0.003128 0.001399 0.002009 -38.648438 140.109375 -346.640625 -0.008334 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308461 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624820 0.317268 0.000000 -0.018854 0.009434 -0.034657 0.046431 0.125286 0.018265 0.074841 0.106447 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.610901 -0.000412 0.004508 -0.941654 -0.005257 -0.000729 0.002009 -38.648438 140.109375 -346.640625 -0.008342 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308356 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625831 0.317783 0.000000 -0.018557 0.009790 -0.034657 0.046447 0.124634 0.018206 0.074900 0.107100 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.615906 0.000809 0.011100 -0.939701 -0.005257 0.001399 0.002009 -40.921875 137.812500 -346.640625 -0.008350 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308253 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627437 0.318361 0.000000 -0.018948 0.009796 -0.034657 0.046475 0.125019 0.017809 0.075297 0.106715 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.620911 -0.000900 0.006461 -0.942386 -0.004193 0.001399 0.002009 -40.921875 137.812500 -346.640625 -0.008357 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308151 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628451 0.319058 0.000000 -0.018968 0.009647 -0.034657 0.046499 0.125199 0.017948 0.075178 0.106555 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.625916 -0.002121 0.005240 -0.937748 -0.003128 0.002463 0.002009 -40.921875 137.812500 -346.640625 -0.008360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308051 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629781 0.319268 0.000000 -0.019159 0.009499 -0.034657 0.046524 0.125537 0.017905 0.075222 0.106217 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.630920 -0.001633 0.010855 -0.938480 -0.004193 0.002463 0.003073 -38.648438 140.109375 -349.031250 -0.008370 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307952 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630650 0.319883 0.000000 -0.019162 0.009698 -0.034973 0.046542 0.125657 0.017387 0.075107 0.106729 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.635925 -0.005295 0.006217 -0.941410 -0.005257 0.001399 0.003073 -38.648438 140.109375 -349.031250 -0.008388 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307855 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630681 0.320914 0.000000 -0.018983 0.009892 -0.034973 0.046546 0.125285 0.017372 0.075122 0.107101 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.640930 -0.001877 0.003775 -0.944828 -0.005257 0.000335 0.005202 -43.195312 135.515625 -341.859375 -0.008407 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307759 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629869 0.321956 0.000000 -0.018797 0.009910 -0.035605 0.046536 0.125712 0.016908 0.074322 0.107938 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.645935 -0.003586 0.008902 -0.945804 -0.004193 0.002463 0.007330 -43.195312 135.515625 -341.859375 -0.008420 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307665 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629578 0.322295 0.000000 -0.019120 0.009749 -0.036237 0.046527 0.126818 0.016103 0.073843 0.108076 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.650940 -0.005051 0.007926 -0.943851 -0.005257 0.000335 0.007330 -43.195312 137.812500 -341.859375 -0.008438 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307571 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627863 0.323202 0.000000 -0.018731 0.009942 -0.036237 0.046500 0.126236 0.016300 0.073645 0.108658 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.655945 -0.001145 0.007926 -0.946781 -0.005257 0.002463 0.010523 -43.195312 137.812500 -341.859375 -0.008457 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307480 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626453 0.324103 0.000000 -0.019021 0.009958 -0.037186 0.046476 0.127459 0.015045 0.073004 0.109332 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.660950 -0.000412 0.003287 -0.946048 -0.003128 0.003528 0.010523 -39.785156 143.554688 -345.445312 -0.008464 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306586 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625164 0.324342 0.000000 -0.019124 0.009637 -0.037186 0.046454 0.127882 0.015264 0.072785 0.108909 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.665955 0.004959 0.006217 -0.948002 -0.002064 0.000335 0.010523 -39.785156 143.554688 -345.445312 -0.008465 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305711 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623001 0.324464 0.000000 -0.018549 0.009503 -0.037186 0.046415 0.127451 0.015983 0.072086 0.109360 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.670959 0.002273 0.008902 -0.943119 -0.005257 0.001399 0.010523 -45.468750 142.406250 -351.421875 -0.008479 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304853 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621531 0.325128 0.000000 -0.018682 0.010037 -0.037186 0.046386 0.127051 0.015315 0.072754 0.109760 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.675964 0.004715 0.004752 -0.944095 -0.007385 0.001399 0.010523 -45.468750 142.406250 -351.421875 -0.008503 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304013 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620585 0.326327 0.000000 -0.018655 0.010377 -0.037186 0.046366 0.126683 0.015003 0.073066 0.110128 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.680969 0.007400 0.001822 -0.949222 -0.002064 0.003528 0.009459 -38.648438 142.406250 -341.859375 -0.008498 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303190 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620892 0.325789 0.000000 -0.018983 0.009519 -0.036869 0.046366 0.127554 0.015848 0.072853 0.108625 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.685974 0.002762 0.004752 -0.945316 -0.003128 0.001399 0.010523 -38.648438 142.406250 -341.859375 -0.008494 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302384 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621222 0.325360 0.000000 -0.018644 0.009704 -0.037186 0.046367 0.127346 0.015686 0.072383 0.109465 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.690979 0.003250 0.005484 -0.938968 -0.004193 0.000335 0.009459 -38.648438 142.406250 -339.468750 -0.008491 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621806 0.325021 0.000000 -0.018506 0.009871 -0.036869 0.046373 0.126724 0.015973 0.072728 0.109455 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.695984 0.005447 0.004752 -0.940433 -0.005257 0.001399 0.008394 -38.648438 142.406250 -339.468750 -0.008490 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300823 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623137 0.324824 0.000000 -0.018725 0.010026 -0.036553 0.046393 0.126472 0.015916 0.073417 0.109074 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.700989 0.002273 0.004508 -0.938236 -0.002064 0.001399 0.008394 -38.648438 142.406250 -346.640625 -0.008471 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300067 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624775 0.323558 0.000000 -0.018775 0.009494 -0.036553 0.046419 0.127054 0.016397 0.072936 0.108492 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.705994 -0.000900 0.006949 -0.945316 -0.003128 0.000335 0.006266 -38.648438 142.406250 -346.640625 -0.008455 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299326 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626209 0.322583 0.000000 -0.018660 0.009657 -0.035921 0.046443 0.126144 0.016981 0.073616 0.108139 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.710999 0.001053 0.002799 -0.945316 -0.004193 0.000335 0.006266 -46.605469 132.070312 -343.054688 -0.008444 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298599 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627542 0.321627 0.000000 -0.018716 0.009802 -0.035921 0.046467 0.126045 0.016771 0.073807 0.108217 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.716003 -0.000656 0.005973 -0.945072 -0.006321 0.000335 0.004137 -46.605469 132.070312 -343.054688 -0.008443 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297888 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628620 0.321580 0.000000 -0.018763 0.010116 -0.035289 0.046487 0.125146 0.017041 0.074800 0.107853 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.721008 -0.001389 0.005973 -0.944584 -0.004193 0.000335 0.004137 -36.375000 142.406250 -344.250000 -0.008431 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297191 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629353 0.320893 0.000000 -0.018798 0.009743 -0.035289 0.046502 0.125554 0.017380 0.074462 0.107445 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.726013 0.000564 0.006217 -0.946537 -0.004193 0.001399 0.002009 -36.375000 142.406250 -344.250000 -0.008419 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296508 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630003 0.320291 0.000000 -0.018988 0.009726 -0.034657 0.046516 0.125129 0.017839 0.075267 0.106605 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.731018 0.000076 0.006705 -0.945072 -0.005257 0.000335 0.003073 -36.375000 142.406250 -344.250000 -0.008415 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295839 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629620 0.320428 0.000000 -0.018811 0.009891 -0.034973 0.046519 0.125113 0.017545 0.074949 0.107273 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.736023 0.000320 0.007682 -0.939701 -0.004193 0.000335 0.000945 -42.058594 138.960938 -343.054688 -0.008408 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295183 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629328 0.320109 0.000000 -0.018813 0.009707 -0.034341 0.046517 0.124667 0.018359 0.075400 0.106455 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.741028 -0.000656 0.003043 -0.940189 -0.004193 -0.000729 0.000945 -42.058594 138.960938 -343.054688 -0.008404 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294541 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628519 0.319947 0.000000 -0.018638 0.009705 -0.034341 0.046506 0.124494 0.018536 0.075223 0.106628 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.746033 0.003494 0.005484 -0.934818 -0.004193 -0.001794 0.003073 -40.921875 144.703125 -349.031250 -0.008400 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293912 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627306 0.319844 0.000000 -0.018466 0.009704 -0.034973 0.046488 0.124955 0.018077 0.074417 0.107431 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.751038 0.001541 0.006949 -0.941166 -0.004193 0.001399 0.002009 -40.921875 144.703125 -349.031250 -0.008397 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293295 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627076 0.319758 0.000000 -0.018974 0.009704 -0.034657 0.046485 0.125147 0.017886 0.075240 0.106607 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.756042 0.004471 0.006461 -0.941898 -0.004193 0.000335 0.003073 -45.468750 137.812500 -339.468750 -0.008395 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292690 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626654 0.319724 0.000000 -0.018787 0.009704 -0.034973 0.046478 0.125276 0.017755 0.074739 0.107110 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.761047 0.002029 0.003775 -0.940433 -0.005257 0.000335 0.003073 -45.468750 137.812500 -339.468750 -0.008399 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626451 0.320038 0.000000 -0.018784 0.009875 -0.034973 0.046475 0.125102 0.017588 0.074906 0.107284 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.766052 0.004227 0.006217 -0.938480 -0.003128 0.001399 0.003073 -45.468750 144.703125 -349.031250 -0.008392 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291918 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626809 0.319696 0.000000 -0.018956 0.009532 -0.034973 0.046481 0.125618 0.017759 0.074735 0.106768 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.771057 0.004227 0.008170 -0.947025 -0.004193 0.000335 0.006266 -45.468750 144.703125 -349.031250 -0.008390 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291741 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627116 0.319687 0.000000 -0.018793 0.009709 -0.035921 0.046486 0.126225 0.016797 0.073801 0.108058 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.776062 0.003494 0.009146 -0.946293 -0.006321 0.000335 0.006266 -38.648438 147.000000 -341.859375 -0.008401 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628058 0.320107 0.000000 -0.018825 0.010042 -0.035921 0.046496 0.125914 0.016422 0.074156 0.108348 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.781067 0.006912 0.007193 -0.940677 -0.006321 0.000335 0.007330 -38.648438 147.000000 -341.859375 -0.008415 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291397 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628914 0.320971 0.000000 -0.018854 0.010038 -0.036237 0.046512 0.126263 0.016081 0.073864 0.108632 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.786072 0.002518 0.004020 -0.941654 -0.005257 0.001399 0.008394 -36.375000 137.812500 -344.250000 -0.008427 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291230 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630346 0.321624 0.000000 -0.019059 0.009872 -0.036553 0.046538 0.126951 0.015726 0.073587 0.108576 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.791077 0.002518 0.006705 -0.941898 -0.006321 0.001399 0.009459 -36.375000 137.812500 -344.250000 -0.008444 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291066 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631923 0.322595 0.000000 -0.019094 0.010053 -0.036869 0.046567 0.127120 0.015194 0.073487 0.109038 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.796082 0.001053 0.002555 -0.942630 -0.007385 0.001399 0.009459 -39.785156 141.257812 -347.835938 -0.008465 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290905 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633490 0.323769 0.000000 -0.019129 0.010225 -0.036869 0.046597 0.126984 0.014986 0.073695 0.109175 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.801086 0.002273 0.003043 -0.942386 -0.005257 0.000335 0.009459 -39.785156 141.257812 -347.835938 -0.008473 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290747 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634617 0.324083 0.000000 -0.018994 0.009881 -0.036869 0.046621 0.127193 0.015466 0.073215 0.108966 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.806091 -0.000900 0.005973 -0.944339 -0.005257 0.002463 0.009459 -39.785156 141.257812 -350.226562 -0.008476 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290592 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636165 0.324143 0.000000 -0.019366 0.009882 -0.036869 0.046653 0.127563 0.015092 0.073589 0.108596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.811096 -0.007248 0.007193 -0.948490 -0.004193 0.002463 0.009459 -39.785156 141.257812 -350.226562 -0.008471 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290440 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637291 0.323725 0.000000 -0.019375 0.009710 -0.036869 0.046678 0.127744 0.015256 0.073426 0.108415 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.816101 0.002273 0.004752 -0.944828 -0.006321 0.001399 0.008394 -40.921875 140.109375 -341.859375 -0.008476 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290292 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637531 0.323885 0.000000 -0.019201 0.010049 -0.036553 0.046689 0.126914 0.015407 0.073907 0.108612 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.821106 -0.002365 0.004020 -0.940677 -0.004193 0.002463 0.009459 -40.921875 140.109375 -341.859375 -0.008469 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290146 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637597 0.323355 0.000000 -0.019358 0.009697 -0.036869 0.046697 0.127750 0.015295 0.073406 0.108428 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.826111 0.000564 0.006461 -0.940433 -0.004193 0.002463 0.007330 -30.691406 138.960938 -345.445312 -0.008460 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290003 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637277 0.322795 0.000000 -0.019330 0.009696 -0.036237 0.046697 0.127091 0.015957 0.074008 0.107823 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.831116 0.001297 0.006217 -0.940433 -0.005257 0.000335 0.007330 -30.691406 138.960938 -345.445312 -0.008457 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289864 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636097 0.322568 0.000000 -0.018959 0.009862 -0.036237 0.046683 0.126554 0.016162 0.073804 0.108361 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.836121 -0.003830 0.005973 -0.941166 -0.006321 0.001399 0.006266 -30.691406 138.960938 -345.445312 -0.008460 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289727 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635124 0.322707 0.000000 -0.019105 0.010023 -0.035921 0.046670 0.126224 0.016171 0.074427 0.108059 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.841125 0.002029 0.004264 -0.942386 -0.004193 0.001399 0.004137 -42.058594 145.851562 -345.445312 -0.008453 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289593 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634055 0.322261 0.000000 -0.019072 0.009672 -0.035289 0.046655 0.125899 0.017177 0.074665 0.107099 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.846130 0.001297 0.002311 -0.942386 -0.004193 0.002463 0.004137 -42.058594 145.851562 -345.445312 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289462 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633311 0.321812 0.000000 -0.019208 0.009673 -0.035289 0.046644 0.126034 0.017040 0.074802 0.106964 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.851135 0.005691 0.003531 -0.939457 -0.005257 0.000335 0.004137 -40.921875 142.406250 -351.421875 -0.008441 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289333 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632120 0.321570 0.000000 -0.018837 0.009838 -0.035289 0.046625 0.125498 0.017246 0.074596 0.107500 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.856140 0.004959 0.004508 -0.940189 -0.004193 0.000335 0.004137 -40.921875 142.406250 -351.421875 -0.008429 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289207 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631324 0.320866 0.000000 -0.018830 0.009654 -0.035289 0.046611 0.125675 0.017438 0.074404 0.107323 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.861145 0.003250 0.005484 -0.944095 -0.005257 0.001399 0.002009 -36.375000 140.109375 -346.640625 -0.008420 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631321 0.320391 0.000000 -0.019004 0.009811 -0.034657 0.046611 0.125060 0.017739 0.075367 0.106674 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.866150 0.001297 0.004020 -0.942875 -0.005257 0.000335 0.003073 -36.375000 140.109375 -346.640625 -0.008410 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289563 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631410 0.320173 0.000000 -0.018844 0.009799 -0.034958 0.046612 0.125223 0.017619 0.074905 0.107133 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.871155 0.002029 0.005973 -0.944339 -0.005257 0.001399 0.003073 -36.375000 142.406250 -344.250000 -0.008399 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290034 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632087 0.319656 0.000000 -0.019037 0.009779 -0.034958 0.046623 0.125435 0.017446 0.075078 0.106920 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.876160 0.003982 0.005240 -0.946537 -0.005257 0.001399 0.003073 -36.375000 142.406250 -344.250000 -0.008389 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290495 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632928 0.319187 0.000000 -0.019058 0.009761 -0.034958 0.046637 0.125475 0.017443 0.075082 0.106881 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.881165 0.003738 0.006705 -0.948734 -0.005257 0.002463 0.002009 -43.195312 140.109375 -346.640625 -0.008381 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290947 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634219 0.318816 0.000000 -0.019253 0.009747 -0.034642 0.046660 0.125368 0.017578 0.075578 0.106355 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.886169 -0.001633 0.003043 -0.947025 -0.005257 0.001399 0.002009 -43.195312 140.109375 -346.640625 -0.008374 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291390 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635246 0.318246 0.000000 -0.019106 0.009727 -0.034657 0.046679 0.125246 0.017720 0.075386 0.106488 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.891174 0.001785 0.005729 -0.944584 -0.005257 0.000335 0.004137 -38.648438 142.406250 -339.468750 -0.008368 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291825 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635880 0.318028 0.000000 -0.018965 0.009718 -0.035289 0.046692 0.125746 0.017239 0.074603 0.107252 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.896179 -0.003342 0.006949 -0.948002 -0.002064 0.001399 0.006266 -38.648438 142.406250 -339.468750 -0.008347 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292251 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636630 0.316935 0.000000 -0.019161 0.009204 -0.035921 0.046708 0.127089 0.016924 0.073654 0.107174 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.901184 -0.002121 0.003287 -0.941654 -0.005257 0.001399 0.006266 -39.785156 138.960938 -352.617188 -0.008343 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292669 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637028 0.316903 0.000000 -0.019171 0.009725 -0.035921 0.046718 0.126577 0.016392 0.074185 0.107686 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.906189 -0.002365 0.006705 -0.943851 -0.004193 0.002463 0.005202 -39.785156 138.960938 -352.617188 -0.008335 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293079 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637299 0.316596 0.000000 -0.019336 0.009549 -0.035605 0.046726 0.126602 0.016719 0.074491 0.107028 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.911194 -0.002121 0.004508 -0.943851 -0.005257 0.001399 0.007330 -43.195312 144.703125 -341.859375 -0.008333 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293482 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636817 0.316943 0.000000 -0.019145 0.009728 -0.036222 0.046721 0.126859 0.016124 0.073871 0.108025 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.916199 -0.000168 0.008170 -0.945072 -0.004193 0.001399 0.008394 -43.195312 144.703125 -341.859375 -0.008326 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293877 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635984 0.316727 0.000000 -0.019120 0.009555 -0.036538 0.046710 0.127324 0.016007 0.073357 0.108193 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.921204 -0.000656 0.006705 -0.944584 -0.003128 0.000335 0.009459 -36.375000 144.703125 -341.859375 -0.008317 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294265 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634616 0.316321 0.000000 -0.018920 0.009392 -0.036854 0.046688 0.127602 0.016054 0.072677 0.108546 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.926208 0.000076 0.004996 -0.950443 -0.005257 0.001399 0.009459 -36.375000 144.703125 -341.859375 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294645 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633475 0.316684 0.000000 -0.019061 0.009745 -0.036854 0.046670 0.127390 0.015560 0.073171 0.108758 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.931213 0.003250 0.007193 -0.944828 -0.006321 0.001399 0.010523 -38.648438 142.406250 -341.859375 -0.008330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295018 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632014 0.317424 0.000000 -0.019015 0.009916 -0.037170 0.046651 0.127489 0.015118 0.072981 0.109291 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.936218 0.000076 0.005484 -0.942142 -0.003128 0.002463 0.010523 -38.648438 142.406250 -341.859375 -0.008326 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295384 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631397 0.317258 0.000000 -0.019155 0.009408 -0.037170 0.046639 0.128137 0.015487 0.072612 0.108644 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.941223 0.003250 0.006705 -0.941166 -0.005257 0.001399 0.008394 -38.648438 142.406250 -341.859375 -0.008333 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630686 0.317781 0.000000 -0.018957 0.009767 -0.036538 0.046625 0.126948 0.015957 0.073406 0.108568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.946228 0.002029 0.006461 -0.941898 -0.006321 0.000335 0.008394 -38.648438 144.703125 -341.859375 -0.008346 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296096 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629952 0.318632 0.000000 -0.018776 0.009943 -0.036538 0.046610 0.126591 0.015962 0.073401 0.108925 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.951233 0.002273 0.003287 -0.945072 -0.006321 0.000335 0.006266 -38.648438 144.703125 -341.859375 -0.008360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296442 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629894 0.319143 0.000000 -0.018790 0.009935 -0.035921 0.046601 0.125986 0.016563 0.074014 0.108276 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.956238 0.003982 0.003287 -0.944828 -0.004193 0.002463 0.006266 -42.058594 143.554688 -338.273438 -0.008361 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296780 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630405 0.319184 0.000000 -0.019139 0.009597 -0.035921 0.046607 0.126673 0.016553 0.074024 0.107589 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.961243 0.003006 0.003775 -0.940433 -0.003128 0.002463 0.005202 -42.058594 143.554688 -338.273438 -0.008353 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297113 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631182 0.318719 0.000000 -0.019144 0.009436 -0.035605 0.046618 0.126523 0.017025 0.074184 0.107107 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.966248 0.002273 0.007437 -0.935550 -0.006321 0.001399 0.006266 -35.238281 141.257812 -347.835938 -0.008359 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296233 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631882 0.319032 0.000000 -0.018989 0.009950 -0.035921 0.046628 0.126170 0.016350 0.074228 0.108092 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.971252 0.000320 0.005240 -0.939213 -0.004193 -0.000729 0.005202 -35.238281 141.257812 -347.835938 -0.008352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295370 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632101 0.318617 0.000000 -0.018678 0.009596 -0.035605 0.046631 0.125897 0.017331 0.073878 0.107733 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.976257 -0.000656 0.004508 -0.945804 -0.003128 0.000335 0.006266 -39.785156 141.257812 -345.445312 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294524 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632660 0.318176 0.000000 -0.018886 0.009434 -0.035921 0.046640 0.126593 0.016980 0.073618 0.107689 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.981262 -0.000900 0.004508 -0.942630 -0.005257 0.002463 0.006266 -39.785156 141.257812 -345.445312 -0.008336 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293695 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633699 0.318047 0.000000 -0.019248 0.009774 -0.035921 0.046658 0.126616 0.016277 0.074321 0.107667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.986267 -0.001633 0.005729 -0.941410 -0.005257 0.000335 0.006266 -36.375000 149.296875 -351.421875 -0.008333 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292882 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633832 0.317873 0.000000 -0.018914 0.009760 -0.035921 0.046661 0.126295 0.016626 0.073972 0.107987 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.991272 0.000809 0.005484 -0.943119 -0.003128 0.001399 0.005202 -36.375000 149.296875 -351.421875 -0.008318 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292086 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633999 0.317068 0.000000 -0.019092 0.009408 -0.035605 0.046665 0.126508 0.017115 0.074115 0.107142 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+456.996277 0.000320 0.005729 -0.944339 -0.004193 0.001399 0.004137 -39.785156 143.554688 -338.273438 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291305 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633925 0.316337 0.000000 -0.019086 0.009570 -0.035289 0.046664 0.126015 0.017265 0.074576 0.106983 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.001282 0.000564 0.006217 -0.943851 -0.005257 -0.000729 0.003073 -39.785156 143.554688 -338.273438 -0.008307 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290539 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633067 0.316285 0.000000 -0.018738 0.009733 -0.034973 0.046651 0.125188 0.017766 0.074708 0.107178 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.006287 0.001785 0.008902 -0.941166 -0.005257 0.001399 0.003073 -40.921875 142.406250 -346.640625 -0.008306 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289788 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632788 0.316343 0.000000 -0.019076 0.009725 -0.034973 0.046646 0.125535 0.017436 0.075038 0.106831 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.011292 -0.002365 0.006705 -0.947025 -0.005257 0.000335 0.000945 -40.921875 142.406250 -346.640625 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289052 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632145 0.316583 0.000000 -0.018891 0.009723 -0.034341 0.046635 0.124720 0.018255 0.075483 0.106382 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.016296 -0.000168 0.006705 -0.942386 -0.004193 0.000335 0.002009 -44.332031 138.960938 -343.054688 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631446 0.316697 0.000000 -0.018880 0.009558 -0.034657 0.046623 0.125189 0.018114 0.074992 0.106545 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.021301 -0.000900 0.008658 -0.944828 -0.006321 -0.000729 0.000945 -44.332031 138.960938 -343.054688 -0.008324 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287625 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630354 0.317914 0.000000 -0.018697 0.009922 -0.034341 0.046603 0.124335 0.018260 0.075498 0.106786 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.026306 -0.000656 0.007926 -0.942875 -0.005257 0.000335 0.003073 -38.648438 144.703125 -341.859375 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286933 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629529 0.318672 0.000000 -0.018855 0.009762 -0.034973 0.046587 0.125286 0.017630 0.074864 0.107100 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.031311 0.003250 0.004996 -0.944095 -0.005257 0.000335 0.004137 -38.648438 144.703125 -341.859375 -0.008352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286254 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628700 0.319558 0.000000 -0.018835 0.009783 -0.035289 0.046570 0.125561 0.017313 0.074549 0.107458 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.036316 0.000564 0.005240 -0.941654 -0.004193 0.000335 0.005202 -44.332031 136.664062 -338.273438 -0.008363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285590 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627974 0.320140 0.000000 -0.018817 0.009636 -0.035605 0.046555 0.126006 0.017161 0.074069 0.107644 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.041321 0.003982 0.003043 -0.940433 -0.004193 0.000335 0.007330 -44.332031 136.664062 -338.273438 -0.008373 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284939 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627437 0.320610 0.000000 -0.018805 0.009662 -0.036237 0.046542 0.126601 0.016516 0.073450 0.108314 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.046326 0.002029 0.004264 -0.943851 -0.005257 0.001399 0.007330 -44.332031 136.664062 -338.273438 -0.008384 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284301 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627455 0.321171 0.000000 -0.018969 0.009848 -0.036237 0.046539 0.126578 0.016166 0.073799 0.108337 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.051331 0.000809 0.006705 -0.941898 -0.004193 0.001399 0.008394 -42.058594 141.257812 -350.226562 -0.008386 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627694 0.321169 0.000000 -0.018963 0.009682 -0.036553 0.046540 0.127055 0.016021 0.073312 0.108492 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.056335 0.002029 0.003531 -0.938236 -0.004193 0.000335 0.008394 -42.058594 141.257812 -350.226562 -0.008385 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283063 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627774 0.320988 0.000000 -0.018795 0.009686 -0.036553 0.046538 0.126883 0.016185 0.073148 0.108664 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.061340 0.004227 0.004264 -0.943851 -0.003128 0.002463 0.008394 -37.511719 136.664062 -343.054688 -0.008376 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282463 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628635 0.320327 0.000000 -0.019146 0.009515 -0.036553 0.046550 0.127405 0.016006 0.073328 0.108142 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.066345 0.005203 0.006461 -0.941654 -0.006321 0.000335 0.008394 -37.511719 136.664062 -343.054688 -0.008379 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281874 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629051 0.320478 0.000000 -0.018814 0.010021 -0.036553 0.046556 0.126566 0.015832 0.073501 0.108980 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.071350 0.003982 0.005240 -0.940189 -0.005257 0.000335 0.009459 -39.785156 141.257812 -345.445312 -0.008376 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282302 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629738 0.320221 0.000000 -0.018843 0.009827 -0.036869 0.046566 0.127104 0.015681 0.073021 0.109074 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.076355 0.002762 0.005484 -0.945316 -0.003128 0.001399 0.008394 -39.785156 141.257812 -345.445312 -0.008362 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282721 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630966 0.319327 0.000000 -0.019046 0.009474 -0.036553 0.046586 0.127345 0.016147 0.073187 0.108201 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.081360 0.000564 0.007193 -0.945560 -0.004193 0.000335 0.008394 -40.921875 142.406250 -337.078125 -0.008353 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283131 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631978 0.318815 0.000000 -0.018908 0.009642 -0.036553 0.046604 0.127039 0.016117 0.073217 0.108508 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.086365 0.000809 0.006461 -0.939945 -0.005257 0.000335 0.008394 -40.921875 142.406250 -337.078125 -0.008351 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283533 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632950 0.318727 0.000000 -0.018944 0.009805 -0.036538 0.046621 0.126898 0.015933 0.073431 0.108619 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.091370 -0.003830 0.004020 -0.941410 -0.004193 0.001399 0.007330 -40.921875 142.406250 -344.250000 -0.008346 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283927 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634019 0.318426 0.000000 -0.019143 0.009626 -0.036222 0.046641 0.126959 0.016229 0.073766 0.107926 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.096375 0.002029 0.004752 -0.942142 -0.004193 0.001399 0.007330 -40.921875 142.406250 -344.250000 -0.008341 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284312 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634732 0.318172 0.000000 -0.019154 0.009625 -0.036222 0.046656 0.126972 0.016219 0.073777 0.107912 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.101379 0.002518 0.004020 -0.944339 -0.004193 0.001399 0.006266 -42.058594 143.554688 -345.445312 -0.008335 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284690 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635138 0.317897 0.000000 -0.019158 0.009622 -0.035906 0.046666 0.126662 0.016534 0.074094 0.107590 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.106384 0.003494 0.005484 -0.942875 -0.005257 0.000335 0.008394 -42.058594 143.554688 -345.445312 -0.008334 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285060 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635093 0.317882 0.000000 -0.018990 0.009786 -0.036553 0.046669 0.126977 0.015891 0.073442 0.108570 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.111389 0.001785 0.009635 -0.939945 -0.004193 0.001399 0.007330 -43.195312 140.109375 -339.468750 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285422 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635345 0.317557 0.000000 -0.019166 0.009606 -0.036237 0.046676 0.127017 0.016211 0.073754 0.107897 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.116394 0.002518 0.006217 -0.939213 -0.005257 0.001399 0.007330 -43.195312 140.109375 -339.468750 -0.008329 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285777 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635619 0.317684 0.000000 -0.019166 0.009775 -0.036237 0.046684 0.126849 0.016042 0.073924 0.108066 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.121399 0.005203 0.006949 -0.943363 -0.004193 0.000335 0.008394 -45.468750 140.109375 -337.078125 -0.008327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286125 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635665 0.317657 0.000000 -0.019001 0.009604 -0.036553 0.046687 0.127171 0.016061 0.073272 0.108376 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.126404 0.004227 0.005240 -0.941654 -0.004193 0.000335 0.007330 -45.468750 140.109375 -337.078125 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286465 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635901 0.317767 0.000000 -0.019018 0.009613 -0.036237 0.046694 0.126862 0.016351 0.073614 0.108053 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.131409 0.003494 0.005484 -0.943363 -0.003128 0.000335 0.007330 -40.921875 140.109375 -341.859375 -0.008325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286798 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636363 0.317632 0.000000 -0.019040 0.009455 -0.036237 0.046705 0.127042 0.016487 0.073478 0.107872 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.136414 0.003738 0.004752 -0.939945 -0.004193 0.001399 0.007330 -40.921875 140.109375 -341.859375 -0.008327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287125 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637333 0.317817 0.000000 -0.019236 0.009640 -0.036237 0.046724 0.127053 0.016106 0.073859 0.107862 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.141418 0.002273 0.007926 -0.941166 -0.005257 0.001399 0.008394 -35.238281 141.257812 -347.835938 -0.008335 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287444 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638426 0.318283 0.000000 -0.019260 0.009816 -0.036553 0.046746 0.127217 0.015590 0.073743 0.108330 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.146423 0.001297 0.004996 -0.945560 -0.004193 -0.000729 0.007330 -35.238281 141.257812 -347.835938 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287757 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638917 0.318415 0.000000 -0.018948 0.009648 -0.036237 0.046759 0.126757 0.016388 0.073578 0.108157 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.151428 -0.000656 0.003287 -0.942875 -0.004193 0.001399 0.006266 -35.238281 141.257812 -347.835938 -0.008338 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288063 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639957 0.318502 0.000000 -0.019322 0.009654 -0.035921 0.046781 0.126809 0.016323 0.074274 0.107473 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.156433 0.000076 0.003287 -0.938724 -0.004193 0.000335 0.006266 -40.921875 147.000000 -334.687500 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288363 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640451 0.318443 0.000000 -0.019167 0.009655 -0.035921 0.046794 0.126653 0.016476 0.074121 0.107629 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.161438 0.001297 0.006705 -0.938724 -0.005257 0.000335 0.005202 -40.921875 147.000000 -334.687500 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288657 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640682 0.318525 0.000000 -0.019181 0.009820 -0.035605 0.046803 0.126186 0.016614 0.074616 0.107464 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.166443 0.002029 0.006217 -0.939945 -0.007385 0.001399 0.004137 -40.921875 137.812500 -339.468750 -0.008349 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288944 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.641007 0.319124 0.000000 -0.019356 0.010144 -0.035289 0.046813 0.125721 0.016430 0.075432 0.107297 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.171448 0.000809 0.005729 -0.942142 -0.005257 0.001399 0.003073 -40.921875 137.812500 -339.468750 -0.008348 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289226 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640803 0.319045 0.000000 -0.019340 0.009781 -0.034958 0.046820 0.125737 0.017141 0.075383 0.106619 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.176453 -0.002121 0.003775 -0.941898 -0.003128 0.000335 0.003073 -43.195312 142.406250 -341.859375 -0.008336 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289501 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.640485 0.318338 0.000000 -0.019162 0.009434 -0.034958 0.046820 0.125905 0.017666 0.074859 0.106450 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.181458 -0.003830 0.005484 -0.943119 -0.004193 0.000335 0.003073 -43.195312 142.406250 -341.859375 -0.008330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289771 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639925 0.317945 0.000000 -0.019153 0.009607 -0.034958 0.046814 0.125723 0.017502 0.075022 0.106632 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.186462 -0.001877 0.005729 -0.945804 -0.004193 0.000335 0.003073 -39.785156 143.554688 -345.445312 -0.008322 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290035 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.639037 0.317542 0.000000 -0.019133 0.009602 -0.034958 0.046802 0.125708 0.017527 0.074997 0.106647 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.191467 -0.002121 0.006217 -0.943363 -0.005257 0.000335 0.002009 -39.785156 143.554688 -345.445312 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290293 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637827 0.317480 0.000000 -0.019102 0.009766 -0.034642 0.046784 0.125198 0.017710 0.075446 0.106525 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.196472 -0.001145 0.008414 -0.943119 -0.004193 0.001399 0.003073 -39.785156 143.554688 -343.054688 -0.008315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290546 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637042 0.317184 0.000000 -0.019243 0.009587 -0.034973 0.046765 0.125849 0.017416 0.075078 0.106537 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.201477 0.002029 0.004508 -0.944339 -0.005257 -0.000729 0.003073 -39.785156 143.554688 -343.054688 -0.008316 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290794 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635142 0.317339 0.000000 -0.018856 0.009758 -0.034973 0.046733 0.125291 0.017633 0.074861 0.107095 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.206482 0.001297 0.009146 -0.939701 -0.005257 -0.000729 0.004137 -42.058594 141.257812 -343.054688 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291037 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633331 0.317618 0.000000 -0.018823 0.009757 -0.035289 0.046701 0.125575 0.017351 0.074511 0.107443 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.211487 0.003006 0.003775 -0.944584 -0.004193 0.001399 0.003073 -42.058594 141.257812 -343.054688 -0.008321 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291275 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632374 0.317700 0.000000 -0.019132 0.009591 -0.034973 0.046682 0.125734 0.017524 0.074970 0.106652 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.216492 0.002029 0.005973 -0.944584 -0.005257 -0.000729 0.004137 -45.468750 142.406250 -344.250000 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291508 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631090 0.317854 0.000000 -0.018760 0.009763 -0.035289 0.046657 0.125506 0.017407 0.074454 0.107512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.221497 0.003494 0.007437 -0.938724 -0.004193 0.000335 0.005202 -45.468750 142.406250 -344.250000 -0.008331 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291737 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630497 0.317998 0.000000 -0.018920 0.009600 -0.035605 0.046642 0.126146 0.017095 0.074135 0.107505 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.226501 0.000564 0.005240 -0.940677 -0.005257 0.001399 0.007330 -40.921875 140.109375 -344.250000 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291961 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630560 0.318483 0.000000 -0.019082 0.009782 -0.036237 0.046639 0.126758 0.016119 0.073847 0.108157 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.231506 0.003494 0.006949 -0.944339 -0.005257 0.002463 0.008394 -40.921875 140.109375 -344.250000 -0.008348 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292181 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631197 0.318966 0.000000 -0.019246 0.009788 -0.036553 0.046645 0.127232 0.015633 0.073701 0.108315 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.236511 0.004227 0.006705 -0.939457 -0.004193 0.001399 0.009459 -48.878906 138.960938 -345.445312 -0.008352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292396 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631752 0.319140 0.000000 -0.019075 0.009626 -0.036869 0.046652 0.127538 0.015650 0.073052 0.108641 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.241516 0.002518 0.005484 -0.939457 -0.004193 0.002463 0.009459 -48.878906 138.960938 -345.445312 -0.008356 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292607 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632862 0.319635 0.000000 -0.019258 0.009650 -0.036869 0.046668 0.127698 0.015443 0.073258 0.108481 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.246521 0.002762 0.004752 -0.944095 -0.004193 0.002463 0.009459 -37.511719 134.367188 -350.226562 -0.008360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292814 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634138 0.319805 0.000000 -0.019273 0.009663 -0.036869 0.046688 0.127699 0.015415 0.073286 0.108480 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.251526 0.001053 0.004020 -0.944584 -0.003128 0.000335 0.008394 -37.511719 134.367188 -350.226562 -0.008357 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293016 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634863 0.319569 0.000000 -0.018954 0.009503 -0.036553 0.046700 0.127225 0.016210 0.073124 0.108322 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.256531 0.002029 0.004752 -0.942875 -0.005257 0.001399 0.009459 -37.511719 134.367188 -350.226562 -0.008362 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293214 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635916 0.319826 0.000000 -0.019158 0.009851 -0.036869 0.046718 0.127396 0.015342 0.073359 0.108783 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.261536 0.000564 0.004752 -0.945560 -0.004193 0.001399 0.009459 -38.648438 137.812500 -339.468750 -0.008359 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293407 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636885 0.319597 0.000000 -0.019182 0.009673 -0.036854 0.046735 0.127583 0.015511 0.073221 0.108565 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.266541 -0.001633 0.005240 -0.945560 -0.004193 0.001399 0.009459 -38.648438 137.812500 -339.468750 -0.008354 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293597 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637675 0.319240 0.000000 -0.019202 0.009667 -0.036854 0.046751 0.127609 0.015497 0.073235 0.108540 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.271545 0.001541 0.006705 -0.942386 -0.005257 0.001399 0.009459 -42.058594 141.257812 -340.664062 -0.008353 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293382 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638210 0.319128 0.000000 -0.019214 0.009828 -0.036854 0.046762 0.127461 0.015324 0.073408 0.108688 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.276550 0.000320 0.004752 -0.943119 -0.005257 0.001399 0.007330 -42.058594 141.257812 -340.664062 -0.008351 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293171 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638499 0.318995 0.000000 -0.019220 0.009812 -0.036222 0.046770 0.126850 0.015966 0.074030 0.108034 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.281555 -0.001145 0.006461 -0.948002 -0.006321 0.001399 0.006266 -40.921875 135.515625 -344.250000 -0.008354 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292964 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638566 0.319184 0.000000 -0.019219 0.009967 -0.035921 0.046773 0.126393 0.016113 0.074485 0.107889 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.286560 -0.000168 0.004508 -0.944828 -0.004193 0.000335 0.005202 -40.921875 135.515625 -344.250000 -0.008347 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292762 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.638094 0.318757 0.000000 -0.019043 0.009611 -0.035605 0.046768 0.126257 0.016961 0.074269 0.107393 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.291565 -0.000412 0.005973 -0.941166 -0.005257 0.000335 0.004137 -44.332031 148.148438 -340.664062 -0.008346 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292564 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637436 0.318682 0.000000 -0.019036 0.009778 -0.035289 0.046759 0.125768 0.017117 0.074745 0.107250 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.296570 0.001297 0.005240 -0.941898 -0.004193 0.000335 0.004137 -44.332031 148.148438 -340.664062 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292370 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636654 0.318316 0.000000 -0.019025 0.009600 -0.035289 0.046747 0.125934 0.017307 0.074555 0.107084 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.301575 0.002273 0.006461 -0.943119 -0.003128 0.001399 0.004137 -40.921875 147.000000 -351.421875 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292181 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636163 0.317691 0.000000 -0.019180 0.009431 -0.035289 0.046739 0.126258 0.017321 0.074541 0.106760 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.306580 0.002518 0.005973 -0.940433 -0.004193 0.000335 0.004137 -40.921875 147.000000 -351.421875 -0.008324 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291995 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635078 0.317466 0.000000 -0.018981 0.009607 -0.035274 0.046727 0.125868 0.017358 0.074534 0.107119 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.311584 0.000564 0.002066 -0.943851 -0.005257 0.000335 0.003073 -37.511719 138.960938 -338.273438 -0.008325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291814 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634508 0.317580 0.000000 -0.018974 0.009775 -0.034958 0.046717 0.125377 0.017514 0.075011 0.106979 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.316589 -0.000656 0.005240 -0.940921 -0.004193 -0.000729 0.003073 -37.511719 138.960938 -338.273438 -0.008319 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291636 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633743 0.317302 0.000000 -0.018800 0.009596 -0.034958 0.046703 0.125381 0.017866 0.074658 0.106974 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.321594 0.000076 0.006705 -0.939701 -0.005257 0.000335 0.003073 -44.332031 143.554688 -343.054688 -0.008317 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291462 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633345 0.317276 0.000000 -0.018970 0.009761 -0.034958 0.046695 0.125387 0.017531 0.074993 0.106968 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.326599 0.003494 0.005240 -0.941410 -0.004193 0.001399 0.003073 -44.332031 143.554688 -343.054688 -0.008311 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291292 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633650 0.316926 0.000000 -0.019144 0.009581 -0.034958 0.046692 0.125741 0.017538 0.074987 0.106614 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.331604 0.002273 0.008414 -0.943363 -0.004193 0.000335 0.004137 -46.605469 145.851562 -345.445312 -0.008305 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291124 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633375 0.316645 0.000000 -0.018965 0.009579 -0.035274 0.046686 0.125880 0.017403 0.074490 0.107107 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.336609 0.002273 0.005973 -0.948002 -0.005257 -0.001794 0.004137 -46.605469 145.851562 -345.445312 -0.008306 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290960 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632636 0.316806 0.000000 -0.018629 0.009749 -0.035274 0.046671 0.125375 0.017568 0.074324 0.107613 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.341614 0.004227 0.004752 -0.941410 -0.005257 0.000335 0.004137 -37.511719 141.257812 -350.226562 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290799 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632734 0.317067 0.000000 -0.018987 0.009746 -0.035274 0.046671 0.125735 0.017213 0.074679 0.107253 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.346619 0.004227 0.007682 -0.941654 -0.005257 0.000335 0.005202 -37.511719 141.257812 -350.226562 -0.008314 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290641 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633057 0.317386 0.000000 -0.018997 0.009746 -0.035590 0.046674 0.126061 0.016887 0.074374 0.107559 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.351624 0.001541 0.006217 -0.943363 -0.004193 0.000335 0.006266 -38.648438 140.109375 -341.859375 -0.008315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290487 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633599 0.317460 0.000000 -0.019014 0.009581 -0.035921 0.046682 0.126574 0.016704 0.073894 0.107708 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.356628 0.002273 0.005729 -0.946537 -0.005257 0.001399 0.007330 -38.648438 140.109375 -341.859375 -0.008322 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290335 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634586 0.317921 0.000000 -0.019204 0.009763 -0.036237 0.046698 0.126898 0.016016 0.073949 0.108016 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.361633 0.001053 0.004996 -0.940677 -0.005257 0.000335 0.007330 -38.648438 140.109375 -341.859375 -0.008330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290187 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635279 0.318384 0.000000 -0.019050 0.009768 -0.036237 0.046709 0.126739 0.016164 0.073801 0.108176 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.366638 0.000320 0.004508 -0.942386 -0.004193 0.001399 0.007330 -37.511719 138.960938 -347.835938 -0.008332 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290041 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636226 0.318474 0.000000 -0.019240 0.009604 -0.036237 0.046726 0.127093 0.016138 0.073827 0.107822 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.371643 0.000076 0.005729 -0.943851 -0.004193 0.002463 0.007330 -37.511719 138.960938 -347.835938 -0.008332 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289899 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636954 0.318482 0.000000 -0.019408 0.009614 -0.036237 0.046745 0.127252 0.015961 0.074005 0.107663 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.376648 -0.001145 0.006705 -0.943607 -0.005257 0.001399 0.007330 -40.921875 137.812500 -346.640625 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289357 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637476 0.318735 0.000000 -0.019237 0.009789 -0.036237 0.046756 0.126906 0.015957 0.074009 0.108009 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.381653 -0.002854 0.005973 -0.942630 -0.006321 0.001399 0.005202 -40.921875 137.812500 -346.640625 -0.008347 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288827 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637680 0.319266 0.000000 -0.019235 0.009956 -0.035605 0.046762 0.126104 0.016424 0.074806 0.107546 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.386658 -0.001145 0.004752 -0.941898 -0.005257 0.000335 0.007330 -43.195312 137.812500 -349.031250 -0.008351 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288307 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637211 0.319444 0.000000 -0.019054 0.009779 -0.036237 0.046756 0.126732 0.016150 0.073816 0.108183 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.391663 0.000320 0.006217 -0.943119 -0.004193 0.001399 0.006266 -43.195312 137.812500 -349.031250 -0.008349 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287798 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.637107 0.319278 0.000000 -0.019219 0.009610 -0.035921 0.046750 0.126750 0.016470 0.074128 0.107532 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.396667 0.003982 0.004020 -0.940189 -0.005257 0.002463 0.006266 -42.058594 138.960938 -340.664062 -0.008352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287299 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636792 0.319398 0.000000 -0.019361 0.009785 -0.035921 0.046746 0.126718 0.016153 0.074445 0.107564 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.401672 0.003494 0.003043 -0.943119 -0.005257 0.002463 0.006266 -42.058594 138.960938 -340.664062 -0.008353 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286810 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636517 0.319420 0.000000 -0.019331 0.009780 -0.035921 0.046742 0.126692 0.016188 0.074410 0.107590 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.406677 -0.000168 0.005729 -0.945072 -0.005257 0.001399 0.006266 -42.058594 141.257812 -347.835938 -0.008352 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636094 0.319304 0.000000 -0.019139 0.009772 -0.035921 0.046736 0.126509 0.016388 0.074210 0.107773 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.411682 0.002029 0.005729 -0.944095 -0.005257 0.001399 0.006266 -42.058594 141.257812 -347.835938 -0.008349 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285862 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635835 0.319095 0.000000 -0.019130 0.009761 -0.035921 0.046732 0.126510 0.016408 0.074190 0.107772 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.416687 0.002273 0.006705 -0.946537 -0.004193 0.000335 0.006266 -37.511719 141.257812 -343.054688 -0.008340 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285402 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635420 0.318563 0.000000 -0.018956 0.009582 -0.035906 0.046725 0.126500 0.016776 0.073852 0.107752 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.421692 0.000809 0.004508 -0.946537 -0.005257 0.000335 0.007330 -37.511719 141.257812 -343.054688 -0.008338 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284951 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635173 0.318398 0.000000 -0.018963 0.009749 -0.036222 0.046720 0.126656 0.016286 0.073709 0.108228 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.426697 0.000320 0.003775 -0.943363 -0.005257 0.001399 0.006266 -38.648438 142.406250 -344.250000 -0.008335 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284510 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635341 0.318243 0.000000 -0.019140 0.009739 -0.035906 0.046722 0.126526 0.016435 0.074193 0.107726 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.431702 0.001541 0.004752 -0.941166 -0.005257 0.000335 0.007330 -38.648438 142.406250 -344.250000 -0.008331 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284078 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635226 0.318048 0.000000 -0.018972 0.009729 -0.036222 0.046720 0.126685 0.016296 0.073699 0.108199 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.436707 0.002029 0.004508 -0.944339 -0.005257 0.001399 0.007330 -44.332031 136.664062 -345.445312 -0.008327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283655 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635460 0.317801 0.000000 -0.019150 0.009718 -0.036222 0.046724 0.126874 0.016129 0.073866 0.108010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.441711 0.000809 0.005240 -0.942386 -0.006321 0.002463 0.008394 -44.332031 136.664062 -345.445312 -0.008327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283240 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636028 0.317828 0.000000 -0.019321 0.009875 -0.036538 0.046733 0.127204 0.015485 0.073879 0.108312 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.446716 0.001541 0.004996 -0.940921 -0.004193 0.001399 0.007330 -35.238281 138.960938 -347.835938 -0.008315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282834 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636271 0.317201 0.000000 -0.019149 0.009519 -0.036222 0.046737 0.127072 0.016329 0.073666 0.107812 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.451721 -0.001389 0.005240 -0.942630 -0.004193 0.001399 0.008394 -35.238281 138.960938 -347.835938 -0.008304 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282437 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636480 0.316605 0.000000 -0.019153 0.009516 -0.036538 0.046741 0.127395 0.016013 0.073351 0.108121 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.456726 0.000564 0.007193 -0.941166 -0.004193 0.000335 0.007330 -39.785156 141.257812 -347.835938 -0.008294 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282047 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636274 0.316080 0.000000 -0.018985 0.009513 -0.036222 0.046738 0.126914 0.016499 0.073497 0.107970 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.461731 0.000564 0.004020 -0.944339 -0.004193 0.000335 0.007330 -39.785156 141.257812 -347.835938 -0.008285 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281666 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635970 0.315657 0.000000 -0.018990 0.009512 -0.036237 0.046734 0.126935 0.016481 0.073485 0.107980 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.466736 -0.001389 0.006705 -0.941898 -0.005257 0.001399 0.006266 -39.785156 141.257812 -347.835938 -0.008283 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281292 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635874 0.315636 0.000000 -0.019158 0.009681 -0.035921 0.046732 0.126619 0.016459 0.074138 0.107664 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.471741 0.001541 0.006217 -0.940921 -0.004193 -0.000729 0.006266 -39.785156 143.554688 -345.445312 -0.008277 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280925 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635036 0.315383 0.000000 -0.018809 0.009507 -0.035921 0.046718 0.126443 0.016982 0.073615 0.107839 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.476746 0.003250 0.004752 -0.945072 -0.005257 0.000335 0.005202 -39.785156 143.554688 -345.445312 -0.008277 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280968 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634506 0.315538 0.000000 -0.018979 0.009681 -0.035605 0.046708 0.126123 0.016954 0.074275 0.107527 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.481750 -0.001633 0.005973 -0.945316 -0.004193 0.000335 0.004137 -38.648438 147.000000 -341.859375 -0.008274 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634024 0.315425 0.000000 -0.018973 0.009511 -0.035289 0.046699 0.125971 0.017447 0.074415 0.107048 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.486755 0.000076 0.009635 -0.943363 -0.004193 0.001399 0.005202 -38.648438 147.000000 -341.859375 -0.008272 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281051 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633867 0.315402 0.000000 -0.019135 0.009520 -0.035605 0.046695 0.126440 0.016960 0.074269 0.107210 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.491760 -0.000412 0.006461 -0.941898 -0.005257 0.001399 0.004137 -45.468750 137.812500 -346.640625 -0.008278 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633651 0.315857 0.000000 -0.019119 0.009701 -0.035289 0.046690 0.125927 0.017111 0.074751 0.107091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.496765 -0.001633 0.004020 -0.943851 -0.004193 0.001399 0.003073 -45.468750 137.812500 -346.640625 -0.008281 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281130 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633349 0.316115 0.000000 -0.019102 0.009541 -0.034973 0.046683 0.125753 0.017604 0.074890 0.106632 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.501770 0.004471 0.005973 -0.943851 -0.005257 0.002463 0.004137 -50.015625 142.406250 -344.250000 -0.008290 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281169 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632949 0.316706 0.000000 -0.019242 0.009727 -0.035274 0.046681 0.126009 0.016977 0.074915 0.106978 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.506775 0.003006 0.006461 -0.944828 -0.005257 0.001399 0.004137 -50.015625 142.406250 -344.250000 -0.008300 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281207 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632673 0.317254 0.000000 -0.019053 0.009735 -0.035274 0.046675 0.125812 0.017158 0.074734 0.107176 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.511780 0.002762 0.004752 -0.941166 -0.004193 0.000335 0.005202 -40.921875 140.109375 -344.250000 -0.008303 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281244 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632299 0.317438 0.000000 -0.018878 0.009574 -0.035590 0.046667 0.126114 0.017178 0.074082 0.107505 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.516785 0.000320 0.002799 -0.944584 -0.005257 0.001399 0.005202 -40.921875 140.109375 -344.250000 -0.008310 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281281 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632460 0.317836 0.000000 -0.019055 0.009754 -0.035590 0.046668 0.126110 0.016821 0.074439 0.107509 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.521790 -0.000412 0.006705 -0.944095 -0.005257 0.001399 0.007330 -42.058594 136.664062 -340.664062 -0.008315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281317 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632730 0.318064 0.000000 -0.019058 0.009754 -0.036222 0.046671 0.126747 0.016186 0.073810 0.108138 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.526794 0.000809 0.005240 -0.941166 -0.005257 0.001399 0.007330 -42.058594 136.664062 -340.664062 -0.008317 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281352 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633363 0.318165 0.000000 -0.019073 0.009750 -0.036237 0.046674 0.126780 0.016159 0.073806 0.108135 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.531799 0.002029 0.003775 -0.941898 -0.005257 0.001399 0.007330 -40.921875 144.703125 -339.468750 -0.008318 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281387 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633608 0.318169 0.000000 -0.019077 0.009745 -0.036237 0.046677 0.126789 0.016161 0.073804 0.108125 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.536804 -0.000168 0.004752 -0.944339 -0.004193 0.000335 0.008394 -40.921875 144.703125 -339.468750 -0.008312 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281421 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633522 0.317749 0.000000 -0.018911 0.009567 -0.036553 0.046675 0.127117 0.016188 0.073146 0.108429 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.541809 0.000564 0.006461 -0.944828 -0.005257 0.001399 0.008394 -40.921875 144.703125 -346.640625 -0.008309 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281455 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633715 0.317575 0.000000 -0.019089 0.009733 -0.036553 0.046678 0.127130 0.015845 0.073489 0.108417 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.546814 -0.001877 0.005729 -0.945560 -0.005257 0.001399 0.006266 -40.921875 144.703125 -346.640625 -0.008306 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281488 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633437 0.317389 0.000000 -0.019077 0.009721 -0.035906 0.046679 0.126481 0.016516 0.074112 0.107771 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.551819 -0.002121 0.005729 -0.937504 -0.004193 0.001399 0.005202 -38.648438 142.406250 -344.250000 -0.008298 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281520 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633336 0.316929 0.000000 -0.019070 0.009543 -0.035590 0.046677 0.126337 0.017017 0.074243 0.107283 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.556824 0.000564 0.006949 -0.941166 -0.004193 0.001399 0.007330 -38.648438 142.406250 -344.250000 -0.008292 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281552 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633028 0.316557 0.000000 -0.019057 0.009543 -0.036222 0.046671 0.126957 0.016398 0.073598 0.107928 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.561829 -0.000412 0.005973 -0.935795 -0.004193 0.000335 0.008394 -37.511719 141.257812 -343.054688 -0.008287 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281583 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632252 0.316303 0.000000 -0.018871 0.009545 -0.036538 0.046657 0.127085 0.016266 0.073098 0.108431 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.566833 -0.000412 0.005240 -0.940433 -0.004193 0.001399 0.007330 -37.511719 141.257812 -343.054688 -0.008284 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281614 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631702 0.316158 0.000000 -0.019027 0.009549 -0.036222 0.046646 0.126921 0.016422 0.073574 0.107964 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.571838 0.000320 0.004752 -0.946048 -0.005257 0.001399 0.007330 -37.511719 141.257812 -343.054688 -0.008286 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281643 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631094 0.316380 0.000000 -0.019005 0.009722 -0.036237 0.046634 0.126740 0.016255 0.073710 0.108175 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.576843 0.002518 0.006217 -0.946048 -0.005257 0.000335 0.008394 -42.058594 136.664062 -345.445312 -0.008290 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282475 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630199 0.316596 0.000000 -0.018815 0.009720 -0.036553 0.046617 0.126868 0.016132 0.073202 0.108679 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.581848 0.000564 0.007926 -0.941898 -0.005257 0.001399 0.006266 -42.058594 136.664062 -345.445312 -0.008293 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283290 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629739 0.316836 0.000000 -0.018973 0.009720 -0.035921 0.046607 0.126394 0.016606 0.073991 0.107888 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.586853 0.001297 0.005240 -0.941654 -0.004193 0.001399 0.005202 -37.511719 141.257812 -343.054688 -0.008293 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284089 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629416 0.316832 0.000000 -0.018958 0.009553 -0.035605 0.046599 0.126231 0.017103 0.074126 0.107420 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.591858 0.002518 0.006705 -0.941410 -0.005257 0.000335 0.007330 -37.511719 141.257812 -343.054688 -0.008299 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284871 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629303 0.317210 0.000000 -0.018791 0.009733 -0.036237 0.046588 0.126515 0.016458 0.073507 0.108399 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.596863 0.002273 0.003287 -0.941410 -0.004193 0.000335 0.006266 -35.238281 143.554688 -340.664062 -0.008301 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285638 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629032 0.317279 0.000000 -0.018795 0.009569 -0.035921 0.046580 0.126368 0.016935 0.073663 0.107915 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.601868 0.001297 0.005240 -0.938724 -0.004193 0.000335 0.005202 -35.238281 143.554688 -340.664062 -0.008301 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286389 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628959 0.317293 0.000000 -0.018803 0.009578 -0.035605 0.046576 0.126050 0.017234 0.073996 0.107600 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.606873 0.000564 0.004508 -0.941654 -0.004193 0.001399 0.004137 -38.648438 144.703125 -339.468750 -0.008300 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287124 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629335 0.317205 0.000000 -0.018983 0.009584 -0.035289 0.046579 0.125909 0.017364 0.074498 0.107109 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.611877 0.001541 0.004996 -0.941898 -0.005257 0.000335 0.005202 -38.648438 144.703125 -339.468750 -0.008302 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287845 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629458 0.317023 0.000000 -0.018820 0.009745 -0.035605 0.046579 0.125890 0.017040 0.074169 0.107740 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.616882 -0.000656 0.005484 -0.944828 -0.004193 0.000335 0.005202 -39.785156 141.257812 -350.226562 -0.008297 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288551 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629595 0.316723 0.000000 -0.018833 0.009567 -0.035605 0.046579 0.126081 0.017205 0.074005 0.107549 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.621887 0.001541 0.005973 -0.943119 -0.004193 0.000335 0.005202 -39.785156 141.257812 -350.226562 -0.008291 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289242 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629689 0.316381 0.000000 -0.018843 0.009564 -0.035605 0.046579 0.126095 0.017197 0.074012 0.107536 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.626892 -0.000656 0.005729 -0.940189 -0.004193 0.000335 0.004137 -38.648438 144.703125 -341.859375 -0.008285 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289919 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629710 0.316043 0.000000 -0.018851 0.009560 -0.035289 0.046578 0.125790 0.017510 0.074332 0.107208 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.631897 0.003006 0.002311 -0.941898 -0.004193 0.001399 0.003073 -38.648438 144.703125 -341.859375 -0.008279 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290582 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629974 0.315697 0.000000 -0.019025 0.009555 -0.034973 0.046581 0.125652 0.017657 0.074817 0.106714 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.636902 0.000076 0.004264 -0.939457 -0.004193 0.001399 0.004137 -45.468750 142.406250 -344.250000 -0.008271 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291232 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630197 0.315272 0.000000 -0.019021 0.009548 -0.035289 0.046583 0.125973 0.017352 0.074490 0.107025 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.641907 -0.000168 0.008658 -0.941654 -0.003128 0.002463 0.005202 -45.468750 142.406250 -344.250000 -0.008256 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291869 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630684 0.314484 0.000000 -0.019187 0.009369 -0.035605 0.046590 0.126633 0.017050 0.074160 0.106997 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.646912 0.000564 0.007193 -0.942386 -0.004193 0.001399 0.006266 -42.058594 138.960938 -340.664062 -0.008248 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292493 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630764 0.314114 0.000000 -0.019006 0.009536 -0.035921 0.046591 0.126601 0.016746 0.073832 0.107661 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.651917 -0.000656 0.009146 -0.939945 -0.006321 0.001399 0.006266 -42.058594 138.960938 -340.664062 -0.008254 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293103 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630753 0.314574 0.000000 -0.019001 0.009871 -0.035921 0.046591 0.126261 0.016417 0.074161 0.108001 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.656921 0.001053 0.007437 -0.946537 -0.005257 0.000335 0.006266 -40.921875 140.109375 -339.468750 -0.008259 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293702 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630340 0.315254 0.000000 -0.018825 0.009702 -0.035921 0.046584 0.126264 0.016772 0.073826 0.108019 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.661926 0.003494 0.007193 -0.946537 -0.004193 0.000335 0.006266 -40.921875 140.109375 -339.468750 -0.008264 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294288 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629924 0.315567 0.000000 -0.018824 0.009542 -0.035921 0.046576 0.126423 0.016933 0.073664 0.107859 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.666931 0.000076 0.008414 -0.946537 -0.006321 0.001399 0.006266 -40.921875 142.406250 -344.250000 -0.008282 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294862 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629897 0.316718 0.000000 -0.018993 0.009902 -0.035921 0.046574 0.126232 0.016405 0.074193 0.108050 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.671936 0.001053 0.008170 -0.942630 -0.005257 0.002463 0.007330 -40.921875 142.406250 -344.250000 -0.008300 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295425 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630241 0.317710 0.000000 -0.019156 0.009746 -0.036237 0.046579 0.126867 0.016080 0.073885 0.108048 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.676941 0.001053 0.005729 -0.939701 -0.005257 0.002463 0.007330 -40.921875 142.406250 -344.250000 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295976 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630603 0.318821 0.000000 -0.019146 0.009773 -0.036237 0.046585 0.126830 0.016064 0.073901 0.108084 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.681946 0.001297 0.006217 -0.942630 -0.005257 0.001399 0.008394 -39.785156 141.257812 -345.445312 -0.008341 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296316 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630673 0.319942 0.000000 -0.018970 0.009800 -0.036553 0.046586 0.126943 0.015896 0.073437 0.108604 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.686951 0.000809 0.008658 -0.942875 -0.005257 0.000335 0.007330 -39.785156 141.257812 -345.445312 -0.008362 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296649 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630461 0.321019 0.000000 -0.018803 0.009827 -0.036237 0.046582 0.126433 0.016352 0.073613 0.108482 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.691956 0.001297 0.005973 -0.944584 -0.005257 0.000335 0.007330 -42.058594 143.554688 -340.664062 -0.008383 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296976 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630289 0.322050 0.000000 -0.018812 0.009854 -0.036237 0.046579 0.126416 0.016317 0.073649 0.108499 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.696960 -0.000656 0.007193 -0.945072 -0.007385 0.001399 0.008394 -42.058594 143.554688 -340.664062 -0.008414 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297296 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630442 0.323634 0.000000 -0.018989 0.010216 -0.036553 0.046581 0.126546 0.015461 0.073872 0.109000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.701965 -0.000412 0.004752 -0.943119 -0.005257 0.000335 0.007330 -37.511719 136.664062 -347.835938 -0.008433 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297610 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630216 0.324151 0.000000 -0.018819 0.009878 -0.036237 0.046577 0.126388 0.016276 0.073670 0.108507 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.706970 -0.000900 0.004020 -0.943363 -0.004193 0.000335 0.006266 -37.511719 136.664062 -347.835938 -0.008443 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297918 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629889 0.324479 0.000000 -0.018821 0.009729 -0.035921 0.046571 0.126223 0.016739 0.073839 0.108039 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.711975 -0.000656 0.003531 -0.942630 -0.005257 0.000335 0.007330 -40.921875 135.515625 -349.031250 -0.008455 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298220 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629437 0.324873 0.000000 -0.018818 0.009916 -0.036237 0.046563 0.126349 0.016239 0.073706 0.108546 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.716980 -0.001145 0.004264 -0.944828 -0.005257 0.000335 0.006266 -40.921875 135.515625 -349.031250 -0.008462 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298515 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628847 0.324967 0.000000 -0.018809 0.009917 -0.035921 0.046552 0.126023 0.016562 0.074015 0.108240 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.721985 -0.002365 0.007437 -0.944584 -0.004193 0.000335 0.006266 -40.921875 140.109375 -341.859375 -0.008459 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298806 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628105 0.324507 0.000000 -0.018795 0.009743 -0.035921 0.046538 0.126183 0.016751 0.073826 0.108079 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.726990 0.000809 0.007193 -0.940433 -0.005257 0.002463 0.005202 -40.921875 140.109375 -341.859375 -0.008460 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299090 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627842 0.324280 0.000000 -0.019113 0.009910 -0.035605 0.046531 0.126018 0.016582 0.074628 0.107612 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.731995 0.001785 0.009146 -0.940677 -0.004193 0.001399 0.005202 -42.058594 143.554688 -338.273438 -0.008455 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299369 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627192 0.323802 0.000000 -0.018909 0.009733 -0.035605 0.046518 0.125992 0.016962 0.074247 0.107639 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.737000 0.001785 0.008414 -0.941898 -0.004193 0.001399 0.005202 -42.058594 143.554688 -338.273438 -0.008454 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299643 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626618 0.323530 0.000000 -0.018886 0.009738 -0.035605 0.046506 0.125963 0.016981 0.074229 0.107667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.742004 0.000809 0.007926 -0.942630 -0.004193 0.001399 0.004137 -39.785156 143.554688 -340.664062 -0.008456 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299911 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626192 0.323522 0.000000 -0.018868 0.009749 -0.035289 0.046496 0.125618 0.017304 0.074537 0.107380 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.747009 -0.000168 0.007437 -0.944095 -0.004193 0.000335 0.004137 -39.785156 143.554688 -340.664062 -0.008463 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300174 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625241 0.324060 0.000000 -0.018675 0.009775 -0.035274 0.046483 0.125394 0.017497 0.074396 0.107594 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.752014 -0.000412 0.006949 -0.944095 -0.003128 0.000335 0.005202 -38.648438 140.109375 -341.859375 -0.008467 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300431 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624762 0.324173 0.000000 -0.018672 0.009627 -0.035590 0.046472 0.125854 0.017331 0.073929 0.107766 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.757019 0.001297 0.009391 -0.943607 -0.003128 0.001399 0.004137 -38.648438 140.109375 -341.859375 -0.008474 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624657 0.324449 0.000000 -0.018838 0.009659 -0.035274 0.046467 0.125673 0.017450 0.074443 0.107315 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.762024 0.002518 0.006461 -0.944095 -0.004193 0.002463 0.005202 -46.605469 141.257812 -338.273438 -0.008489 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300931 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624938 0.325174 0.000000 -0.018999 0.009860 -0.035590 0.046469 0.125949 0.016771 0.074489 0.107671 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.767029 -0.000900 0.008902 -0.944095 -0.004193 0.001399 0.004137 -46.605469 141.257812 -338.273438 -0.008506 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301173 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625340 0.325976 0.000000 -0.018830 0.009887 -0.035289 0.046466 0.125453 0.017214 0.074648 0.107566 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.772034 0.000809 0.005240 -0.947269 -0.004193 0.000335 0.005202 -38.648438 137.812500 -344.250000 -0.008523 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301410 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625117 0.326801 0.000000 -0.018661 0.009914 -0.035605 0.046460 0.125572 0.017040 0.074189 0.108078 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.777039 0.000320 0.005240 -0.944339 -0.004193 0.001399 0.005202 -38.648438 137.812500 -344.250000 -0.008539 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301643 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625228 0.327550 0.000000 -0.018836 0.009938 -0.035605 0.046460 0.125723 0.016841 0.074389 0.107927 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.782043 0.002518 0.004264 -0.943363 -0.005257 -0.000729 0.005202 -38.648438 137.812500 -344.250000 -0.008558 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301872 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624731 0.328419 0.000000 -0.018497 0.010125 -0.035605 0.046449 0.125197 0.016992 0.074238 0.108453 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.787048 0.000809 0.005973 -0.940921 -0.004193 0.001399 0.005202 -45.468750 137.812500 -337.078125 -0.008568 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302096 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624939 0.328717 0.000000 -0.018849 0.009961 -0.035605 0.046450 0.125714 0.016804 0.074425 0.107937 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.792053 0.003006 0.006705 -0.940433 -0.004193 0.000335 0.006266 -45.468750 137.812500 -337.078125 -0.008574 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302316 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624907 0.328505 0.000000 -0.018682 0.009958 -0.035921 0.046447 0.125855 0.016649 0.073928 0.108407 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.797058 0.001785 0.004508 -0.940921 -0.004193 0.002463 0.007330 -40.921875 135.515625 -341.859375 -0.008577 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302532 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625611 0.328434 0.000000 -0.019031 0.009958 -0.036237 0.046457 0.126520 0.015983 0.073962 0.108375 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.802063 0.004227 0.002311 -0.943607 -0.004193 0.001399 0.007330 -40.921875 135.515625 -341.859375 -0.008576 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626112 0.328180 0.000000 -0.018864 0.009953 -0.036237 0.046464 0.126358 0.016156 0.073790 0.108537 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.807068 -0.000168 0.005729 -0.940189 -0.005257 0.001399 0.007330 -44.332031 143.554688 -340.664062 -0.008577 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302950 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626737 0.328015 0.000000 -0.018878 0.010110 -0.036237 0.046474 0.126215 0.015985 0.073961 0.108679 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.812073 0.000564 0.004508 -0.945804 -0.006321 0.000335 0.006266 -44.332031 143.554688 -340.664062 -0.008579 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303153 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627083 0.328266 0.000000 -0.018725 0.010264 -0.035921 0.046480 0.125602 0.016310 0.074287 0.108680 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.817078 -0.000168 0.007437 -0.946048 -0.004193 0.002463 0.007330 -42.058594 134.367188 -345.445312 -0.008568 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303352 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628004 0.327480 0.000000 -0.019083 0.009894 -0.036237 0.046496 0.126647 0.016006 0.073960 0.108268 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.822083 -0.001633 0.007193 -0.942142 -0.005257 0.001399 0.008394 -42.058594 134.367188 -345.445312 -0.008563 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303547 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628441 0.327052 0.000000 -0.018916 0.010047 -0.036553 0.046504 0.126642 0.015703 0.073631 0.108904 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.827087 -0.004074 0.005484 -0.942142 -0.003128 0.001399 0.007330 -43.195312 142.406250 -344.250000 -0.008549 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303738 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628604 0.326115 0.000000 -0.018919 0.009691 -0.036237 0.046508 0.126685 0.016373 0.073592 0.108229 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.832092 -0.000412 0.005973 -0.941654 -0.005257 0.001399 0.006266 -43.195312 142.406250 -344.250000 -0.008546 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303925 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628417 0.325652 0.000000 -0.018911 0.010018 -0.035921 0.046506 0.126024 0.016359 0.074218 0.108239 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.837097 -0.001877 0.006949 -0.943607 -0.005257 0.000335 0.006266 -40.921875 147.000000 -344.250000 -0.008546 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304108 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627601 0.325594 0.000000 -0.018725 0.010006 -0.035921 0.046493 0.125850 0.016558 0.074019 0.108412 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.842102 0.000564 0.004996 -0.942386 -0.003128 0.000335 0.006266 -40.921875 147.000000 -344.250000 -0.008536 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304288 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626577 0.325012 0.000000 -0.018708 0.009659 -0.035921 0.046476 0.126179 0.016922 0.073656 0.108083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.847107 0.001053 0.004996 -0.945560 -0.005257 0.001399 0.007330 -45.468750 140.109375 -341.859375 -0.008538 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304464 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625784 0.325136 0.000000 -0.018856 0.010005 -0.036237 0.046462 0.126298 0.016113 0.073833 0.108596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.852112 0.000809 0.005973 -0.941410 -0.005257 0.000335 0.007330 -45.468750 140.109375 -341.859375 -0.008540 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304636 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624707 0.325256 0.000000 -0.018659 0.009997 -0.036237 0.046442 0.126109 0.016317 0.073629 0.108785 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.857117 0.001053 0.006217 -0.942386 -0.005257 0.000335 0.006266 -40.921875 144.703125 -349.031250 -0.008542 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304805 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623755 0.325672 0.000000 -0.018641 0.010000 -0.035921 0.046424 0.125783 0.016658 0.073940 0.108500 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.862122 0.001785 0.008658 -0.940189 -0.005257 0.000335 0.005202 -40.921875 144.703125 -349.031250 -0.008545 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304971 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622978 0.325833 0.000000 -0.018628 0.009996 -0.035605 0.046408 0.125457 0.016991 0.074239 0.108193 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.867126 0.001297 0.007437 -0.940433 -0.005257 0.000335 0.004137 -38.648438 140.109375 -344.250000 -0.008550 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305133 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622409 0.326114 0.000000 -0.018619 0.009997 -0.035289 0.046395 0.125132 0.017315 0.074547 0.107886 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.872131 0.000809 0.007193 -0.945316 -0.004193 0.001399 0.004137 -38.648438 140.109375 -344.250000 -0.008552 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305292 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622353 0.326231 0.000000 -0.018785 0.009834 -0.035289 0.046391 0.125460 0.017312 0.074550 0.107558 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.877136 -0.000412 0.003287 -0.941654 -0.004193 0.000335 0.003073 -47.742188 144.703125 -344.250000 -0.008556 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305448 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622108 0.326445 0.000000 -0.018609 0.009850 -0.034973 0.046384 0.124952 0.017788 0.074706 0.107434 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.882141 0.002518 0.006217 -0.942630 -0.004193 0.000335 0.005202 -47.742188 144.703125 -344.250000 -0.008560 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305399 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621968 0.326637 0.000000 -0.018613 0.009864 -0.035605 0.046378 0.125574 0.017138 0.074092 0.108076 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.887146 0.001297 0.004996 -0.942875 -0.004193 0.000335 0.005202 -47.742188 144.703125 -344.250000 -0.008563 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305351 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621929 0.326748 0.000000 -0.018618 0.009875 -0.035605 0.046374 0.125569 0.017122 0.074108 0.108081 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.892151 -0.000168 0.006705 -0.945316 -0.005257 0.000335 0.005202 -42.058594 141.257812 -343.054688 -0.008569 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305304 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621972 0.327088 0.000000 -0.018626 0.010051 -0.035605 0.046372 0.125400 0.016939 0.074291 0.108250 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.897156 0.001297 0.008414 -0.944339 -0.006321 0.001399 0.005202 -42.058594 141.257812 -343.054688 -0.008581 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305258 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622354 0.327694 0.000000 -0.018802 0.010219 -0.035605 0.046376 0.125408 0.016594 0.074636 0.108242 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.902161 0.002029 0.007926 -0.940677 -0.004193 0.000335 0.005202 -37.511719 138.960938 -343.054688 -0.008583 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305213 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622425 0.327712 0.000000 -0.018634 0.009877 -0.035605 0.046375 0.125582 0.017105 0.074125 0.108068 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.907166 0.000809 0.008170 -0.945072 -0.005257 0.000335 0.006266 -37.511719 138.960938 -343.054688 -0.008592 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305169 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622533 0.328178 0.000000 -0.018643 0.010060 -0.035921 0.046375 0.125724 0.016596 0.074001 0.108558 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.912170 0.001785 0.004996 -0.942875 -0.004193 0.000335 0.006266 -40.921875 147.000000 -341.859375 -0.008598 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305126 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622671 0.328436 0.000000 -0.018652 0.009901 -0.035921 0.046376 0.125892 0.016746 0.073852 0.108390 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.917175 0.002762 0.004508 -0.942630 -0.004193 0.000335 0.006266 -40.921875 147.000000 -341.859375 -0.008604 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622852 0.328713 0.000000 -0.018662 0.009919 -0.035921 0.046377 0.125885 0.016718 0.073880 0.108398 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.922180 0.000076 0.007193 -0.942142 -0.005257 0.000335 0.007330 -42.058594 141.257812 -340.664062 -0.008615 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305042 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622725 0.329234 0.000000 -0.018662 0.010102 -0.036222 0.046380 0.126002 0.016233 0.073762 0.108882 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.927185 0.001785 0.007437 -0.940677 -0.005257 0.000335 0.006266 -42.058594 141.257812 -340.664062 -0.008625 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305002 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622970 0.329692 0.000000 -0.018673 0.010108 -0.035906 0.046383 0.125691 0.016533 0.074095 0.108561 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.932190 0.000076 0.003287 -0.947025 -0.004193 -0.001794 0.006266 -43.195312 140.109375 -339.468750 -0.008629 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304962 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622572 0.329781 0.000000 -0.018345 0.009944 -0.035906 0.046376 0.125527 0.017025 0.073603 0.108725 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.937195 -0.000412 0.006217 -0.941410 -0.004193 0.000335 0.007330 -43.195312 140.109375 -339.468750 -0.008631 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304923 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622765 0.329773 0.000000 -0.018704 0.009953 -0.036222 0.046378 0.126193 0.016342 0.073654 0.108691 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.942200 -0.001145 0.005729 -0.943119 -0.006321 0.001399 0.007330 -39.785156 143.554688 -343.054688 -0.008642 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304885 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623490 0.330280 0.000000 -0.018884 0.010295 -0.036237 0.046384 0.126046 0.015804 0.074161 0.108869 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.947205 -0.002609 0.006949 -0.944339 -0.005257 0.000335 0.007330 -39.785156 143.554688 -343.054688 -0.008646 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304848 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623314 0.330377 0.000000 -0.018702 0.010115 -0.036237 0.046380 0.126045 0.016166 0.073800 0.108870 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.952209 -0.000412 0.007437 -0.941410 -0.004193 0.001399 0.006266 -40.921875 135.515625 -341.859375 -0.008644 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304812 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623199 0.330152 0.000000 -0.018859 0.009943 -0.035921 0.046378 0.126058 0.016497 0.074101 0.108225 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.957214 -0.002609 0.005240 -0.940433 -0.005257 0.000335 0.007330 -40.921875 135.515625 -341.859375 -0.008648 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304776 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622521 0.330285 0.000000 -0.018665 0.010117 -0.036237 0.046366 0.126005 0.016201 0.073765 0.108909 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.962219 -0.000656 0.004752 -0.938724 -0.004193 0.000335 0.006266 -37.511719 143.554688 -343.054688 -0.008647 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304742 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621633 0.330104 0.000000 -0.018641 0.009946 -0.035921 0.046350 0.125836 0.016712 0.073885 0.108446 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.967224 0.003738 0.006705 -0.939457 -0.004193 0.001399 0.006266 -37.511719 143.554688 -343.054688 -0.008645 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304707 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620966 0.329602 0.000000 -0.018782 0.009941 -0.035921 0.046337 0.125973 0.016566 0.074012 0.108289 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.972229 0.000809 0.005240 -0.940677 -0.005257 0.000335 0.006266 -40.921875 144.703125 -344.250000 -0.008648 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304673 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620059 0.329697 0.000000 -0.018582 0.010112 -0.035921 0.046319 0.125602 0.016595 0.073983 0.108661 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.977234 0.000320 0.007193 -0.939945 -0.004193 0.002463 0.005202 -40.921875 144.703125 -344.250000 -0.008646 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304640 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619942 0.329467 0.000000 -0.018901 0.009938 -0.035605 0.046315 0.125779 0.016766 0.074444 0.107852 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.982239 0.003006 0.004264 -0.942630 -0.004193 0.003528 0.006266 -39.785156 141.257812 -340.664062 -0.008643 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304606 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620291 0.329247 0.000000 -0.019044 0.009940 -0.035921 0.046318 0.126235 0.016305 0.074273 0.108027 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.987244 0.002273 0.006461 -0.938236 -0.005257 0.001399 0.005202 -39.785156 141.257812 -340.664062 -0.008645 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304573 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620200 0.329630 0.000000 -0.018683 0.010119 -0.035605 0.046314 0.125389 0.016814 0.074416 0.108261 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.992249 -0.000656 0.004020 -0.941654 -0.004193 0.001399 0.006266 -39.785156 141.257812 -340.664062 -0.008641 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304540 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620322 0.329355 0.000000 -0.018682 0.009942 -0.035921 0.046314 0.125881 0.016675 0.073923 0.108401 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+457.997253 0.000076 0.004020 -0.942875 -0.005257 0.001399 0.006266 -37.511719 143.554688 -338.273438 -0.008641 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304507 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620551 0.329321 0.000000 -0.018685 0.010108 -0.035921 0.046316 0.125718 0.016505 0.074093 0.108564 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.002258 -0.000412 0.003287 -0.944828 -0.005257 0.000335 0.006266 -37.511719 143.554688 -338.273438 -0.008639 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304475 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620478 0.329140 0.000000 -0.018520 0.010094 -0.035921 0.046313 0.125567 0.016684 0.073914 0.108715 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.007263 0.000320 0.002555 -0.944095 -0.005257 0.001399 0.006266 -43.195312 137.812500 -349.031250 -0.008633 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304442 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620688 0.328765 0.000000 -0.018699 0.010076 -0.035921 0.046315 0.125764 0.016524 0.074073 0.108518 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.012268 0.000320 0.004020 -0.945804 -0.005257 0.001399 0.005202 -43.195312 137.812500 -349.031250 -0.008623 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304410 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620467 0.328181 0.000000 -0.018688 0.010052 -0.035605 0.046317 0.125461 0.016876 0.074354 0.108189 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.017273 0.001053 0.003531 -0.943363 -0.005257 0.000335 0.005202 -39.785156 138.960938 -340.664062 -0.008609 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304379 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620244 0.327418 0.000000 -0.018518 0.010023 -0.035605 0.046312 0.125320 0.017074 0.074155 0.108330 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.022278 -0.000168 0.005240 -0.943363 -0.004193 0.000335 0.004137 -39.785156 138.960938 -340.664062 -0.008588 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304348 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619999 0.326236 0.000000 -0.018522 0.009823 -0.035289 0.046307 0.125209 0.017586 0.074276 0.107809 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.027283 0.003250 0.006217 -0.946048 -0.005257 0.000335 0.004137 -32.964844 138.960938 -347.835938 -0.008571 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304318 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619768 0.325377 0.000000 -0.018526 0.009967 -0.035289 0.046301 0.125068 0.017438 0.074424 0.107951 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.032288 0.002029 0.004020 -0.944584 -0.005257 0.000335 0.006266 -32.964844 138.960938 -347.835938 -0.008556 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304289 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619991 0.324593 0.000000 -0.018542 0.009938 -0.035906 0.046298 0.125730 0.016834 0.073794 0.108522 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.037292 0.000320 0.003531 -0.939213 -0.004193 0.001399 0.006266 -39.785156 141.257812 -347.835938 -0.008535 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304261 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620278 0.323572 0.000000 -0.018718 0.009743 -0.035906 0.046301 0.126101 0.016853 0.073775 0.108151 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.042297 0.000564 0.004752 -0.942875 -0.006321 0.000335 0.005202 -39.785156 141.257812 -347.835938 -0.008526 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304234 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620297 0.323234 0.000000 -0.018551 0.010063 -0.035590 0.046301 0.125298 0.017016 0.074244 0.108321 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.047302 0.001297 0.004752 -0.942630 -0.004193 0.001399 0.006266 -39.785156 143.554688 -345.445312 -0.008506 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304207 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620653 0.322301 0.000000 -0.018729 0.009694 -0.035906 0.046306 0.126161 0.016890 0.073738 0.108091 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.052307 0.004471 0.005729 -0.943363 -0.005257 0.000335 0.006266 -39.785156 143.554688 -345.445312 -0.008493 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304181 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620737 0.321770 0.000000 -0.018564 0.009850 -0.035921 0.046306 0.125855 0.016885 0.073713 0.108427 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.057312 0.002273 0.003531 -0.942630 -0.005257 0.001399 0.006266 -39.785156 138.960938 -340.664062 -0.008481 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304156 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621264 0.321318 0.000000 -0.018748 0.009832 -0.035921 0.046315 0.126057 0.016719 0.073878 0.108225 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.062317 0.002273 0.003531 -0.943607 -0.005257 0.000335 0.007330 -39.785156 138.960938 -340.664062 -0.008470 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304131 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621615 0.320900 0.000000 -0.018591 0.009815 -0.036237 0.046321 0.126233 0.016577 0.073388 0.108682 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.067322 0.001053 0.002799 -0.946048 -0.005257 0.001399 0.007330 -39.785156 143.554688 -343.054688 -0.008457 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304107 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622379 0.320449 0.000000 -0.018781 0.009798 -0.036237 0.046334 0.126441 0.016404 0.073562 0.108474 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.072327 -0.001389 0.004752 -0.942386 -0.004193 0.001399 0.006266 -39.785156 143.554688 -343.054688 -0.008439 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304084 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623121 0.319625 0.000000 -0.018795 0.009610 -0.035921 0.046348 0.126326 0.016893 0.073705 0.107956 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.077332 0.001785 0.006217 -0.941166 -0.005257 0.001399 0.006266 -40.921875 142.406250 -349.031250 -0.008425 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304061 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623385 0.319114 0.000000 -0.018796 0.009767 -0.035906 0.046360 0.126155 0.016751 0.073877 0.108097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.082336 -0.000412 0.003287 -0.940677 -0.006321 0.001399 0.007330 -40.921875 142.406250 -349.031250 -0.008418 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304039 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623869 0.318952 0.000000 -0.018804 0.009918 -0.036222 0.046370 0.126329 0.016276 0.073720 0.108555 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.087341 0.001053 0.004996 -0.943363 -0.005257 0.000335 0.006266 -35.238281 143.554688 -340.664062 -0.008405 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304018 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623892 0.318497 0.000000 -0.018640 0.009725 -0.035906 0.046372 0.126041 0.016949 0.073679 0.108211 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.092346 0.002273 0.005729 -0.942630 -0.005257 0.000335 0.007330 -35.238281 143.554688 -340.664062 -0.008394 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303997 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623825 0.318090 0.000000 -0.018648 0.009711 -0.036222 0.046373 0.126379 0.016638 0.073358 0.108505 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.097351 0.000076 0.003043 -0.939213 -0.006321 0.000335 0.006266 -35.238281 143.554688 -340.664062 -0.008388 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303976 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624077 0.318051 0.000000 -0.018665 0.009869 -0.035921 0.046373 0.125938 0.016765 0.073832 0.108345 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.102356 0.000809 0.003043 -0.938724 -0.006321 0.000335 0.005202 -39.785156 138.960938 -345.445312 -0.008383 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303955 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623930 0.317993 0.000000 -0.018669 0.009850 -0.035605 0.046372 0.125644 0.017096 0.074134 0.108007 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.107361 0.000320 0.005729 -0.939213 -0.006321 0.000335 0.006266 -39.785156 138.960938 -345.445312 -0.008377 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303935 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623743 0.317883 0.000000 -0.018670 0.009833 -0.035921 0.046370 0.125979 0.016796 0.073802 0.108304 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.112366 0.000076 0.005484 -0.941410 -0.005257 0.001399 0.004137 -42.058594 141.257812 -343.054688 -0.008366 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303915 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623812 0.317461 0.000000 -0.018838 0.009648 -0.035289 0.046373 0.125700 0.017445 0.074417 0.107318 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.117371 -0.000656 0.005729 -0.942142 -0.005257 0.001399 0.005202 -42.058594 141.257812 -343.054688 -0.008356 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303894 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623798 0.317115 0.000000 -0.018828 0.009641 -0.035605 0.046374 0.126012 0.017146 0.074084 0.107638 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.122375 -0.001145 0.005729 -0.942875 -0.004193 0.001399 0.005202 -45.468750 140.109375 -346.640625 -0.008342 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303874 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623668 0.316264 0.000000 -0.018815 0.009460 -0.035605 0.046372 0.126171 0.017330 0.073880 0.107459 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.127380 0.000076 0.008902 -0.941898 -0.005257 0.000335 0.004137 -45.468750 140.109375 -346.640625 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303854 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623097 0.316201 0.000000 -0.018631 0.009636 -0.035289 0.046363 0.125494 0.017654 0.074188 0.107504 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.132385 0.001541 0.007682 -0.943363 -0.004193 0.001399 0.005202 -40.921875 144.703125 -344.250000 -0.008331 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303834 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622780 0.316062 0.000000 -0.018790 0.009473 -0.035605 0.046358 0.126132 0.017342 0.073868 0.107498 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.137390 0.003006 0.008658 -0.943363 -0.005257 0.001399 0.005202 -40.921875 144.703125 -344.250000 -0.008335 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303814 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622491 0.316534 0.000000 -0.018773 0.009663 -0.035605 0.046353 0.125926 0.017169 0.074041 0.107705 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.142395 0.000809 0.007437 -0.943851 -0.006321 0.002463 0.004137 -43.195312 142.406250 -339.468750 -0.008350 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303794 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622631 0.317887 0.000000 -0.018930 0.009862 -0.035289 0.046356 0.125577 0.017139 0.074723 0.107441 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.147400 0.001541 0.005484 -0.942386 -0.004193 0.002463 0.005202 -43.195312 142.406250 -339.468750 -0.008358 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303774 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622894 0.318492 0.000000 -0.018917 0.009545 -0.035605 0.046360 0.126197 0.017153 0.074077 0.107453 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.152405 0.002518 0.005240 -0.943119 -0.004193 0.002463 0.005202 -47.742188 142.406250 -344.250000 -0.008368 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303755 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623277 0.319174 0.000000 -0.018910 0.009582 -0.035605 0.046367 0.126153 0.017124 0.074106 0.107497 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.157410 0.002518 0.006217 -0.947269 -0.004193 0.001399 0.005202 -47.742188 142.406250 -344.250000 -0.008378 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303736 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623492 0.319819 0.000000 -0.018740 0.009615 -0.035605 0.046371 0.125950 0.017260 0.073970 0.107700 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.162415 0.002273 0.006949 -0.947513 -0.004193 0.001399 0.005202 -38.648438 142.406250 -341.859375 -0.008388 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303718 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623513 0.320392 0.000000 -0.018741 0.009645 -0.035590 0.046378 0.125906 0.017244 0.074017 0.107713 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.167419 0.000809 0.006461 -0.945560 -0.004193 0.002463 0.006266 -38.648438 142.406250 -341.859375 -0.008397 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303700 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624337 0.320896 0.000000 -0.018926 0.009671 -0.035906 0.046393 0.126381 0.016716 0.073912 0.107871 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.172424 -0.001145 0.006217 -0.944339 -0.004193 0.000335 0.006266 -42.058594 145.851562 -352.617188 -0.008405 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624548 0.321337 0.000000 -0.018599 0.009694 -0.035906 0.046398 0.126031 0.017021 0.073607 0.108221 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.177429 0.001297 0.004508 -0.943851 -0.004193 0.001399 0.007330 -42.058594 145.851562 -352.617188 -0.008412 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625015 0.321686 0.000000 -0.018790 0.009713 -0.036222 0.046407 0.126519 0.016494 0.073502 0.108365 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.182434 0.001541 0.007193 -0.938236 -0.005257 0.001399 0.007330 -47.742188 137.812500 -339.468750 -0.008422 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303652 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625390 0.322234 0.000000 -0.018802 0.009897 -0.036222 0.046415 0.126347 0.016299 0.073697 0.108537 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.187439 0.001053 0.007926 -0.943119 -0.004193 0.000335 0.006266 -47.742188 137.812500 -339.468750 -0.008427 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304241 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625749 0.322096 0.000000 -0.018653 0.009725 -0.035921 0.046417 0.126060 0.016911 0.073667 0.108202 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.192444 -0.002854 0.003287 -0.942142 -0.004193 0.000335 0.007330 -38.648438 142.406250 -349.031250 -0.008431 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304818 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625669 0.322232 0.000000 -0.018666 0.009736 -0.036237 0.046418 0.126377 0.016570 0.073375 0.108517 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.197449 -0.001145 0.005484 -0.943119 -0.005257 0.001399 0.007330 -38.648438 142.406250 -349.031250 -0.008439 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305383 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625722 0.322595 0.000000 -0.018841 0.009914 -0.036237 0.046420 0.126375 0.016218 0.073727 0.108520 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.202454 0.001541 0.007437 -0.940677 -0.005257 0.001399 0.007330 -38.648438 142.406250 -349.031250 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305938 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625566 0.322848 0.000000 -0.018833 0.009912 -0.036237 0.046419 0.126369 0.016228 0.073718 0.108526 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.207458 -0.001633 0.006461 -0.939457 -0.006321 0.001399 0.007330 -43.195312 140.109375 -344.250000 -0.008456 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306481 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625265 0.323376 0.000000 -0.018821 0.010079 -0.036237 0.046415 0.126190 0.016072 0.073873 0.108705 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.212463 0.001297 0.005729 -0.940677 -0.005257 0.000335 0.008394 -43.195312 140.109375 -344.250000 -0.008461 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307013 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624555 0.323576 0.000000 -0.018638 0.009903 -0.036553 0.046404 0.126498 0.016116 0.073197 0.109028 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.217468 -0.000168 0.008170 -0.942386 -0.004193 0.001399 0.007330 -42.058594 134.367188 -340.664062 -0.008462 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624125 0.323490 0.000000 -0.018798 0.009736 -0.036237 0.046397 0.126509 0.016439 0.073506 0.108386 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.222473 0.002518 0.006461 -0.947269 -0.004193 0.001399 0.006266 -42.058594 134.367188 -340.664062 -0.008464 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308045 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623715 0.323489 0.000000 -0.018781 0.009747 -0.035921 0.046390 0.126165 0.016760 0.073818 0.108097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.227478 0.002029 0.008414 -0.941410 -0.005257 0.002463 0.006266 -42.058594 141.257812 -345.445312 -0.008473 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308546 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623725 0.323909 0.000000 -0.018938 0.009930 -0.035921 0.046390 0.126140 0.016421 0.074156 0.108123 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.232483 -0.000412 0.005240 -0.942875 -0.005257 0.001399 0.004137 -42.058594 141.257812 -345.445312 -0.008483 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309036 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623544 0.324416 0.000000 -0.018755 0.009938 -0.035289 0.046387 0.125316 0.017228 0.074614 0.107683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.237488 0.001785 0.006705 -0.944339 -0.005257 0.001399 0.005202 -39.785156 138.960938 -347.835938 -0.008495 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309516 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623478 0.324960 0.000000 -0.018752 0.009949 -0.035605 0.046385 0.125618 0.016904 0.074306 0.108012 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.242493 0.003006 0.007193 -0.945804 -0.005257 0.000335 0.006266 -39.785156 138.960938 -347.835938 -0.008507 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309986 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623224 0.325509 0.000000 -0.018584 0.009960 -0.035921 0.046380 0.125755 0.016745 0.073833 0.108507 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.247498 -0.000412 0.006217 -0.942142 -0.005257 0.000335 0.006266 -39.785156 141.257812 -345.445312 -0.008519 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310447 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623119 0.326061 0.000000 -0.018596 0.009972 -0.035921 0.046378 0.125755 0.016721 0.073857 0.108508 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.252502 -0.000412 0.009879 -0.946048 -0.004193 0.001399 0.005202 -39.785156 141.257812 -345.445312 -0.008527 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310899 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623390 0.326628 0.000000 -0.018776 0.009826 -0.035605 0.046382 0.125776 0.017013 0.074217 0.107875 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.257507 0.000809 0.005729 -0.946537 -0.004193 0.000335 0.004137 -39.785156 143.554688 -345.445312 -0.008536 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311342 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623315 0.326978 0.000000 -0.018611 0.009848 -0.035289 0.046380 0.125271 0.017472 0.074390 0.107747 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.262512 0.000564 0.004020 -0.941654 -0.004193 0.000335 0.005202 -39.785156 143.554688 -345.445312 -0.008545 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311776 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623209 0.327343 0.000000 -0.018619 0.009870 -0.035605 0.046378 0.125575 0.017126 0.074104 0.108075 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.267517 0.001541 0.006949 -0.943363 -0.005257 0.001399 0.005202 -44.332031 138.960938 -345.445312 -0.008559 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312202 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623394 0.327934 0.000000 -0.018795 0.010056 -0.035605 0.046381 0.125564 0.016764 0.074466 0.108086 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.272522 -0.000168 0.004508 -0.943119 -0.004193 0.000335 0.005202 -44.332031 138.960938 -345.445312 -0.008565 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312620 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623240 0.328081 0.000000 -0.018625 0.009894 -0.035605 0.046378 0.125556 0.017097 0.074133 0.108094 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.277527 0.001053 0.006217 -0.942630 -0.004193 0.000335 0.005202 -43.195312 135.515625 -344.250000 -0.008568 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313030 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623068 0.328104 0.000000 -0.018629 0.009903 -0.035605 0.046374 0.125551 0.017082 0.074147 0.108099 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.282532 0.002762 0.005973 -0.945316 -0.004193 0.001399 0.006266 -43.195312 135.515625 -344.250000 -0.008570 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313431 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623221 0.328016 0.000000 -0.018802 0.009909 -0.035921 0.046376 0.126035 0.016588 0.074010 0.108247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.287537 0.002762 0.004996 -0.939213 -0.004193 0.000335 0.006266 -38.648438 142.406250 -346.640625 -0.008570 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313825 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623131 0.327844 0.000000 -0.018632 0.009910 -0.035921 0.046374 0.125863 0.016756 0.073841 0.108419 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.292542 -0.000412 0.003775 -0.945072 -0.005257 0.001399 0.006266 -38.648438 142.406250 -346.640625 -0.008573 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315015 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623458 0.327878 0.000000 -0.018810 0.010077 -0.035921 0.046379 0.125875 0.016411 0.074186 0.108408 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.297546 0.002029 0.005973 -0.940677 -0.005257 0.000335 0.005202 -38.648438 142.406250 -341.859375 -0.008574 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316181 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623510 0.327775 0.000000 -0.018645 0.010064 -0.035605 0.046380 0.125406 0.016906 0.074323 0.108245 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.302551 0.001541 0.003287 -0.945072 -0.005257 0.002463 0.006266 -38.648438 142.406250 -341.859375 -0.008572 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317324 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624227 0.327546 0.000000 -0.018994 0.010048 -0.035921 0.046392 0.126087 0.016257 0.074341 0.108196 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.307556 -0.000412 0.005484 -0.944339 -0.004193 0.002463 0.006266 -38.648438 142.406250 -341.859375 -0.008563 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318444 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624925 0.326888 0.000000 -0.018991 0.009861 -0.035921 0.046405 0.126271 0.016446 0.074152 0.108011 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.312561 0.002273 0.004264 -0.943119 -0.004193 0.001399 0.007330 -34.101562 140.109375 -346.640625 -0.008551 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319541 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625262 0.326155 0.000000 -0.018822 0.009848 -0.036237 0.046411 0.126431 0.016313 0.073652 0.108483 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.317566 0.000809 0.004996 -0.941654 -0.004193 0.000335 0.007330 -34.101562 140.109375 -346.640625 -0.008539 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320617 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625262 0.325077 0.000000 -0.018659 0.009823 -0.036237 0.046413 0.126284 0.016490 0.073455 0.108611 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.322571 0.002273 0.005240 -0.947513 -0.003128 0.000335 0.006266 -39.785156 138.960938 -340.664062 -0.008520 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321671 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625271 0.323975 0.000000 -0.018673 0.009637 -0.035921 0.046414 0.126167 0.016979 0.073599 0.108095 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.327576 0.002273 0.006217 -0.943119 -0.004193 0.001399 0.006266 -39.785156 138.960938 -340.664062 -0.008506 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322704 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625631 0.323239 0.000000 -0.018855 0.009796 -0.035921 0.046421 0.126190 0.016639 0.073939 0.108072 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.332581 0.003006 0.008414 -0.943607 -0.005257 0.002463 0.007330 -37.511719 141.257812 -343.054688 -0.008499 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323716 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626366 0.322933 0.000000 -0.019031 0.009949 -0.036237 0.046435 0.126529 0.015993 0.073953 0.108366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.337585 0.002029 0.007437 -0.944828 -0.005257 0.001399 0.007330 -37.511719 141.257812 -343.054688 -0.008495 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324708 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626859 0.322826 0.000000 -0.018866 0.009934 -0.036237 0.046445 0.126380 0.016173 0.073773 0.108515 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.342590 -0.000168 0.005729 -0.941654 -0.005257 0.002463 0.005202 -42.058594 141.257812 -343.054688 -0.008496 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325680 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627347 0.323241 0.000000 -0.019038 0.009935 -0.035605 0.046462 0.125928 0.016641 0.074588 0.107722 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.347595 0.001541 0.004996 -0.942386 -0.005257 0.000335 0.007330 -42.058594 141.257812 -343.054688 -0.008499 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326633 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627537 0.323505 0.000000 -0.018707 0.009933 -0.036237 0.046468 0.126231 0.016342 0.073624 0.108683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.352600 0.002762 0.001822 -0.945072 -0.004193 0.000335 0.006266 -42.058594 143.554688 -345.445312 -0.008497 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327567 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627706 0.323468 0.000000 -0.018728 0.009764 -0.035921 0.046473 0.126105 0.016807 0.073791 0.108177 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.357605 0.001541 0.003287 -0.947757 -0.005257 0.001399 0.006266 -42.058594 143.554688 -345.445312 -0.008498 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328483 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628197 0.323613 0.000000 -0.018916 0.009936 -0.035921 0.046484 0.126121 0.016447 0.074151 0.108161 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.362610 -0.000168 0.004264 -0.947513 -0.005257 0.000335 0.007330 -43.195312 142.406250 -346.640625 -0.008496 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329380 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628711 0.323236 0.000000 -0.018768 0.009916 -0.036237 0.046489 0.126299 0.016288 0.073657 0.108595 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.367615 0.001297 0.006705 -0.944828 -0.004193 0.001399 0.006266 -43.195312 142.406250 -346.640625 -0.008485 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330259 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629112 0.322678 0.000000 -0.018952 0.009733 -0.035921 0.046499 0.126351 0.016604 0.073974 0.107911 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.372620 0.002273 0.008902 -0.945560 -0.005257 0.001399 0.006266 -42.058594 136.664062 -343.054688 -0.008480 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331122 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629437 0.322429 0.000000 -0.018958 0.009894 -0.035921 0.046507 0.126195 0.016438 0.074140 0.108067 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.377625 0.000564 0.006705 -0.945804 -0.006321 0.001399 0.006266 -42.058594 136.664062 -343.054688 -0.008482 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331967 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629717 0.322620 0.000000 -0.018962 0.010051 -0.035921 0.046515 0.126042 0.016275 0.074302 0.108220 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.382629 -0.000168 0.007193 -0.942875 -0.005257 0.001399 0.006266 -44.332031 141.257812 -347.835938 -0.008481 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332796 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629573 0.322965 0.000000 -0.018954 0.009880 -0.035906 0.046522 0.126200 0.016479 0.074149 0.108052 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.387634 0.003250 0.008170 -0.946293 -0.005257 0.001399 0.005202 -44.332031 141.257812 -347.835938 -0.008484 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.333609 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629724 0.323213 0.000000 -0.018956 0.009884 -0.035590 0.046527 0.125882 0.016791 0.074470 0.107738 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.392639 0.002518 0.007682 -0.942630 -0.004193 0.000335 0.006266 -42.058594 138.960938 -347.835938 -0.008486 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.333401 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629576 0.323362 0.000000 -0.018789 0.009725 -0.035906 0.046527 0.126190 0.016800 0.073828 0.108062 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.397644 0.001297 0.006949 -0.938236 -0.005257 0.000335 0.005202 -42.058594 138.960938 -347.835938 -0.008497 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.333197 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629504 0.324030 0.000000 -0.018800 0.009917 -0.035590 0.046529 0.125693 0.016913 0.074347 0.107927 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.402649 0.001053 0.004996 -0.943851 -0.006321 0.001399 0.005202 -39.785156 143.554688 -340.664062 -0.008515 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332998 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629803 0.325112 0.000000 -0.018980 0.010104 -0.035590 0.046536 0.125686 0.016546 0.074714 0.107934 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.407654 0.001297 0.006949 -0.945316 -0.005257 0.000335 0.006266 -39.785156 143.554688 -340.664062 -0.008529 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332803 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630161 0.325573 0.000000 -0.018826 0.009939 -0.035921 0.046538 0.126018 0.016524 0.074054 0.108244 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.412659 0.000076 0.005729 -0.945072 -0.004193 0.000335 0.006266 -39.785156 143.554688 -340.664062 -0.008537 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332613 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630148 0.325977 0.000000 -0.018836 0.009790 -0.035921 0.046540 0.126177 0.016663 0.073915 0.108085 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.417664 -0.000412 0.004752 -0.945560 -0.004193 0.000335 0.007330 -40.921875 144.703125 -344.250000 -0.008544 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332426 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630075 0.326305 0.000000 -0.018843 0.009814 -0.036237 0.046541 0.126477 0.016316 0.073630 0.108417 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.422668 0.000809 0.005484 -0.947513 -0.005257 0.000335 0.006266 -40.921875 144.703125 -344.250000 -0.008555 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332243 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629898 0.326813 0.000000 -0.018846 0.010001 -0.035921 0.046540 0.125977 0.016442 0.074136 0.108285 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.427673 0.002029 0.004508 -0.945072 -0.004193 0.001399 0.005202 -38.648438 142.406250 -349.031250 -0.008557 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.332064 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629956 0.327133 0.000000 -0.019015 0.009846 -0.035605 0.046543 0.125994 0.016754 0.074476 0.107656 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.432678 -0.000412 0.006705 -0.941654 -0.006321 0.001399 0.006266 -38.648438 142.406250 -349.031250 -0.008568 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331888 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629966 0.327630 0.000000 -0.019006 0.010191 -0.035921 0.046544 0.125956 0.016101 0.074496 0.108326 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.437683 0.001053 0.008902 -0.938724 -0.003128 0.000335 0.006266 -40.921875 140.109375 -339.468750 -0.008561 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331717 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629618 0.327105 0.000000 -0.018828 0.009676 -0.035921 0.046540 0.126294 0.016794 0.073803 0.107989 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.442688 -0.000412 0.006217 -0.943119 -0.005257 0.001399 0.006266 -40.921875 140.109375 -339.468750 -0.008566 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331549 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629545 0.327283 0.000000 -0.018994 0.010028 -0.035921 0.046539 0.126107 0.016276 0.074321 0.108175 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.447693 0.000076 0.005729 -0.942875 -0.005257 0.001399 0.006266 -39.785156 141.257812 -340.664062 -0.008571 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331384 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629408 0.327520 0.000000 -0.018982 0.010029 -0.035921 0.046538 0.126094 0.016287 0.074310 0.108188 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.452698 0.002029 0.007437 -0.945560 -0.004193 0.001399 0.007330 -39.785156 141.257812 -340.664062 -0.008573 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331223 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629229 0.327184 0.000000 -0.018970 0.009854 -0.036237 0.046536 0.126563 0.016149 0.073797 0.108331 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.457703 0.000564 0.008170 -0.943851 -0.004193 0.000335 0.007330 -45.468750 140.109375 -339.468750 -0.008575 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.331065 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628748 0.327232 0.000000 -0.018790 0.009866 -0.036237 0.046528 0.126371 0.016317 0.073628 0.108523 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.462708 0.000076 0.004264 -0.940189 -0.005257 0.000335 0.007330 -45.468750 140.109375 -339.468750 -0.008584 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330911 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628307 0.327677 0.000000 -0.018786 0.010048 -0.036237 0.046521 0.126186 0.016138 0.073807 0.108709 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.467712 0.000809 0.004752 -0.939701 -0.005257 0.000335 0.006266 -44.332031 138.960938 -347.835938 -0.008593 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330759 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627887 0.328098 0.000000 -0.018783 0.010053 -0.035921 0.046513 0.125860 0.016453 0.074125 0.108402 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.472717 0.000809 0.005973 -0.942875 -0.005257 0.000335 0.007330 -44.332031 138.960938 -347.835938 -0.008601 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330610 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627497 0.328420 0.000000 -0.018779 0.010057 -0.036237 0.046506 0.126169 0.016137 0.073808 0.108725 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.477722 0.000809 0.008414 -0.946048 -0.005257 0.000335 0.006266 -46.605469 143.554688 -335.882812 -0.008607 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330464 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627138 0.328677 0.000000 -0.018775 0.010059 -0.035921 0.046499 0.125847 0.016455 0.074122 0.108416 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.482727 0.003250 0.007437 -0.947757 -0.005257 0.001399 0.006266 -46.605469 143.554688 -335.882812 -0.008614 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330320 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627160 0.328954 0.000000 -0.018941 0.010062 -0.035921 0.046498 0.126010 0.016286 0.074292 0.108253 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.487732 -0.000900 0.004508 -0.945560 -0.004193 -0.000729 0.005202 -40.921875 135.515625 -346.640625 -0.008616 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.330180 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626631 0.328962 0.000000 -0.018596 0.009899 -0.035605 0.046488 0.125512 0.017111 0.074099 0.108118 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.492737 0.001541 0.006217 -0.944095 -0.005257 0.001399 0.006266 -40.921875 135.515625 -346.640625 -0.008624 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329640 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626804 0.329281 0.000000 -0.018942 0.010079 -0.035921 0.046490 0.125994 0.016268 0.074310 0.108269 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.497742 0.001541 0.004508 -0.945316 -0.004193 0.001399 0.006266 -38.648438 142.406250 -346.640625 -0.008625 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.329112 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626996 0.329223 0.000000 -0.018936 0.009913 -0.035921 0.046492 0.126154 0.016440 0.074138 0.108108 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.502747 0.000320 0.006705 -0.944584 -0.004193 0.000335 0.006266 -38.648438 142.406250 -346.640625 -0.008625 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328594 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626899 0.329099 0.000000 -0.018763 0.009920 -0.035921 0.046489 0.125975 0.016605 0.073972 0.108288 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.507751 0.000809 0.006705 -0.944828 -0.003128 0.002463 0.004137 -38.648438 140.109375 -346.640625 -0.008619 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.328087 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627433 0.328629 0.000000 -0.019105 0.009756 -0.035289 0.046497 0.125848 0.017060 0.074782 0.107150 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.512756 0.001297 0.007193 -0.944095 -0.004193 0.000335 0.005202 -38.648438 140.109375 -346.640625 -0.008618 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327590 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627311 0.328507 0.000000 -0.018757 0.009935 -0.035605 0.046495 0.125637 0.016912 0.074297 0.107993 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.517761 -0.001633 0.007682 -0.944584 -0.003128 0.000335 0.005202 -38.648438 140.109375 -346.640625 -0.008613 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.327104 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626805 0.328442 0.000000 -0.018751 0.009779 -0.035605 0.046492 0.125797 0.017085 0.074145 0.107854 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.522766 0.002762 0.006705 -0.940189 -0.005257 0.001399 0.006266 -39.785156 136.664062 -340.664062 -0.008620 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326627 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626923 0.328818 0.000000 -0.018921 0.010130 -0.035921 0.046493 0.125933 0.016248 0.074350 0.108350 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.527771 -0.000168 0.005484 -0.938724 -0.004193 -0.000729 0.005202 -39.785156 136.664062 -340.664062 -0.008623 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.326161 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626375 0.328939 0.000000 -0.018577 0.009961 -0.035605 0.046484 0.125441 0.017077 0.074153 0.108209 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.532776 0.000320 0.006461 -0.942875 -0.005257 0.000335 0.004137 -42.058594 145.851562 -347.835938 -0.008632 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325704 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626138 0.329396 0.000000 -0.018753 0.010138 -0.035289 0.046479 0.125124 0.017040 0.074822 0.107894 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.537781 0.000809 0.006461 -0.944339 -0.004193 0.000335 0.005202 -42.058594 145.851562 -347.835938 -0.008635 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.325256 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626237 0.329522 0.000000 -0.018761 0.009971 -0.035605 0.046473 0.125615 0.016884 0.074346 0.108035 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.542786 -0.001389 0.006705 -0.939457 -0.004193 0.000335 0.004137 -43.195312 137.812500 -341.859375 -0.008639 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324817 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625929 0.329650 0.000000 -0.018756 0.009979 -0.035289 0.046467 0.125286 0.017196 0.074666 0.107733 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.547791 0.001785 0.003775 -0.938236 -0.005257 0.001399 0.004137 -43.195312 137.812500 -341.859375 -0.008647 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.324386 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625879 0.330059 0.000000 -0.018918 0.010155 -0.035289 0.046465 0.125271 0.016858 0.075004 0.107747 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.552795 0.003494 0.005240 -0.942875 -0.005257 0.002463 0.006266 -39.785156 145.851562 -345.445312 -0.008653 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323964 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626145 0.330350 0.000000 -0.019073 0.010153 -0.035921 0.046468 0.126062 0.016073 0.074525 0.108220 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.557800 0.001785 0.006705 -0.946537 -0.004193 0.001399 0.006266 -39.785156 145.851562 -345.445312 -0.008653 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323550 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626189 0.330203 0.000000 -0.018889 0.009979 -0.035921 0.046468 0.126052 0.016431 0.074167 0.108230 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.562805 -0.000900 0.004752 -0.944828 -0.005257 0.001399 0.006266 -38.648438 147.000000 -346.640625 -0.008656 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.323144 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626339 0.329992 0.000000 -0.018886 0.010138 -0.035921 0.046469 0.125879 0.016264 0.074313 0.108383 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.567810 -0.001389 0.004020 -0.950199 -0.004193 0.000335 0.007330 -38.648438 147.000000 -346.640625 -0.008651 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322745 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626180 0.329665 0.000000 -0.018716 0.009959 -0.036237 0.046466 0.126204 0.016298 0.073647 0.108691 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.572815 0.000320 0.006217 -0.941654 -0.004193 0.002463 0.006266 -50.015625 144.703125 -341.859375 -0.008645 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.322355 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626568 0.329241 0.000000 -0.019056 0.009953 -0.035921 0.046472 0.126234 0.016280 0.074298 0.108029 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.577820 -0.001145 0.007682 -0.948978 -0.004193 0.001399 0.006266 -50.015625 144.703125 -341.859375 -0.008638 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321972 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626506 0.328786 0.000000 -0.018872 0.009946 -0.035921 0.046470 0.126058 0.016471 0.074107 0.108204 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.582825 -0.001877 0.004996 -0.946293 -0.004193 0.000335 0.005202 -45.468750 144.703125 -341.859375 -0.008631 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321598 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625983 0.328678 0.000000 -0.018693 0.009948 -0.035605 0.046461 0.125570 0.016975 0.074255 0.108080 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.587830 0.000564 0.003775 -0.947757 -0.003128 0.000335 0.006266 -45.468750 144.703125 -341.859375 -0.008620 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.321231 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625325 0.327984 0.000000 -0.018685 0.009772 -0.035921 0.046449 0.126054 0.016842 0.073755 0.108228 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.592834 0.002029 0.003775 -0.947025 -0.004193 0.001399 0.006266 -44.332031 143.554688 -347.835938 -0.008612 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320872 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624920 0.327566 0.000000 -0.018842 0.009938 -0.035921 0.046441 0.126045 0.016518 0.074079 0.108237 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.597839 0.002762 0.005240 -0.948734 -0.005257 0.000335 0.006266 -44.332031 143.554688 -347.835938 -0.008607 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320722 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624259 0.327366 0.000000 -0.018657 0.010093 -0.035921 0.046428 0.125704 0.016549 0.074049 0.108578 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.602844 -0.000412 0.004264 -0.938724 -0.005257 0.000335 0.006266 -43.195312 137.812500 -344.250000 -0.008601 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320576 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623745 0.326768 0.000000 -0.018651 0.010062 -0.035921 0.046418 0.125720 0.016576 0.074001 0.108542 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.607849 0.004715 0.007437 -0.942386 -0.004193 0.000335 0.006266 -43.195312 137.812500 -344.250000 -0.008589 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320433 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623402 0.326117 0.000000 -0.018649 0.009871 -0.035921 0.046410 0.125910 0.016769 0.073809 0.108353 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.612854 0.000564 0.004264 -0.942630 -0.005257 -0.000729 0.007330 -42.058594 145.851562 -345.445312 -0.008582 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320294 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622959 0.325816 0.000000 -0.018484 0.010026 -0.036237 0.046400 0.125905 0.016463 0.073482 0.108989 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.617859 0.001053 0.002311 -0.942142 -0.006321 0.002463 0.006266 -42.058594 145.851562 -345.445312 -0.008580 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320157 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623639 0.325821 0.000000 -0.019005 0.010174 -0.035921 0.046409 0.125962 0.016110 0.074468 0.108300 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.622864 0.002518 0.004264 -0.946781 -0.005257 0.002463 0.005202 -42.058594 145.851562 -345.445312 -0.008572 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.320024 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624397 0.325412 0.000000 -0.019001 0.009977 -0.035605 0.046420 0.125839 0.016627 0.074583 0.107791 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.627869 0.001785 0.005484 -0.946781 -0.004193 0.001399 0.006266 -38.648438 142.406250 -344.250000 -0.008556 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319894 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624555 0.324910 0.000000 -0.018823 0.009796 -0.035906 0.046427 0.126153 0.016695 0.073932 0.108099 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.632874 0.000320 0.004508 -0.944584 -0.005257 0.001399 0.004137 -38.648438 142.406250 -344.250000 -0.008545 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319766 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625122 0.324409 0.000000 -0.018835 0.009950 -0.035274 0.046436 0.125379 0.017162 0.074730 0.107609 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.637878 0.001541 0.005240 -0.939213 -0.004193 0.000335 0.006266 -37.511719 145.851562 -340.664062 -0.008529 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319641 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625378 0.323601 0.000000 -0.018678 0.009759 -0.035906 0.046441 0.126045 0.016877 0.073751 0.108207 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.642883 0.002518 0.005729 -0.940189 -0.004193 0.002463 0.005202 -37.511719 145.851562 -340.664062 -0.008513 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319519 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626253 0.322853 0.000000 -0.019035 0.009745 -0.035590 0.046456 0.126099 0.016850 0.074410 0.107521 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.647888 0.002273 0.005729 -0.941898 -0.005257 0.001399 0.005202 -45.468750 147.000000 -341.859375 -0.008504 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319399 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627167 0.322215 0.000000 -0.018882 0.009893 -0.035605 0.046466 0.125803 0.016830 0.074380 0.107827 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.652893 -0.000656 0.006705 -0.946537 -0.005257 0.000335 0.005202 -45.468750 147.000000 -341.859375 -0.008496 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319281 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627402 0.321989 0.000000 -0.018726 0.009878 -0.035605 0.046471 0.125663 0.017000 0.074209 0.107967 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.657898 -0.000656 0.004996 -0.947269 -0.005257 0.000335 0.005202 -37.511719 143.554688 -347.835938 -0.008491 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319166 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627560 0.321889 0.000000 -0.018744 0.009868 -0.035605 0.046475 0.125691 0.016993 0.074217 0.107940 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.662903 -0.000900 0.006217 -0.948490 -0.005257 0.001399 0.006266 -37.511719 143.554688 -347.835938 -0.008488 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319053 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627868 0.321895 0.000000 -0.018924 0.009862 -0.035921 0.046482 0.126193 0.016503 0.074074 0.108069 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.667908 -0.000656 0.005484 -0.942630 -0.004193 0.000335 0.005202 -35.238281 145.851562 -347.835938 -0.008481 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318942 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627641 0.321673 0.000000 -0.018752 0.009690 -0.035605 0.046480 0.125877 0.017163 0.074047 0.107753 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.672913 0.002762 0.006705 -0.941654 -0.005257 0.002463 0.005202 -35.238281 145.851562 -347.835938 -0.008481 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318833 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627516 0.322153 0.000000 -0.019078 0.009874 -0.035605 0.046485 0.126029 0.016663 0.074567 0.107622 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.677917 0.002029 0.005973 -0.943851 -0.004193 0.001399 0.005202 -43.195312 135.515625 -339.468750 -0.008477 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318727 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627369 0.322093 0.000000 -0.018892 0.009707 -0.035605 0.046484 0.126011 0.017016 0.074214 0.107639 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.682922 -0.000168 0.006461 -0.944584 -0.004193 0.001399 0.005202 -43.195312 135.515625 -339.468750 -0.008475 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318623 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627246 0.322113 0.000000 -0.018885 0.009717 -0.035605 0.046483 0.125993 0.017013 0.074217 0.107657 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.687927 -0.000168 0.004996 -0.941898 -0.005257 0.002463 0.006266 -37.511719 143.554688 -331.101562 -0.008479 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318521 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627444 0.322497 0.000000 -0.019048 0.009897 -0.035921 0.046487 0.126292 0.016354 0.074243 0.107990 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.692932 0.000809 0.006461 -0.945316 -0.004193 0.000335 0.006266 -37.511719 143.554688 -331.101562 -0.008478 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318421 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627341 0.322269 0.000000 -0.018707 0.009723 -0.035921 0.046480 0.126116 0.016859 0.073719 0.108147 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.697937 0.000320 0.004752 -0.947757 -0.005257 0.003528 0.006266 -37.511719 143.554688 -340.664062 -0.008483 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318324 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627814 0.322644 0.000000 -0.019215 0.009902 -0.035921 0.046489 0.126444 0.016172 0.074406 0.107818 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.702942 0.000320 0.003287 -0.942386 -0.005257 0.001399 0.007330 -37.511719 143.554688 -340.664062 -0.008487 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318228 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627621 0.322932 0.000000 -0.018857 0.009903 -0.036237 0.046487 0.126401 0.016213 0.073733 0.108493 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.707947 -0.001389 0.002555 -0.940189 -0.004193 0.001399 0.006266 -39.785156 138.960938 -350.226562 -0.008482 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318135 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627394 0.322730 0.000000 -0.018852 0.009730 -0.035921 0.046483 0.126253 0.016707 0.073871 0.108010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.712952 -0.000168 0.006217 -0.945072 -0.004193 0.002463 0.006266 -39.785156 138.960938 -350.226562 -0.008475 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318043 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627050 0.322635 0.000000 -0.019003 0.009737 -0.035906 0.046484 0.126392 0.016575 0.074053 0.107860 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.717957 -0.001633 0.006461 -0.941410 -0.005257 0.000335 0.007330 -42.058594 141.257812 -350.226562 -0.008470 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317953 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626339 0.322443 0.000000 -0.018648 0.009899 -0.036222 0.046473 0.126191 0.016451 0.073545 0.108693 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.722961 0.001541 0.005484 -0.944095 -0.004193 0.000335 0.007330 -42.058594 141.257812 -350.226562 -0.008460 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317865 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625570 0.321918 0.000000 -0.018643 0.009715 -0.036222 0.046459 0.126370 0.016639 0.073356 0.108514 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.727966 0.003250 0.006705 -0.945316 -0.004193 0.001399 0.006266 -42.058594 141.257812 -350.226562 -0.008450 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317779 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625151 0.321449 0.000000 -0.018806 0.009709 -0.035906 0.046452 0.126223 0.016798 0.073830 0.108029 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.732971 0.002518 0.007682 -0.943851 -0.004193 0.000335 0.006266 -46.605469 143.554688 -347.835938 -0.008442 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317694 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624575 0.321098 0.000000 -0.018628 0.009706 -0.035906 0.046441 0.126048 0.016980 0.073648 0.108204 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.737976 -0.000168 0.004752 -0.939701 -0.005257 0.000335 0.007330 -46.605469 143.554688 -347.835938 -0.008442 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317611 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624572 0.320903 0.000000 -0.018642 0.009866 -0.036237 0.046433 0.126224 0.016464 0.073481 0.108671 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.742981 0.001053 0.005729 -0.942386 -0.005257 0.001399 0.006266 -42.058594 141.257812 -345.445312 -0.008443 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317530 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624664 0.321093 0.000000 -0.018817 0.009862 -0.035921 0.046433 0.126087 0.016609 0.073968 0.108176 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.747986 -0.000900 0.005729 -0.943119 -0.004193 0.002463 0.005202 -42.058594 141.257812 -345.445312 -0.008440 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317450 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625118 0.321011 0.000000 -0.018986 0.009691 -0.035605 0.046439 0.126110 0.016927 0.074283 0.107520 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.752991 0.001541 0.005240 -0.945072 -0.005257 0.001399 0.007330 -43.195312 144.703125 -351.421875 -0.008443 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317372 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625247 0.321268 0.000000 -0.018812 0.009867 -0.036237 0.046440 0.126392 0.016295 0.073651 0.108502 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.757996 0.000320 0.006705 -0.945804 -0.005257 0.001399 0.006266 -43.195312 144.703125 -351.421875 -0.008446 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317294 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625002 0.321820 0.000000 -0.018803 0.009875 -0.035921 0.046441 0.126069 0.016622 0.073976 0.108213 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.763000 0.000320 0.006461 -0.947269 -0.004193 0.001399 0.006266 -40.921875 147.000000 -337.078125 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317219 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625100 0.321776 0.000000 -0.018804 0.009706 -0.035921 0.046442 0.126239 0.016788 0.073809 0.108043 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.768005 0.000809 0.006217 -0.943363 -0.006321 0.002463 0.005202 -40.921875 147.000000 -337.078125 -0.008454 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317145 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625475 0.322404 0.000000 -0.018974 0.010053 -0.035605 0.046448 0.125746 0.016588 0.074642 0.107904 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.773010 0.000564 0.005240 -0.943363 -0.003128 0.001399 0.005202 -38.648438 140.109375 -344.250000 -0.008449 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317072 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625496 0.322096 0.000000 -0.018799 0.009542 -0.035605 0.046448 0.126082 0.017274 0.073956 0.107568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.778015 0.002029 0.004508 -0.941410 -0.005257 0.001399 0.006266 -38.648438 140.109375 -344.250000 -0.008454 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317001 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625519 0.322416 0.000000 -0.018800 0.009897 -0.035921 0.046449 0.126045 0.016602 0.073996 0.108237 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.783020 0.001541 0.006705 -0.945560 -0.004193 0.001399 0.005202 -36.375000 140.109375 -344.250000 -0.008453 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316932 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625942 0.322061 0.000000 -0.018814 0.009718 -0.035605 0.046450 0.125911 0.017073 0.074137 0.107719 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.788025 0.000564 0.006217 -0.938480 -0.005257 0.000335 0.005202 -36.375000 140.109375 -344.250000 -0.008456 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316864 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625747 0.322297 0.000000 -0.018649 0.009893 -0.035605 0.046446 0.125571 0.017062 0.074148 0.108059 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.793030 0.002273 0.005729 -0.943363 -0.004193 0.001399 0.004137 -45.468750 149.296875 -349.031250 -0.008455 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316797 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625929 0.322212 0.000000 -0.018830 0.009723 -0.035289 0.046449 0.125606 0.017367 0.074474 0.107392 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.798035 0.001785 0.008414 -0.943363 -0.004193 0.001399 0.005202 -45.468750 149.296875 -349.031250 -0.008454 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316932 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626176 0.322166 0.000000 -0.018837 0.009730 -0.035605 0.046453 0.125922 0.017038 0.074171 0.107709 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.803040 0.001541 0.006217 -0.941410 -0.005257 0.000335 0.006266 -43.195312 142.406250 -344.250000 -0.008460 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317065 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626187 0.322818 0.000000 -0.018676 0.009916 -0.035921 0.046454 0.125901 0.016706 0.073891 0.108382 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.808044 0.001297 0.005484 -0.942630 -0.005257 0.002463 0.006266 -43.195312 142.406250 -344.250000 -0.008467 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317195 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626891 0.323231 0.000000 -0.019031 0.009920 -0.035921 0.046466 0.126252 0.016348 0.074250 0.108030 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.813049 0.000076 0.005973 -0.942386 -0.006321 0.002463 0.007330 -40.921875 140.109375 -349.031250 -0.008480 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317322 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627588 0.323962 0.000000 -0.019034 0.010094 -0.036237 0.046478 0.126397 0.015855 0.074110 0.108517 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.818054 -0.001145 0.006949 -0.942142 -0.004193 0.001399 0.005202 -40.921875 140.109375 -349.031250 -0.008482 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317446 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627885 0.324043 0.000000 -0.018867 0.009755 -0.035605 0.046485 0.125938 0.016993 0.074237 0.107713 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.823059 0.001541 0.006705 -0.945560 -0.004193 0.001399 0.006266 -42.058594 143.554688 -340.664062 -0.008485 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317567 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627707 0.324149 0.000000 -0.018863 0.009769 -0.035921 0.046489 0.126235 0.016667 0.073931 0.108047 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.828064 0.002518 0.007437 -0.939945 -0.004193 0.001399 0.006266 -42.058594 143.554688 -340.664062 -0.008489 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317686 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627817 0.324302 0.000000 -0.018868 0.009783 -0.035921 0.046492 0.126226 0.016648 0.073950 0.108057 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.833069 0.003250 0.006461 -0.939213 -0.004193 0.001399 0.006266 -42.058594 143.554688 -340.664062 -0.008493 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317802 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627953 0.324513 0.000000 -0.018873 0.009798 -0.035921 0.046496 0.126216 0.016628 0.073970 0.108067 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.838074 0.001053 0.006461 -0.939945 -0.005257 0.002463 0.007330 -37.511719 136.664062 -345.445312 -0.008504 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317915 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628490 0.325079 0.000000 -0.019049 0.009982 -0.036237 0.046507 0.126524 0.015951 0.074014 0.108390 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.843079 -0.000168 0.005240 -0.943851 -0.004193 0.000335 0.006266 -37.511719 136.664062 -345.445312 -0.008510 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318026 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628438 0.325318 0.000000 -0.018714 0.009821 -0.035921 0.046508 0.126034 0.016763 0.073834 0.108248 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.848083 -0.001877 0.004752 -0.944584 -0.004193 0.000335 0.007330 -40.921875 144.703125 -346.640625 -0.008515 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318134 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628717 0.325497 0.000000 -0.018740 0.009834 -0.036237 0.046508 0.126363 0.016408 0.073557 0.108551 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.853088 -0.003830 0.006217 -0.943851 -0.004193 0.001399 0.007330 -40.921875 144.703125 -346.640625 -0.008518 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318240 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628769 0.325575 0.000000 -0.018917 0.009843 -0.036237 0.046510 0.126531 0.016222 0.073743 0.108383 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.858093 -0.000168 0.003043 -0.943363 -0.003128 0.001399 0.005202 -39.785156 136.664062 -340.664062 -0.008513 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318343 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628527 0.325217 0.000000 -0.018909 0.009679 -0.035605 0.046507 0.126055 0.017027 0.074202 0.107596 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.863098 0.002273 0.006461 -0.940921 -0.004193 0.000335 0.006266 -39.785156 136.664062 -340.664062 -0.008511 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318443 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627761 0.325040 0.000000 -0.018725 0.009854 -0.035921 0.046495 0.126012 0.016720 0.073877 0.108270 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.868103 0.001785 0.004996 -0.941898 -0.005257 0.001399 0.006266 -42.058594 143.554688 -338.273438 -0.008513 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318542 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626915 0.325055 0.000000 -0.018873 0.010017 -0.035921 0.046488 0.125998 0.016409 0.074189 0.108285 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.873108 0.002273 0.003531 -0.944339 -0.004193 0.001399 0.006266 -42.058594 143.554688 -338.273438 -0.008507 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318638 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626512 0.324643 0.000000 -0.018858 0.009832 -0.035921 0.046481 0.126168 0.016609 0.073989 0.108115 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.878113 0.003982 0.006705 -0.941654 -0.005257 0.002463 0.006266 -39.785156 145.851562 -345.445312 -0.008504 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318732 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626602 0.324450 0.000000 -0.019018 0.009990 -0.035921 0.046482 0.126170 0.016291 0.074306 0.108113 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.883118 0.003738 0.005484 -0.943363 -0.005257 -0.000729 0.006266 -39.785156 145.851562 -345.445312 -0.008500 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318824 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626014 0.324211 0.000000 -0.018504 0.009971 -0.035921 0.046472 0.125675 0.016824 0.073774 0.108608 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.888123 0.003006 0.005729 -0.942630 -0.005257 0.000335 0.005202 -38.648438 137.812500 -344.250000 -0.008496 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.318914 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626080 0.323979 0.000000 -0.018696 0.009953 -0.035605 0.046472 0.125568 0.016965 0.074264 0.108082 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.893127 0.003006 0.005484 -0.943851 -0.004193 0.000335 0.006266 -38.648438 137.812500 -344.250000 -0.008488 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319002 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626800 0.323467 0.000000 -0.018729 0.009769 -0.035921 0.046477 0.126101 0.016800 0.073797 0.108181 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.898132 -0.000656 0.004508 -0.939457 -0.005257 0.001399 0.005202 -38.648438 140.109375 -346.640625 -0.008484 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.319089 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627653 0.323309 0.000000 -0.018925 0.009931 -0.035605 0.046492 0.125819 0.016759 0.074471 0.107832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.903137 -0.000900 0.005729 -0.938968 -0.005257 0.000335 0.005202 -38.648438 140.109375 -346.640625 -0.008481 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.317967 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628186 0.323158 0.000000 -0.018775 0.009918 -0.035605 0.046501 0.125682 0.016922 0.074307 0.107968 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.908142 -0.001145 0.005240 -0.941654 -0.005257 0.000335 0.005202 -35.238281 143.554688 -343.054688 -0.008478 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.316868 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628564 0.323017 0.000000 -0.018796 0.009906 -0.035605 0.046508 0.125715 0.016913 0.074316 0.107935 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.913147 0.000076 0.005240 -0.946048 -0.004193 0.000335 0.005202 -35.238281 143.554688 -343.054688 -0.008470 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.315790 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628345 0.322578 0.000000 -0.018798 0.009726 -0.035605 0.046512 0.125897 0.017091 0.074139 0.107754 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.918152 0.003250 0.004996 -0.941654 -0.004193 0.000335 0.005202 -40.921875 142.406250 -344.250000 -0.008462 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.314734 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628294 0.322163 0.000000 -0.018804 0.009723 -0.035605 0.046512 0.125906 0.017088 0.074142 0.107744 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.923157 0.002029 0.005973 -0.939945 -0.005257 0.001399 0.005202 -40.921875 142.406250 -344.250000 -0.008459 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.313699 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628483 0.322081 0.000000 -0.018976 0.009888 -0.035605 0.046516 0.125913 0.016751 0.074479 0.107738 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.928162 0.001053 0.009391 -0.942630 -0.005257 0.001399 0.006266 -42.058594 141.257812 -343.054688 -0.008458 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.312684 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628665 0.322066 0.000000 -0.018972 0.009880 -0.035921 0.046520 0.126233 0.016448 0.074150 0.108049 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.933167 0.000320 0.004508 -0.941898 -0.005257 0.002463 0.005202 -42.058594 141.257812 -343.054688 -0.008458 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.311690 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629507 0.322189 0.000000 -0.019148 0.009876 -0.035605 0.046530 0.126097 0.016591 0.074639 0.107553 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.938171 0.002518 0.007682 -0.944095 -0.006321 0.001399 0.005202 -42.058594 141.257812 -343.054688 -0.008467 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.310715 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629647 0.322748 0.000000 -0.018970 0.010046 -0.035605 0.046534 0.125749 0.016599 0.074631 0.107901 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.943176 0.003250 0.005240 -0.940189 -0.005257 0.001399 0.006266 -43.195312 142.406250 -349.031250 -0.008472 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.309759 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629833 0.323070 0.000000 -0.018971 0.009875 -0.035921 0.046538 0.126237 0.016453 0.074145 0.108046 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.948181 0.003982 0.003531 -0.942630 -0.004193 0.001399 0.006266 -43.195312 142.406250 -349.031250 -0.008472 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.308823 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630148 0.323102 0.000000 -0.018976 0.009714 -0.035921 0.046545 0.126404 0.016609 0.073989 0.107879 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.953186 0.001785 0.004264 -0.943119 -0.004193 0.002463 0.006266 -43.195312 137.812500 -344.250000 -0.008471 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307905 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630937 0.323062 0.000000 -0.019156 0.009725 -0.035921 0.046560 0.126572 0.016418 0.074180 0.107710 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.958191 0.001785 0.006949 -0.945316 -0.005257 0.002463 0.006266 -43.195312 137.812500 -344.250000 -0.008474 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.307005 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631471 0.323230 0.000000 -0.019154 0.009901 -0.035906 0.046578 0.126379 0.016260 0.074368 0.107873 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.963196 0.003494 0.002555 -0.945316 -0.004193 0.002463 0.007330 -43.195312 137.812500 -341.859375 -0.008470 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.306123 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632431 0.322976 0.000000 -0.019166 0.009728 -0.036222 0.046597 0.126880 0.016104 0.073892 0.108004 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.968201 -0.000168 0.007926 -0.945316 -0.005257 0.001399 0.007330 -43.195312 137.812500 -341.859375 -0.008469 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.305259 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633104 0.322953 0.000000 -0.019012 0.009897 -0.036222 0.046611 0.126557 0.016088 0.073908 0.108327 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.973206 0.002273 0.005729 -0.944095 -0.004193 0.001399 0.006266 -42.058594 143.554688 -338.273438 -0.008463 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.304413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633749 0.322585 0.000000 -0.019034 0.009721 -0.035906 0.046626 0.126440 0.016559 0.074069 0.107812 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.978210 -0.000168 0.004996 -0.942630 -0.004193 0.001399 0.005202 -42.058594 143.554688 -338.273438 -0.008456 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.303583 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634670 0.322250 0.000000 -0.019064 0.009720 -0.035590 0.046640 0.126154 0.016845 0.074415 0.107466 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.983215 0.000564 0.004020 -0.942875 -0.005257 0.000335 0.006266 -36.375000 142.406250 -341.859375 -0.008455 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.302770 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634790 0.322226 0.000000 -0.018911 0.009888 -0.035906 0.046646 0.126149 0.016515 0.074113 0.108103 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.988220 0.000809 0.005729 -0.948002 -0.005257 0.001399 0.006266 -36.375000 142.406250 -341.859375 -0.008453 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301974 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635082 0.322151 0.000000 -0.019096 0.009878 -0.035906 0.046655 0.126344 0.016340 0.074288 0.107908 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.993225 -0.000656 0.007193 -0.944584 -0.005257 0.000335 0.007330 -43.195312 137.812500 -341.859375 -0.008451 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.301194 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634900 0.322063 0.000000 -0.018931 0.009869 -0.036222 0.046656 0.126504 0.016198 0.073798 0.108380 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+458.998230 0.001297 0.005973 -0.943851 -0.005257 0.001399 0.006266 -43.195312 137.812500 -341.859375 -0.008450 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300430 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634884 0.322029 0.000000 -0.019105 0.009862 -0.035906 0.046659 0.126369 0.016347 0.074281 0.107883 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.003235 0.003494 0.005729 -0.942875 -0.004193 0.001399 0.006266 -38.648438 142.406250 -346.640625 -0.008444 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.300084 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634422 0.321756 0.000000 -0.019089 0.009689 -0.035921 0.046660 0.126542 0.016521 0.074077 0.107741 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.008240 0.004227 0.005973 -0.942875 -0.005257 0.000335 0.005202 -38.648438 142.406250 -346.640625 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299745 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634068 0.321873 0.000000 -0.018917 0.009863 -0.035605 0.046657 0.125880 0.016835 0.074395 0.107771 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.013245 0.000564 0.006461 -0.945804 -0.004193 0.000335 0.004137 -39.785156 145.851562 -347.835938 -0.008442 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633870 0.321730 0.000000 -0.018925 0.009693 -0.035289 0.046656 0.125741 0.017313 0.074549 0.107277 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.018250 -0.000900 0.006217 -0.947025 -0.003128 0.000335 0.004137 -39.785156 145.851562 -347.835938 -0.008435 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.299088 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633767 0.321351 0.000000 -0.018934 0.009532 -0.035289 0.046657 0.125911 0.017465 0.074397 0.107107 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.023254 0.000320 0.004020 -0.944095 -0.005257 0.000335 0.005202 -40.921875 144.703125 -341.859375 -0.008439 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298770 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634004 0.321350 0.000000 -0.018952 0.009876 -0.035605 0.046656 0.125891 0.016777 0.074432 0.107739 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.028259 -0.001877 0.005973 -0.941410 -0.006321 0.001399 0.005202 -40.921875 144.703125 -341.859375 -0.008448 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298459 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634087 0.321920 0.000000 -0.019123 0.010043 -0.035605 0.046659 0.125895 0.016438 0.074771 0.107735 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.033264 0.001541 0.006217 -0.946537 -0.005257 0.000335 0.006266 -39.785156 141.257812 -340.664062 -0.008451 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.298154 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633704 0.322117 0.000000 -0.018945 0.009866 -0.035921 0.046654 0.126211 0.016478 0.074100 0.108052 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.038269 -0.000656 0.004508 -0.943363 -0.004193 0.001399 0.005202 -39.785156 141.257812 -340.664062 -0.008448 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297855 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633516 0.321969 0.000000 -0.019108 0.009697 -0.035605 0.046652 0.126227 0.016800 0.074410 0.107403 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.043274 0.002518 0.004996 -0.946048 -0.004193 0.001399 0.006266 -39.785156 141.257812 -340.664062 -0.008445 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297563 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633255 0.322078 0.000000 -0.019093 0.009710 -0.035921 0.046649 0.126524 0.016495 0.074102 0.107758 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.048279 -0.000656 0.006705 -0.946293 -0.004193 0.001399 0.006266 -40.921875 142.406250 -341.859375 -0.008441 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.297277 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632974 0.321846 0.000000 -0.019078 0.009713 -0.035921 0.046645 0.126507 0.016508 0.074090 0.107776 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.053284 -0.000656 0.004508 -0.942630 -0.004193 0.000335 0.006266 -40.921875 142.406250 -341.859375 -0.008436 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296997 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632358 0.321597 0.000000 -0.018895 0.009714 -0.035921 0.046635 0.126322 0.016691 0.073907 0.107960 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.058289 -0.000656 0.005484 -0.943119 -0.005257 0.000335 0.006266 -39.785156 141.257812 -343.054688 -0.008436 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296723 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631698 0.321641 0.000000 -0.018885 0.009882 -0.035921 0.046623 0.126145 0.016532 0.074066 0.108138 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.063293 -0.001389 0.005973 -0.943851 -0.004193 0.001399 0.006266 -39.785156 141.257812 -343.054688 -0.008431 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296455 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631279 0.321340 0.000000 -0.019041 0.009704 -0.035921 0.046615 0.126478 0.016553 0.074044 0.107804 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.068298 -0.000168 0.005973 -0.943607 -0.003128 0.001399 0.006266 -47.742188 142.406250 -344.250000 -0.008420 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296192 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630761 0.320446 0.000000 -0.019018 0.009525 -0.035921 0.046606 0.126625 0.016745 0.073832 0.107638 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.073303 0.000320 0.004264 -0.943119 -0.004193 0.002463 0.006266 -47.742188 142.406250 -344.250000 -0.008414 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295935 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630489 0.320199 0.000000 -0.019163 0.009699 -0.035921 0.046600 0.126595 0.016426 0.074151 0.107667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.078308 0.001541 0.004508 -0.943607 -0.004193 0.000335 0.006266 -50.015625 135.515625 -346.640625 -0.008408 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295683 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629585 0.319928 0.000000 -0.018796 0.009695 -0.035921 0.046583 0.126232 0.016798 0.073780 0.108030 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.083313 0.002762 0.006949 -0.944339 -0.004193 -0.000729 0.006266 -50.015625 135.515625 -346.640625 -0.008402 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295436 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628494 0.319628 0.000000 -0.018616 0.009689 -0.035921 0.046562 0.126058 0.016983 0.073594 0.108205 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.088318 0.001541 0.005973 -0.942142 -0.005257 -0.000729 0.007330 -32.964844 143.554688 -345.445312 -0.008401 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295195 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627626 0.319662 0.000000 -0.018616 0.009853 -0.036237 0.046545 0.126210 0.016504 0.073442 0.108684 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.093323 0.002029 0.005729 -0.945804 -0.004193 -0.000729 0.006266 -32.964844 143.554688 -345.445312 -0.008395 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294958 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626994 0.319423 0.000000 -0.018620 0.009674 -0.035921 0.046531 0.126078 0.016995 0.073582 0.108185 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.098328 0.000809 0.005729 -0.943363 -0.004193 0.000335 0.006266 -35.238281 141.257812 -343.054688 -0.008391 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294726 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626882 0.319240 0.000000 -0.018796 0.009672 -0.035921 0.046525 0.126255 0.016820 0.073757 0.108007 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.103333 -0.001145 0.004996 -0.942386 -0.004193 0.000335 0.007330 -35.238281 141.257812 -343.054688 -0.008387 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626880 0.319092 0.000000 -0.018799 0.009672 -0.036237 0.046521 0.126574 0.016503 0.073443 0.108320 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.108337 0.004715 0.005973 -0.944095 -0.005257 0.001399 0.006266 -40.921875 140.109375 -344.250000 -0.008388 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293480 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627240 0.319270 0.000000 -0.018971 0.009840 -0.035921 0.046524 0.126263 0.016478 0.074100 0.108000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.113342 0.002273 0.004996 -0.944584 -0.005257 0.001399 0.006266 -40.921875 140.109375 -344.250000 -0.008389 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292876 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627330 0.319734 0.000000 -0.018960 0.009841 -0.035921 0.046529 0.126261 0.016497 0.074100 0.108022 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.118347 0.000809 0.006949 -0.943851 -0.004193 0.001399 0.006266 -44.332031 138.960938 -340.664062 -0.008386 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292284 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627890 0.319581 0.000000 -0.018965 0.009666 -0.035921 0.046536 0.126441 0.016667 0.073930 0.107842 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.123352 0.003006 0.008170 -0.943363 -0.005257 0.001399 0.007330 -44.332031 138.960938 -340.664062 -0.008388 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291704 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628517 0.319805 0.000000 -0.018974 0.009838 -0.036237 0.046546 0.126593 0.016171 0.073795 0.108321 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.128357 0.000320 0.009635 -0.945560 -0.005257 0.001399 0.006266 -40.921875 140.109375 -344.250000 -0.008394 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291135 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.629176 0.320180 0.000000 -0.018984 0.009839 -0.035921 0.046556 0.126287 0.016476 0.074122 0.107996 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.133362 0.002762 0.009879 -0.945316 -0.005257 0.001399 0.006266 -40.921875 140.109375 -344.250000 -0.008404 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290578 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630195 0.320803 0.000000 -0.019007 0.009848 -0.035906 0.046567 0.126284 0.016459 0.074169 0.107968 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.138367 -0.000900 0.006461 -0.944584 -0.004193 0.003528 0.006266 -40.921875 144.703125 -337.078125 -0.008414 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290033 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631432 0.321381 0.000000 -0.019356 0.009698 -0.035906 0.046588 0.126784 0.016260 0.074368 0.107468 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.143372 0.002518 0.005240 -0.941410 -0.004193 0.002463 0.005202 -40.921875 144.703125 -337.078125 -0.008427 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289498 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632235 0.322125 0.000000 -0.019184 0.009729 -0.035590 0.046603 0.126265 0.016717 0.074543 0.107355 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.148376 0.000320 0.006949 -0.942630 -0.004193 0.001399 0.005202 -40.921875 144.703125 -337.078125 -0.008441 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288975 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632623 0.322893 0.000000 -0.019019 0.009759 -0.035590 0.046611 0.126069 0.016852 0.074408 0.107550 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.153381 0.001297 0.006461 -0.942386 -0.004193 0.001399 0.005202 -38.648438 137.812500 -344.250000 -0.008455 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288462 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632928 0.323616 0.000000 -0.019028 0.009787 -0.035590 0.046618 0.126051 0.016815 0.074445 0.107569 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.158386 0.002029 0.004996 -0.943363 -0.006321 0.001399 0.006266 -38.648438 137.812500 -344.250000 -0.008478 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287959 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633169 0.324866 0.000000 -0.019036 0.010150 -0.035906 0.046625 0.126012 0.016129 0.074499 0.108240 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.163391 0.000076 0.004996 -0.944584 -0.005257 0.001399 0.006266 -39.785156 141.257812 -340.664062 -0.008494 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287466 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633363 0.325609 0.000000 -0.019042 0.009987 -0.035906 0.046630 0.126181 0.016286 0.074342 0.108071 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.168396 0.001297 0.004264 -0.943119 -0.005257 0.000335 0.005202 -39.785156 141.257812 -340.664062 -0.008506 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286984 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633190 0.326124 0.000000 -0.018877 0.009995 -0.035590 0.046629 0.125692 0.016758 0.074502 0.107928 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.173401 0.003006 0.007193 -0.946293 -0.004193 0.000335 0.006266 -38.648438 142.406250 -346.640625 -0.008509 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286511 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633010 0.326108 0.000000 -0.018887 0.009828 -0.035906 0.046628 0.126185 0.016599 0.074029 0.108067 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.178406 0.001297 0.006461 -0.942386 -0.006321 0.000335 0.005202 -38.648438 142.406250 -346.640625 -0.008521 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286047 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632513 0.326593 0.000000 -0.018886 0.010172 -0.035605 0.046627 0.125539 0.016557 0.074672 0.108111 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.183411 0.003250 0.002311 -0.941654 -0.005257 -0.000729 0.005202 -48.878906 143.554688 -343.054688 -0.008525 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285593 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632145 0.326636 0.000000 -0.018727 0.009991 -0.035605 0.046623 0.125561 0.016897 0.074333 0.108089 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.188416 0.000320 0.004752 -0.948002 -0.005257 0.001399 0.005202 -48.878906 143.554688 -343.054688 -0.008526 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285148 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632497 0.326514 0.000000 -0.019083 0.009983 -0.035605 0.046630 0.125924 0.016549 0.074681 0.107726 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.193420 0.003250 0.004264 -0.945316 -0.005257 0.001399 0.005202 -40.921875 137.812500 -344.250000 -0.008524 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284712 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632894 0.326212 0.000000 -0.019087 0.009971 -0.035605 0.046637 0.125941 0.016558 0.074672 0.107709 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.198425 0.003250 0.000846 -0.944095 -0.005257 0.001399 0.006266 -40.921875 137.812500 -344.250000 -0.008518 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284285 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633358 0.325719 0.000000 -0.019094 0.009953 -0.035921 0.046647 0.126282 0.016252 0.074345 0.108000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.203430 0.002273 0.006461 -0.947757 -0.004193 0.001399 0.006266 -39.785156 136.664062 -340.664062 -0.008503 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283866 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633916 0.324713 0.000000 -0.019104 0.009760 -0.035921 0.046658 0.126485 0.016434 0.074163 0.107797 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.208435 -0.001633 0.004020 -0.943119 -0.004193 0.001399 0.006266 -39.785156 136.664062 -340.664062 -0.008485 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283859 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634504 0.323609 0.000000 -0.019116 0.009740 -0.035921 0.046670 0.126518 0.016442 0.074155 0.107765 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.213440 0.001785 0.004508 -0.942630 -0.003128 0.001399 0.005202 -38.648438 140.109375 -341.859375 -0.008461 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283851 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635005 0.322176 0.000000 -0.019127 0.009549 -0.035605 0.046681 0.126403 0.016939 0.074290 0.107247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.218445 0.002762 0.007682 -0.941410 -0.004193 0.001399 0.006266 -38.648438 140.109375 -341.859375 -0.008442 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283844 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635415 0.321129 0.000000 -0.019135 0.009702 -0.035921 0.046690 0.126574 0.016462 0.074136 0.107708 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.223450 -0.000656 0.007437 -0.945072 -0.005257 0.001399 0.006266 -38.648438 140.109375 -346.640625 -0.008430 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283837 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636117 0.320273 0.000000 -0.019152 0.009843 -0.035921 0.046699 0.126441 0.016294 0.074284 0.107822 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.228455 -0.001389 0.003531 -0.944095 -0.004193 0.000335 0.006266 -38.648438 140.109375 -346.640625 -0.008417 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283831 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636015 0.319617 0.000000 -0.018986 0.009654 -0.035921 0.046700 0.126463 0.016648 0.073930 0.107799 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.233459 -0.000656 0.007437 -0.942142 -0.004193 0.002463 0.006266 -38.648438 137.812500 -349.031250 -0.008406 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283825 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636346 0.319146 0.000000 -0.019328 0.009647 -0.035921 0.046708 0.126812 0.016313 0.074264 0.107451 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.238464 -0.001633 0.007682 -0.942630 -0.003128 0.001399 0.006266 -38.648438 137.812500 -349.031250 -0.008393 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283819 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.636110 0.318561 0.000000 -0.019142 0.009477 -0.035921 0.046707 0.126796 0.016670 0.073907 0.107466 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.243469 0.002762 0.006949 -0.945072 -0.003128 0.000335 0.006266 -40.921875 142.406250 -344.250000 -0.008385 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283813 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.635372 0.318222 0.000000 -0.018958 0.009487 -0.035921 0.046697 0.126602 0.016843 0.073734 0.107661 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.248474 -0.000412 0.004020 -0.944339 -0.006321 0.000335 0.006266 -40.921875 142.406250 -344.250000 -0.008395 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283807 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.634569 0.319007 0.000000 -0.018948 0.010008 -0.035921 0.046685 0.126071 0.016333 0.074244 0.108192 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.253479 0.000320 0.004996 -0.942142 -0.005257 0.000335 0.006266 -40.921875 142.406250 -344.250000 -0.008401 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283801 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633759 0.319494 0.000000 -0.018935 0.009833 -0.035921 0.046672 0.126233 0.016520 0.074057 0.108029 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.258484 0.000076 0.003531 -0.943607 -0.005257 0.001399 0.006266 -44.332031 141.257812 -345.445312 -0.008406 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283796 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633266 0.319906 0.000000 -0.019090 0.009835 -0.035921 0.046663 0.126387 0.016364 0.074214 0.107875 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.263489 -0.000168 0.002799 -0.941410 -0.006321 -0.000729 0.004137 -44.332031 141.257812 -345.445312 -0.008414 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283790 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632144 0.320464 0.000000 -0.018732 0.010001 -0.035289 0.046644 0.125229 0.017188 0.074654 0.107769 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.268494 0.001785 0.006705 -0.941654 -0.005257 0.000335 0.006266 -46.605469 141.257812 -345.445312 -0.008414 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283785 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631400 0.320495 0.000000 -0.018894 0.009819 -0.035921 0.046630 0.126206 0.016576 0.074002 0.108056 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.273499 0.004959 0.006949 -0.943119 -0.005257 0.000335 0.006266 -46.605469 141.257812 -345.445312 -0.008412 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283779 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630795 0.320424 0.000000 -0.018883 0.009811 -0.035921 0.046618 0.126203 0.016594 0.073983 0.108060 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.278503 0.002029 0.006217 -0.944095 -0.005257 0.000335 0.005202 -30.691406 136.664062 -343.054688 -0.008410 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283773 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630442 0.320364 0.000000 -0.018878 0.009805 -0.035605 0.046610 0.125889 0.016922 0.074288 0.107741 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.283508 0.000809 0.004752 -0.939213 -0.004193 0.001399 0.005202 -30.691406 136.664062 -343.054688 -0.008404 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283768 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630652 0.320036 0.000000 -0.019050 0.009631 -0.035605 0.046611 0.126234 0.016924 0.074286 0.107396 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.288513 -0.000656 0.003531 -0.945072 -0.004193 0.001399 0.004137 -40.921875 137.812500 -339.468750 -0.008398 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283762 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630982 0.319722 0.000000 -0.019049 0.009633 -0.035289 0.046615 0.125915 0.017239 0.074603 0.107083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.293518 0.002029 0.005973 -0.945316 -0.003128 0.001399 0.005202 -40.921875 137.812500 -339.468750 -0.008385 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283756 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631338 0.319064 0.000000 -0.019050 0.009464 -0.035605 0.046619 0.126402 0.017091 0.074119 0.107229 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.298523 -0.001633 0.006705 -0.944584 -0.004193 0.001399 0.006266 -40.921875 142.406250 -341.859375 -0.008378 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283750 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631662 0.318731 0.000000 -0.019052 0.009638 -0.035921 0.046624 0.126545 0.016599 0.073978 0.107717 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.303528 0.001297 0.005729 -0.948734 -0.004193 0.001399 0.004137 -40.921875 142.406250 -341.859375 -0.008372 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283744 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631888 0.318450 0.000000 -0.019051 0.009635 -0.035289 0.046627 0.125915 0.017234 0.074608 0.107083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.308533 0.003006 0.007193 -0.943851 -0.004193 0.001399 0.005202 -44.332031 136.664062 -347.835938 -0.008366 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283537 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632049 0.318552 0.000000 -0.019050 0.009644 -0.035605 0.046629 0.126231 0.016921 0.074308 0.107419 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.313538 0.002273 0.007193 -0.943119 -0.004193 0.001399 0.006266 -44.332031 136.664062 -347.835938 -0.008363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283334 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632234 0.318474 0.000000 -0.019050 0.009646 -0.035921 0.046631 0.126545 0.016603 0.073995 0.107737 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.318542 0.000809 0.006705 -0.943607 -0.005257 0.002463 0.005202 -45.468750 144.703125 -346.640625 -0.008368 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283136 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632786 0.318851 0.000000 -0.019221 0.009821 -0.035605 0.046641 0.126225 0.016573 0.074657 0.107425 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.323547 -0.000656 0.005240 -0.940921 -0.004193 0.001399 0.005202 -45.468750 144.703125 -346.640625 -0.008369 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282942 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633017 0.319012 0.000000 -0.019049 0.009654 -0.035605 0.046645 0.126220 0.016912 0.074318 0.107431 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.328552 -0.000168 0.006217 -0.940921 -0.003128 0.000335 0.006266 -40.921875 140.109375 -344.250000 -0.008366 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282751 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632871 0.318916 0.000000 -0.018883 0.009497 -0.035921 0.046643 0.126527 0.016919 0.073679 0.107755 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.333557 0.001541 0.006705 -0.944584 -0.003128 0.001399 0.007330 -40.921875 140.109375 -344.250000 -0.008364 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282565 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632961 0.318862 0.000000 -0.019059 0.009515 -0.036237 0.046645 0.127001 0.016409 0.073557 0.107914 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.338562 0.000564 0.005973 -0.943119 -0.004193 0.000335 0.005202 -39.785156 138.960938 -345.445312 -0.008368 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282382 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632664 0.319152 0.000000 -0.018887 0.009701 -0.035605 0.046640 0.126011 0.017027 0.074203 0.107639 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.343567 0.000320 0.007193 -0.942386 -0.004193 0.001399 0.005202 -39.785156 138.960938 -345.445312 -0.008372 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282203 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632646 0.319452 0.000000 -0.019058 0.009710 -0.035605 0.046640 0.126174 0.016847 0.074383 0.107476 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.348572 0.001297 0.004996 -0.942142 -0.005257 0.001399 0.006266 -35.238281 145.851562 -345.445312 -0.008382 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282028 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632588 0.320061 0.000000 -0.019052 0.009887 -0.035921 0.046639 0.126306 0.016359 0.074238 0.107976 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.353577 0.003494 0.002799 -0.939945 -0.003128 -0.000729 0.005202 -35.238281 145.851562 -345.445312 -0.008381 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281855 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631561 0.319954 0.000000 -0.018698 0.009550 -0.035605 0.046627 0.125974 0.017367 0.073863 0.107677 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.358582 0.002029 0.005729 -0.941410 -0.004193 0.001399 0.006266 -35.238281 145.851562 -345.445312 -0.008382 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281686 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631657 0.320019 0.000000 -0.019048 0.009728 -0.035921 0.046628 0.126460 0.016523 0.074075 0.107822 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.363586 0.001541 0.004996 -0.947513 -0.005257 0.000335 0.006266 -43.195312 140.109375 -349.031250 -0.008385 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281521 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631563 0.320234 0.000000 -0.018878 0.009894 -0.035921 0.046626 0.126125 0.016526 0.074071 0.108157 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.368591 0.000320 0.004508 -0.941654 -0.004193 0.000335 0.006266 -43.195312 140.109375 -349.031250 -0.008381 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281358 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631565 0.319988 0.000000 -0.018888 0.009712 -0.035921 0.046626 0.126317 0.016699 0.073898 0.107965 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.373596 0.002518 0.004996 -0.940433 -0.003128 0.001399 0.006266 -42.058594 136.664062 -343.054688 -0.008370 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281198 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631929 0.319316 0.000000 -0.019067 0.009534 -0.035921 0.046632 0.126674 0.016698 0.073899 0.107608 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.378601 0.000564 0.007682 -0.941166 -0.006321 0.001399 0.006266 -42.058594 136.664062 -343.054688 -0.008373 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281042 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632670 0.319543 0.000000 -0.019081 0.010036 -0.035921 0.046638 0.126186 0.016182 0.074416 0.108096 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.383606 0.000320 0.005729 -0.941898 -0.003128 0.001399 0.007330 -45.468750 140.109375 -349.031250 -0.008361 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280888 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633030 0.318838 0.000000 -0.019085 0.009505 -0.036237 0.046644 0.127037 0.016393 0.073572 0.107877 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.388611 0.001053 0.007682 -0.944584 -0.005257 0.001399 0.006266 -45.468750 140.109375 -349.031250 -0.008361 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280736 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633323 0.318878 0.000000 -0.019087 0.009844 -0.035921 0.046650 0.126385 0.016368 0.074230 0.107898 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.393616 -0.000168 0.003043 -0.942875 -0.005257 0.000335 0.005202 -34.101562 137.812500 -341.859375 -0.008362 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280588 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633217 0.318996 0.000000 -0.018919 0.009833 -0.035605 0.046649 0.125911 0.016863 0.074367 0.107739 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.398621 0.000076 0.006217 -0.939945 -0.005257 0.000335 0.005202 -34.101562 137.812500 -341.859375 -0.008363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280443 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633021 0.319131 0.000000 -0.018924 0.009824 -0.035605 0.046646 0.125925 0.016867 0.074363 0.107726 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.403625 -0.002365 0.006461 -0.944828 -0.006321 0.001399 0.005202 -45.468750 142.406250 -341.859375 -0.008371 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280299 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.633000 0.319579 0.000000 -0.019092 0.009986 -0.035605 0.046646 0.125931 0.016537 0.074693 0.107719 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.408630 0.000076 0.005484 -0.945560 -0.003128 0.000335 0.007330 -45.468750 142.406250 -341.859375 -0.008362 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280360 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.632478 0.319100 0.000000 -0.018909 0.009468 -0.036237 0.046637 0.126899 0.016605 0.073360 0.108016 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.413635 0.000809 0.006949 -0.946048 -0.005257 0.000335 0.005202 -39.785156 138.960938 -343.054688 -0.008366 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280419 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631810 0.319315 0.000000 -0.018898 0.009817 -0.035605 0.046626 0.125906 0.016899 0.074331 0.107744 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.418640 -0.003586 0.005729 -0.944828 -0.004193 0.000335 0.004137 -39.785156 138.960938 -343.054688 -0.008364 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280477 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.631030 0.319259 0.000000 -0.018883 0.009646 -0.035289 0.046612 0.125735 0.017392 0.074450 0.107263 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.423645 -0.002854 0.006217 -0.942386 -0.004193 0.000335 0.006266 -39.785156 145.851562 -338.273438 -0.008364 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280534 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.630085 0.319257 0.000000 -0.018861 0.009653 -0.035921 0.046595 0.126339 0.016774 0.073804 0.107923 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.428650 -0.000168 0.006217 -0.941410 -0.005257 -0.000729 0.004137 -39.785156 145.851562 -338.273438 -0.008370 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280590 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.628633 0.319607 0.000000 -0.018664 0.009829 -0.035289 0.046568 0.125334 0.017427 0.074415 0.107664 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.433655 0.001297 0.004508 -0.949466 -0.005257 0.001399 0.005202 -40.921875 135.515625 -337.078125 -0.008376 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280645 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.627740 0.319954 0.000000 -0.018978 0.009830 -0.035605 0.046550 0.125963 0.016798 0.074412 0.107667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.438660 0.001541 0.001578 -0.949222 -0.004193 0.000335 0.006266 -40.921875 135.515625 -337.078125 -0.008375 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280699 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626583 0.319889 0.000000 -0.018771 0.009659 -0.035921 0.046527 0.126243 0.016858 0.073719 0.108020 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.443665 0.001053 0.004996 -0.944095 -0.005257 0.001399 0.005202 -44.332031 134.367188 -347.835938 -0.008376 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280752 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625906 0.319651 0.000000 -0.018915 0.009819 -0.035605 0.046511 0.125910 0.016871 0.074339 0.107720 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.448669 0.003006 0.006949 -0.943607 -0.004193 0.000335 0.006266 -44.332031 134.367188 -347.835938 -0.008369 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280805 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625138 0.319231 0.000000 -0.018720 0.009639 -0.035921 0.046494 0.126213 0.016930 0.073648 0.108049 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.453674 -0.000900 0.005240 -0.948734 -0.006321 0.001399 0.006266 -40.921875 142.406250 -346.640625 -0.008372 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280857 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624932 0.319387 0.000000 -0.018879 0.009970 -0.035921 0.046485 0.126040 0.016440 0.074138 0.108222 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.458679 0.001785 0.005729 -0.947513 -0.003128 0.001399 0.005202 -40.921875 142.406250 -346.640625 -0.008358 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280908 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624900 0.318585 0.000000 -0.018867 0.009443 -0.035605 0.046480 0.126239 0.017294 0.073916 0.107391 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.463684 0.001785 0.005240 -0.944095 -0.004193 0.000335 0.006266 -40.921875 142.406250 -346.640625 -0.008350 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.280959 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624706 0.318144 0.000000 -0.018693 0.009615 -0.035921 0.046472 0.126209 0.016981 0.073596 0.108053 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.468689 -0.000168 0.003287 -0.944584 -0.004193 0.001399 0.007330 -39.785156 143.554688 -338.273438 -0.008342 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281010 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624964 0.317714 0.000000 -0.018867 0.009609 -0.036237 0.046473 0.126706 0.016497 0.073448 0.108189 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.473694 -0.000900 0.005484 -0.938236 -0.005257 0.001399 0.007330 -39.785156 143.554688 -338.273438 -0.008338 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281060 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625255 0.317568 0.000000 -0.018867 0.009770 -0.036237 0.046474 0.126544 0.016337 0.073609 0.108350 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.478699 0.000076 0.005973 -0.939457 -0.004193 0.000335 0.006266 -43.195312 137.812500 -344.250000 -0.008329 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281109 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625177 0.317085 0.000000 -0.018697 0.009585 -0.035921 0.046469 0.126242 0.017007 0.073571 0.108020 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.483704 0.001297 0.005973 -0.939213 -0.005257 0.002463 0.005202 -43.195312 137.812500 -344.250000 -0.008325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281158 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625662 0.316959 0.000000 -0.019039 0.009748 -0.035605 0.046475 0.126106 0.016819 0.074391 0.107524 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.488708 0.001053 0.005729 -0.943363 -0.005257 0.001399 0.006266 -38.648438 135.515625 -339.468750 -0.008322 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281205 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625781 0.317193 0.000000 -0.018859 0.009745 -0.035921 0.046474 0.126246 0.016685 0.073893 0.108017 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.493713 -0.001145 0.006461 -0.941166 -0.004193 0.000335 0.006266 -38.648438 135.515625 -339.468750 -0.008316 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281252 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625555 0.316895 0.000000 -0.018688 0.009568 -0.035921 0.046468 0.126251 0.017033 0.073544 0.108011 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.498718 -0.000168 0.007437 -0.946537 -0.005257 0.000335 0.006266 -42.058594 150.445312 -340.664062 -0.008317 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281297 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625272 0.317032 0.000000 -0.018690 0.009739 -0.035921 0.046461 0.126082 0.016860 0.073718 0.108181 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.503723 0.001541 0.004752 -0.948734 -0.004193 0.000335 0.006266 -42.058594 150.445312 -340.664062 -0.008314 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281341 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624932 0.316971 0.000000 -0.018689 0.009569 -0.035921 0.046453 0.126251 0.017030 0.073547 0.108012 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.508728 0.001785 0.005973 -0.945316 -0.004193 0.000335 0.007330 -43.195312 144.703125 -346.640625 -0.008313 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281384 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624601 0.316990 0.000000 -0.018687 0.009578 -0.036237 0.046445 0.126567 0.016718 0.073248 0.108348 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.513733 0.001541 0.007193 -0.942142 -0.005257 0.001399 0.006266 -43.195312 144.703125 -346.640625 -0.008318 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.281827 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624646 0.317377 0.000000 -0.018856 0.009756 -0.035921 0.046443 0.126241 0.016687 0.073910 0.108042 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.518738 -0.000656 0.005729 -0.943119 -0.004193 0.001399 0.006266 -38.648438 140.109375 -344.250000 -0.008319 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282262 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624744 0.317496 0.000000 -0.018850 0.009591 -0.035921 0.046443 0.126400 0.016858 0.073739 0.107882 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.523743 0.003250 0.003287 -0.944095 -0.004193 0.000335 0.006266 -38.648438 140.109375 -344.250000 -0.008321 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.282688 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624570 0.317625 0.000000 -0.018677 0.009602 -0.035921 0.046438 0.126216 0.017020 0.073578 0.108066 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.528748 -0.000168 0.004752 -0.945316 -0.005257 0.001399 0.006266 -39.785156 138.960938 -343.054688 -0.008326 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283106 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624780 0.317979 0.000000 -0.018851 0.009778 -0.035921 0.046439 0.126214 0.016669 0.073928 0.108068 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.533752 0.001053 0.006217 -0.945316 -0.004193 0.001399 0.006266 -39.785156 138.960938 -343.054688 -0.008325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283516 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625022 0.317890 0.000000 -0.018851 0.009606 -0.035921 0.046442 0.126386 0.016842 0.073756 0.107897 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.538757 -0.002121 0.007193 -0.945560 -0.005257 0.000335 0.006266 -42.058594 138.960938 -345.445312 -0.008327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.283917 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624920 0.318066 0.000000 -0.018681 0.009778 -0.035921 0.046439 0.126044 0.016840 0.073758 0.108238 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.543762 0.000564 0.005973 -0.943363 -0.004193 0.000335 0.006266 -42.058594 138.960938 -345.445312 -0.008325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284310 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624732 0.317934 0.000000 -0.018685 0.009605 -0.035921 0.046434 0.126221 0.017009 0.073588 0.108062 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.548767 0.001297 0.006461 -0.942142 -0.005257 0.000335 0.006266 -39.785156 141.257812 -347.835938 -0.008329 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.284696 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624461 0.318167 0.000000 -0.018685 0.009779 -0.035921 0.046428 0.126047 0.016836 0.073762 0.108235 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.553772 -0.000412 0.004996 -0.941166 -0.004193 0.002463 0.006266 -39.785156 141.257812 -347.835938 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285074 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624770 0.318115 0.000000 -0.019020 0.009608 -0.035921 0.046432 0.126553 0.016670 0.073927 0.107729 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.558777 -0.000168 0.005729 -0.940677 -0.004193 0.001399 0.005202 -39.785156 141.257812 -347.835938 -0.008327 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285445 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624685 0.318080 0.000000 -0.018834 0.009615 -0.035605 0.046429 0.126044 0.017167 0.074063 0.107606 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.563782 0.000076 0.005240 -0.939213 -0.005257 0.000335 0.006266 -39.785156 141.257812 -347.835938 -0.008332 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.285808 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624227 0.318346 0.000000 -0.018654 0.009789 -0.035921 0.046420 0.126007 0.016856 0.073742 0.108276 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.568787 -0.000168 0.006461 -0.939213 -0.004193 0.001399 0.006266 -39.785156 141.257812 -347.835938 -0.008331 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286163 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624042 0.318270 0.000000 -0.018818 0.009617 -0.035921 0.046416 0.126342 0.016864 0.073734 0.107940 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.573792 -0.000168 0.006461 -0.939457 -0.004193 0.001399 0.006266 -43.195312 142.406250 -346.640625 -0.008330 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623806 0.317910 0.000000 -0.018804 0.009613 -0.035921 0.046410 0.126323 0.016871 0.073706 0.107940 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.578796 -0.000656 0.004508 -0.948490 -0.004193 0.002463 0.005202 -43.195312 142.406250 -346.640625 -0.008329 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.286852 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623829 0.317869 0.000000 -0.018959 0.009618 -0.035605 0.046409 0.126156 0.017028 0.074182 0.107474 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.583801 -0.002609 0.004508 -0.948490 -0.004193 0.001399 0.006266 -38.648438 140.109375 -346.640625 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287186 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623446 0.317795 0.000000 -0.018767 0.009621 -0.035921 0.046401 0.126278 0.016900 0.073677 0.107985 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.588806 -0.002365 0.007926 -0.942875 -0.004193 0.001399 0.006266 -38.648438 140.109375 -346.640625 -0.008326 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287512 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622924 0.317683 0.000000 -0.018749 0.009622 -0.035921 0.046390 0.126258 0.016917 0.073660 0.108004 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.593811 -0.000900 0.009391 -0.943851 -0.004193 0.002463 0.006266 -45.468750 137.812500 -344.250000 -0.008325 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.287832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622552 0.317634 0.000000 -0.018895 0.009625 -0.035921 0.046382 0.126402 0.016769 0.073809 0.107861 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.598816 0.001785 0.004996 -0.942142 -0.005257 0.001399 0.007330 -45.468750 137.812500 -344.250000 -0.008332 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288145 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621768 0.318342 0.000000 -0.018695 0.009809 -0.036237 0.046367 0.126343 0.016479 0.073487 0.108572 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.603821 0.003250 0.002311 -0.943363 -0.005257 0.002463 0.007330 -45.468750 140.109375 -346.640625 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288452 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621376 0.318786 0.000000 -0.018843 0.009810 -0.036237 0.046357 0.126489 0.016330 0.073636 0.108425 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.608826 0.003982 0.005729 -0.946293 -0.005257 0.002463 0.007330 -45.468750 140.109375 -346.640625 -0.008346 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.288752 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621216 0.319129 0.000000 -0.018822 0.009810 -0.036237 0.046352 0.126470 0.016350 0.073615 0.108445 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.613831 0.001541 0.005240 -0.947025 -0.006321 0.001399 0.007330 -38.648438 142.406250 -346.640625 -0.008355 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289247 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621066 0.319652 0.000000 -0.018645 0.009976 -0.036237 0.046347 0.126126 0.016362 0.073604 0.108788 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.618835 0.000564 0.004508 -0.940921 -0.006321 0.001399 0.007330 -38.648438 142.406250 -346.640625 -0.008363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289733 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621212 0.320040 0.000000 -0.018653 0.009964 -0.036237 0.046346 0.126146 0.016366 0.073599 0.108768 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.623840 0.001053 0.006461 -0.941654 -0.005257 0.001399 0.006266 -42.058594 143.554688 -345.445312 -0.008364 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290209 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621546 0.320008 0.000000 -0.018666 0.009783 -0.035921 0.046350 0.126025 0.016850 0.073747 0.108258 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.628845 0.001053 0.002799 -0.944828 -0.005257 0.001399 0.007330 -42.058594 143.554688 -345.445312 -0.008363 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621990 0.319900 0.000000 -0.018682 0.009776 -0.036237 0.046355 0.126363 0.016524 0.073441 0.108552 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.633850 0.003494 0.001578 -0.943119 -0.005257 0.000335 0.006266 -38.648438 144.703125 -339.468750 -0.008360 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291133 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622200 0.319652 0.000000 -0.018531 0.009766 -0.035921 0.046358 0.125906 0.017001 0.073596 0.108377 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.638855 0.003494 0.005973 -0.942630 -0.004193 0.000335 0.006266 -38.648438 144.703125 -339.468750 -0.008348 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291581 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622546 0.318906 0.000000 -0.018559 0.009582 -0.035921 0.046362 0.126118 0.017158 0.073440 0.108164 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.643860 -0.000168 0.004264 -0.944584 -0.005257 0.000335 0.006266 -46.605469 141.257812 -345.445312 -0.008339 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292021 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623017 0.318067 0.000000 -0.018588 0.009730 -0.035921 0.046370 0.125990 0.016971 0.073607 0.108273 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.648865 -0.000412 0.006461 -0.951420 -0.005257 0.000335 0.006266 -46.605469 141.257812 -345.445312 -0.008329 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292451 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623498 0.317496 0.000000 -0.018616 0.009709 -0.035921 0.046377 0.126038 0.016964 0.073614 0.108224 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.653870 0.000076 0.005973 -0.943363 -0.004193 0.002463 0.006266 -43.195312 140.109375 -341.859375 -0.008315 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292873 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624493 0.316671 0.000000 -0.018977 0.009522 -0.035921 0.046394 0.126587 0.016790 0.073787 0.107676 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.658875 0.000320 0.004996 -0.941898 -0.005257 0.002463 0.006266 -43.195312 140.109375 -341.859375 -0.008307 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293287 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625292 0.316286 0.000000 -0.018981 0.009682 -0.035921 0.046409 0.126430 0.016626 0.073952 0.107832 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.663879 0.000809 0.003775 -0.943363 -0.003128 0.001399 0.006266 -40.921875 144.703125 -341.859375 -0.008289 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293692 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625594 0.315663 0.000000 -0.018813 0.009340 -0.035921 0.046415 0.126614 0.017146 0.073451 0.107669 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.668884 -0.000168 0.007193 -0.946293 -0.004193 0.002463 0.006266 -40.921875 144.703125 -341.859375 -0.008278 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294090 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626060 0.315153 0.000000 -0.018986 0.009511 -0.035921 0.046425 0.126616 0.016802 0.073796 0.107667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.673889 -0.000168 0.005973 -0.940189 -0.005257 0.001399 0.006266 -40.921875 144.703125 -341.859375 -0.008275 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294480 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626058 0.315069 0.000000 -0.018810 0.009676 -0.035921 0.046427 0.126275 0.016812 0.073786 0.108007 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.678894 -0.001877 0.004508 -0.940677 -0.004193 0.002463 0.005202 -40.921875 137.812500 -341.859375 -0.008267 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294862 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.626212 0.314777 0.000000 -0.018976 0.009500 -0.035605 0.046431 0.126301 0.017138 0.074091 0.107349 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.683899 -0.000412 0.004996 -0.946537 -0.007385 0.000335 0.005202 -40.921875 137.812500 -341.859375 -0.008277 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295237 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625556 0.315487 0.000000 -0.018623 0.010008 -0.035605 0.046422 0.125440 0.016983 0.074247 0.108210 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.688904 -0.000168 0.007437 -0.945804 -0.004193 0.001399 0.005202 -39.785156 143.554688 -338.273438 -0.008271 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295604 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625085 0.315265 0.000000 -0.018787 0.009484 -0.035605 0.046415 0.126128 0.017343 0.073887 0.107522 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.693909 -0.000412 0.007437 -0.940433 -0.005257 0.000335 0.006266 -39.785156 143.554688 -338.273438 -0.008273 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295963 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624214 0.315466 0.000000 -0.018602 0.009662 -0.035921 0.046401 0.126082 0.017034 0.073563 0.108201 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.698914 -0.001877 0.005729 -0.940921 -0.005257 0.002463 0.005202 -42.058594 138.960938 -345.445312 -0.008277 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296316 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623907 0.315795 0.000000 -0.018929 0.009667 -0.035605 0.046396 0.126087 0.017019 0.074210 0.107564 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.703918 0.002029 0.005973 -0.946781 -0.003128 0.001399 0.006266 -42.058594 138.960938 -345.445312 -0.008272 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296661 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623232 0.315593 0.000000 -0.018732 0.009337 -0.035921 0.046384 0.126536 0.017229 0.073369 0.107746 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.708923 -0.000656 0.006949 -0.947513 -0.004193 0.000335 0.005202 -43.195312 144.703125 -344.250000 -0.008275 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296999 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622276 0.315798 0.000000 -0.018545 0.009530 -0.035605 0.046367 0.125840 0.017540 0.073690 0.107810 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.713928 -0.000412 0.006461 -0.944339 -0.004193 0.002463 0.006266 -43.195312 144.703125 -344.250000 -0.008278 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296728 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622020 0.316065 0.000000 -0.018872 0.009546 -0.035921 0.046361 0.126467 0.016880 0.073718 0.107815 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.718933 0.000809 0.006461 -0.941410 -0.004193 0.000335 0.006266 -44.332031 145.851562 -345.445312 -0.008283 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296461 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621181 0.316385 0.000000 -0.018511 0.009563 -0.035921 0.046345 0.126089 0.017224 0.073374 0.108193 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.723938 0.002273 0.005973 -0.939701 -0.005257 0.000335 0.006266 -44.332031 145.851562 -345.445312 -0.008294 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.296201 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620468 0.317042 0.000000 -0.018506 0.009749 -0.035921 0.046330 0.125898 0.017043 0.073554 0.108384 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.728943 0.004471 0.004264 -0.943607 -0.004193 0.000335 0.005202 -43.195312 137.812500 -349.031250 -0.008299 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295946 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619975 0.317344 0.000000 -0.018506 0.009589 -0.035605 0.046319 0.125742 0.017520 0.073709 0.107909 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.733948 0.002273 0.004508 -0.945804 -0.006321 0.001399 0.005202 -43.195312 137.812500 -349.031250 -0.008314 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295695 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620102 0.318168 0.000000 -0.018681 0.009940 -0.035605 0.046319 0.125567 0.016994 0.074236 0.108083 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.738953 0.001541 0.003775 -0.944584 -0.005257 0.001399 0.007330 -40.921875 137.812500 -341.859375 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295450 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620510 0.318478 0.000000 -0.018689 0.009765 -0.036237 0.046323 0.126382 0.016529 0.073437 0.108533 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.743958 0.001785 0.007682 -0.944584 -0.004193 0.001399 0.006266 -40.921875 137.812500 -341.859375 -0.008318 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.295210 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621110 0.318312 0.000000 -0.018703 0.009594 -0.035921 0.046331 0.126251 0.017001 0.073596 0.108032 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.748962 0.001541 0.007437 -0.939945 -0.005257 0.001399 0.006266 -38.648438 142.406250 -341.859375 -0.008321 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294974 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621831 0.318419 0.000000 -0.018722 0.009766 -0.035921 0.046342 0.126096 0.016811 0.073787 0.108186 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.753967 0.000076 0.007682 -0.939945 -0.004193 0.001399 0.007330 -38.648438 142.406250 -341.859375 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294743 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622595 0.317974 0.000000 -0.018742 0.009587 -0.036237 0.046354 0.126602 0.016644 0.073301 0.108293 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.758972 0.000320 0.005973 -0.942142 -0.004193 0.003528 0.007330 -37.511719 141.257812 -345.445312 -0.008320 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294517 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623926 0.317954 0.000000 -0.019098 0.009596 -0.036237 0.046376 0.126950 0.016279 0.073666 0.107945 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.763977 -0.000168 0.006949 -0.940189 -0.005257 0.001399 0.006266 -37.511719 141.257812 -345.445312 -0.008328 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294295 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624472 0.318357 0.000000 -0.018762 0.009776 -0.035921 0.046387 0.126118 0.016751 0.073827 0.108144 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.768982 0.000809 0.006949 -0.943363 -0.005257 0.001399 0.006266 -44.332031 141.257812 -343.054688 -0.008337 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.294077 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624866 0.318839 0.000000 -0.018776 0.009782 -0.035921 0.046395 0.126125 0.016731 0.073847 0.108137 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.773987 -0.000900 0.005729 -0.942386 -0.005257 0.000335 0.007330 -44.332031 141.257812 -343.054688 -0.008348 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293863 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624791 0.319379 0.000000 -0.018616 0.009791 -0.036237 0.046395 0.126272 0.016566 0.073379 0.108623 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.778992 -0.000168 0.005484 -0.944828 -0.005257 0.000335 0.006266 -44.332031 141.257812 -343.054688 -0.008359 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293654 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624559 0.319924 0.000000 -0.018625 0.009801 -0.035921 0.046393 0.125955 0.016862 0.073715 0.108307 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.783997 0.001297 0.006705 -0.939213 -0.004193 0.000335 0.007330 -32.964844 141.257812 -347.835938 -0.008364 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293448 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624199 0.320121 0.000000 -0.018629 0.009642 -0.036237 0.046388 0.126434 0.016702 0.073244 0.108460 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.789001 0.002518 0.007193 -0.942875 -0.005257 -0.000729 0.005202 -32.964844 141.257812 -347.835938 -0.008375 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293246 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623481 0.320624 0.000000 -0.018461 0.009827 -0.035605 0.046376 0.125449 0.017317 0.073893 0.108182 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.794006 0.002762 0.005973 -0.943607 -0.004193 0.000335 0.006266 -37.511719 134.367188 -350.226562 -0.008380 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293047 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623165 0.320809 0.000000 -0.018637 0.009667 -0.035921 0.046371 0.126102 0.016984 0.073593 0.108161 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.799011 -0.001145 0.004996 -0.947757 -0.004193 0.000335 0.005202 -37.511719 134.367188 -350.226562 -0.008386 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292852 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622948 0.320980 0.000000 -0.018639 0.009682 -0.035605 0.046367 0.125772 0.017284 0.073926 0.107858 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.804016 0.000809 0.007193 -0.948978 -0.004193 0.001399 0.005202 -38.648438 142.406250 -349.031250 -0.008390 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292661 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623085 0.321108 0.000000 -0.018810 0.009695 -0.035605 0.046369 0.125930 0.017100 0.074109 0.107700 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.809021 0.003982 0.005973 -0.948002 -0.005257 0.000335 0.006266 -38.648438 142.406250 -349.031250 -0.008399 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292474 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622940 0.321516 0.000000 -0.018637 0.009874 -0.035921 0.046367 0.125894 0.016778 0.073800 0.108369 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.814026 -0.000412 0.003287 -0.943851 -0.004193 0.001399 0.005202 -43.195312 147.000000 -344.250000 -0.008402 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292291 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623195 0.321541 0.000000 -0.018811 0.009707 -0.035605 0.046371 0.125920 0.017087 0.074123 0.107711 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.819031 0.000564 0.007193 -0.940189 -0.004193 0.001399 0.005202 -43.195312 147.000000 -344.250000 -0.008403 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292112 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623123 0.321771 0.000000 -0.018800 0.009722 -0.035605 0.046376 0.125904 0.017093 0.074137 0.107746 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.824036 -0.001145 0.005729 -0.938724 -0.004193 0.001399 0.005202 -32.964844 138.960938 -340.664062 -0.008403 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291937 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623368 0.321638 0.000000 -0.018800 0.009725 -0.035605 0.046380 0.125901 0.017090 0.074139 0.107750 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.829041 -0.002121 0.005729 -0.939945 -0.006321 0.000335 0.005202 -32.964844 138.960938 -340.664062 -0.008413 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291766 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623172 0.322102 0.000000 -0.018628 0.010064 -0.035605 0.046377 0.125389 0.016924 0.074306 0.108261 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.834045 -0.001877 0.004508 -0.943119 -0.005257 0.000335 0.006266 -32.964844 145.851562 -343.054688 -0.008416 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291598 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622782 0.322185 0.000000 -0.018625 0.009881 -0.035921 0.046371 0.125885 0.016792 0.073805 0.108397 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.839050 0.001053 0.005729 -0.943363 -0.004193 0.001399 0.005202 -32.964844 145.851562 -343.054688 -0.008413 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291433 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622865 0.321595 0.000000 -0.018796 0.009697 -0.035605 0.046366 0.125914 0.017112 0.074097 0.107717 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.844055 -0.000412 0.007437 -0.942386 -0.005257 0.000335 0.005202 -40.921875 144.703125 -351.421875 -0.008415 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291271 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622139 0.321605 0.000000 -0.018606 0.009866 -0.035605 0.046353 0.125555 0.017133 0.074077 0.108075 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.849060 0.000564 0.005484 -0.947757 -0.004193 0.001399 0.005202 -40.921875 144.703125 -351.421875 -0.008412 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291113 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621683 0.321331 0.000000 -0.018760 0.009691 -0.035605 0.046345 0.125884 0.017154 0.074056 0.107746 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.854065 0.001785 0.008902 -0.942386 -0.005257 0.001399 0.006266 -38.648438 140.109375 -341.859375 -0.008415 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290958 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621241 0.321459 0.000000 -0.018739 0.009863 -0.035921 0.046336 0.126007 0.016687 0.073891 0.108256 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.859070 -0.001633 0.006217 -0.940921 -0.005257 0.000335 0.005202 -38.648438 140.109375 -341.859375 -0.008420 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290805 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620544 0.321709 0.000000 -0.018551 0.009864 -0.035605 0.046322 0.125503 0.017190 0.074020 0.108128 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.864075 0.002518 0.004264 -0.945316 -0.003128 0.002463 0.005202 -37.511719 148.148438 -340.664062 -0.008417 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290656 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620549 0.321427 0.000000 -0.018879 0.009529 -0.035605 0.046321 0.126165 0.017196 0.074014 0.107465 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.869080 0.000076 0.004752 -0.943851 -0.004193 0.001399 0.006266 -37.511719 148.148438 -340.664062 -0.008419 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290509 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620315 0.321477 0.000000 -0.018690 0.009715 -0.035921 0.046315 0.126106 0.016883 0.073694 0.108156 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.874084 -0.000412 0.005729 -0.944584 -0.004193 0.001399 0.007330 -45.468750 140.109375 -334.687500 -0.008420 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290366 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620169 0.321462 0.000000 -0.018681 0.009721 -0.036237 0.046310 0.126407 0.016570 0.073375 0.108488 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.879089 0.002273 0.006217 -0.947757 -0.004193 0.000335 0.006266 -45.468750 140.109375 -334.687500 -0.008419 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290225 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619772 0.321387 0.000000 -0.018506 0.009725 -0.035921 0.046302 0.125912 0.017058 0.073519 0.108351 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.884094 0.001053 0.005973 -0.944828 -0.005257 0.001399 0.005202 -45.468750 140.109375 -334.687500 -0.008423 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290087 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619793 0.321892 0.000000 -0.018677 0.009905 -0.035590 0.046300 0.125583 0.017048 0.074212 0.108037 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.889099 0.000809 0.006217 -0.943607 -0.004193 0.001399 0.006266 -39.785156 150.445312 -343.054688 -0.008422 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289952 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.619911 0.321763 0.000000 -0.018676 0.009730 -0.035906 0.046300 0.126072 0.016908 0.073720 0.108180 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.894104 0.001785 0.007926 -0.944095 -0.005257 0.002463 0.007330 -39.785156 150.445312 -343.054688 -0.008426 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289821 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620425 0.321980 0.000000 -0.018847 0.009902 -0.036222 0.046307 0.126386 0.016249 0.073747 0.108498 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.899109 0.002273 0.006217 -0.937259 -0.005257 0.001399 0.007330 -44.332031 141.257812 -338.273438 -0.008432 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289692 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.620700 0.322264 0.000000 -0.018676 0.009901 -0.036222 0.046311 0.126218 0.016421 0.073575 0.108667 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.904114 0.001297 0.007193 -0.939213 -0.004193 0.001399 0.006266 -44.332031 141.257812 -338.273438 -0.008434 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289565 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621073 0.322315 0.000000 -0.018686 0.009734 -0.035906 0.046316 0.126078 0.016895 0.073733 0.108174 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.909119 0.002762 0.006461 -0.937504 -0.004193 0.002463 0.006266 -42.058594 145.851562 -340.664062 -0.008437 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289441 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.621853 0.322459 0.000000 -0.018867 0.009745 -0.035921 0.046329 0.126263 0.016686 0.073911 0.108019 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.914124 0.002518 0.005240 -0.941166 -0.004193 0.000335 0.005202 -42.058594 145.851562 -340.664062 -0.008442 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289320 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622091 0.322659 0.000000 -0.018539 0.009758 -0.035605 0.046333 0.125606 0.017318 0.073911 0.108044 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.919128 0.000809 0.006705 -0.945072 -0.004193 0.001399 0.005202 -42.058594 143.554688 -343.054688 -0.008446 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289602 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622746 0.322864 0.000000 -0.018734 0.009770 -0.035605 0.046345 0.125790 0.017111 0.074119 0.107861 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.924133 0.000809 0.007682 -0.945316 -0.004193 0.002463 0.005202 -42.058594 143.554688 -343.054688 -0.008451 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.289879 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623728 0.323078 0.000000 -0.018922 0.009781 -0.035605 0.046362 0.125966 0.016912 0.074318 0.107684 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.929138 -0.000656 0.005729 -0.937992 -0.004193 0.002463 0.005202 -38.648438 137.812500 -346.640625 -0.008457 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290149 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624624 0.323318 0.000000 -0.018933 0.009793 -0.035590 0.046379 0.125950 0.016905 0.074355 0.107670 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.934143 -0.001633 0.006705 -0.942142 -0.005257 0.001399 0.005202 -38.648438 137.812500 -346.640625 -0.008467 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290413 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625031 0.323879 0.000000 -0.018771 0.009973 -0.035590 0.046388 0.125608 0.016886 0.074374 0.108012 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.939148 -0.000168 0.007682 -0.941898 -0.005257 0.001399 0.006266 -38.648438 140.109375 -349.031250 -0.008479 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290672 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625213 0.324433 0.000000 -0.018779 0.009978 -0.035906 0.046394 0.125927 0.016557 0.074071 0.108325 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.944153 0.000320 0.005973 -0.943363 -0.006321 0.000335 0.004137 -38.648438 140.109375 -349.031250 -0.008495 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.290925 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624862 0.325307 0.000000 -0.018611 0.010153 -0.035274 0.046390 0.124952 0.017182 0.074710 0.108036 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.949158 0.001297 0.006705 -0.944339 -0.004193 0.001399 0.005202 -40.921875 147.000000 -349.031250 -0.008502 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291173 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624338 0.325535 0.000000 -0.018772 0.009816 -0.035590 0.046389 0.125766 0.017041 0.074219 0.107854 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.954163 0.000564 0.006705 -0.943119 -0.006321 0.001399 0.005202 -40.921875 147.000000 -349.031250 -0.008519 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291415 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624107 0.326385 0.000000 -0.018765 0.010170 -0.035590 0.046387 0.125405 0.016695 0.074566 0.108215 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.959167 0.000076 0.006461 -0.941166 -0.004193 0.001399 0.006266 -39.785156 141.257812 -345.445312 -0.008526 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291652 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623854 0.326575 0.000000 -0.018758 0.009834 -0.035906 0.046384 0.126050 0.016722 0.073906 0.108202 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.964172 0.000320 0.003775 -0.940677 -0.005257 0.000335 0.006266 -39.785156 141.257812 -345.445312 -0.008536 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.291885 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623277 0.327034 0.000000 -0.018581 0.010018 -0.035906 0.046376 0.125689 0.016715 0.073913 0.108563 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.969177 0.001785 0.004752 -0.946048 -0.005257 0.000335 0.007330 -43.195312 137.812500 -339.468750 -0.008545 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292112 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622735 0.327355 0.000000 -0.018580 0.010022 -0.036222 0.046367 0.126000 0.016396 0.073600 0.108884 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.974182 0.000076 0.005484 -0.948978 -0.004193 0.001399 0.006266 -43.195312 137.812500 -339.468750 -0.008546 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292335 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622929 0.327192 0.000000 -0.018759 0.009852 -0.035921 0.046364 0.126048 0.016688 0.073910 0.108234 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.979187 0.003006 0.005240 -0.946537 -0.005257 0.001399 0.005202 -42.058594 138.960938 -343.054688 -0.008549 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292553 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622833 0.327208 0.000000 -0.018752 0.010023 -0.035605 0.046362 0.125555 0.016840 0.074390 0.108096 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.984192 0.003006 0.002066 -0.945316 -0.006321 0.000335 0.005202 -42.058594 138.960938 -343.054688 -0.008554 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292767 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622565 0.327374 0.000000 -0.018582 0.010182 -0.035605 0.046358 0.125225 0.016852 0.074378 0.108425 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.989197 0.000564 0.004020 -0.941898 -0.005257 0.000335 0.006266 -42.058594 138.960938 -343.054688 -0.008551 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292977 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622487 0.327005 0.000000 -0.018592 0.009990 -0.035921 0.046356 0.125743 0.016716 0.073881 0.108540 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.994202 0.000320 0.005729 -0.941410 -0.006321 0.000335 0.005202 -36.375000 142.406250 -349.031250 -0.008549 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293183 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622529 0.326768 0.000000 -0.018604 0.010140 -0.035605 0.046356 0.125289 0.016870 0.074359 0.108361 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+459.999207 0.000320 0.006217 -0.939213 -0.005257 0.001399 0.007330 -36.375000 142.406250 -349.031250 -0.008540 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293385 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.622922 0.326131 0.000000 -0.018786 0.009944 -0.036237 0.046363 0.126299 0.016253 0.073712 0.108616 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.004211 -0.000412 0.005484 -0.942142 -0.004193 0.001399 0.006266 -38.648438 140.109375 -344.250000 -0.008526 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293584 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623260 0.325216 0.000000 -0.018789 0.009756 -0.035921 0.046368 0.126174 0.016753 0.073844 0.108109 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.009216 0.000809 0.003775 -0.943851 -0.005257 0.002463 0.006266 -38.648438 140.109375 -344.250000 -0.008517 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293778 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.623818 0.324686 0.000000 -0.018959 0.009915 -0.035921 0.046378 0.126185 0.016424 0.074173 0.108097 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.014221 0.002029 0.005729 -0.940921 -0.004193 0.002463 0.006266 -37.511719 141.257812 -343.054688 -0.008503 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293969 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624287 0.323885 0.000000 -0.018953 0.009730 -0.035921 0.046387 0.126365 0.016616 0.073981 0.107918 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.019226 0.000564 0.005240 -0.947269 -0.004193 0.002463 0.007330 -37.511719 141.257812 -343.054688 -0.008490 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293753 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624718 0.322851 0.000000 -0.018948 0.009712 -0.036237 0.046395 0.126693 0.016323 0.073643 0.108222 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.024231 0.001541 0.004020 -0.947025 -0.005257 0.002463 0.006266 -42.058594 143.554688 -343.054688 -0.008483 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293542 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625127 0.322494 0.000000 -0.018944 0.009873 -0.035921 0.046403 0.126213 0.016482 0.074116 0.108070 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.029236 -0.000168 0.004020 -0.942630 -0.004193 0.002463 0.004137 -42.058594 143.554688 -343.054688 -0.008470 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293335 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625511 0.321831 0.000000 -0.018942 0.009689 -0.035289 0.046411 0.125762 0.017301 0.074561 0.107256 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.034241 0.001297 0.004752 -0.939945 -0.006321 0.001399 0.005202 -42.058594 145.851562 -343.054688 -0.008467 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.293133 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625555 0.321783 0.000000 -0.018771 0.010017 -0.035605 0.046414 0.125579 0.016826 0.074403 0.108071 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.039246 0.001785 0.005973 -0.943119 -0.004193 0.000335 0.005202 -42.058594 145.851562 -343.054688 -0.008454 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292934 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625289 0.321090 0.000000 -0.018608 0.009657 -0.035605 0.046411 0.125767 0.017340 0.073870 0.107863 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.044250 0.000320 0.003775 -0.948246 -0.004193 0.001399 0.005202 -34.101562 144.703125 -341.859375 -0.008440 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292740 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.625376 0.320436 0.000000 -0.018790 0.009649 -0.035605 0.046414 0.125956 0.017166 0.074044 0.107675 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.049255 0.002029 0.005240 -0.946537 -0.004193 -0.000729 0.005202 -34.101562 144.703125 -341.859375 -0.008427 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292549 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624862 0.319811 0.000000 -0.018457 0.009641 -0.035605 0.046407 0.125631 0.017507 0.073703 0.108000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.054260 -0.000412 0.006217 -0.944584 -0.004193 0.000335 0.006266 -40.921875 149.296875 -339.468750 -0.008414 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292363 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.624712 0.319231 0.000000 -0.018644 0.009633 -0.035921 0.046405 0.126142 0.017012 0.073566 0.108121 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
+460.059265 0.002273 0.009146 -0.940433 -0.005257 0.000335 0.006266 -40.921875 149.296875 -339.468750 -0.008408 0.000000 0.000000 0.000000 -0.880000 0.000000 -0.292180 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -1.556118 0.319092 0.000000 -0.046599 0.009797 0.003249 0.046403 0.114773 0.028073 0.140864 0.041169 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -0.087602 0.098929 0.000000 0.000000
diff --git a/controls/README.md b/controls/README.md
index 8a1d285f263eea8ecc25b67f4ec5d80e7ee04709..3dc51e0812f5cf04783e8e0fcd4e0f49bc5c72c1 100644
--- a/controls/README.md
+++ b/controls/README.md
@@ -2,6 +2,32 @@
This folder contains the files used in developing the model of the quadcopter.
-## Documentation
+### **1. Simulink Flight Simulator**
+
+**How to Run the Simulator**
+1. In the project folder, open “MicroCART/controls/modelâ€. The “model†folder contains the files needed to run the Simulink simulator. Make sure this folder is the current workspace directory.
+2. Open “modelParameters.m†in MATLAB and run the script. This will create/update parameters in the MATLAB workspace which are used by the simulator. At this point you should also check that the contents of the “model†folder are displayed in the “Current Folder†window in MATLAB.
+3. Open “Quadcopter_Model.slxâ€
+4. To view the 3D simulator, navigate within the model by clicking on the following blocks: Sensors -> 3D Graphical Simulation -> VR Sink
+5. Press “Run†in Simulink
+
+
+**Changing Setpoints**
+1. To change the simulation setpoints, return to the top level of the simulink model and then enter the “Setpoints†block.
+2. The default version of the simulator has five step functions which individually instruct the quad to move 1 unit in the x-direction, 1 unit in the y-direction, 1 unit in the z-direction, turn clockwise by 1 unit along the yaw angle, and then return to its starting values. Each step function can be thought of as a setpoint.
+3. Open a step function block by double clicking on it. Altering the step time will change when the quad begins to move towards a setpoint. Initial and final value have the format [x-position, y-position, z-position, yaw-angle], and any alterations to these fields will change where the quad starts and where it goes to respectively.
+4. Setpoints can be added or removed by adding or removing step functions from the Simulink model diagram.
+
+ *Note:
+ For this model, negative z values correspond to a position above the starting point [0,0,0,0] and positive z values correspond to a position beneath the starting point. (Example: If the quad is instructed to move from [0,0,-2,0] to [0,0,-1,0], it will be moving from a height of 2 units above the starting point down to a height of 1 unit above the starting point.) This means we will usually only work with negative z-values since our starting point is usually the ground and we cannot fly beneath it :)*
+
+
+**Changing Control Models**
+1. To select which controller is used to simulate quad flight, navigate to the top level of the Simulink model and toggle the controller switch to either LQR or PID
+
+
+
+
+## Additional Documents
[Measuring Motor Resistance](documentation/MeasuringMotorResistance.pdf)
[Simulink Model](documentation/SimulinkModel.md)
\ No newline at end of file
diff --git a/groundStation/Makefile b/groundStation/Makefile
index 2ca5036b56e0fed2b3a9cb4de318b766139275d8..620bbcefd1a2f32773a283dfad29e9b3e2fd308a 100644
--- a/groundStation/Makefile
+++ b/groundStation/Makefile
@@ -7,7 +7,7 @@ CFLAGS= -Wall -pedantic -Wextra -std=gnu99 -g -Wno-unused-parameter -Wno-unused-
CXXFLAGS= -Wall -pedantic -Wextra -Wno-reorder -Wno-unused-variable -std=c++0x -g
INCLUDES = $(foreach dir, $(INCDIR), -I$(dir))
INCDIR= src/vrpn src/vrpn/quat src/vrpn/build $(BESRCDIR) $(CLISRCDIR) $(FESRCDIR) $(MASRCDIR) ../quad/inc
-LIBS= -lpthread -lbluetooth -lvrpn -lquat -Lsrc/vrpn/build -Lsrc/vrpn/build/quat -L../quad/lib -lquad_app -lcommands -lgraph_blocks -lcomputation_graph -lm
+LIBS= -lpthread -lvrpn -lquat -Lsrc/vrpn/build -Lsrc/vrpn/build/quat -L../quad/lib -lquad_app -lcommands -lgraph_blocks -lcomputation_graph -lm
OBJDIR=obj
# Manual Assist Specific Variables
@@ -82,7 +82,7 @@ vrpn/build:
cd src/vrpn/build && cmake .. && make
GroundStation:
- cd gui/MicroCART && qmake
+ cd gui/MicroCART && qmake-qt5
cd gui/MicroCART && make
ln -s gui/MicroCART/MicroCART GroundStation
diff --git a/groundStation/gui/MicroCART/.qmake.stash b/groundStation/gui/MicroCART/.qmake.stash
new file mode 100644
index 0000000000000000000000000000000000000000..6ea5b2126ee311f11a3da7fd84e4ec97bd9b1ab6
--- /dev/null
+++ b/groundStation/gui/MicroCART/.qmake.stash
@@ -0,0 +1,22 @@
+QMAKE_CXX.INCDIRS = \
+ /usr/include/c++/4.8.5 \
+ /usr/include/c++/4.8.5/x86_64-redhat-linux \
+ /usr/include/c++/4.8.5/backward \
+ /usr/lib/gcc/x86_64-redhat-linux/4.8.5/include \
+ /usr/local/include \
+ /usr/include
+QMAKE_CXX.LIBDIRS = \
+ /usr/lib/gcc/x86_64-redhat-linux/4.8.5 \
+ /usr/lib64 \
+ /lib64 \
+ /usr/lib \
+ /lib
+QMAKE_CXX.QT_COMPILER_STDCXX = 199711L
+QMAKE_CXX.QMAKE_GCC_MAJOR_VERSION = 4
+QMAKE_CXX.QMAKE_GCC_MINOR_VERSION = 8
+QMAKE_CXX.QMAKE_GCC_PATCH_VERSION = 5
+QMAKE_CXX.COMPILER_MACROS = \
+ QT_COMPILER_STDCXX \
+ QMAKE_GCC_MAJOR_VERSION \
+ QMAKE_GCC_MINOR_VERSION \
+ QMAKE_GCC_PATCH_VERSION
diff --git a/groundStation/gui/MicroCART/MicroCART.pro b/groundStation/gui/MicroCART/MicroCART.pro
index f5bb8ea5069cd4d1a8c4c451e005f03e383ac737..811433dab205a3e207bfc5af4ceed1f71f5d38a4 100644
--- a/groundStation/gui/MicroCART/MicroCART.pro
+++ b/groundStation/gui/MicroCART/MicroCART.pro
@@ -1,58 +1,59 @@
-#-------------------------------------------------
-#
-# Project created by QtCreator 2017-02-23T15:03:45
-#
-#-------------------------------------------------
-
-QT += core gui
-
-greaterThan(QT_MAJOR_VERSION, 4): QT += widgets
-
-TARGET = MicroCART
-TEMPLATE = app
-
-LIBS += ../../frontend.a
-INCLUDEPATH += ../../src/frontend/
-
-SOURCES += main.cpp\
- mainwindow.cpp \
- trackerworker.cpp \
- controlworker.cpp \
- quaditem.cpp \
- slotprocess.cpp \
- qFlightInstruments.cpp
-
-HEADERS += mainwindow.h \
- trackerworker.h \
- controlworker.h \
- quaditem.h \
- slotprocess.h \
- qFlightInstruments.h
-
-FORMS += mainwindow.ui
-
-INCLUDEPATH += $$PWD/../../../quad/inc
-DEPENDPATH += $$PWD/../../../quad/inc
-
-win32:CONFIG(release, debug|release): LIBS += -L$$PWD/../../../quad/lib/release/ -lgraph_blocks
-else:win32:CONFIG(debug, debug|release): LIBS += -L$$PWD/../../../quad/lib/debug/ -lgraph_blocks
-else:unix: LIBS += -L$$PWD/../../../quad/lib/ -lgraph_blocks
-
-win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/libgraph_blocks.a
-else:win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/libgraph_blocks.a
-else:win32:!win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/graph_blocks.lib
-else:win32:!win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/graph_blocks.lib
-else:unix: PRE_TARGETDEPS += $$PWD/../../../quad/lib/libgraph_blocks.a
-
-win32:CONFIG(release, debug|release): LIBS += -L$$PWD/../../../quad/lib/release/ -lcomputation_graph
-else:win32:CONFIG(debug, debug|release): LIBS += -L$$PWD/../../../quad/lib/debug/ -lcomputation_graph
-else:unix: LIBS += -L$$PWD/../../../quad/lib/ -lcomputation_graph
-
-win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/libcomputation_graph.a
-else:win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/libcomputation_graph.a
-else:win32:!win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/computation_graph.lib
-else:win32:!win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/computation_graph.lib
-else:unix: PRE_TARGETDEPS += $$PWD/../../../quad/lib/libcomputation_graph.a
-
-RESOURCES += \
- resources.qrc
+#-------------------------------------------------
+#
+# Project created by QtCreator 2017-02-23T15:03:45
+#
+#-------------------------------------------------
+
+QT += core gui
+
+greaterThan(QT_MAJOR_VERSION, 4): QT += widgets
+
+TARGET = MicroCART
+TEMPLATE = app
+
+LIBS += ../../frontend.a
+INCLUDEPATH += ../../src/frontend/
+
+SOURCES += main.cpp\
+ mainwindow.cpp \
+ trackerworker.cpp \
+ controlworker.cpp \
+ quaditem.cpp \
+ slotprocess.cpp \
+ qFlightInstruments.cpp
+
+HEADERS += mainwindow.h \
+ trackerworker.h \
+ controlworker.h \
+ quaditem.h \
+ slotprocess.h \
+ graph_blocks.h \
+ qFlightInstruments.h
+
+FORMS += mainwindow.ui
+
+INCLUDEPATH += $$PWD/../../../quad/inc
+DEPENDPATH += $$PWD/../../../quad/inc
+
+win32:CONFIG(release, debug|release): LIBS += -L$$PWD/../../../quad/lib/release/ -lgraph_blocks
+else:win32:CONFIG(debug, debug|release): LIBS += -L$$PWD/../../../quad/lib/debug/ -lgraph_blocks
+else:unix: LIBS += -L$$PWD/../../../quad/lib/ -lgraph_blocks
+
+win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/libgraph_blocks.a
+else:win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/libgraph_blocks.a
+else:win32:!win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/graph_blocks.lib
+else:win32:!win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/graph_blocks.lib
+else:unix: PRE_TARGETDEPS += $$PWD/../../../quad/lib/libgraph_blocks.a
+
+win32:CONFIG(release, debug|release): LIBS += -L$$PWD/../../../quad/lib/release/ -lcomputation_graph
+else:win32:CONFIG(debug, debug|release): LIBS += -L$$PWD/../../../quad/lib/debug/ -lcomputation_graph
+else:unix: LIBS += -L$$PWD/../../../quad/lib/ -lcomputation_graph
+
+win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/libcomputation_graph.a
+else:win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/libcomputation_graph.a
+else:win32:!win32-g++:CONFIG(release, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/release/computation_graph.lib
+else:win32:!win32-g++:CONFIG(debug, debug|release): PRE_TARGETDEPS += $$PWD/../../../quad/lib/debug/computation_graph.lib
+else:unix: PRE_TARGETDEPS += $$PWD/../../../quad/lib/libcomputation_graph.a
+
+RESOURCES += \
+ resources.qrc
diff --git a/groundStation/gui/MicroCART/mainwindow.cpp b/groundStation/gui/MicroCART/mainwindow.cpp
index 28846792e8ea260db53deaa2a83f160fd1fc7287..ca0d2ee6f8bbedbe5d8950b8b110873477cdecd7 100644
--- a/groundStation/gui/MicroCART/mainwindow.cpp
+++ b/groundStation/gui/MicroCART/mainwindow.cpp
@@ -1,595 +1,612 @@
-#include "mainwindow.h"
-#include "ui_mainwindow.h"
-
-#include <QFileDialog>
-#include <QThread>
-#include <QTimer>
-#include <QRegExp>
-#include <QProcessEnvironment>
-#include <QPixmap>
-#include <QProcess>
-
-#include "trackerworker.h"
-#include "controlworker.h"
-#include "graph_blocks.h"
-#include "quaditem.h"
-#include "slotprocess.h"
-#include "qFlightInstruments.h"
-
-#include <iostream>
-MainWindow::MainWindow(QWidget *parent) :
- QMainWindow(parent),
- ui(new Ui::MainWindow),
- setpointList(new QStandardItemModel(this)),
- nextSpTimer(new QTimer(this)),
- sp_x(0.0f),
- sp_y(0.0f),
- sp_z(0.0f),
- trackerTimer(new QTimer(this)),
- workerStartTimer(new QTimer(this)),
- backendProcess(new QProcess(this)),
- connectedWorkers(0)
-{
- ui->setupUi(this);
-
- QGraphicsScene *posScene = new QGraphicsScene(this);
- ui->posView->setScene(posScene);
- QuadItem * posIndicator = new QuadItem();
- posScene->addItem(posIndicator);
-
- QGraphicsScene *attScene = new QGraphicsScene(this);
- ui->attView->setScene(attScene);
- QADI * attIndicator = new QADI();
- attScene->addWidget(attIndicator);
-
-
- workerStartTimer->setSingleShot(true);
-
- /* Create a thread for workers */
- QThread* workerThread = new QThread(this);
-
- /* Create a worker to update the tracker */
- TrackerWorker * trackerWorker = new TrackerWorker();
-
- /* Move it to the worker thread. This means that slots of this worker
- * will run in the worker thread, and not block the UI */
- trackerWorker->moveToThread(workerThread);
-
- /* Connect tracker worker */
- connect(trackerWorker, SIGNAL (finished(float, float, float, float, float, float)),
- this, SLOT (updateTracker(float, float, float, float, float, float)));
-
- connect(trackerWorker, SIGNAL (finished(float, float, float, float, float, float)),
- posIndicator, SLOT(updatePos(float,float,float,float,float,float)));
-
- connect(trackerWorker, SIGNAL (finished(float, float, float, float, float, float)),
- attIndicator, SLOT(updateAttitude(float, float, float, float, float, float)));
-
- backendProcess->setProcessChannelMode(QProcess::MergedChannels);
-
- /* Create another worker for the control graph */
- QThread * cwThread = new QThread(this);
- ControlWorker * controlWorker = new ControlWorker();
- controlWorker->moveToThread(cwThread);
-
- /* Connect signals from control worker */
- connect(controlWorker, SIGNAL (gotNodes(QStringList)), this, SLOT (newNodes(QStringList)));
- connect(controlWorker, SIGNAL (gotParams(QStringList)), this, SLOT (newParams(QStringList)));
- connect(controlWorker, SIGNAL (gotParamValue(QString, QString, float)), this, SLOT (newParamValue(QString, QString, float)));
- connect(controlWorker, SIGNAL (gotNodeOutput(QString, float)), this, SLOT (newNodeOutput(QString, float)));
- connect(controlWorker, SIGNAL (gotConstantBlocks(QStringList)), this, SLOT (newConstantBlocks(QStringList)));
- connect(controlWorker, SIGNAL (graphRendered(QString)), this, SLOT (newControlGraph(QString)));
- connect(controlWorker, SIGNAL (paramSet(QString, QString)), controlWorker, SLOT (getParamValue(QString, QString)));
-
- /* Signals to control worker */
- connect(ui->pbControlRefresh, SIGNAL (clicked()), controlWorker, SLOT (getNodes()));
- connect(ui->nodeSelect, SIGNAL (currentIndexChanged(QString)), controlWorker, SLOT (getParams(QString)));
- connect(this, SIGNAL (getParamValue(QString, QString)), controlWorker, SLOT (getParamValue(QString, QString)));
- connect(this, SIGNAL (setParamValue(QString, QString, float)), controlWorker, SLOT (setParamValue(QString, QString, float)));
- connect(this, SIGNAL (getNodeOutput(QString)), controlWorker, SLOT (getNodeOutput(QString)));
-
- /* Connect and disconnect from backend when signals emitted */
- connect(workerStartTimer, SIGNAL (timeout()), trackerWorker, SLOT (connectBackend()));
- connect(workerStartTimer, SIGNAL (timeout()), controlWorker, SLOT (connectBackend()));
- connect(this, SIGNAL (connectWorkers()), trackerWorker, SLOT (connectBackend()));
- connect(this, SIGNAL (connectWorkers()), controlWorker, SLOT (connectBackend()));
- connect(this, SIGNAL (disconnectWorkers()), trackerWorker, SLOT (disconnectBackend()));
- connect(this, SIGNAL (disconnectWorkers()), controlWorker, SLOT (disconnectBackend()));
-
- connect(backendProcess, SIGNAL (started()), this, SLOT (backendStarted()));
- connect(backendProcess, SIGNAL (errorOccurred(QProcess::ProcessError)), this, SLOT (backendError(QProcess::ProcessError)));
- connect(backendProcess, SIGNAL (finished(int, QProcess::ExitStatus)), this, SLOT (backendFinished(int, QProcess::ExitStatus)));
- connect(backendProcess, SIGNAL (readyReadStandardOutput()), this, SLOT (backendRead()));
- connect(backendProcess, SIGNAL (readyReadStandardError()), this, SLOT (backendRead()));
-
- connect(controlWorker, SIGNAL (connected()), this, SLOT (workerConnected()));
- connect(controlWorker, SIGNAL (disconnected()), this, SLOT (workerDisconnected()));
-
- connect(trackerWorker, SIGNAL (connected()), this, SLOT (workerConnected()));
- connect(trackerWorker, SIGNAL (disconnected()), this, SLOT (workerDisconnected()));
-
- /* Connect refresh button and refresh timer to tracker worker */
- connect(trackerTimer, SIGNAL(timeout()), this, SLOT(updatePosAtt()));
- connect(ui->pbRefresh, SIGNAL (clicked()), this, SLOT (updatePosAtt()));
-
- connect(this, SIGNAL(getPosAttFromBackend()), trackerWorker, SLOT(process()));
-
- /* Timer used for next setpoint */
- nextSpTimer->setSingleShot(true);
- connect(nextSpTimer, SIGNAL (timeout()), this, SLOT (on_pbNextSetpoint_clicked()));
-
- /* Start the things */
- trackerTimer->start(100);
- workerThread->start();
- cwThread->start();
-
- /* Connect the setpointlist to the model */
- ui->setpointList->setModel(setpointList);
-
- /* Connect various things that can result in sending setpoints */
- connect(ui->pbSendSetpoint, SIGNAL (clicked()), this, SLOT (sendSetpoints()));
- connect(ui->setpointList, SIGNAL (doubleClicked(QModelIndex)), this, SLOT (sendSelectedSetpoint()));
-
- /* Populate scripts list */
- QDir scriptsDir("scripts/");
- QStringList scripts = scriptsDir.entryList();
- for (int i = 0; i < scripts.size(); i++) {
- QAction * action = ui->menuScripts->addAction(scripts[i]);
- SlotProcess * scriptProcess = new SlotProcess(action);
- scriptProcess->setProgram(scriptsDir.filePath(scripts[i]));
- connect(action, SIGNAL (triggered()), scriptProcess, SLOT (startProcess()));
- }
-}
-
-MainWindow::~MainWindow()
-{
- delete ui;
-}
-
-void MainWindow::updatePosAtt()
-{
- if (ui->posattSrcVrpn->isChecked()) {
- emit(getPosAttFromBackend());
- } else if (ui->posattSrcQuad->isChecked()) {
- emit(getNodeOutput(ui->xPositionSelect->currentText()));
- emit(getNodeOutput(ui->yPositionSelect->currentText()));
- emit(getNodeOutput(ui->zPositionSelect->currentText()));
- emit(getNodeOutput(ui->pAttitudeSelect->currentText()));
- emit(getNodeOutput(ui->rAttitudeSelect->currentText()));
- emit(getNodeOutput(ui->yAttitudeSelect->currentText()));
- }
-}
-
-void MainWindow::updateTracker(float x, float y, float z, float p, float r, float yaw)
-{
- ui->xActual->setText(QString::number(x));
- ui->yActual->setText(QString::number(y));
- ui->zActual->setText(QString::number(z));
- ui->pitchActual->setText(QString::number(p));
- ui->rollActual->setText(QString::number(r));
- ui->yawActual->setText(QString::number(yaw));
-
- float dist = sqrt(pow(x - sp_x, 2.0) + pow(y - sp_y, 2.0) + pow(z - sp_z, 2.0));
-
- ui->dist->setText(QString::number(dist));
-
- if (!nextSpTimer->isActive() && ui->autonavEnabled->isChecked() &&
- (dist < ui->autonavThreshold->text().toFloat())) {
- nextSpTimer->start(ui->autonavDelay->text().toInt());
- }
-}
-
-void MainWindow::on_pbStart_clicked()
-{
- backendProcess->setProgram(ui->backendPath->text());
-
- backendProcess->start();
-}
-
-void MainWindow::backendStarted()
-{
- ui->pbStart->setEnabled(false);
- ui->pbStop->setEnabled(true);
- workerStartTimer->start(750);
-}
-
-void MainWindow::backendError(QProcess::ProcessError error)
-{
- ui->vConsole->append(backendProcess->errorString());
-}
-
-void MainWindow::backendRead()
-{
- ui->vConsole->append(backendProcess->readAll());
-}
-
-void MainWindow::workerConnected()
-{
- connectedWorkers++;
- if (connectedWorkers == 2) {
- ui->pbStart->setEnabled(false);
- ui->pbConnect->setEnabled(false);
- ui->pbStop->setEnabled(true);
- }
-}
-
-void MainWindow::workerDisconnected()
-{
- connectedWorkers--;
- if (( connectedWorkers == 0) && (backendProcess->state() == QProcess::Running)) {
- backendProcess->terminate();
- } else if (connectedWorkers == 0) {
- ui->pbStart->setEnabled(true);
- ui->pbConnect->setEnabled(true);
- ui->pbStop->setEnabled(false);
- }
-}
-
-void MainWindow::backendFinished(int exitCode, QProcess::ExitStatus exitStatus)
-{
- ui->pbStart->setEnabled(true);
- ui->pbConnect->setEnabled(true);
- ui->pbStop->setEnabled(false);
-}
-
-void MainWindow::on_pbConnect_clicked()
-{
- emit(connectWorkers());
-}
-
-void MainWindow::on_pbStop_clicked()
-{
- emit(disconnectWorkers());
-}
-
-void MainWindow::on_chooseBackend_clicked()
-{
- QString backendPath = QFileDialog::getOpenFileName(this,
- tr("Path to Backend Executable"));
- ui->backendPath->setText(backendPath);
-}
-
-
-void MainWindow::newNodes(QStringList blocks)
-{
- QComboBox * select = ui->nodeSelect;
- select->clear();
- select->addItems(blocks);
-
- this->ui->noGraphWarning1->setVisible(false);
- this->ui->noGraphWarning2->setVisible(false);
- this->ui->noGraphWarningLine->setVisible(false);
-}
-
-void MainWindow::newConstantBlocks(QStringList blocks)
-{
- ui->xSetpointSelect->clear();
- ui->xSetpointSelect->addItems(blocks);
-
- ui->ySetpointSelect->clear();
- ui->ySetpointSelect->addItems(blocks);
-
- ui->zSetpointSelect->clear();
- ui->zSetpointSelect->addItems(blocks);
-
- ui->yawSetpointSelect->clear();
- ui->yawSetpointSelect->addItems(blocks);
-
- ui->xPositionSelect->clear();
- ui->xPositionSelect->addItems(blocks);
-
- ui->yPositionSelect->clear();
- ui->yPositionSelect->addItems(blocks);
-
- ui->zPositionSelect->clear();
- ui->zPositionSelect->addItems(blocks);
-
- ui->pAttitudeSelect->clear();
- ui->pAttitudeSelect->addItems(blocks);
-
- ui->rAttitudeSelect->clear();
- ui->rAttitudeSelect->addItems(blocks);
-
- ui->yAttitudeSelect->clear();
- ui->yAttitudeSelect->addItems(blocks);
-
- for (ssize_t i = 0; i < blocks.size(); i++) {
- if (blocks[i].contains("setpoint", Qt::CaseInsensitive) || blocks[i].contains("sp", Qt::CaseInsensitive)) {
- if (blocks[i].contains("x ", Qt::CaseInsensitive)) {
- ui->xSetpointSelect->setCurrentIndex(i);
- }
- if (blocks[i].contains("y ", Qt::CaseInsensitive)) {
- ui->ySetpointSelect->setCurrentIndex(i);
- }
- if (blocks[i].contains("z ", Qt::CaseInsensitive) || blocks[i].contains("alt", Qt::CaseInsensitive)) {
- ui->zSetpointSelect->setCurrentIndex(i);
- }
- if (blocks[i].contains("yaw", Qt::CaseInsensitive) || blocks[i].contains("alt", Qt::CaseInsensitive)) {
- ui->yawSetpointSelect->setCurrentIndex(i);
- }
- }
-
- if (blocks[i] == QString("Pitch")) {
- ui->pAttitudeSelect->setCurrentIndex(i);
- }
-
- if (blocks[i] == QString("Roll")) {
- ui->rAttitudeSelect->setCurrentIndex(i);
- }
-
- if (blocks[i] == QString("Yaw")) {
- ui->yAttitudeSelect->setCurrentIndex(i);
- }
-
- if (blocks[i] == QString("Lidar")) {
- ui->zPositionSelect->setCurrentIndex(i);
- }
-
- if (blocks[i] == QString("OF X Trim Add")) {
- ui->xPositionSelect->setCurrentIndex(i);
- }
-
- if (blocks[i] == QString("OF Y Trim Add")) {
- ui->yPositionSelect->setCurrentIndex(i);
- }
- }
-}
-
-void MainWindow::newNodeOutput(QString node, float val)
-{
- /* Update the nav page if quad is set as the source for pos/att */
- if (node == ui->xPositionSelect->currentText()) {
- ui->xActual->setText(QString::number(val));
- } else if (node == ui->yPositionSelect->currentText()) {
- ui->yActual->setText(QString::number(val));
- } else if (node == ui->zPositionSelect->currentText()) {
- ui->zActual->setText(QString::number(val));
- } else if (node == ui->pAttitudeSelect->currentText()) {
- ui->pitchActual->setText(QString::number(val));
- } else if (node == ui->rAttitudeSelect->currentText()) {
- ui->rollActual->setText(QString::number(val));
- } else if (node == ui->yAttitudeSelect->currentText()) {
- ui->yawActual->setText(QString::number(val));
- }
-}
-
-void MainWindow::newParams(QStringList params)
-{
- QComboBox * select = ui->paramSelect;
- select->clear();
- select->addItems(params);
-}
-
-void MainWindow::newParamValue(QString node, QString param, float val)
-{
- ui->paramValue->setText(QString::number(val));
-
- /* Update the nav page setpoints if it's a setpoint paramvalue */
- if (node == ui->xSetpointSelect->currentText()) {
- ui->xSetpoint->setText(QString::number(val));
- } else if (node == ui->ySetpointSelect->currentText()) {
- ui->ySetpoint->setText(QString::number(val));
- } else if (node == ui->zSetpointSelect->currentText()) {
- ui->zSetpoint->setText(QString::number(val));
- }
-}
-
-void MainWindow::on_paramSelect_currentIndexChanged(const QString &arg1)
-{
- emit(getParamValue(ui->nodeSelect->currentText(), arg1));
-}
-
-void MainWindow::on_paramValue_returnPressed()
-{
- emit (setParamValue(ui->nodeSelect->currentText(),
- ui->paramSelect->currentText(),
- ui->paramValue->text().toFloat()));
-}
-
-void MainWindow::sendSetpoints()
-{
- if (ui->sendX->isChecked()) {
- sp_x = ui->xSetpoint->text().toFloat();
- emit (setParamValue(ui->xSetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0], sp_x));
- }
-
- if (ui->sendY->isChecked()) {
- sp_y = ui->ySetpoint->text().toFloat();
- emit (setParamValue(ui->ySetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0], sp_y));
- }
-
- if (ui->sendZ->isChecked()) {
- sp_z = ui->zSetpoint->text().toFloat();
- emit (setParamValue(ui->zSetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0], sp_z));
- }
-
- if (ui->sendYaw->isChecked()) {
- emit (setParamValue(ui->yawSetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0],
- ui->yawSetpoint->text().toFloat()));
- }
-}
-
-void MainWindow::on_pbAppendSetpoint_clicked()
-{
- QString str("[" + ui->xSetpoint->text() + ", "+
- ui->ySetpoint->text() + ", " +
- ui->zSetpoint->text() + ", " +
- ui->yawSetpoint->text() + "]");
-
- setpointList->appendRow(new QStandardItem(str));
-}
-
-void MainWindow::on_pbNextSetpoint_clicked()
-{
- QListView * listView = ui->setpointList;
- if (listView->currentIndex().isValid() && setpointList->index(listView->currentIndex().row() + 1, 0).isValid()) {
- listView->setCurrentIndex(setpointList->index(listView->currentIndex().row() + 1, 0));
- } else {
- listView->setCurrentIndex(setpointList->index(0, 0));
- }
- sendSelectedSetpoint();
-}
-
-
-void MainWindow::sendSelectedSetpoint()
-{
- if (ui->setpointList->currentIndex().isValid()) {
- QRegExp regex("\\[(.*), (.*), (.*), (.*)\\]");
- int row = ui->setpointList->currentIndex().row();
-
- regex.indexIn(setpointList->item(row)->text());
- ui->xSetpoint->setText(regex.cap(1));
- ui->ySetpoint->setText(regex.cap(2));
- ui->zSetpoint->setText(regex.cap(3));
- ui->yawSetpoint->setText(regex.cap(4));
-
- sendSetpoints();
- }
-}
-
-void MainWindow::on_pbActualToSetpoint_clicked()
-{
- ui->xSetpoint->setText(ui->xActual->text());
- ui->ySetpoint->setText(ui->yActual->text());
- ui->zSetpoint->setText(ui->zActual->text());
- ui->yawSetpoint->setText(ui->yawActual->text());
-}
-
-void MainWindow::on_pbDeleteSetpoint_clicked()
-{
- if (ui->setpointList->currentIndex().isValid()) {
- setpointList->removeRow(ui->setpointList->currentIndex().row());
- }
-}
-
-void MainWindow::newControlGraph(QString graph)
-{
- ui->graphImage->setPixmap(QPixmap(graph));
-}
-
-void MainWindow::on_pbActualToWaypoint_clicked()
-{
- QString str("[" + ui->xActual->text() + ", "+
- ui->yActual->text() + ", " +
- ui->zActual->text() + ", " +
- ui->yawActual->text() + "]");
-
- setpointList->appendRow(new QStandardItem(str));
-}
-
-void MainWindow::on_pbMoveUp_clicked()
-{
- if (ui->setpointList->currentIndex().isValid()) {
- int current = ui->setpointList->currentIndex().row();
- if (current > 0) {
- setpointList->insertRow(current - 1, setpointList->takeItem(current));
- setpointList->removeRow(current + 1);
- }
- }
-}
-
-void MainWindow::on_pbMoveDown_clicked()
-{
- if (ui->setpointList->currentIndex().isValid()) {
- int current = ui->setpointList->currentIndex().row();
- if (current < (setpointList->rowCount() - 1)) {
- setpointList->insertRow(current + 2, setpointList->takeItem(current));
- setpointList->removeRow(current);
- }
- }
-}
-
-void MainWindow::on_pbInsertSetpoint_clicked()
-{
- int current = 0;
- if (ui->setpointList->currentIndex().isValid()) {
- current = ui->setpointList->currentIndex().row();
- }
-
- QString str("[" + ui->xSetpoint->text() + ", "+
- ui->ySetpoint->text() + ", " +
- ui->zSetpoint->text() + ", " +
- ui->yawSetpoint->text() + "]");
- setpointList->insertRow(current, new QStandardItem(str));
-}
-
-void MainWindow::on_pbSaveWaypoints_clicked()
-{
- QString filter = "Waypoints (*.wpt)";
- QString savePath = QFileDialog::getSaveFileName(this, tr("Save waypoint"), QString(), filter, &filter, QFileDialog::DontUseNativeDialog);
-
- if (!savePath.isEmpty()) {
- QFileInfo finfo(savePath);
- if (finfo.suffix().isNull())
- savePath.append(".wpt");
- QFile f(savePath);
- f.open(QIODevice::WriteOnly | QIODevice::Text);
- for (int i= 0; i < setpointList->rowCount(); i++) {
- f.write(setpointList->item(i)->text().toStdString().c_str());
- f.write("\n");
- }
- f.close();
- }
-}
-
-void MainWindow::on_pbLoadWaypoints_clicked()
-{
-
- QString filter = "Waypoints (*.wpt)";
- QString openPath = QFileDialog::getOpenFileName(this, tr("Open Waypoint File"), QString(),filter);
-
- if (!openPath.isEmpty()) {
- QFile f(openPath);
- f.open(QIODevice::ReadOnly | QIODevice::Text);
-
- setpointList->clear();
- while (!f.atEnd()) {
- QString line = f.readLine();
- line.chop(1);
- setpointList->appendRow(new QStandardItem(line));
- }
- f.close();
- }
-}
-
-void MainWindow::on_xSetpoint_returnPressed()
-{
- sp_x = ui->xSetpoint->text().toFloat();
- emit (setParamValue(ui->xSetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0], sp_x));
-}
-
-void MainWindow::on_ySetpoint_returnPressed()
-{
- sp_y = ui->ySetpoint->text().toFloat();
- emit (setParamValue(ui->ySetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0], sp_y));
-}
-
-void MainWindow::on_zSetpoint_returnPressed()
-{
- sp_z = ui->zSetpoint->text().toFloat();
- emit (setParamValue(ui->zSetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0], sp_z));
-}
-
-void MainWindow::on_yawSetpoint_returnPressed()
-{
- emit (setParamValue(ui->yawSetpointSelect->currentText(),
- blockDefs[BLOCK_CONSTANT]->param_names[0],
- ui->yawSetpoint->text().toFloat()));
-}
-
-void MainWindow::on_posattSrcVrpn_clicked()
-{
- trackerTimer->setInterval(100);
-}
-
-void MainWindow::on_posattSrcQuad_clicked()
-{
- trackerTimer->setInterval(750);
-}
+#include "mainwindow.h"
+#include "ui_mainwindow.h"
+
+#include <QFileDialog>
+#include <QDesktopServices>
+#include <QMessageBox>
+#include <QThread>
+#include <QTimer>
+#include <QRegExp>
+#include <QProcessEnvironment>
+#include <QPixmap>
+#include <QProcess>
+
+#include "trackerworker.h"
+#include "controlworker.h"
+#include "quaditem.h"
+#include "slotprocess.h"
+#include "qFlightInstruments.h"
+#include "graph_blocks.h"
+
+#include <iostream>
+MainWindow::MainWindow(QWidget *parent) :
+ QMainWindow(parent),
+ ui(new Ui::MainWindow),
+ setpointList(new QStandardItemModel(this)),
+ nextSpTimer(new QTimer(this)),
+ sp_x(0.0f),
+ sp_y(0.0f),
+ sp_z(0.0f),
+ trackerTimer(new QTimer(this)),
+ workerStartTimer(new QTimer(this)),
+ backendProcess(new QProcess(this)),
+ matlabProcess(new QProcess(this)),
+ connectedWorkers(0)
+{
+ ui->setupUi(this);
+
+ QGraphicsScene *posScene = new QGraphicsScene(this);
+ ui->posView->setScene(posScene);
+ QuadItem * posIndicator = new QuadItem();
+ posScene->addItem(posIndicator);
+
+ QGraphicsScene *attScene = new QGraphicsScene(this);
+ ui->attView->setScene(attScene);
+ QADI * attIndicator = new QADI();
+ attScene->addWidget(attIndicator);
+
+
+ workerStartTimer->setSingleShot(true);
+
+ /* Create a thread for workers */
+ QThread* workerThread = new QThread(this);
+
+ /* Create a worker to update the tracker */
+ TrackerWorker * trackerWorker = new TrackerWorker();
+
+ /* Move it to the worker thread. This means that slots of this worker
+ * will run in the worker thread, and not block the UI */
+ trackerWorker->moveToThread(workerThread);
+
+ /* Connect tracker worker */
+ connect(trackerWorker, SIGNAL (finished(float, float, float, float, float, float)),
+ this, SLOT (updateTracker(float, float, float, float, float, float)));
+
+ connect(trackerWorker, SIGNAL (finished(float, float, float, float, float, float)),
+ posIndicator, SLOT(updatePos(float,float,float,float,float,float)));
+
+ connect(trackerWorker, SIGNAL (finished(float, float, float, float, float, float)),
+ attIndicator, SLOT(updateAttitude(float, float, float, float, float, float)));
+
+ backendProcess->setProcessChannelMode(QProcess::MergedChannels);
+
+ /* Create another worker for the control graph */
+ QThread * cwThread = new QThread(this);
+ ControlWorker * controlWorker = new ControlWorker();
+ controlWorker->moveToThread(cwThread);
+
+ /* Connect signals from control worker */
+ connect(controlWorker, SIGNAL (gotNodes(QStringList)), this, SLOT (newNodes(QStringList)));
+ connect(controlWorker, SIGNAL (gotParams(QStringList)), this, SLOT (newParams(QStringList)));
+ connect(controlWorker, SIGNAL (gotParamValue(QString, QString, float)), this, SLOT (newParamValue(QString, QString, float)));
+ connect(controlWorker, SIGNAL (gotNodeOutput(QString, float)), this, SLOT (newNodeOutput(QString, float)));
+ connect(controlWorker, SIGNAL (gotConstantBlocks(QStringList)), this, SLOT (newConstantBlocks(QStringList)));
+ connect(controlWorker, SIGNAL (graphRendered(QString)), this, SLOT (newControlGraph(QString)));
+ connect(controlWorker, SIGNAL (paramSet(QString, QString)), controlWorker, SLOT (getParamValue(QString, QString)));
+
+ /* Signals to control worker */
+ connect(ui->pbControlRefresh, SIGNAL (clicked()), controlWorker, SLOT (getNodes()));
+ connect(ui->nodeSelect, SIGNAL (currentIndexChanged(QString)), controlWorker, SLOT (getParams(QString)));
+ connect(this, SIGNAL (getParamValue(QString, QString)), controlWorker, SLOT (getParamValue(QString, QString)));
+ connect(this, SIGNAL (setParamValue(QString, QString, float)), controlWorker, SLOT (setParamValue(QString, QString, float)));
+ connect(this, SIGNAL (getNodeOutput(QString)), controlWorker, SLOT (getNodeOutput(QString)));
+
+ /* Connect and disconnect from backend when signals emitted */
+ connect(workerStartTimer, SIGNAL (timeout()), trackerWorker, SLOT (connectBackend()));
+ connect(workerStartTimer, SIGNAL (timeout()), controlWorker, SLOT (connectBackend()));
+ connect(this, SIGNAL (connectWorkers()), trackerWorker, SLOT (connectBackend()));
+ connect(this, SIGNAL (connectWorkers()), controlWorker, SLOT (connectBackend()));
+ connect(this, SIGNAL (disconnectWorkers()), trackerWorker, SLOT (disconnectBackend()));
+ connect(this, SIGNAL (disconnectWorkers()), controlWorker, SLOT (disconnectBackend()));
+
+ connect(backendProcess, SIGNAL (started()), this, SLOT (backendStarted()));
+ connect(backendProcess, SIGNAL (errorOccurred(QProcess::ProcessError)), this, SLOT (backendError(QProcess::ProcessError)));
+ connect(backendProcess, SIGNAL (finished(int, QProcess::ExitStatus)), this, SLOT (backendFinished(int, QProcess::ExitStatus)));
+ connect(backendProcess, SIGNAL (readyReadStandardOutput()), this, SLOT (backendRead()));
+ connect(backendProcess, SIGNAL (readyReadStandardError()), this, SLOT (backendRead()));
+
+ connect(controlWorker, SIGNAL (connected()), this, SLOT (workerConnected()));
+ connect(controlWorker, SIGNAL (disconnected()), this, SLOT (workerDisconnected()));
+
+ connect(trackerWorker, SIGNAL (connected()), this, SLOT (workerConnected()));
+ connect(trackerWorker, SIGNAL (disconnected()), this, SLOT (workerDisconnected()));
+
+ /* Connect refresh button and refresh timer to tracker worker */
+ connect(trackerTimer, SIGNAL(timeout()), this, SLOT(updatePosAtt()));
+ connect(ui->pbRefresh, SIGNAL (clicked()), this, SLOT (updatePosAtt()));
+
+ connect(this, SIGNAL(getPosAttFromBackend()), trackerWorker, SLOT(process()));
+
+ /* Timer used for next setpoint */
+ nextSpTimer->setSingleShot(true);
+ connect(nextSpTimer, SIGNAL (timeout()), this, SLOT (on_pbNextSetpoint_clicked()));
+
+ /* Start the things */
+ trackerTimer->start(100);
+ workerThread->start();
+ cwThread->start();
+ matlabProcess->start();
+
+ /* Connect the setpointlist to the model */
+ ui->setpointList->setModel(setpointList);
+
+ /* Connect various things that can result in sending setpoints */
+ connect(ui->pbSendSetpoint, SIGNAL (clicked()), this, SLOT (sendSetpoints()));
+ connect(ui->setpointList, SIGNAL (doubleClicked(QModelIndex)), this, SLOT (sendSelectedSetpoint()));
+
+ /* Populate scripts list */
+ QDir scriptsDir("scripts/");
+ QStringList scripts = scriptsDir.entryList();
+ for (int i = 0; i < scripts.size(); i++) {
+ QAction * action = ui->menuScripts->addAction(scripts[i]);
+ SlotProcess * scriptProcess = new SlotProcess(action);
+ scriptProcess->setProgram(scriptsDir.filePath(scripts[i]));
+ connect(action, SIGNAL (triggered()), scriptProcess, SLOT (startProcess()));
+ }
+
+}
+
+MainWindow::~MainWindow()
+{
+ delete ui;
+}
+
+void MainWindow::connectMatlab()
+{
+
+}
+
+void MainWindow::on_run_data_analysis_button_clicked()
+{
+ QProcess * matProcess = new QProcess(this);
+ QString matlab = "/usr/local/bin/matlab";
+ matProcess->start(matlab, QStringList() << QString("-nodesktop")<< QString("-nosplash")<<QString("-r")<<QString("run('../../../controls/DataAnalysisTool/Tool/GUI.m');"));
+}
+
+void MainWindow::updatePosAtt()
+{
+ if (ui->posattSrcVrpn->isChecked()) {
+ emit(getPosAttFromBackend());
+ } else if (ui->posattSrcQuad->isChecked()) {
+ emit(getNodeOutput(ui->xPositionSelect->currentText()));
+ emit(getNodeOutput(ui->yPositionSelect->currentText()));
+ emit(getNodeOutput(ui->zPositionSelect->currentText()));
+ emit(getNodeOutput(ui->pAttitudeSelect->currentText()));
+ emit(getNodeOutput(ui->rAttitudeSelect->currentText()));
+ emit(getNodeOutput(ui->yAttitudeSelect->currentText()));
+ }
+}
+
+void MainWindow::updateTracker(float x, float y, float z, float p, float r, float yaw)
+{
+ ui->xActual->setText(QString::number(x));
+ ui->yActual->setText(QString::number(y));
+ ui->zActual->setText(QString::number(z));
+ ui->pitchActual->setText(QString::number(p));
+ ui->rollActual->setText(QString::number(r));
+ ui->yawActual->setText(QString::number(yaw));
+
+ float dist = sqrt(pow(x - sp_x, 2.0) + pow(y - sp_y, 2.0) + pow(z - sp_z, 2.0));
+
+ ui->dist->setText(QString::number(dist));
+
+ if (!nextSpTimer->isActive() && ui->autonavEnabled->isChecked() &&
+ (dist < ui->autonavThreshold->text().toFloat())) {
+ nextSpTimer->start(ui->autonavDelay->text().toInt());
+ }
+}
+
+void MainWindow::on_pbStart_clicked()
+{
+ backendProcess->setProgram(ui->backendPath->text());
+
+ backendProcess->start();
+}
+
+void MainWindow::backendStarted()
+{
+ ui->pbStart->setEnabled(false);
+ ui->pbStop->setEnabled(true);
+ workerStartTimer->start(750);
+}
+
+void MainWindow::backendError(QProcess::ProcessError error)
+{
+ ui->vConsole->append(backendProcess->errorString());
+}
+
+void MainWindow::backendRead()
+{
+ ui->vConsole->append(backendProcess->readAll());
+}
+
+void MainWindow::workerConnected()
+{
+ connectedWorkers++;
+ if (connectedWorkers == 2) {
+ ui->pbStart->setEnabled(false);
+ ui->pbConnect->setEnabled(false);
+ ui->pbStop->setEnabled(true);
+ }
+}
+
+void MainWindow::workerDisconnected()
+{
+ connectedWorkers--;
+ if (( connectedWorkers == 0) && (backendProcess->state() == QProcess::Running)) {
+ backendProcess->terminate();
+ } else if (connectedWorkers == 0) {
+ ui->pbStart->setEnabled(true);
+ ui->pbConnect->setEnabled(true);
+ ui->pbStop->setEnabled(false);
+ }
+}
+
+void MainWindow::backendFinished(int exitCode, QProcess::ExitStatus exitStatus)
+{
+ ui->pbStart->setEnabled(true);
+ ui->pbConnect->setEnabled(true);
+ ui->pbStop->setEnabled(false);
+}
+
+void MainWindow::on_pbConnect_clicked()
+{
+ emit(connectWorkers());
+}
+
+void MainWindow::on_pbStop_clicked()
+{
+ emit(disconnectWorkers());
+}
+
+void MainWindow::on_chooseBackend_clicked()
+{
+ QString backendPath = QFileDialog::getOpenFileName(this,
+ tr("Path to Backend Executable"));
+ ui->backendPath->setText(backendPath);
+}
+
+
+void MainWindow::newNodes(QStringList blocks)
+{
+ QComboBox * select = ui->nodeSelect;
+ select->clear();
+ select->addItems(blocks);
+
+ this->ui->noGraphWarning1->setVisible(false);
+ this->ui->noGraphWarning2->setVisible(false);
+ this->ui->noGraphWarningLine->setVisible(false);
+}
+
+void MainWindow::newConstantBlocks(QStringList blocks)
+{
+ ui->xSetpointSelect->clear();
+ ui->xSetpointSelect->addItems(blocks);
+
+ ui->ySetpointSelect->clear();
+ ui->ySetpointSelect->addItems(blocks);
+
+ ui->zSetpointSelect->clear();
+ ui->zSetpointSelect->addItems(blocks);
+
+ ui->yawSetpointSelect->clear();
+ ui->yawSetpointSelect->addItems(blocks);
+
+ ui->xPositionSelect->clear();
+ ui->xPositionSelect->addItems(blocks);
+
+ ui->yPositionSelect->clear();
+ ui->yPositionSelect->addItems(blocks);
+
+ ui->zPositionSelect->clear();
+ ui->zPositionSelect->addItems(blocks);
+
+ ui->pAttitudeSelect->clear();
+ ui->pAttitudeSelect->addItems(blocks);
+
+ ui->rAttitudeSelect->clear();
+ ui->rAttitudeSelect->addItems(blocks);
+
+ ui->yAttitudeSelect->clear();
+ ui->yAttitudeSelect->addItems(blocks);
+
+ for (ssize_t i = 0; i < blocks.size(); i++) {
+ if (blocks[i].contains("setpoint", Qt::CaseInsensitive) || blocks[i].contains("sp", Qt::CaseInsensitive)) {
+ if (blocks[i].contains("x ", Qt::CaseInsensitive)) {
+ ui->xSetpointSelect->setCurrentIndex(i);
+ }
+ if (blocks[i].contains("y ", Qt::CaseInsensitive)) {
+ ui->ySetpointSelect->setCurrentIndex(i);
+ }
+ if (blocks[i].contains("z ", Qt::CaseInsensitive) || blocks[i].contains("alt", Qt::CaseInsensitive)) {
+ ui->zSetpointSelect->setCurrentIndex(i);
+ }
+ if (blocks[i].contains("yaw", Qt::CaseInsensitive) || blocks[i].contains("alt", Qt::CaseInsensitive)) {
+ ui->yawSetpointSelect->setCurrentIndex(i);
+ }
+ }
+
+ if (blocks[i] == QString("Pitch")) {
+ ui->pAttitudeSelect->setCurrentIndex(i);
+ }
+
+ if (blocks[i] == QString("Roll")) {
+ ui->rAttitudeSelect->setCurrentIndex(i);
+ }
+
+ if (blocks[i] == QString("Yaw")) {
+ ui->yAttitudeSelect->setCurrentIndex(i);
+ }
+
+ if (blocks[i] == QString("Lidar")) {
+ ui->zPositionSelect->setCurrentIndex(i);
+ }
+
+ if (blocks[i] == QString("OF X Trim Add")) {
+ ui->xPositionSelect->setCurrentIndex(i);
+ }
+
+ if (blocks[i] == QString("OF Y Trim Add")) {
+ ui->yPositionSelect->setCurrentIndex(i);
+ }
+ }
+}
+
+void MainWindow::newNodeOutput(QString node, float val)
+{
+ /* Update the nav page if quad is set as the source for pos/att */
+ if (node == ui->xPositionSelect->currentText()) {
+ ui->xActual->setText(QString::number(val));
+ } else if (node == ui->yPositionSelect->currentText()) {
+ ui->yActual->setText(QString::number(val));
+ } else if (node == ui->zPositionSelect->currentText()) {
+ ui->zActual->setText(QString::number(val));
+ } else if (node == ui->pAttitudeSelect->currentText()) {
+ ui->pitchActual->setText(QString::number(val));
+ } else if (node == ui->rAttitudeSelect->currentText()) {
+ ui->rollActual->setText(QString::number(val));
+ } else if (node == ui->yAttitudeSelect->currentText()) {
+ ui->yawActual->setText(QString::number(val));
+ }
+}
+
+void MainWindow::newParams(QStringList params)
+{
+ QComboBox * select = ui->paramSelect;
+ select->clear();
+ select->addItems(params);
+}
+
+void MainWindow::newParamValue(QString node, QString param, float val)
+{
+ ui->paramValue->setText(QString::number(val));
+
+ /* Update the nav page setpoints if it's a setpoint paramvalue */
+ if (node == ui->xSetpointSelect->currentText()) {
+ ui->xSetpoint->setText(QString::number(val));
+ } else if (node == ui->ySetpointSelect->currentText()) {
+ ui->ySetpoint->setText(QString::number(val));
+ } else if (node == ui->zSetpointSelect->currentText()) {
+ ui->zSetpoint->setText(QString::number(val));
+ }
+}
+
+void MainWindow::on_paramSelect_currentIndexChanged(const QString &arg1)
+{
+ emit(getParamValue(ui->nodeSelect->currentText(), arg1));
+}
+
+void MainWindow::on_paramValue_returnPressed()
+{
+ emit (setParamValue(ui->nodeSelect->currentText(),
+ ui->paramSelect->currentText(),
+ ui->paramValue->text().toFloat()));
+}
+
+void MainWindow::sendSetpoints()
+{
+ if (ui->sendX->isChecked()) {
+ sp_x = ui->xSetpoint->text().toFloat();
+ emit (setParamValue(ui->xSetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0], sp_x));
+ }
+
+ if (ui->sendY->isChecked()) {
+ sp_y = ui->ySetpoint->text().toFloat();
+ emit (setParamValue(ui->ySetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0], sp_y));
+ }
+
+ if (ui->sendZ->isChecked()) {
+ sp_z = ui->zSetpoint->text().toFloat();
+ emit (setParamValue(ui->zSetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0], sp_z));
+ }
+
+ if (ui->sendYaw->isChecked()) {
+ emit (setParamValue(ui->yawSetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0],
+ ui->yawSetpoint->text().toFloat()));
+ }
+}
+
+void MainWindow::on_pbAppendSetpoint_clicked()
+{
+ QString str("[" + ui->xSetpoint->text() + ", "+
+ ui->ySetpoint->text() + ", " +
+ ui->zSetpoint->text() + ", " +
+ ui->yawSetpoint->text() + "]");
+
+ setpointList->appendRow(new QStandardItem(str));
+}
+
+void MainWindow::on_pbNextSetpoint_clicked()
+{
+ QListView * listView = ui->setpointList;
+ if (listView->currentIndex().isValid() && setpointList->index(listView->currentIndex().row() + 1, 0).isValid()) {
+ listView->setCurrentIndex(setpointList->index(listView->currentIndex().row() + 1, 0));
+ } else {
+ listView->setCurrentIndex(setpointList->index(0, 0));
+ }
+ sendSelectedSetpoint();
+}
+
+
+void MainWindow::sendSelectedSetpoint()
+{
+ if (ui->setpointList->currentIndex().isValid()) {
+ QRegExp regex("\\[(.*), (.*), (.*), (.*)\\]");
+ int row = ui->setpointList->currentIndex().row();
+
+ regex.indexIn(setpointList->item(row)->text());
+ ui->xSetpoint->setText(regex.cap(1));
+ ui->ySetpoint->setText(regex.cap(2));
+ ui->zSetpoint->setText(regex.cap(3));
+ ui->yawSetpoint->setText(regex.cap(4));
+
+ sendSetpoints();
+ }
+}
+
+void MainWindow::on_pbActualToSetpoint_clicked()
+{
+ ui->xSetpoint->setText(ui->xActual->text());
+ ui->ySetpoint->setText(ui->yActual->text());
+ ui->zSetpoint->setText(ui->zActual->text());
+ ui->yawSetpoint->setText(ui->yawActual->text());
+}
+
+void MainWindow::on_pbDeleteSetpoint_clicked()
+{
+ if (ui->setpointList->currentIndex().isValid()) {
+ setpointList->removeRow(ui->setpointList->currentIndex().row());
+ }
+}
+
+void MainWindow::newControlGraph(QString graph)
+{
+ ui->graphImage->setPixmap(QPixmap(graph));
+}
+
+void MainWindow::on_pbActualToWaypoint_clicked()
+{
+ QString str("[" + ui->xActual->text() + ", "+
+ ui->yActual->text() + ", " +
+ ui->zActual->text() + ", " +
+ ui->yawActual->text() + "]");
+
+ setpointList->appendRow(new QStandardItem(str));
+}
+
+void MainWindow::on_pbMoveUp_clicked()
+{
+ if (ui->setpointList->currentIndex().isValid()) {
+ int current = ui->setpointList->currentIndex().row();
+ if (current > 0) {
+ setpointList->insertRow(current - 1, setpointList->takeItem(current));
+ setpointList->removeRow(current + 1);
+ }
+ }
+}
+
+void MainWindow::on_pbMoveDown_clicked()
+{
+ if (ui->setpointList->currentIndex().isValid()) {
+ int current = ui->setpointList->currentIndex().row();
+ if (current < (setpointList->rowCount() - 1)) {
+ setpointList->insertRow(current + 2, setpointList->takeItem(current));
+ setpointList->removeRow(current);
+ }
+ }
+}
+
+void MainWindow::on_pbInsertSetpoint_clicked()
+{
+ int current = 0;
+ if (ui->setpointList->currentIndex().isValid()) {
+ current = ui->setpointList->currentIndex().row();
+ }
+
+ QString str("[" + ui->xSetpoint->text() + ", "+
+ ui->ySetpoint->text() + ", " +
+ ui->zSetpoint->text() + ", " +
+ ui->yawSetpoint->text() + "]");
+ setpointList->insertRow(current, new QStandardItem(str));
+}
+
+void MainWindow::on_pbSaveWaypoints_clicked()
+{
+ QString filter = "Waypoints (*.wpt)";
+ QString savePath = QFileDialog::getSaveFileName(this, tr("Save waypoint"), QString(), filter, &filter, QFileDialog::DontUseNativeDialog);
+
+ if (!savePath.isEmpty()) {
+ QFileInfo finfo(savePath);
+ if (finfo.suffix().isNull())
+ savePath.append(".wpt");
+ QFile f(savePath);
+ f.open(QIODevice::WriteOnly | QIODevice::Text);
+ for (int i= 0; i < setpointList->rowCount(); i++) {
+ f.write(setpointList->item(i)->text().toStdString().c_str());
+ f.write("\n");
+ }
+ f.close();
+ }
+}
+
+void MainWindow::on_pbLoadWaypoints_clicked()
+{
+
+ QString filter = "Waypoints (*.wpt)";
+ QString openPath = QFileDialog::getOpenFileName(this, tr("Open Waypoint File"), QString(),filter);
+
+ if (!openPath.isEmpty()) {
+ QFile f(openPath);
+ f.open(QIODevice::ReadOnly | QIODevice::Text);
+
+ setpointList->clear();
+ while (!f.atEnd()) {
+ QString line = f.readLine();
+ line.chop(1);
+ setpointList->appendRow(new QStandardItem(line));
+ }
+ f.close();
+ }
+}
+
+void MainWindow::on_xSetpoint_returnPressed()
+{
+ sp_x = ui->xSetpoint->text().toFloat();
+ emit (setParamValue(ui->xSetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0], sp_x));
+}
+
+void MainWindow::on_ySetpoint_returnPressed()
+{
+ sp_y = ui->ySetpoint->text().toFloat();
+ emit (setParamValue(ui->ySetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0], sp_y));
+}
+
+void MainWindow::on_zSetpoint_returnPressed()
+{
+ sp_z = ui->zSetpoint->text().toFloat();
+ emit (setParamValue(ui->zSetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0], sp_z));
+}
+
+void MainWindow::on_yawSetpoint_returnPressed()
+{
+ emit (setParamValue(ui->yawSetpointSelect->currentText(),
+ blockDefs[BLOCK_CONSTANT]->param_names[0],
+ ui->yawSetpoint->text().toFloat()));
+}
+
+void MainWindow::on_posattSrcVrpn_clicked()
+{
+ trackerTimer->setInterval(100);
+}
+
+void MainWindow::on_posattSrcQuad_clicked()
+{
+ trackerTimer->setInterval(750);
+}
diff --git a/groundStation/gui/MicroCART/mainwindow.h b/groundStation/gui/MicroCART/mainwindow.h
index db5534abe83d6d4301fe593f7db2531a591c469b..3ad5ed1da5fd958ad1f1b1a7f4c534e0ed7763d6 100644
--- a/groundStation/gui/MicroCART/mainwindow.h
+++ b/groundStation/gui/MicroCART/mainwindow.h
@@ -1,109 +1,113 @@
-#ifndef MAINWINDOW_H
-#define MAINWINDOW_H
-
-#include <QMainWindow>
-#include <QStringList>
-#include <QStandardItemModel>
-#include <QGraphicsScene>
-#include "quaditem.h"
-
-namespace Ui {
-class MainWindow;
-}
-
-class MainWindow : public QMainWindow
-{
- Q_OBJECT
-
-public:
- explicit MainWindow(QWidget *parent = 0);
- ~MainWindow();
-
-signals:
- void connectWorkers();
- void disconnectWorkers();
- void getParamValue(QString node, QString param);
- void getNodeOutput(QString node);
- void setParamValue(QString node, QString param, float value);
- void getPosAttFromBackend();
-
-private slots:
- void on_pbStart_clicked();
-
- void on_pbConnect_clicked();
-
- void on_pbStop_clicked();
-
- void on_chooseBackend_clicked();
-
- void updateTracker(float x, float y, float z, float p, float r, float yaw);
-
- void updatePosAtt();
-
- void newNodes(QStringList blocks);
- void newParams(QStringList params);
- void newParamValue(QString node, QString param, float val);
- void newNodeOutput(QString node, float output);
- void newConstantBlocks(QStringList blocks);
- void newControlGraph(QString graph);
-
- void on_paramSelect_currentIndexChanged(const QString &arg1);
-
- void on_paramValue_returnPressed();
-
- void on_pbAppendSetpoint_clicked();
-
- void on_pbNextSetpoint_clicked();
-
- void sendSetpoints();
- void sendSelectedSetpoint();
-
- void on_pbActualToSetpoint_clicked();
-
- void on_pbDeleteSetpoint_clicked();
-
- void on_pbActualToWaypoint_clicked();
-
- void on_pbMoveUp_clicked();
-
- void on_pbMoveDown_clicked();
-
- void on_pbInsertSetpoint_clicked();
-
- void on_pbSaveWaypoints_clicked();
-
- void on_pbLoadWaypoints_clicked();
-
- void on_xSetpoint_returnPressed();
-
- void on_ySetpoint_returnPressed();
-
- void on_zSetpoint_returnPressed();
-
- void on_posattSrcVrpn_clicked();
-
- void on_posattSrcQuad_clicked();
-
- void on_yawSetpoint_returnPressed();
-
- void backendStarted();
- void backendFinished(int exitCode, QProcess::ExitStatus exitStatus);
- void backendError(QProcess::ProcessError error);
- void backendRead();
- void workerConnected();
- void workerDisconnected();
-
-private:
- Ui::MainWindow *ui;
- QStandardItemModel * setpointList;
- QTimer * nextSpTimer;
- float sp_x;
- float sp_y;
- float sp_z;
- QTimer * trackerTimer;
- QTimer * workerStartTimer;
- QProcess * backendProcess;
- int connectedWorkers;
-};
-
-#endif // MAINWINDOW_H
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include <QMainWindow>
+#include <QStringList>
+#include <QStandardItemModel>
+#include <QGraphicsScene>
+#include "quaditem.h"
+
+namespace Ui {
+class MainWindow;
+}
+
+class MainWindow : public QMainWindow
+{
+ Q_OBJECT
+
+public:
+ explicit MainWindow(QWidget *parent = 0);
+ ~MainWindow();
+
+signals:
+ void connectWorkers();
+ void disconnectWorkers();
+ void getParamValue(QString node, QString param);
+ void getNodeOutput(QString node);
+ void setParamValue(QString node, QString param, float value);
+ void getPosAttFromBackend();
+
+private slots:
+ void on_pbStart_clicked();
+
+ void on_pbConnect_clicked();
+
+ void on_pbStop_clicked();
+
+ void on_chooseBackend_clicked();
+
+ void updateTracker(float x, float y, float z, float p, float r, float yaw);
+
+ void updatePosAtt();
+
+ void newNodes(QStringList blocks);
+ void newParams(QStringList params);
+ void newParamValue(QString node, QString param, float val);
+ void newNodeOutput(QString node, float output);
+ void newConstantBlocks(QStringList blocks);
+ void newControlGraph(QString graph);
+
+ void on_paramSelect_currentIndexChanged(const QString &arg1);
+
+ void on_paramValue_returnPressed();
+
+ void on_pbAppendSetpoint_clicked();
+
+ void on_pbNextSetpoint_clicked();
+
+ void sendSetpoints();
+ void sendSelectedSetpoint();
+
+ void on_pbActualToSetpoint_clicked();
+
+ void on_pbDeleteSetpoint_clicked();
+
+ void on_pbActualToWaypoint_clicked();
+
+ void on_pbMoveUp_clicked();
+
+ void on_pbMoveDown_clicked();
+
+ void on_pbInsertSetpoint_clicked();
+
+ void on_pbSaveWaypoints_clicked();
+
+ void on_pbLoadWaypoints_clicked();
+
+ void on_xSetpoint_returnPressed();
+
+ void on_run_data_analysis_button_clicked();
+
+ void on_ySetpoint_returnPressed();
+
+ void on_zSetpoint_returnPressed();
+
+ void on_posattSrcVrpn_clicked();
+
+ void on_posattSrcQuad_clicked();
+
+ void on_yawSetpoint_returnPressed();
+
+ void backendStarted();
+ void connectMatlab();
+ void backendFinished(int exitCode, QProcess::ExitStatus exitStatus);
+ void backendError(QProcess::ProcessError error);
+ void backendRead();
+ void workerConnected();
+ void workerDisconnected();
+
+private:
+ Ui::MainWindow *ui;
+ QStandardItemModel * setpointList;
+ QTimer * nextSpTimer;
+ float sp_x;
+ float sp_y;
+ float sp_z;
+ QTimer * trackerTimer;
+ QTimer * workerStartTimer;
+ QProcess * backendProcess;
+ QProcess * matlabProcess;
+ int connectedWorkers;
+};
+
+#endif // MAINWINDOW_H
diff --git a/groundStation/gui/MicroCART/mainwindow.ui b/groundStation/gui/MicroCART/mainwindow.ui
index a835da062a8fe7f7363120294c375fe0342d933e..17c9cd8d63690583cc97a24c8833e934c7414244 100644
--- a/groundStation/gui/MicroCART/mainwindow.ui
+++ b/groundStation/gui/MicroCART/mainwindow.ui
@@ -1,1130 +1,1148 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<ui version="4.0">
- <class>MainWindow</class>
- <widget class="QMainWindow" name="MainWindow">
- <property name="geometry">
- <rect>
- <x>0</x>
- <y>0</y>
- <width>1186</width>
- <height>1034</height>
- </rect>
- </property>
- <property name="windowTitle">
- <string>MainWindow</string>
- </property>
- <widget class="QWidget" name="centralWidget">
- <layout class="QVBoxLayout" name="verticalLayout_4">
- <item>
- <widget class="QTabWidget" name="tabWidget">
- <property name="currentIndex">
- <number>0</number>
- </property>
- <widget class="QWidget" name="backend">
- <attribute name="title">
- <string>Backend</string>
- </attribute>
- <layout class="QVBoxLayout" name="verticalLayout">
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_8">
- <item>
- <widget class="QLineEdit" name="backendPath">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="text">
- <string>./BackEnd</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="chooseBackend">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="text">
- <string>Choose...</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_7">
- <item>
- <widget class="QPushButton" name="pbStart">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="text">
- <string>Start</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbConnect">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="text">
- <string>Connect</string>
- </property>
- </widget>
- </item>
- <item>
- <spacer name="horizontalSpacer_2">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- <property name="sizeHint" stdset="0">
- <size>
- <width>40</width>
- <height>20</height>
- </size>
- </property>
- </spacer>
- </item>
- <item>
- <widget class="QPushButton" name="pbStop">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="text">
- <string>Stop/Disconnect</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <widget class="Line" name="line_7">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QTextEdit" name="vConsole">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="readOnly">
- <bool>true</bool>
- </property>
- </widget>
- </item>
- </layout>
- </widget>
- <widget class="QWidget" name="controlGraph">
- <attribute name="title">
- <string>Controller Graph</string>
- </attribute>
- <layout class="QVBoxLayout" name="verticalLayout_2">
- <item>
- <widget class="QScrollArea" name="scrollArea">
- <property name="widgetResizable">
- <bool>true</bool>
- </property>
- <widget class="QWidget" name="scrollAreaWidgetContents">
- <property name="geometry">
- <rect>
- <x>0</x>
- <y>0</y>
- <width>1144</width>
- <height>677</height>
- </rect>
- </property>
- <layout class="QVBoxLayout" name="verticalLayout_8">
- <item>
- <widget class="QLabel" name="graphImage">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="MinimumExpanding">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="font">
- <font>
- <pointsize>32</pointsize>
- </font>
- </property>
- <property name="text">
- <string/>
- </property>
- <property name="alignment">
- <set>Qt::AlignCenter</set>
- </property>
- </widget>
- </item>
- </layout>
- </widget>
- </widget>
- </item>
- <item>
- <widget class="Line" name="line_2">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbControlRefresh">
- <property name="text">
- <string>Refresh Controller Graph</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="Line" name="line">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_6">
- <item>
- <widget class="QLabel" name="label">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Minimum">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Node:</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="nodeSelect">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QLabel" name="label_2">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Param:</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="paramSelect"/>
- </item>
- <item>
- <widget class="QLineEdit" name="paramValue">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <widget class="Line" name="line_5">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_4">
- <item>
- <widget class="QLabel" name="label_4">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Minimum">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>X Setpoint</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="xSetpointSelect">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QLabel" name="label_5">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Y Setpoint</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="ySetpointSelect"/>
- </item>
- <item>
- <widget class="QLabel" name="label_3">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Z Setpoint</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="zSetpointSelect"/>
- </item>
- <item>
- <widget class="QLabel" name="label_18">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Yaw Setpoint:</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="yawSetpointSelect"/>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_10">
- <item>
- <widget class="QLabel" name="label_11">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>X Position</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="xPositionSelect"/>
- </item>
- <item>
- <widget class="QLabel" name="label_13">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Y Position </string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="yPositionSelect"/>
- </item>
- <item>
- <widget class="QLabel" name="label_14">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Z Position</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="zPositionSelect"/>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_11">
- <item>
- <widget class="QLabel" name="label_15">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>P Attitude</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="pAttitudeSelect"/>
- </item>
- <item>
- <widget class="QLabel" name="label_16">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>R Attitude</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="rAttitudeSelect"/>
- </item>
- <item>
- <widget class="QLabel" name="label_17">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Y Attitude</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QComboBox" name="yAttitudeSelect"/>
- </item>
- </layout>
- </item>
- </layout>
- </widget>
- <widget class="QWidget" name="navigation">
- <attribute name="title">
- <string>Navigation</string>
- </attribute>
- <layout class="QVBoxLayout" name="verticalLayout_3">
- <item>
- <widget class="QLabel" name="noGraphWarning1">
- <property name="font">
- <font>
- <pointsize>32</pointsize>
- <weight>75</weight>
- <bold>true</bold>
- <underline>true</underline>
- </font>
- </property>
- <property name="styleSheet">
- <string notr="true">QLabel {color : red; }</string>
- </property>
- <property name="text">
- <string>NO CONTROL GRAPH LOADED!</string>
- </property>
- <property name="alignment">
- <set>Qt::AlignCenter</set>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QLabel" name="noGraphWarning2">
- <property name="text">
- <string>These controls won't work right unless the correct control graph is loaded.</string>
- </property>
- <property name="alignment">
- <set>Qt::AlignCenter</set>
- </property>
- </widget>
- </item>
- <item>
- <widget class="Line" name="noGraphWarningLine">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_9">
- <item>
- <widget class="QLabel" name="label_12">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Position/Attitude Source: </string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QRadioButton" name="posattSrcVrpn">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Backend Tracker (&VRPN)</string>
- </property>
- <property name="checked">
- <bool>true</bool>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QRadioButton" name="posattSrcQuad">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>From &Quad</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_3">
- <item>
- <layout class="QVBoxLayout" name="verticalLayout_7">
- <item>
- <widget class="QLabel" name="label_6">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Current Position</string>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QFormLayout" name="formLayout">
- <property name="fieldGrowthPolicy">
- <enum>QFormLayout::ExpandingFieldsGrow</enum>
- </property>
- <item row="0" column="0">
- <widget class="QLabel" name="xLabel">
- <property name="text">
- <string>X</string>
- </property>
- </widget>
- </item>
- <item row="0" column="1">
- <widget class="QLineEdit" name="xActual">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item row="1" column="0">
- <widget class="QLabel" name="yLabel">
- <property name="text">
- <string>Y</string>
- </property>
- </widget>
- </item>
- <item row="1" column="1">
- <widget class="QLineEdit" name="yActual">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item row="2" column="0">
- <widget class="QLabel" name="zLabel">
- <property name="text">
- <string>Z</string>
- </property>
- </widget>
- </item>
- <item row="2" column="1">
- <widget class="QLineEdit" name="zActual">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item row="3" column="0">
- <widget class="QLabel" name="pLabel">
- <property name="text">
- <string>P</string>
- </property>
- </widget>
- </item>
- <item row="3" column="1">
- <widget class="QLineEdit" name="pitchActual">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item row="4" column="0">
- <widget class="QLabel" name="rLabel">
- <property name="text">
- <string>R</string>
- </property>
- </widget>
- </item>
- <item row="4" column="1">
- <widget class="QLineEdit" name="rollActual">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item row="5" column="0">
- <widget class="QLabel" name="yLabel_2">
- <property name="text">
- <string>Y</string>
- </property>
- </widget>
- </item>
- <item row="5" column="1">
- <widget class="QLineEdit" name="yawActual">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <widget class="Line" name="line_6">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QFormLayout" name="formLayout_5">
- <item row="0" column="1">
- <widget class="QLineEdit" name="dist">
- <property name="enabled">
- <bool>false</bool>
- </property>
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item row="0" column="0">
- <widget class="QLabel" name="label_10">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>D</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_5"/>
- </item>
- <item>
- <widget class="QPushButton" name="pbActualToSetpoint">
- <property name="text">
- <string>To Setpoint</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbActualToWaypoint">
- <property name="text">
- <string>To Waypoint</string>
- </property>
- </widget>
- </item>
- <item>
- <spacer name="verticalSpacer_4">
- <property name="orientation">
- <enum>Qt::Vertical</enum>
- </property>
- <property name="sizeHint" stdset="0">
- <size>
- <width>20</width>
- <height>40</height>
- </size>
- </property>
- </spacer>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QVBoxLayout" name="verticalLayout_5">
- <item>
- <widget class="QLabel" name="label_7">
- <property name="text">
- <string>Position Setpoints</string>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QFormLayout" name="formLayout_2">
- <item row="0" column="0">
- <widget class="QLabel" name="setpointLabel">
- <property name="text">
- <string>X</string>
- </property>
- </widget>
- </item>
- <item row="2" column="0">
- <widget class="QLabel" name="setpointLabel_3">
- <property name="text">
- <string>Z</string>
- </property>
- </widget>
- </item>
- <item row="1" column="0">
- <widget class="QLabel" name="setpointLabel_2">
- <property name="text">
- <string>Y</string>
- </property>
- </widget>
- </item>
- <item row="3" column="0">
- <widget class="QLabel" name="yawLabel">
- <property name="text">
- <string>Yaw</string>
- </property>
- </widget>
- </item>
- <item row="0" column="1">
- <layout class="QHBoxLayout" name="horizontalLayout_12">
- <item>
- <widget class="QLineEdit" name="xSetpoint">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QCheckBox" name="sendX">
- <property name="text">
- <string/>
- </property>
- <property name="checked">
- <bool>true</bool>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item row="1" column="1">
- <layout class="QHBoxLayout" name="horizontalLayout_13">
- <item>
- <widget class="QLineEdit" name="ySetpoint">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QCheckBox" name="sendY">
- <property name="text">
- <string/>
- </property>
- <property name="checked">
- <bool>true</bool>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item row="2" column="1">
- <layout class="QHBoxLayout" name="horizontalLayout_14">
- <item>
- <widget class="QLineEdit" name="zSetpoint">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QCheckBox" name="sendZ">
- <property name="text">
- <string/>
- </property>
- <property name="checked">
- <bool>true</bool>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item row="3" column="1">
- <layout class="QHBoxLayout" name="horizontalLayout_15">
- <item>
- <widget class="QLineEdit" name="yawSetpoint">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QCheckBox" name="sendYaw">
- <property name="text">
- <string/>
- </property>
- <property name="checked">
- <bool>false</bool>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- </layout>
- </item>
- <item>
- <widget class="QPushButton" name="pbSendSetpoint">
- <property name="text">
- <string>Send to Quad</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="Line" name="line_3">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbAppendSetpoint">
- <property name="text">
- <string>Append</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbInsertSetpoint">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="text">
- <string>Insert</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbDeleteSetpoint">
- <property name="enabled">
- <bool>true</bool>
- </property>
- <property name="text">
- <string>Delete</string>
- </property>
- </widget>
- </item>
- <item>
- <spacer name="verticalSpacer_3">
- <property name="orientation">
- <enum>Qt::Vertical</enum>
- </property>
- <property name="sizeHint" stdset="0">
- <size>
- <width>20</width>
- <height>40</height>
- </size>
- </property>
- </spacer>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QVBoxLayout" name="verticalLayout_6">
- <item>
- <widget class="QLabel" name="label_8">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Waypoints</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QListView" name="setpointList">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Minimum" vsizetype="Expanding">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="editTriggers">
- <set>QAbstractItemView::NoEditTriggers</set>
- </property>
- <property name="dragEnabled">
- <bool>false</bool>
- </property>
- <property name="dragDropOverwriteMode">
- <bool>false</bool>
- </property>
- <property name="dragDropMode">
- <enum>QAbstractItemView::NoDragDrop</enum>
- </property>
- <property name="defaultDropAction">
- <enum>Qt::MoveAction</enum>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbNextSetpoint">
- <property name="text">
- <string>Send Next</string>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout_2">
- <item>
- <widget class="QPushButton" name="pbMoveUp">
- <property name="text">
- <string>Move Up</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbMoveDown">
- <property name="text">
- <string>Move Down</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QHBoxLayout" name="horizontalLayout">
- <item>
- <widget class="QPushButton" name="pbSaveWaypoints">
- <property name="text">
- <string>Save</string>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QPushButton" name="pbLoadWaypoints">
- <property name="text">
- <string>Load</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- <item>
- <widget class="Line" name="line_4">
- <property name="orientation">
- <enum>Qt::Horizontal</enum>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QCheckBox" name="autonavEnabled">
- <property name="text">
- <string>Enable Autonavigation</string>
- </property>
- </widget>
- </item>
- <item>
- <layout class="QFormLayout" name="formLayout_6">
- <item row="0" column="0">
- <widget class="QLabel" name="label_9">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>Threshold</string>
- </property>
- </widget>
- </item>
- <item row="1" column="0">
- <widget class="QLabel" name="delayLabel">
- <property name="text">
- <string>Delay</string>
- </property>
- </widget>
- </item>
- <item row="0" column="1">
- <widget class="QLineEdit" name="autonavThreshold">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>0.1</string>
- </property>
- </widget>
- </item>
- <item row="1" column="1">
- <widget class="QLineEdit" name="autonavDelay">
- <property name="sizePolicy">
- <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
- <horstretch>0</horstretch>
- <verstretch>0</verstretch>
- </sizepolicy>
- </property>
- <property name="text">
- <string>88</string>
- </property>
- </widget>
- </item>
- </layout>
- </item>
- </layout>
- </item>
- <item>
- <layout class="QVBoxLayout" name="verticalLayout_9">
- <item>
- <widget class="QGraphicsView" name="posView">
- <property name="verticalScrollBarPolicy">
- <enum>Qt::ScrollBarAlwaysOff</enum>
- </property>
- <property name="horizontalScrollBarPolicy">
- <enum>Qt::ScrollBarAlwaysOff</enum>
- </property>
- </widget>
- </item>
- <item>
- <widget class="QGraphicsView" name="attView"/>
- </item>
- </layout>
- </item>
- </layout>
- </item>
- <item>
- <widget class="QPushButton" name="pbRefresh">
- <property name="text">
- <string>Refresh</string>
- </property>
- </widget>
- </item>
- </layout>
- </widget>
- </widget>
- </item>
- </layout>
- </widget>
- <widget class="QMenuBar" name="menuBar">
- <property name="geometry">
- <rect>
- <x>0</x>
- <y>0</y>
- <width>1186</width>
- <height>27</height>
- </rect>
- </property>
- <widget class="QMenu" name="menuScripts">
- <property name="title">
- <string>Scripts</string>
- </property>
- </widget>
- <addaction name="menuScripts"/>
- </widget>
- <widget class="QToolBar" name="mainToolBar">
- <attribute name="toolBarArea">
- <enum>TopToolBarArea</enum>
- </attribute>
- <attribute name="toolBarBreak">
- <bool>false</bool>
- </attribute>
- </widget>
- <widget class="QStatusBar" name="statusBar"/>
- </widget>
- <layoutdefault spacing="6" margin="11"/>
- <resources/>
- <connections/>
-</ui>
+<?xml version="1.0" encoding="UTF-8"?>
+<ui version="4.0">
+ <class>MainWindow</class>
+ <widget class="QMainWindow" name="MainWindow">
+ <property name="geometry">
+ <rect>
+ <x>0</x>
+ <y>0</y>
+ <width>1186</width>
+ <height>1034</height>
+ </rect>
+ </property>
+ <property name="windowTitle">
+ <string>MainWindow</string>
+ </property>
+ <widget class="QWidget" name="centralWidget">
+ <layout class="QVBoxLayout" name="verticalLayout_4">
+ <item>
+ <widget class="QTabWidget" name="tabWidget">
+ <property name="currentIndex">
+ <number>3</number>
+ </property>
+ <widget class="QWidget" name="backend">
+ <attribute name="title">
+ <string>Backend</string>
+ </attribute>
+ <layout class="QVBoxLayout" name="verticalLayout">
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_8">
+ <item>
+ <widget class="QLineEdit" name="backendPath">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="text">
+ <string>./BackEnd</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="chooseBackend">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="text">
+ <string>Choose...</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_7">
+ <item>
+ <widget class="QPushButton" name="pbStart">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="text">
+ <string>Start</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbConnect">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="text">
+ <string>Connect</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <spacer name="horizontalSpacer_2">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ <property name="sizeHint" stdset="0">
+ <size>
+ <width>40</width>
+ <height>20</height>
+ </size>
+ </property>
+ </spacer>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbStop">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="text">
+ <string>Stop/Disconnect</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <widget class="Line" name="line_7">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QTextEdit" name="vConsole">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="readOnly">
+ <bool>true</bool>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </widget>
+ <widget class="QWidget" name="controlGraph">
+ <attribute name="title">
+ <string>Controller Graph</string>
+ </attribute>
+ <layout class="QVBoxLayout" name="verticalLayout_2">
+ <item>
+ <widget class="QScrollArea" name="scrollArea">
+ <property name="widgetResizable">
+ <bool>true</bool>
+ </property>
+ <widget class="QWidget" name="scrollAreaWidgetContents">
+ <property name="geometry">
+ <rect>
+ <x>0</x>
+ <y>0</y>
+ <width>1144</width>
+ <height>679</height>
+ </rect>
+ </property>
+ <layout class="QVBoxLayout" name="verticalLayout_8">
+ <item>
+ <widget class="QLabel" name="graphImage">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="MinimumExpanding">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="font">
+ <font>
+ <pointsize>32</pointsize>
+ </font>
+ </property>
+ <property name="text">
+ <string/>
+ </property>
+ <property name="alignment">
+ <set>Qt::AlignCenter</set>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </widget>
+ </widget>
+ </item>
+ <item>
+ <widget class="Line" name="line_2">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbControlRefresh">
+ <property name="text">
+ <string>Refresh Controller Graph</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="Line" name="line">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_6">
+ <item>
+ <widget class="QLabel" name="label">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Minimum">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Node:</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="nodeSelect">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_2">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Param:</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="paramSelect"/>
+ </item>
+ <item>
+ <widget class="QLineEdit" name="paramValue">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <widget class="Line" name="line_5">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_4">
+ <item>
+ <widget class="QLabel" name="label_4">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Minimum">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>X Setpoint</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="xSetpointSelect">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_5">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Y Setpoint</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="ySetpointSelect"/>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_3">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Z Setpoint</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="zSetpointSelect"/>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_18">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Yaw Setpoint:</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="yawSetpointSelect"/>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_10">
+ <item>
+ <widget class="QLabel" name="label_11">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>X Position</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="xPositionSelect"/>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_13">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Y Position </string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="yPositionSelect"/>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_14">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Z Position</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="zPositionSelect"/>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_11">
+ <item>
+ <widget class="QLabel" name="label_15">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>P Attitude</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="pAttitudeSelect"/>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_16">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>R Attitude</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="rAttitudeSelect"/>
+ </item>
+ <item>
+ <widget class="QLabel" name="label_17">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Y Attitude</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QComboBox" name="yAttitudeSelect"/>
+ </item>
+ </layout>
+ </item>
+ </layout>
+ </widget>
+ <widget class="QWidget" name="navigation">
+ <attribute name="title">
+ <string>Navigation</string>
+ </attribute>
+ <layout class="QVBoxLayout" name="verticalLayout_3">
+ <item>
+ <widget class="QLabel" name="noGraphWarning1">
+ <property name="font">
+ <font>
+ <pointsize>32</pointsize>
+ <weight>75</weight>
+ <bold>true</bold>
+ <underline>true</underline>
+ </font>
+ </property>
+ <property name="styleSheet">
+ <string notr="true">QLabel {color : red; }</string>
+ </property>
+ <property name="text">
+ <string>NO CONTROL GRAPH LOADED!</string>
+ </property>
+ <property name="alignment">
+ <set>Qt::AlignCenter</set>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QLabel" name="noGraphWarning2">
+ <property name="text">
+ <string>These controls won't work right unless the correct control graph is loaded.</string>
+ </property>
+ <property name="alignment">
+ <set>Qt::AlignCenter</set>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="Line" name="noGraphWarningLine">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_9">
+ <item>
+ <widget class="QLabel" name="label_12">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Position/Attitude Source: </string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QRadioButton" name="posattSrcVrpn">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Backend Tracker (&VRPN)</string>
+ </property>
+ <property name="checked">
+ <bool>true</bool>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QRadioButton" name="posattSrcQuad">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>From &Quad</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_3">
+ <item>
+ <layout class="QVBoxLayout" name="verticalLayout_7">
+ <item>
+ <widget class="QLabel" name="label_6">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Current Position</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QFormLayout" name="formLayout">
+ <property name="fieldGrowthPolicy">
+ <enum>QFormLayout::ExpandingFieldsGrow</enum>
+ </property>
+ <item row="0" column="0">
+ <widget class="QLabel" name="xLabel">
+ <property name="text">
+ <string>X</string>
+ </property>
+ </widget>
+ </item>
+ <item row="0" column="1">
+ <widget class="QLineEdit" name="xActual">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item row="1" column="0">
+ <widget class="QLabel" name="yLabel">
+ <property name="text">
+ <string>Y</string>
+ </property>
+ </widget>
+ </item>
+ <item row="1" column="1">
+ <widget class="QLineEdit" name="yActual">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item row="2" column="0">
+ <widget class="QLabel" name="zLabel">
+ <property name="text">
+ <string>Z</string>
+ </property>
+ </widget>
+ </item>
+ <item row="2" column="1">
+ <widget class="QLineEdit" name="zActual">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item row="3" column="0">
+ <widget class="QLabel" name="pLabel">
+ <property name="text">
+ <string>P</string>
+ </property>
+ </widget>
+ </item>
+ <item row="3" column="1">
+ <widget class="QLineEdit" name="pitchActual">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item row="4" column="0">
+ <widget class="QLabel" name="rLabel">
+ <property name="text">
+ <string>R</string>
+ </property>
+ </widget>
+ </item>
+ <item row="4" column="1">
+ <widget class="QLineEdit" name="rollActual">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item row="5" column="0">
+ <widget class="QLabel" name="yLabel_2">
+ <property name="text">
+ <string>Y</string>
+ </property>
+ </widget>
+ </item>
+ <item row="5" column="1">
+ <widget class="QLineEdit" name="yawActual">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <widget class="Line" name="line_6">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QFormLayout" name="formLayout_5">
+ <item row="0" column="1">
+ <widget class="QLineEdit" name="dist">
+ <property name="enabled">
+ <bool>false</bool>
+ </property>
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item row="0" column="0">
+ <widget class="QLabel" name="label_10">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>D</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_5"/>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbActualToSetpoint">
+ <property name="text">
+ <string>To Setpoint</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbActualToWaypoint">
+ <property name="text">
+ <string>To Waypoint</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <spacer name="verticalSpacer_4">
+ <property name="orientation">
+ <enum>Qt::Vertical</enum>
+ </property>
+ <property name="sizeHint" stdset="0">
+ <size>
+ <width>20</width>
+ <height>40</height>
+ </size>
+ </property>
+ </spacer>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QVBoxLayout" name="verticalLayout_5">
+ <item>
+ <widget class="QLabel" name="label_7">
+ <property name="text">
+ <string>Position Setpoints</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QFormLayout" name="formLayout_2">
+ <item row="0" column="0">
+ <widget class="QLabel" name="setpointLabel">
+ <property name="text">
+ <string>X</string>
+ </property>
+ </widget>
+ </item>
+ <item row="2" column="0">
+ <widget class="QLabel" name="setpointLabel_3">
+ <property name="text">
+ <string>Z</string>
+ </property>
+ </widget>
+ </item>
+ <item row="1" column="0">
+ <widget class="QLabel" name="setpointLabel_2">
+ <property name="text">
+ <string>Y</string>
+ </property>
+ </widget>
+ </item>
+ <item row="3" column="0">
+ <widget class="QLabel" name="yawLabel">
+ <property name="text">
+ <string>Yaw</string>
+ </property>
+ </widget>
+ </item>
+ <item row="0" column="1">
+ <layout class="QHBoxLayout" name="horizontalLayout_12">
+ <item>
+ <widget class="QLineEdit" name="xSetpoint">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QCheckBox" name="sendX">
+ <property name="text">
+ <string/>
+ </property>
+ <property name="checked">
+ <bool>true</bool>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item row="1" column="1">
+ <layout class="QHBoxLayout" name="horizontalLayout_13">
+ <item>
+ <widget class="QLineEdit" name="ySetpoint">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QCheckBox" name="sendY">
+ <property name="text">
+ <string/>
+ </property>
+ <property name="checked">
+ <bool>true</bool>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item row="2" column="1">
+ <layout class="QHBoxLayout" name="horizontalLayout_14">
+ <item>
+ <widget class="QLineEdit" name="zSetpoint">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QCheckBox" name="sendZ">
+ <property name="text">
+ <string/>
+ </property>
+ <property name="checked">
+ <bool>true</bool>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item row="3" column="1">
+ <layout class="QHBoxLayout" name="horizontalLayout_15">
+ <item>
+ <widget class="QLineEdit" name="yawSetpoint">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QCheckBox" name="sendYaw">
+ <property name="text">
+ <string/>
+ </property>
+ <property name="checked">
+ <bool>false</bool>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbSendSetpoint">
+ <property name="text">
+ <string>Send to Quad</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="Line" name="line_3">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbAppendSetpoint">
+ <property name="text">
+ <string>Append</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbInsertSetpoint">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="text">
+ <string>Insert</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbDeleteSetpoint">
+ <property name="enabled">
+ <bool>true</bool>
+ </property>
+ <property name="text">
+ <string>Delete</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <spacer name="verticalSpacer_3">
+ <property name="orientation">
+ <enum>Qt::Vertical</enum>
+ </property>
+ <property name="sizeHint" stdset="0">
+ <size>
+ <width>20</width>
+ <height>40</height>
+ </size>
+ </property>
+ </spacer>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QVBoxLayout" name="verticalLayout_6">
+ <item>
+ <widget class="QLabel" name="label_8">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Waypoints</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QListView" name="setpointList">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Minimum" vsizetype="Expanding">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="editTriggers">
+ <set>QAbstractItemView::NoEditTriggers</set>
+ </property>
+ <property name="dragEnabled">
+ <bool>false</bool>
+ </property>
+ <property name="dragDropOverwriteMode">
+ <bool>false</bool>
+ </property>
+ <property name="dragDropMode">
+ <enum>QAbstractItemView::NoDragDrop</enum>
+ </property>
+ <property name="defaultDropAction">
+ <enum>Qt::MoveAction</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbNextSetpoint">
+ <property name="text">
+ <string>Send Next</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout_2">
+ <item>
+ <widget class="QPushButton" name="pbMoveUp">
+ <property name="text">
+ <string>Move Up</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbMoveDown">
+ <property name="text">
+ <string>Move Down</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QHBoxLayout" name="horizontalLayout">
+ <item>
+ <widget class="QPushButton" name="pbSaveWaypoints">
+ <property name="text">
+ <string>Save</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbLoadWaypoints">
+ <property name="text">
+ <string>Load</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <widget class="Line" name="line_4">
+ <property name="orientation">
+ <enum>Qt::Horizontal</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QCheckBox" name="autonavEnabled">
+ <property name="text">
+ <string>Enable Autonavigation</string>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <layout class="QFormLayout" name="formLayout_6">
+ <item row="0" column="0">
+ <widget class="QLabel" name="label_9">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Fixed" vsizetype="Preferred">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>Threshold</string>
+ </property>
+ </widget>
+ </item>
+ <item row="1" column="0">
+ <widget class="QLabel" name="delayLabel">
+ <property name="text">
+ <string>Delay</string>
+ </property>
+ </widget>
+ </item>
+ <item row="0" column="1">
+ <widget class="QLineEdit" name="autonavThreshold">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>0.1</string>
+ </property>
+ </widget>
+ </item>
+ <item row="1" column="1">
+ <widget class="QLineEdit" name="autonavDelay">
+ <property name="sizePolicy">
+ <sizepolicy hsizetype="Preferred" vsizetype="Fixed">
+ <horstretch>0</horstretch>
+ <verstretch>0</verstretch>
+ </sizepolicy>
+ </property>
+ <property name="text">
+ <string>88</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <layout class="QVBoxLayout" name="verticalLayout_9">
+ <item>
+ <widget class="QGraphicsView" name="posView">
+ <property name="verticalScrollBarPolicy">
+ <enum>Qt::ScrollBarAlwaysOff</enum>
+ </property>
+ <property name="horizontalScrollBarPolicy">
+ <enum>Qt::ScrollBarAlwaysOff</enum>
+ </property>
+ </widget>
+ </item>
+ <item>
+ <widget class="QGraphicsView" name="attView"/>
+ </item>
+ </layout>
+ </item>
+ </layout>
+ </item>
+ <item>
+ <widget class="QPushButton" name="pbRefresh">
+ <property name="text">
+ <string>Refresh</string>
+ </property>
+ </widget>
+ </item>
+ </layout>
+ </widget>
+ <widget class="QWidget" name="tab">
+ <attribute name="title">
+ <string>Flight Data</string>
+ </attribute>
+ <widget class="QPushButton" name="run_data_analysis_button">
+ <property name="geometry">
+ <rect>
+ <x>0</x>
+ <y>0</y>
+ <width>1141</width>
+ <height>28</height>
+ </rect>
+ </property>
+ <property name="text">
+ <string>Run Data Analysis (Will Open Separate Window)</string>
+ </property>
+ </widget>
+ </widget>
+ </widget>
+ </item>
+ </layout>
+ </widget>
+ <widget class="QMenuBar" name="menuBar">
+ <property name="geometry">
+ <rect>
+ <x>0</x>
+ <y>0</y>
+ <width>1186</width>
+ <height>28</height>
+ </rect>
+ </property>
+ <widget class="QMenu" name="menuScripts">
+ <property name="title">
+ <string>Scripts</string>
+ </property>
+ </widget>
+ <addaction name="menuScripts"/>
+ </widget>
+ <widget class="QToolBar" name="mainToolBar">
+ <attribute name="toolBarArea">
+ <enum>TopToolBarArea</enum>
+ </attribute>
+ <attribute name="toolBarBreak">
+ <bool>false</bool>
+ </attribute>
+ </widget>
+ <widget class="QStatusBar" name="statusBar"/>
+ </widget>
+ <layoutdefault spacing="6" margin="11"/>
+ <resources/>
+ <connections/>
+</ui>
diff --git a/groundStation/src/backend/backend.c b/groundStation/src/backend/backend.c
index af32a16407831f4a4ff07857b55f0acb5c000315..295b8544208f952efcc3dc27dca4f0ce2e453452 100644
--- a/groundStation/src/backend/backend.c
+++ b/groundStation/src/backend/backend.c
@@ -22,8 +22,8 @@
#include <arpa/inet.h>
#include <sys/select.h>
#include <sys/stat.h>
-#include <bluetooth/bluetooth.h>
-#include <bluetooth/rfcomm.h>
+//#include <bluetooth/bluetooth.h> Bluetooth not currently used
+//#include <bluetooth/rfcomm.h> Bluetooth not currently used
#include <pthread.h>
#include <assert.h>
#include <errno.h>
@@ -471,7 +471,7 @@ int connectToZybo(int index) {
status = 0;
sock = trackables[index].fifo_rx;
}
- else if (trackables[index].isBluetooth == 1) {
+ /*else if (trackables[index].isBluetooth == 1) { //Bluetooth functionality currently disabled
printf("Using BT Settings\n");
struct sockaddr_rc addr;
@@ -486,7 +486,7 @@ int connectToZybo(int index) {
printf("Attempting to connect to zybo. Please be patient...\n");
// blocking call to connect to socket sock ie. zybo board
status = connect(sock, (struct sockaddr *)&addr, sizeof(addr));
- }
+ }*/
else {
printf("Using WIFI settings\n");
struct sockaddr_in addr;
@@ -875,6 +875,10 @@ static void client_recv(int fd) {
case ADDNODE_ID:
result = EncodeAddNode(&m, data, 128, buffer);
break;
+ case OUTPUT_OVERRIDE_ID:
+ result = EncodeSetOutputOverride(&m, data, 128, buffer);
+ break;
+
default:
result = -1;
break;
@@ -919,7 +923,7 @@ static void client_recv(int fd) {
static void quad_recv(int index) {
static unsigned char respBuf[CMD_MAX_LENGTH];
static size_t respBufLen;
- static int receiving_logs;
+ static int receiving_logs;
struct metadata m;
uint8_t data[CMD_MAX_LENGTH];
@@ -1005,6 +1009,13 @@ static void quad_recv(int index) {
}
fwrite((char *) data, sizeof(char), m.data_len, quadlog_file);
break;
+ case SEND_RT_ID:
+ quadlog_file = fopen("quad_log_data.txt", "w");
+
+ //fwrite((char *) formatted_data, sizeof(char), m.data_len, quadlog_file);
+ fclose(quadlog_file);
+ //free(formatted_data);
+ break;
case RESPPARAM_ID:
case RESPSOURCE_ID:
case RESPOUTPUT_ID:
diff --git a/groundStation/src/backend/override.c b/groundStation/src/backend/override.c
new file mode 100644
index 0000000000000000000000000000000000000000..e51c09496cde94448dcb40619c84486a331139e7
--- /dev/null
+++ b/groundStation/src/backend/override.c
@@ -0,0 +1,51 @@
+#include <sys/types.h>
+#include <inttypes.h>
+#include <string.h>
+
+#include "output.h"
+#include "commands.h"
+#include "bitwise.h"
+
+#define NUM_OUTPUTS 4
+#define DATA_SIZE (1+NUM_OUTPUTS*4)
+
+/* Creates data and metadata for a overrideoutput packet
+ * Returns data size.
+ */
+ssize_t EncodeSetOutputOverride(
+ struct metadata * m, /* data_len and msg_type will be populated*/
+ uint8_t * data, /* Output buffer */
+ size_t data_size, /* Max buffer size */
+ const char * msg) /* Message to encode */
+{
+ m->msg_type = OUTPUT_OVERRIDE_ID;
+ m->data_len = DATA_SIZE;
+
+ if (data_size < DATA_SIZE) {
+ return -1;
+ }
+
+ float values[NUM_OUTPUTS];
+ values[0] = -1;
+ char* tok = strtok(msg, " ");
+ char* ena = strtok(NULL, " ");
+ data[0] = atoi(ena);
+ int i;
+ for (i = 0; i < NUM_OUTPUTS; i++) {
+ char* value = strtok(NULL, " ");
+ if (value == NULL) {
+ return -1;
+ }
+ float a;
+ sscanf(value, "%f", &a);
+ values[i] = a;
+ }
+
+ for (i = 0; i < NUM_OUTPUTS; i++) {
+ data[1+i*4+0] = FloatByte1(values[i]);
+ data[1+i*4+1] = FloatByte2(values[i]);
+ data[1+i*4+2] = FloatByte3(values[i]);
+ data[1+i*4+3] = FloatByte4(values[i]);
+ }
+ return DATA_SIZE;
+}
diff --git a/groundStation/src/backend/override.h b/groundStation/src/backend/override.h
new file mode 100644
index 0000000000000000000000000000000000000000..f07fa6b41c577ddb7deccb4fc7adaf98a9ea21d3
--- /dev/null
+++ b/groundStation/src/backend/override.h
@@ -0,0 +1,18 @@
+#ifndef _OVERRIDE_h
+#define _OVERRIDE_h
+
+#include "packet.h"
+
+#include <sys/types.h>
+
+
+/* Creates data and metadata for a overrideoutput packet.
+ * Returns data size.
+ */
+ssize_t EncodeSetOutputOverride(
+ struct metadata *m, /* Out */
+ uint8_t *data, /* Out */
+ size_t data_size, /* Data buffer max size */
+ const char * msg); /* Value is not used; only IDs */
+
+#endif
diff --git a/groundStation/src/cli/cli.c b/groundStation/src/cli/cli.c
index 139534a4742e4b68b388cd9240d001c257c7fb77..6f258f2e268777d406dc347e6c41f8b137ed9571 100644
--- a/groundStation/src/cli/cli.c
+++ b/groundStation/src/cli/cli.c
@@ -57,7 +57,7 @@ int main(int argc, char **argv)
for (i = 0; i < MAX_COMMANDS; ++i) {
if (strncmp(command, commandNames[i], strlen(commandNames[i])) == 0) {
cmdID = i;
- }
+ }
}
}
@@ -233,4 +233,4 @@ int convert_to_id(struct backend_conn * conn, char **argv, struct convert_data *
}
frontend_free_node_data(search_data, num_nodes);
return search_2;
-}
\ No newline at end of file
+}
diff --git a/groundStation/src/cli/cli.h b/groundStation/src/cli/cli.h
index f91e40fbce9ef8184592b1aa9cfd04d8d415b165..7dca99d7426298353bb7e11154ee27558fa3eba6 100644
--- a/groundStation/src/cli/cli.h
+++ b/groundStation/src/cli/cli.h
@@ -7,6 +7,7 @@
#include "cli_output.h"
#include "cli_nodes.h"
#include "cli_trackable.h"
+#include "cli_override.h"
struct backend_conn;
@@ -20,6 +21,7 @@ enum CommandNameIds{
CMD_ADDNODE,
CMD_GETTRACKABLE,
CMD_SETTRACKABLE,
+ CMD_OUTPUTOVERRIDE,
MAX_COMMANDS
};
@@ -33,7 +35,8 @@ static cli_function_ptr cli_functions[] = {
&cli_getnodes,
&cli_addnode,
&cli_gettrackable,
- &cli_settrackable
+ &cli_settrackable,
+ &cli_outputoverride
};
static char* commandNames[MAX_COMMANDS] = {
@@ -45,7 +48,8 @@ static char* commandNames[MAX_COMMANDS] = {
"getnodes",
"addnode",
"gettrackable",
- "settrackable"
+ "settrackable",
+ "outputoverride"
};
/**
diff --git a/groundStation/src/cli/cli_override.c b/groundStation/src/cli/cli_override.c
new file mode 100644
index 0000000000000000000000000000000000000000..8ee4fe283394a79b9534e138c684fa5c7caf5898
--- /dev/null
+++ b/groundStation/src/cli/cli_override.c
@@ -0,0 +1,34 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <inttypes.h>
+
+#include "cli.h"
+#include "cli_override.h"
+#include "frontend_override.h"
+
+int cli_outputoverride(struct backend_conn * conn, int argc, char ** argv) {
+ int needHelp = 0;
+ struct frontend_override_data values;
+
+ if ((needHelp = help_check(argc, argv))) {
+ printf("outputoverride sets the override state of the hardware platform\n");
+ printf("Usage Syntax : \n\t./Cli outputoverride <enable> Throttle Pitch Roll Yaw \n");
+ return 0;
+ }
+
+ if (argc < 6) {
+ printf("Incorrect Usage, run './cli outputoverride --help' for correct usage.\n");
+ return 1;
+ }
+ int ena;
+ sscanf(argv[1], "%d", &ena); values.enable = ena;
+ sscanf(argv[2], "%f", &values.throttle);
+ sscanf(argv[3], "%f", &values.pitch);
+ sscanf(argv[4], "%f", &values.roll);
+ sscanf(argv[5], "%f", &values.yaw);
+
+ if (frontend_setoutputoverride(conn, &values)) {
+ return 1;
+ }
+ return 0;
+}
diff --git a/groundStation/src/cli/cli_override.h b/groundStation/src/cli/cli_override.h
new file mode 100644
index 0000000000000000000000000000000000000000..ebb8340c572c000a2f663b8b1831418c505be2b0
--- /dev/null
+++ b/groundStation/src/cli/cli_override.h
@@ -0,0 +1,8 @@
+#ifndef _CLI_OVERRIDE_H
+#define _CLI_OVERRIDE_H
+
+#include "frontend_output.h"
+
+int cli_outputoverride(struct backend_conn * conn, int argc, char ** argv);
+
+#endif /* _CLI_OVERRIDE_H */
diff --git a/groundStation/src/frontend/frontend_common.h b/groundStation/src/frontend/frontend_common.h
index 827802875d089908631568fa4d1b713e39569c44..27983cb082dfd725ac7ad788c378d4471f078686 100644
--- a/groundStation/src/frontend/frontend_common.h
+++ b/groundStation/src/frontend/frontend_common.h
@@ -56,6 +56,14 @@ struct frontend_node_data {
char *name;
};
+struct frontend_override_data {
+ int8_t enable;
+ float throttle;
+ float pitch;
+ float roll;
+ float yaw;
+};
+
#ifdef __cplusplus
}
#endif
diff --git a/groundStation/src/frontend/frontend_override.c b/groundStation/src/frontend/frontend_override.c
new file mode 100644
index 0000000000000000000000000000000000000000..aac819df9677628a275ce73fffd66843007ba2e8
--- /dev/null
+++ b/groundStation/src/frontend/frontend_override.c
@@ -0,0 +1,42 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <err.h>
+#include <inttypes.h>
+
+#include "frontend_override.h"
+
+/* Set the override state of outputs
+ *
+ * Returns 0 on success, 1 on error
+ */
+int frontend_setoutputoverride(
+ struct backend_conn * conn,
+ struct frontend_override_data * values) {
+
+ char msg[64] = "";
+ int written;
+
+ snprintf(msg, 64, "outputoverride %" PRId8 " %f %f %f %f\n",
+ values->enable,
+ values->throttle, values->pitch, values->roll, values->yaw);
+
+ if((written = ucart_backendWrite(conn, msg)) < 0) {
+ return 1;
+ }
+
+ size_t pendingResponses = 0;
+ char * response;
+
+ while (pendingResponses) {
+ response = ucart_backendGetline(conn);
+ if (response == NULL) {
+ warnx("Line not returned from backend");
+ return 1;
+ }
+
+
+ }
+
+ return 0;
+}
diff --git a/groundStation/src/frontend/frontend_override.h b/groundStation/src/frontend/frontend_override.h
new file mode 100644
index 0000000000000000000000000000000000000000..53f016d323305afe8b47b9a154d7c4f461023eea
--- /dev/null
+++ b/groundStation/src/frontend/frontend_override.h
@@ -0,0 +1,25 @@
+/**
+ * frontend_output writes the getoutput command to the backend connection.
+ */
+
+#ifndef _FRONTEND_OVERRIDE_H
+#define _FRONTEND_OVERRIDE_H
+
+#include "frontend_common.h"
+
+/* Set the override state of outputs
+ *
+ * Returns 0 on success, 1 on error
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+int frontend_setoutputoverride(
+ struct backend_conn * conn,
+ struct frontend_override_data * values);
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __FRONTEND_OVERRIDE_H */
diff --git a/quad/src/commands/commands.c b/quad/src/commands/commands.c
index 766bb4a909a6d0ac6f6dc69312c4ad092e287265..6b903e33ac04afeec771aa8e4531c160a25ad953 100644
--- a/quad/src/commands/commands.c
+++ b/quad/src/commands/commands.c
@@ -74,9 +74,10 @@ command_cb cb_respnodes __attribute__((weak, alias("cb_default")));
command_cb cb_addnode __attribute__((weak, alias("cb_default")));
command_cb cb_respaddnode __attribute__((weak, alias("cb_default")));
-
command_cb cb_overrideoutput __attribute__((weak, alias("cb_default")));
+command_cb cb_sendrtdata __attribute__((weak, alias("cb_default")));
+
/*
* Command structure.
@@ -265,11 +266,20 @@ struct MessageType MessageTypes[MAX_TYPE_ID] =
// OVERRIDE_OUTPUT
{
// Command text
- "overrideoutput",
+ "outputoverride",
// Type of the command data
stringType,
// Function pointer
&cb_overrideoutput
+ },
+ // SENDRTDATA
+ {
+ // Command text
+ "sendrtdata",
+ // Type of the command data
+ stringType,
+ // Function pointer
+ &cb_sendrtdata
}
};
diff --git a/quad/src/commands/commands.h b/quad/src/commands/commands.h
index 226a9306ff0034b2bdd2b6e3ca60ebc7722e2244..f3af95b73a7238945d66e67e336243d9359f03da 100644
--- a/quad/src/commands/commands.h
+++ b/quad/src/commands/commands.h
@@ -54,7 +54,8 @@ enum MessageTypeID{
ADDNODE_ID, // 17 - Add a node of specified type_id
RESPADDNODE_ID, // 18 - Responding with the block_id of the newly added node
OUTPUT_OVERRIDE_ID, // 19 - Override the outputs from the controller and use provided values instead
- MAX_TYPE_ID // 20 - Just used to keep track of the size. Must remain at the end
+ SEND_RT_ID, // 20 - Real Time sensor data sent to groundstation
+ MAX_TYPE_ID // 21 - Just used to keep track of the size. Must remain at the end
};
struct modular_structs;
diff --git a/quad/src/quad_app/RTSensorPacketDocumentation.md b/quad/src/quad_app/RTSensorPacketDocumentation.md
new file mode 100644
index 0000000000000000000000000000000000000000..e2e534320e0c26cc4abd0f4484800da0af06c5f2
--- /dev/null
+++ b/quad/src/quad_app/RTSensorPacketDocumentation.md
@@ -0,0 +1,151 @@
+#Sensor Data - Real Time
+
+### Sends data in "raw sensor struct"
+
+**NOTE**
+It is important to keep the payload as small as possible. So if the code seems strange, keep in mind NOT to change the payload size to be fixed, even if it would be cleaner or easier to understand
+
+* In the main quad loop, a function is called that is "get sensors". It places stuff in the hardware struct into the raw sensor struct.
+* The hardware struct includes all the drivers for the various sensors on the quadcopter. The get sensors function essentially calls "read" on the drivers and places that info into the raw sensor struct
+* Each driver has these things:
+ * reset function pointer
+ * read function pointer
+ * state void pointer
+
+* The raw sensor struct holds these values
+ * optical flow sensor data (px4flow)
+ * lidar data
+ * imu data (gam struct)
+ * UNUSED gps struct
+ * All these structs have an error variable
+ * called SensorError_t struct
+ * has an error count variable
+
+### Structs for sensors
+* lidar struct
+ * distance the quad is from the ground in meters
+ * float (32 bits)
+
+
+* optical flow struct
+ * All the below are doubles (64 bits)
+ * xy flow
+ * xy filter
+ * xy velocity
+
+* imu data
+ * All the below values are floats (32 bits)
+ * gyroscope data
+ * xyz velocity (angular)
+ * accelerometer data
+ * xyz acceleration
+ * magnetometer data
+ * xyz direction
+
+* actuator data
+ *
+
+* SensorError struct (all the above have this)
+ * Errors
+ * Consecutive Errors
+ * all the above is 32 bits wide
+
+
+
+### Packet structure
+
+#### Groundstation to Quad: Sensor RT Data Configuration Packet
+
+| index | Description | Size |
+|---|---|---|
+| 0 | start char | 1 |
+| 1 + 2 | message type - 20 | 2 |
+| 3 + 4 | message id - 0 | 2 |
+| 5 + 6 | # bytes - 14 | 2 |
+| 7 | first 8 variables (see table) | 1 |
+| 8 | second 8 varibales (see table) | 1 |
+| 9 | last 6 variables (see table) | 1 |
+| 10 | reserved for future use | 1 |
+| end| checksum | 1 |
+
+Bit map:
+
+Payload of configuration packet
+
+MSB (Bit 31) -------- LSB (bit 0)
+|Byte 4| Byte 3| Byte 2| Byte 1|
+
+** Byte 4 **
+
+| bit | Description |
+|---|---|
+| 31 | lidar - distance to ground |
+| 30 | optical flow - x flow|
+| 29 | optical flow - y flow|
+| 28 | optical flow - x filter|
+| 27 | optical flow - y filter|
+| 26 | optical flow - x velocity |
+| 25 | optical flow - y velocity |
+| 24 | gyroscope - x velocity|
+
+
+
+** byte 3 **
+
+| bit | Description |
+|---|---|
+| 23 | gyroscope - y velocity|
+| 22 | gyroscope - z velocity|
+| 21 | accelerometer - x acceleration|
+| 20 | accelerometer - y acceleration|
+| 19 | accelerometer - z acceleration|
+| 18 | magnetometer - x |
+| 17 | magnetometer - y |
+| 16 | magnetometer - z |
+
+
+** byte 2**
+
+| bit | Description |
+|---|---|
+| 15 | lidar err total|
+| 14 | consecutive lidar err|
+| 13 | opt flow error total|
+| 12 | consecutive opt flow error|
+| 11 | imu total errors|
+| 10 | consecutive imu errors|
+| 9 | EMPTY |
+| 8 | EMPTY |
+
+
+** byte 1**
+
+| bit | Description |
+|---|---|
+| 7 | EMPTY |
+| 6 | EMPTY |
+| 5 | EMPTY |
+| 4 | EMPTY |
+| 3 | EMPTY |
+| 2 | EMPTY |
+| 1 | EMPTY |
+| 0 | EMPTY |
+
+
+#### Quad to Groundstation Packet - Contains payload data
+
+| index | 0 | 1 + 2 | 3+4 | 5&6 | ? | end |
+|---|---|---|---|---|---|---|
+| description | start char | msg type - SEND_RT_ID | msg id - 0 | # bytes| payload | checksum |
+| bytes | 1 | 2 | 2 | 2 | variable | 1 |
+
+
+* The packet has a msg type of send_rt_id, which has a value of 20
+* The structure of the payload depends on what variables are selected
+ * See "Checklist" below
+ * There are 22 available things to send, but depending on how much data the user wants sent, the payload will vary
+ * They will be sent in the order listed by the configuration packet
+
+
+
+
diff --git a/quad/src/quad_app/callbacks.c b/quad/src/quad_app/callbacks.c
index 4ca905fb2a4c2a7914760e9dd82cf6150af642d7..3de4b471c7b740e6132772932da128424186e5c6 100644
--- a/quad/src/quad_app/callbacks.c
+++ b/quad/src/quad_app/callbacks.c
@@ -452,5 +452,40 @@ int cb_overrideoutput(struct modular_structs *structs, struct metadata *meta, un
float f = build_float(&data[1+i*4]);
override_info->values[i] = f;
}
+}
+
+int cb_sendrtdata(struct modular_structs *structs, struct metadata *meta, unsigned char *data, unsigned short length) {
+ //Check to ensure sufficient length for rt_data config packet
+ if (length < 4)
+ return -1;
+ int size = 0;
+ u32 configData = (data[2] << 24) | (data[3] << 16) | (data[4] << 8) | (data[5]);
+ structs->flags_struct.lidarflags->quadHeight = read_bit(configData, 31); size += read_bit(configData, 31);
+ /*BEGIN DOUBLE-TYPE FLAGS. If these are enabled, actual size of data sent is 2*read_bit due to
+ * length of data. This needs to be compensated for in methods where total length of payload packet
+ * needs to be known ahead of time. */
+ structs->flags_struct.optflowflags->x_flow = read_bit(configData, 30); size += read_bit(configData, 30);
+ structs->flags_struct.optflowflags->y_flow = read_bit(configData, 29); size += read_bit(configData, 29);
+ structs->flags_struct.optflowflags->x_filter = read_bit(configData, 28); size += read_bit(configData, 28);
+ structs->flags_struct.optflowflags->y_filter = read_bit(configData, 27); size += read_bit(configData, 27);
+ structs->flags_struct.optflowflags->x_velocity = read_bit(configData, 26); size += read_bit(configData, 26);
+ structs->flags_struct.optflowflags->y_velocity = read_bit(configData, 25); size += read_bit(configData, 25);
+ //END DOUBLE TYPE FLAGS.
+ structs->flags_struct.imuflags->gyro_x = read_bit(configData, 24); size += read_bit(configData, 24);
+ structs->flags_struct.imuflags->gyro_y = read_bit(configData, 23); size += read_bit(configData, 23);
+ structs->flags_struct.imuflags->gyro_z = read_bit(configData, 22); size += read_bit(configData, 22);
+ structs->flags_struct.imuflags->acc_x = read_bit(configData, 21); size += read_bit(configData, 21);
+ structs->flags_struct.imuflags->acc_y = read_bit(configData, 20); size += read_bit(configData, 20);
+ structs->flags_struct.imuflags->acc_z = read_bit(configData, 19); size += read_bit(configData, 19);
+ structs->flags_struct.imuflags->mag_x = read_bit(configData, 18); size += read_bit(configData, 18);
+ structs->flags_struct.imuflags->mag_y = read_bit(configData, 17); size += read_bit(configData, 17);
+ structs->flags_struct.imuflags->mag_z = read_bit(configData, 16); size += read_bit(configData, 16);
+ structs->flags_struct.errorflags->lidar = read_bit(configData, 15); size += read_bit(configData, 15);
+ structs->flags_struct.errorflags->consec_lidar = read_bit(configData, 14); size += read_bit(configData, 14);
+ structs->flags_struct.errorflags->optFlow = read_bit(configData, 13); size += read_bit(configData, 13);
+ structs->flags_struct.errorflags->consec_optFlow = read_bit(configData, 12); size += read_bit(configData, 12);
+ structs->flags_struct.errorflags->imu = read_bit(configData, 11); size += read_bit(configData, 11);
+ structs->flags_struct.errorflags->consec_imu = read_bit(configData, 10); size += read_bit(configData, 10);
+ structs->flags_struct.flag_count = size;
return 0;
}
diff --git a/quad/src/quad_app/communication.c b/quad/src/quad_app/communication.c
index 2f0183c984d3ad1d38ff8a07d3f72a8427675481..891c4f94e662fd848e09ca47f31c39dbe333cf38 100644
--- a/quad/src/quad_app/communication.c
+++ b/quad/src/quad_app/communication.c
@@ -20,7 +20,6 @@ void Handler(void *CallBackRef, u32 Event, unsigned int EventData);
u8 packet[MAX_PACKET_SIZE];
int bytes_recv = 0;
-
int try_receive_packet(struct UARTDriver *uart) {
int attempts = 0;
while (attempts++ < MAX_PACKET_SIZE) {
diff --git a/quad/src/quad_app/debug_level_readme.txt b/quad/src/quad_app/debug_level_readme.txt
new file mode 100644
index 0000000000000000000000000000000000000000..49e181c720a7ee1b6df3ea750f345bfe334c83b8
--- /dev/null
+++ b/quad/src/quad_app/debug_level_readme.txt
@@ -0,0 +1,101 @@
+
+DEBUG LEVEL ONE
+
+// Sensor blocks
+ int cur_pitch;
+ int cur_roll;
+ int cur_yaw;
+ int gyro_y;
+ int gyro_x;
+ int gyro_z;
+ int lidar;
+ int flow_vel_x; // optical flow
+ int flow_vel_y;
+ int flow_vel_x_filt;
+ int flow_vel_y_filt;
+ int flow_quality; // Quality value returned by optical flow sensor
+ int flow_distance;
+
+// Sensor processing
+ int yaw_correction;
+ int of_angle_corr; // Corrects for the optical flow mounting angle
+ int of_integ_x; // Integrates the optical flow data
+ int of_integ_y;
+ int of_trim_x; // Trim value for optical flow integrated value
+ int of_trim_y;
+ int of_trimmed_x; // Trimmed optical flow integrated value (of_integ_x + of_trim_x)
+ int of_trimmed_y;
+
+
+DEBUG LEVEL TWO
+
+// PID blocks
+ int roll_pid;
+ int pitch_pid;
+ int yaw_pid;
+ int roll_r_pid;
+ int pitch_r_pid;
+ int yaw_r_pid;
+ int x_pos_pid;
+ int y_pos_pid;
+ int alt_pid;
+
+DEBUG LEVEL THREE
+
+// Velocity nodes
+ int x_vel_pid;
+ int y_vel_pid;
+ int x_vel;
+ int y_vel;
+ int x_vel_clamp;
+ int y_vel_clamp;
+ int vel_x_gain;
+ int vel_y_gain;
+
+ // VRPN blocks
+ int vrpn_x;
+ int vrpn_y;
+ int vrpn_alt;
+ int vrpn_pitch, vrpn_roll;
+
+ // RC blocks
+ int rc_pitch;
+ int rc_roll;
+ int rc_yaw;
+ int rc_throttle;
+
+ // Desired positions
+ int x_set;
+ int y_set;
+ int alt_set;
+ int yaw_set;
+
+DEBUG LEVEL FOUR
+
+
+ // Clamps
+ int clamp_d_pwmP;
+ int clamp_d_pwmR;
+ int clamp_d_pwmY;
+ int yaw_clamp;
+ // Loop times
+ int angle_time;
+ int pos_time;
+
+ // Signal mixer
+ int mixer;
+ int throttle_trim;
+ int throttle_trim_add;
+ int pitch_trim;
+ int pitch_trim_add;
+ int yaw_trim;
+ int yaw_trim_add;
+
+ //psi dot integration chain
+ int psi_dot;
+ int psi_dot_offset;
+ int psi_dot_sum;
+ int psi;
+ int psi_offset;
+ int psi_sum;
+ int mag_yaw; //Complementary filtered magnetometer/gyro yaw
diff --git a/quad/src/quad_app/initialize_components.c b/quad/src/quad_app/initialize_components.c
index 3c8aba206d38df2e15df7a34a96e448c9cbf148f..6eeee7b8854c8e0f044bd28d375fcd35a4f01c94 100644
--- a/quad/src/quad_app/initialize_components.c
+++ b/quad/src/quad_app/initialize_components.c
@@ -49,8 +49,8 @@ int init_structs(modular_structs_t *structs) {
// Initialize the controller
control_algorithm_init(&structs->parameter_struct);
- // Initialize the logging
- initialize_logging(&structs->log_struct, &structs->parameter_struct);
+ // Initialize the logging
+ //initialize_logging(&structs->log_struct, &structs->parameter_struct);
// Initialize loop timers
struct TimerDriver *global_timer = &structs->hardware_struct.global_timer;
@@ -105,6 +105,7 @@ int init_structs(modular_structs_t *structs) {
}
sensor_processing_init(&structs->sensor_struct);
+ initializeFlags(&structs->flags_struct);
structs->override_struct.mode = OVERRIDE_NONE;
int num_overrides = sizeof(structs->override_struct.values)
diff --git a/quad/src/quad_app/log_data.c b/quad/src/quad_app/log_data.c
index e3de87aadcb8bdd0827cd3ea17850406761ca26d..fe8aef14daa9865b5dafd3a68fb8538359de0149 100644
--- a/quad/src/quad_app/log_data.c
+++ b/quad/src/quad_app/log_data.c
@@ -91,12 +91,13 @@ void addParamToLog(log_t* log_struct, int controller_id, int param_id, char* uni
}
}
-void initialize_logging(log_t* log_struct, parameter_t* ps) {
+void initialize_logging(log_t* log_struct, parameter_t* ps, SensorRTFlags_t * flags) {
char* rad = "rad";
char* rad_s = "rad/s";
char* pwm_val = "10ns_dutycycle";
char* m = "m";
char* m_s = "m/s";
+
addOutputToLog(log_struct, ps->alt_pid, PID_CORRECTION, pwm_val);
addOutputToLog(log_struct, ps->x_pos_pid, PID_CORRECTION, rad);
addOutputToLog(log_struct, ps->y_pos_pid, PID_CORRECTION, rad);
@@ -136,8 +137,46 @@ void initialize_logging(log_t* log_struct, parameter_t* ps) {
addParamToLog(log_struct, ps->flow_vel_y, CONST_VAL, m_s);
addParamToLog(log_struct, ps->flow_quality, CONST_VAL, "none");
- // TODO: Make this not stupid. Adding 6 for IMU and 1 for timestamp
- row_size = n_outputs + n_params + 9 + 1;
+ int num_outputs = 0;
+ if (flags->imuflags->acc_x)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->acc_y)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->acc_z)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->gyro_x)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->gyro_y)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->gyro_z)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->mag_x)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->mag_y)
+ {
+ num_outputs++;
+ }
+ if (flags->imuflags->mag_z)
+ {
+ num_outputs++;
+ }
+ //Track number of outputs desired for log utilizing flags struct. Add 1 for timestamp as
+ //time stamp will always be required for any logging.
+ row_size = n_outputs + n_params + num_outputs + 1;
size_t needed_memory = sizeof(float) * row_size * LOG_STARTING_SIZE;
logArray = malloc(needed_memory);
if (!logArray) { // malloc failed
@@ -147,7 +186,7 @@ void initialize_logging(log_t* log_struct, parameter_t* ps) {
}
}
-int log_data(log_t* log_struct, parameter_t* ps)
+int log_data(log_t* log_struct, parameter_t* ps, SensorRTFlags_t * flags)
{
if(arrayIndex >= arraySize)
{
@@ -155,18 +194,45 @@ int log_data(log_t* log_struct, parameter_t* ps)
}
float* thisRow = &logArray[arrayIndex * row_size];
int offset = 0;
- thisRow[offset++] = log_struct->time_stamp;
- thisRow[offset++] = log_struct->gam.accel_x;
- thisRow[offset++] = log_struct->gam.accel_y;
- thisRow[offset++] = log_struct->gam.accel_z;
- thisRow[offset++] = log_struct->gam.gyro_xVel_p;
- thisRow[offset++] = log_struct->gam.gyro_yVel_q;
- thisRow[offset++] = log_struct->gam.gyro_zVel_r;
- thisRow[offset++] = log_struct->gam.mag_x;
- thisRow[offset++] = log_struct->gam.mag_y;
- thisRow[offset++] = log_struct->gam.mag_z;
-
+ //TODO make this not stupid
+ thisRow[offset++] = log_struct->time_stamp;
+ if (flags->imuflags->acc_x)
+ {
+ thisRow[offset++] = log_struct->gam.accel_x;
+ }
+ if (flags->imuflags->acc_y)
+ {
+ thisRow[offset++] = log_struct->gam.accel_y;
+ }
+ if (flags->imuflags->acc_z)
+ {
+ thisRow[offset++] = log_struct->gam.accel_z;
+ }
+ if (flags->imuflags->gyro_x)
+ {
+ thisRow[offset++] = log_struct->gam.gyro_xVel_p;
+ }
+ if (flags->imuflags->gyro_y)
+ {
+ thisRow[offset++] = log_struct->gam.gyro_yVel_q;
+ }
+ if (flags->imuflags->gyro_z)
+ {
+ thisRow[offset++] = log_struct->gam.gyro_zVel_r;
+ }
+ if (flags->imuflags->mag_x)
+ {
+ thisRow[offset++] = log_struct->gam.mag_x;
+ }
+ if (flags->imuflags->mag_y)
+ {
+ thisRow[offset++] = log_struct->gam.mag_y;
+ }
+ if (flags->imuflags->mag_z)
+ {
+ thisRow[offset++] = log_struct->gam.mag_z;
+ }
int i;
for (i = 0; i < n_params; i++) {
thisRow[offset++] = graph_get_param_val(ps->graph, log_params[i].block_id, log_params[i].sub_id);
@@ -174,14 +240,190 @@ int log_data(log_t* log_struct, parameter_t* ps)
for (i = 0; i < n_outputs; i++) {
thisRow[offset++] = graph_get_output(ps->graph, log_outputs[i].block_id, log_outputs[i].sub_id);
}
-
arrayIndex++;
return 0;
}
+void RTprintheader(struct CommDriver *comm, log_t* log_struct, parameter_t* ps, raw_sensor_t* raw_sensors, SensorRTFlags_t * flags) {
+ if (arrayIndex == 0) {
+ // Don't send any logs if nothing was logged
+ return;
+ }
+ else if (flags->flag_count == 0)
+ {
+ //Don't send anything if flags has not been configured or if no data has been requested to be sent.
+ return;
+ }
+ char buf_arr[2560] = {};
+ struct str buf = {.str = buf_arr, .size = 0, .capacity = sizeof(buf_arr)};
+
+ // Let user know that allocation failed
+ if (arraySize != LOG_STARTING_SIZE) {
+ safe_sprintf_cat(&buf, "Failed to allocate enough log memory\n");
+ send_data(comm->uart, LOG_ID, 0, (u8*)buf.str, buf.size);
+ return;
+ }
+
+ int i;
+ // Comment header
+ safe_sprintf_cat(&buf, "# MicroCART On-board Quad Log\n# Sample number: %d\n", arrayIndex);
+ safe_sprintf_cat(&buf, "# IMU IIC failures: %d\n", raw_sensors->gam.error.consErrorCount);
+ safe_sprintf_cat(&buf, "# LiDAR IIC failures: %d\n", raw_sensors->lidar.error.consErrorCount);
+ safe_sprintf_cat(&buf, "# Optical Flow IIC failures: %d\n", raw_sensors->optical_flow.error.consErrorCount);
+
+ // List Pid Constants
+ for (i = 0; i < ps->graph->n_nodes; ++i) {
+ struct graph_node* node = &ps->graph->nodes[i];
+ if (node->type->type_id == BLOCK_PID) {
+ double kp, ki, kd, alpha;
+ kp = graph_get_param_val(ps->graph, i, 0);
+ ki = graph_get_param_val(ps->graph, i, 1);
+ kd = graph_get_param_val(ps->graph, i, 2);
+ alpha = graph_get_param_val(ps->graph, i, 3);
+ safe_sprintf_cat(&buf, "# %s :\tKp = %lf Ki = %lf Kd = %lf Alpha = %lf\n", node->name, kp, ki, kd, alpha);
+ }
+ }
+
+ // TODO make this not stupid
+ safe_sprintf_cat(&buf, "%%Time");
+ if (flags->imuflags->acc_x)
+ {
+ safe_sprintf_cat(&buf, "\taccel_x");
+ }
+ if (flags->imuflags->acc_y)
+ {
+ safe_sprintf_cat(&buf, "\taccel_y");
+ }
+ if (flags->imuflags->acc_z)
+ {
+ safe_sprintf_cat(&buf, "\taccel_z");
+ }
+ if (flags->imuflags->gyro_x)
+ {
+ safe_sprintf_cat(&buf, "\tgyro_x");
+ }
+ if (flags->imuflags->gyro_y)
+ {
+ safe_sprintf_cat(&buf, "\tgyro_y");
+ }
+ if (flags->imuflags->gyro_z)
+ {
+ safe_sprintf_cat(&buf, "\tgyro_z");
+ }
+ if (flags->imuflags->mag_x)
+ {
+ safe_sprintf_cat(&buf, "\tmag_x");
+ }
+ if (flags->imuflags->mag_y)
+ {
+ safe_sprintf_cat(&buf, "\tmag_y_x");
+ }
+ if (flags->imuflags->mag_z)
+ {
+ safe_sprintf_cat(&buf, "\tmag_z");
+ }
+
+ // Print all the recorded block parameters
+ for (i = 0; i < n_params; i++) {
+ const char* block_name = ps->graph->nodes[log_params[i].block_id].name;
+ const char* output_name = ps->graph->nodes[log_params[i].block_id].type->param_names[log_params[i].sub_id];
+ safe_sprintf_cat(&buf, "\t%s_%s", block_name, output_name);
+ }
+ // Print all the recorded block outputs
+ for (i = 0; i < n_outputs; i++) {
+ const char* block_name = ps->graph->nodes[log_outputs[i].block_id].name;
+ const char* param_name = ps->graph->nodes[log_outputs[i].block_id].type->output_names[log_outputs[i].sub_id];
+ safe_sprintf_cat(&buf, "\t%s_%s", block_name, param_name);
+ }
+ safe_sprintf_cat(&buf, "\n");
+
+ // Send header names
+ send_data(comm->uart, LOG_ID, 0, (u8*)buf.str, buf.size);
+
+ // Send units header
+ buf.size = 0;
+
+ safe_sprintf_cat(&buf, "&s"); // The pre-defined ones
+ if (flags->imuflags->acc_x)
+ {
+ safe_sprintf_cat(&buf, "\tG");
+ }
+ if (flags->imuflags->acc_y)
+ {
+ safe_sprintf_cat(&buf, "\tG");
+ }
+ if (flags->imuflags->acc_z)
+ {
+ safe_sprintf_cat(&buf, "\tG");
+ }
+ if (flags->imuflags->gyro_x)
+ {
+ safe_sprintf_cat(&buf, "\trad/s");
+ }
+ if (flags->imuflags->gyro_y)
+ {
+ safe_sprintf_cat(&buf, "\trad/s");
+ }
+ if (flags->imuflags->gyro_z)
+ {
+ safe_sprintf_cat(&buf, "\trad/s");
+ }
+ if (flags->imuflags->mag_x)
+ {
+ safe_sprintf_cat(&buf, "\tuT");
+ }
+ if (flags->imuflags->mag_y)
+ {
+ safe_sprintf_cat(&buf, "\tuT");
+ }
+ if (flags->imuflags->mag_z)
+ {
+ safe_sprintf_cat(&buf, "\tuT");
+ }
+
+ safe_sprintf_cat(&buf, units_output.str);
+ safe_sprintf_cat(&buf, units_param.str);
+ safe_sprintf_cat(&buf, "\n");
+ send_data(comm->uart, LOG_ID, 0, (u8*)buf.str, buf.size);
+}
+
+/**
+ * Print current sensor info to log file. This data is held at the current ArrayIndex entry of the log_struct.
+ */
+void RTprintLogging(struct CommDriver *comm, log_t* log_struct, parameter_t* ps, raw_sensor_t* raw_sensors, SensorRTFlags_t * flags){
+ if (arrayIndex == 0)
+ {
+ return;
+ }
+ else if (flags->flag_count == 0)
+ {
+ //Don't send anything if flags has not been configured or if no data has been requested to be sent.
+ return;
+ }
+ char buf_arr[2560] = {};
+ struct str buf = {.str = buf_arr, .size = 0, .capacity = sizeof(buf_arr)};
+ //Send only the most previous log data.
+ format_log(arrayIndex - 1, log_struct, &buf);
+ send_data(comm->uart, LOG_ID, 0, (u8*)buf.str, buf.size);
+ // This is a stupid hack because if the axi timer is not reset in awhile, it always returns 0, and the timer_end_loop() call hangs forever after a long log
+ // Not 100% certain this works
+ timer_axi_reset();
+}
+
+void RTprintend(struct CommDriver *comm)
+{
+ if (arrayIndex == 0)
+ {
+ return;
+ }
+ char buf_arr[2560] = {};
+ struct str buf = {.str = buf_arr, .size = 0, .capacity = sizeof(buf_arr)};
+ // Empty message of type LOG_END to indicate end of log
+ send_data(comm->uart, LOG_END_ID, 0, (u8*)buf.str, 0);
+}
/**
- * Prints all the log information.
+ * Prints all the log information. Currently replaced by the RTprintglogging method.
*
* TODO: This should probably be transmitting in binary instead of ascii
*/
@@ -203,7 +445,7 @@ void printLogging(struct CommDriver *comm, log_t* log_struct, parameter_t* ps, r
int i;
// Comment header
- safe_sprintf_cat(&buf, "# MicroCART On-board Quad Log\n# Sample size: %d\n", arrayIndex);
+ safe_sprintf_cat(&buf, "# MicroCART On-board Quad Log\n# Sample number: %d\n", arrayIndex);
safe_sprintf_cat(&buf, "# IMU IIC failures: %d\n", raw_sensors->gam.error.consErrorCount);
safe_sprintf_cat(&buf, "# LiDAR IIC failures: %d\n", raw_sensors->lidar.error.consErrorCount);
safe_sprintf_cat(&buf, "# Optical Flow IIC failures: %d\n", raw_sensors->optical_flow.error.consErrorCount);
@@ -218,7 +460,6 @@ void printLogging(struct CommDriver *comm, log_t* log_struct, parameter_t* ps, r
kd = graph_get_param_val(ps->graph, i, 2);
alpha = graph_get_param_val(ps->graph, i, 3);
safe_sprintf_cat(&buf, "# %s :\tKp = %lf Ki = %lf Kd = %lf Alpha = %lf\n", node->name, kp, ki, kd, alpha);
-
}
}
@@ -283,3 +524,25 @@ void format_log(int idx, log_t* log_struct, struct str* buf) {
}
safe_sprintf_cat(buf, "\n");
}
+
+/*
+ Initially sets it so that all debug values are zero
+*/
+void initializeFlags(SensorRTFlags_t * flags) {
+
+ flags = calloc(1, sizeof(SensorRTFlags_t));
+ flags -> imuflags = calloc(1, sizeof(IMUFlags_t));
+ flags -> optflowflags = calloc(1, sizeof(OptFlowFlags_t));
+ flags -> lidarflags = calloc(1, sizeof(lidarFlags_t));
+ flags -> errorflags = calloc(1, sizeof(SensorErrorFlags_t));
+ flags -> flag_count = 0;
+}
+
+void freeFlags(SensorRTFlags_t * flags){
+ free(flags -> imuflags);
+ free(flags -> optflowflags);
+ free(flags -> lidarflags);
+ free(flags -> errorflags);
+ free(flags -> flag_count);
+ free(flags);
+}
diff --git a/quad/src/quad_app/log_data.h b/quad/src/quad_app/log_data.h
index 9c4b8b7d9cf61f9d86bca21543100b5c48fdb38f..b7271752413895bd2eebca149dc34ab8b2cc6d4f 100644
--- a/quad/src/quad_app/log_data.h
+++ b/quad/src/quad_app/log_data.h
@@ -13,7 +13,7 @@
// Maximum number of block outputs you can record, and maximum number of block parameters to record
#define MAX_LOG_NUM 50
-void initialize_logging(log_t* log_struct, parameter_t* ps);
+void initialize_logging(log_t* log_struct, parameter_t* ps, SensorRTFlags_t * flags);
/**
* Adds the given block output to the data to be logged
@@ -37,13 +37,28 @@ void addParamToLog(log_t* log_struct, int controller_id, int param_id, char* uni
* error message
*
*/
- int log_data(log_t* log_struct, parameter_t* ps);
+ int log_data(log_t* log_struct, parameter_t* ps, SensorRTFlags_t * flags);
/**
* Fills up an xbox hueg amount of memory with log data
*/
void updateLog(log_t log_struct);
+/**
+ * Prints the latest log entry. Used for Real-Time Data Transfer
+ */
+void RTprintLogging(struct CommDriver *comm, log_t* log_struct, parameter_t* ps, raw_sensor_t* raw_sensors, SensorRTFlags_t * flags);
+/**
+ * Prints the beginning header for a flight data file. Used for Real-Time Data Transfer
+ * */
+void RTprintheader(struct CommDriver *comm, log_t* log_struct, parameter_t* ps, raw_sensor_t* raw_sensors, SensorRTFlags_t * flags);
+
+/**
+ * Sends the required ending message to close a log file following the end of a flight. Used for
+ * Real-Time Data Transfer
+ * */
+void RTprintend(struct CommDriver *comm);
+
/**
* Prints all the log information.
*/
diff --git a/quad/src/quad_app/quad_app.c b/quad/src/quad_app/quad_app.c
index f3b284ef8026be6dd79dee1c9ac5a608534adc28..b605081d56c864739935cbbe731e712a1b8d9ad4 100644
--- a/quad/src/quad_app/quad_app.c
+++ b/quad/src/quad_app/quad_app.c
@@ -9,6 +9,7 @@
#include "log_data.h"
#include "initialize_components.h"
#include "user_input.h"
+#include "log_data.h"
#include "sensor.h"
#include "sensor_processing.h"
#include "control_algorithm.h"
@@ -19,9 +20,9 @@
int quad_main(int (*setup_hardware)(hardware_t *hardware_struct))
{
+ u8 init_cond = 0x0;
// Structures to be used throughout
modular_structs_t structs = { };
-
// Wire up hardware
setup_hardware(&structs.hardware_struct);
@@ -30,6 +31,7 @@ int quad_main(int (*setup_hardware)(hardware_t *hardware_struct))
// Xilinx Platform, Loop Timer, Control Algorithm
int init_error = init_structs(&(structs));
+
if (init_error != 0) {
return -1;
}
@@ -38,7 +40,7 @@ int quad_main(int (*setup_hardware)(hardware_t *hardware_struct))
protection_loops(&structs);
int last_kill_condition = kill_condition(&(structs.user_input_struct));
-
+
// Main control loop
while (1)
{
@@ -59,24 +61,34 @@ int quad_main(int (*setup_hardware)(hardware_t *hardware_struct))
// Process the sensor data and put it into sensor_struct
sensor_processing(&(structs.log_struct), &(structs.user_input_struct), &(structs.raw_sensor_struct), &(structs.sensor_struct));
-
+
+
if (!this_kill_condition) {
// Run the control algorithm
control_algorithm(&(structs.log_struct), &(structs.user_input_struct), &(structs.sensor_struct), &(structs.setpoint_struct),
&(structs.parameter_struct), &(structs.user_defined_struct), &(structs.actuator_command_struct), &structs);
-
do_output_override(&(structs.log_struct), &(structs.override_struct), &(structs.actuator_command_struct));
+
+ //print the actuator commands
+
// send the actuator commands
- send_actuator_commands(&(structs.hardware_struct.motors), &(structs.log_struct), &(structs.actuator_command_struct));
- }
- else {
+ send_actuator_commands(&(structs.hardware_struct.motors),
+ &(structs.log_struct), &(structs.actuator_command_struct));
+ } else {
kill_motors(&(structs.hardware_struct.motors));
}
+
if (!this_kill_condition) {
// Log the data collected in this loop
- log_data(&(structs.log_struct), &(structs.parameter_struct));
-
+ if (init_cond == 0x0)
+ {
+ init_cond = 0x1;
+ initialize_logging(&(structs.log_struct), &(structs.parameter_struct), &(structs.flags_struct));
+ RTprintheader(&(structs.hardware_struct.comm), &(structs.log_struct), &(structs.parameter_struct), &(structs.raw_sensor_struct), &(structs.flags_struct));
+ }
+ log_data(&(structs.log_struct), &(structs.parameter_struct), &(structs.flags_struct));
+ RTprintLogging(&(structs.hardware_struct.comm), &(structs.log_struct), &(structs.parameter_struct), &structs.raw_sensor_struct, &(structs.flags_struct));
if(structs.user_defined_struct.flight_mode == AUTO_FLIGHT_MODE)
{
static int loop_counter = 0;
@@ -101,8 +113,7 @@ int quad_main(int (*setup_hardware)(hardware_t *hardware_struct))
}
if (this_kill_condition == 1 && last_kill_condition == 0) {
- // Just disabled
- printLogging(&structs.hardware_struct.comm, &(structs.log_struct), &(structs.parameter_struct), &structs.raw_sensor_struct);
+ RTprintend(&(structs.hardware_struct.comm));
resetLogging();
MIO7_led_off();
}
@@ -116,7 +127,10 @@ int quad_main(int (*setup_hardware)(hardware_t *hardware_struct))
kill_motors(&(structs.hardware_struct.motors));
char err_msg[] = "More than 10 IMU errors";
send_data(structs.hardware_struct.comm.uart, DEBUG_ID, 0, (u8*)err_msg, sizeof(err_msg));
- printLogging(&structs.hardware_struct.comm, &(structs.log_struct), &(structs.parameter_struct), &structs.raw_sensor_struct);
+ //Send end of log message. Uncomment printLogging below for post-flight log.
+ RTprintend(&(structs.hardware_struct.comm));
+ resetLogging();
+ //printLogging(&structs.hardware_struct.comm, &(structs.log_struct), &(structs.parameter_struct), &structs.raw_sensor_struct);
break;
}
}
diff --git a/quad/src/quad_app/sensor.c b/quad/src/quad_app/sensor.c
index 6ae875ce931c2ac931de5c18f427acdf85d0fa1a..3c0dd036519997b41477a09444d72bfa2e7e7a73 100644
--- a/quad/src/quad_app/sensor.c
+++ b/quad/src/quad_app/sensor.c
@@ -52,7 +52,7 @@ int get_sensors(hardware_t *hardware_struct, log_t* log_struct, user_input_t* us
status = lidar->read(lidar, &lidar_val);
updateError(&(raw_sensor_struct->lidar.error), status);
if (status == 0) {
- raw_sensor_struct->lidar_distance_m = lidar_val.distance_m;
+ raw_sensor_struct->lidar.distance_m = lidar_val.distance_m;
}
status = of->read(of, &raw_sensor_struct->optical_flow);
diff --git a/quad/src/quad_app/sensor_processing.c b/quad/src/quad_app/sensor_processing.c
index e91da27f5910fa10ad241d64f6f904735aaa9806..29bccdee95510abfbc62c170945a7a6450a7f826 100644
--- a/quad/src/quad_app/sensor_processing.c
+++ b/quad/src/quad_app/sensor_processing.c
@@ -230,7 +230,7 @@ int sensor_processing(log_t* log_struct, user_input_t *user_input_struct, raw_se
+ (1. - ALPHA) * accel_roll;
// Z-axis points upward, so negate distance
- //sensor_struct->lidar_altitude = -raw_sensor_struct->lidar_distance_m;
+ //sensor_struct->lidar_altitude = -raw_sensor_struct->lidar->distance_m;
//-------- Optical flow -----------//
@@ -238,7 +238,7 @@ int sensor_processing(log_t* log_struct, user_input_t *user_input_struct, raw_se
sensor_struct->optical_flow = raw_sensor_struct->optical_flow;
flow_gyro_compensation(sensor_struct,
- raw_sensor_struct->lidar_distance_m,
+ raw_sensor_struct->lidar.distance_m,
sensor_struct->roll_angle_filtered,
sensor_struct->pitch_angle_filtered,
sensor_struct->psi_dot);
@@ -258,7 +258,7 @@ int sensor_processing(log_t* log_struct, user_input_t *user_input_struct, raw_se
static float filtered_alt = 0;
static float last_lidar = 0;
- float this_lidar = -raw_sensor_struct->lidar_distance_m;
+ float this_lidar = -raw_sensor_struct->lidar.distance_m;
if(this_lidar < (-MAX_VALID_LIDAR)) {
this_lidar = filtered_alt;
}
diff --git a/quad/src/quad_app/type_def.h b/quad/src/quad_app/type_def.h
index 6cf91b43a00a458be1ca468057f4f6c32a49ba98..8ffcea2c69c72211c8233dd895d42258700a7601 100644
--- a/quad/src/quad_app/type_def.h
+++ b/quad/src/quad_app/type_def.h
@@ -52,6 +52,7 @@ typedef struct commands{
typedef struct raw{
int x,y,z;
}raw;
+
typedef struct PID_Consts{
float P, I, D;
}PID_Consts;
@@ -140,6 +141,7 @@ typedef struct px4flow {
SensorError_t error;
} px4flow_t;
+/** is this used??? */
typedef struct gps {
double lat, lon;
double vel, course;
@@ -245,41 +247,15 @@ typedef struct log_t {
*
*/
typedef struct raw_sensor {
- int acc_x; // accelerometer x data
- int acc_x_t; // time of accelerometer x data
-
- int acc_y; // accelerometer y data
- int acc_y_t; // time of accelerometer y data
-
- int acc_z; // accelerometer z data
- int acc_z_t; // time of accelerometer z data
-
-
- int gyr_x; // gyroscope x data
- int gyr_x_t; // time of gyroscope x data
-
- int gyr_y; // gyroscope y data
- int gyr_y_t; // time of gyroscope y data
-
- int gyr_z; // gyroscope z data
- int gyr_z_t; // time of gyroscope z data
-
- int ldr_z; //lidar z data (altitude)
- int ldr_z_t; //time of lidar z data
gam_t gam;
-
lidar_t lidar;
-
+ px4flow_t optical_flow;
// Structures to hold the current quad position & orientation
+ // This is mostly unused?
quadPosition_t currentQuadPosition;
- // Distance from the ground, in meters, that the quadcopter is.
- // Ideally equals 0 when landed
- float lidar_distance_m;
-
- // Information obtained from optical flow sensor
- px4flow_t optical_flow;
+
} raw_sensor_t;
@@ -502,7 +478,7 @@ typedef struct hardware_t {
} hardware_t;
typedef enum {
- OVERRIDE_NONE, // 0 Use controller output
+ OVERRIDE_NONE, // 0 Use controller output
OVERRIDE_ALL // 1 Use override values
} override_mode_t;
@@ -511,6 +487,64 @@ typedef struct override_t {
float values[4];
} override_t;
+/* BEGIN FLAG STRUCTS CONTAINING ENABLED/DISABLED RT DATA TRANSFERS */
+typedef struct lidarFlags
+{
+ int quadHeight;
+
+} lidarFlags_t;
+
+typedef struct IMUFlags
+{
+ int gyro_x;
+ int gyro_y;
+ int gyro_z;
+ int acc_x;
+ int acc_y;
+ int acc_z;
+ int mag_x;
+ int mag_y;
+ int mag_z;
+
+} IMUFlags_t;
+
+typedef struct OptFlowFlags
+{
+ int x_flow;
+ int y_flow;
+ int x_filter;
+ int y_filter;
+ int x_velocity;
+ int y_velocity;
+
+} OptFlowFlags_t;
+
+typedef struct SensorErrorFlags
+{
+ int consec_lidar;
+ int consec_imu;
+ int consec_optFlow;
+ int lidar;
+ int imu;
+ int optFlow;
+
+} SensorErrorFlags_t;
+
+/*
+ This struct contains all of the above pre-defined flag structs. For use in RT data logging configuration
+*/
+typedef struct SensorRTFlags
+{
+ IMUFlags_t * imuflags;
+ OptFlowFlags_t * optflowflags;
+ lidarFlags_t * lidarflags;
+ SensorErrorFlags_t * errorflags;
+ int flag_count;
+
+} SensorRTFlags_t;
+
+/* END FLAG STRUCTS */
+
/**
* @brief
* Structures to be used throughout
@@ -527,8 +561,10 @@ typedef struct modular_structs {
actuator_command_t actuator_command_struct;
hardware_t hardware_struct;
override_t override_struct;
+ SensorRTFlags_t flags_struct;
} modular_structs_t;
+
//////// END MAIN MODULAR STRUCTS
#endif /* TYPE_DEF_H_ */
diff --git a/quad/src/quad_app/util.c b/quad/src/quad_app/util.c
index 698d453c7734dc2fd4dd5975d722fcdfa2ac6581..9507faae367f8eba4bc161e47c05d6333b07f601 100644
--- a/quad/src/quad_app/util.c
+++ b/quad/src/quad_app/util.c
@@ -121,3 +121,12 @@ void pack_short(int16_t val, u8* buff) {
void pack_float(float val, u8* buff) {
memcpy(buff, &val, sizeof(val));
}
+
+/*
+ Helper to return single bit of u32 data. This returns the "position"'th bit of the given u32,
+ assuming it is Zero indexed.
+*/
+u32 read_bit(u32 data, int position) {
+ return (data >> position) & 1;
+}
+
diff --git a/quad/src/quad_app/util.h b/quad/src/quad_app/util.h
index d675428293bc3108673bf953f78e089f8877caea..f3e87401478dac45cef99f6373e24a00dddbc544 100644
--- a/quad/src/quad_app/util.h
+++ b/quad/src/quad_app/util.h
@@ -24,5 +24,6 @@ int16_t build_short(u8* buff);
void pack_short(int16_t val, u8* buff);
void pack_float(float val, u8* buff);
+u32 read_bit(u32 data, int position);
#endif //_UTIL_H
diff --git a/quad/vivado_workspace/quad_hw.tcl b/quad/vivado_workspace/quad_hw.tcl
index a34e1e0e27eb6d4499ffe03a695560a28cc2c56d..8fca7d74d082b521eadc5d83cfbb7d89615fe804 100644
--- a/quad/vivado_workspace/quad_hw.tcl
+++ b/quad/vivado_workspace/quad_hw.tcl
@@ -37,7 +37,7 @@ set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
- set origin_dir $::origin_dir_loc
+ set origin_dir $::origin_dir_loc
}
# Set the project name
@@ -45,7 +45,7 @@ set _xil_proj_name_ "quad_hw"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
- set _xil_proj_name_ $::user_project_name
+ set _xil_proj_name_ $::user_project_name
}
variable script_file
@@ -53,47 +53,47 @@ set script_file "quad_hw.tcl"
# Help information for this script
proc help {} {
- variable script_file
- puts "\nDescription:"
- puts "Recreate a Vivado project from this script. The created project will be"
- puts "functionally equivalent to the original project for which this script was"
- puts "generated. The script contains commands for creating a project, filesets,"
- puts "runs, adding/importing sources and setting properties on various objects.\n"
- puts "Syntax:"
- puts "$script_file"
- puts "$script_file -tclargs \[--origin_dir <path>\]"
- puts "$script_file -tclargs \[--project_name <name>\]"
- puts "$script_file -tclargs \[--help\]\n"
- puts "Usage:"
- puts "Name Description"
- puts "-------------------------------------------------------------------------"
- puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
- puts " origin_dir path value is \".\", otherwise, the value"
- puts " that was set with the \"-paths_relative_to\" switch"
- puts " when this script was generated.\n"
- puts "\[--project_name <name>\] Create project with the specified name. Default"
- puts " name is the name of the project from where this"
- puts " script was generated.\n"
- puts "\[--help\] Print help information for this script"
- puts "-------------------------------------------------------------------------\n"
- exit 0
+ variable script_file
+ puts "\nDescription:"
+ puts "Recreate a Vivado project from this script. The created project will be"
+ puts "functionally equivalent to the original project for which this script was"
+ puts "generated. The script contains commands for creating a project, filesets,"
+ puts "runs, adding/importing sources and setting properties on various objects.\n"
+ puts "Syntax:"
+ puts "$script_file"
+ puts "$script_file -tclargs \[--origin_dir <path>\]"
+ puts "$script_file -tclargs \[--project_name <name>\]"
+ puts "$script_file -tclargs \[--help\]\n"
+ puts "Usage:"
+ puts "Name Description"
+ puts "-------------------------------------------------------------------------"
+ puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
+ puts " origin_dir path value is \".\", otherwise, the value"
+ puts " that was set with the \"-paths_relative_to\" switch"
+ puts " when this script was generated.\n"
+ puts "\[--project_name <name>\] Create project with the specified name. Default"
+ puts " name is the name of the project from where this"
+ puts " script was generated.\n"
+ puts "\[--help\] Print help information for this script"
+ puts "-------------------------------------------------------------------------\n"
+ exit 0
}
if { $::argc > 0 } {
- for {set i 0} {$i < $::argc} {incr i} {
- set option [string trim [lindex $::argv $i]]
- switch -regexp -- $option {
- "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
- "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
- "--help" { help }
- default {
- if { [regexp {^-} $option] } {
- puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
- return 1
- }
- }
+ for {set i 0} {$i < $::argc} {incr i} {
+ set option [string trim [lindex $::argv $i]]
+ switch -regexp -- $option {
+ "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
+ "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+ "--help" { help }
+ default {
+ if { [regexp {^-} $option] } {
+ puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+ return 1
+ }
+ }
+ }
}
- }
}
# Set the directory path for the original project from where this script was exported
@@ -149,7 +149,7 @@ set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
- create_fileset -srcset sources_1
+ create_fileset -srcset sources_1
}
# Set IP repository paths
@@ -170,7 +170,7 @@ set_property -name "top_auto_set" -value "0" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
- create_fileset -constrset constrs_1
+ create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
@@ -184,7 +184,7 @@ set obj [get_filesets constrs_1]
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
- create_fileset -simset sim_1
+ create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
@@ -204,20 +204,20 @@ set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
# Proc to create BD design_1
proc cr_bd_design_1 { parentCell } {
- # CHANGE DESIGN NAME HERE
- set design_name design_1
+ # CHANGE DESIGN NAME HERE
+ set design_name design_1
- common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+ common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
- create_bd_design $design_name
+ create_bd_design $design_name
- set bCheckIPsPassed 1
- ##################################################################
- # CHECK IPs
- ##################################################################
- set bCheckIPs 1
- if { $bCheckIPs == 1 } {
- set list_check_ips "\
+ set bCheckIPsPassed 1
+ ##################################################################
+ # CHECK IPs
+ ##################################################################
+ set bCheckIPs 1
+ if { $bCheckIPs == 1 } {
+ set list_check_ips "\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_timer:2.0\
xilinx.com:ip:processing_system7:5.5\
@@ -226,713 +226,708 @@ proc cr_bd_design_1 { parentCell } {
xilinx.com:ip:proc_sys_reset:5.0\
"
- set list_ips_missing ""
- common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
-
- foreach ip_vlnv $list_check_ips {
- set ip_obj [get_ipdefs -all $ip_vlnv]
- if { $ip_obj eq "" } {
- lappend list_ips_missing $ip_vlnv
- }
- }
-
- if { $list_ips_missing ne "" } {
- catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
- set bCheckIPsPassed 0
- }
-
- }
-
- if { $bCheckIPsPassed != 1 } {
- common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
- return 3
- }
-
- variable script_folder
-
- if { $parentCell eq "" } {
- set parentCell [get_bd_cells /]
- }
-
- # Get object for parentCell
- set parentObj [get_bd_cells $parentCell]
- if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
- return
- }
-
- # Make sure parentObj is hier blk
- set parentType [get_property TYPE $parentObj]
- if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
- return
- }
-
- # Save current instance; Restore later
- set oldCurInst [current_bd_instance .]
-
- # Set parent object as current
- current_bd_instance $parentObj
-
-
- # Create interface ports
- set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
- set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
- set I2C0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C0 ]
- set I2C1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C1 ]
- set UART0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART0 ]
- set UART1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART1 ]
- set btns_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 btns_4bits ]
- set leds_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 leds_4bits ]
- set rgb_led [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rgb_led ]
- set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ]
-
- # Create ports
- set pwm_in_0 [ create_bd_port -dir I pwm_in_0 ]
- set pwm_in_1 [ create_bd_port -dir I pwm_in_1 ]
- set pwm_in_2 [ create_bd_port -dir I pwm_in_2 ]
- set pwm_in_3 [ create_bd_port -dir I pwm_in_3 ]
- set pwm_in_4 [ create_bd_port -dir I pwm_in_4 ]
- set pwm_in_5 [ create_bd_port -dir I pwm_in_5 ]
- set pwm_out_0 [ create_bd_port -dir O pwm_out_0 ]
- set pwm_out_1 [ create_bd_port -dir O pwm_out_1 ]
- set pwm_out_2 [ create_bd_port -dir O pwm_out_2 ]
- set pwm_out_3 [ create_bd_port -dir O pwm_out_3 ]
-
- # Create instance: axi_gpio_3, and set properties
- set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ]
- set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {rgb_led} \
- CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_3
-
- # Create instance: axi_gpio_btns, and set properties
- set axi_gpio_btns [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_btns ]
- set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {btns_4bits} \
- CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_btns
-
- # Create instance: axi_gpio_leds, and set properties
- set axi_gpio_leds [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_leds ]
- set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {leds_4bits} \
- CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_leds
-
- # Create instance: axi_gpio_sws, and set properties
- set axi_gpio_sws [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sws ]
- set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {sws_4bits} \
- CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_sws
-
- # Create instance: axi_timer_0, and set properties
- set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
-
- # Create instance: processing_system7_0, and set properties
- set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
- set_property -dict [ list \
- CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
- CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
- CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
- CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
- CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
- CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_CLK0_FREQ {100000000} \
- CONFIG.PCW_CLK1_FREQ {10000000} \
- CONFIG.PCW_CLK2_FREQ {10000000} \
- CONFIG.PCW_CLK3_FREQ {10000000} \
- CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
- CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
- CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
- CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
- CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
- CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
- CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
- CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
- CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
- CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
- CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
- CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
- CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
- CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
- CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
- CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
- CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
- CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
- CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET0_RESET_ENABLE {0} \
- CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET1_RESET_ENABLE {0} \
- CONFIG.PCW_ENET_RESET_ENABLE {1} \
- CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
- CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_EN_4K_TIMER {0} \
- CONFIG.PCW_EN_EMIO_I2C0 {1} \
- CONFIG.PCW_EN_EMIO_I2C1 {1} \
- CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
- CONFIG.PCW_EN_EMIO_UART0 {1} \
- CONFIG.PCW_EN_EMIO_UART1 {1} \
- CONFIG.PCW_EN_ENET0 {1} \
- CONFIG.PCW_EN_GPIO {1} \
- CONFIG.PCW_EN_I2C0 {1} \
- CONFIG.PCW_EN_I2C1 {1} \
- CONFIG.PCW_EN_MODEM_UART0 {0} \
- CONFIG.PCW_EN_QSPI {1} \
- CONFIG.PCW_EN_SDIO0 {1} \
- CONFIG.PCW_EN_UART0 {1} \
- CONFIG.PCW_EN_UART1 {1} \
- CONFIG.PCW_EN_USB0 {1} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
- CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
- CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
- CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
- CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
- CONFIG.PCW_I2C0_I2C0_IO {EMIO} \
- CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_I2C0_RESET_ENABLE {0} \
- CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
- CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
- CONFIG.PCW_I2C1_I2C1_IO {EMIO} \
- CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_I2C1_RESET_ENABLE {0} \
- CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
- CONFIG.PCW_I2C_RESET_ENABLE {1} \
- CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
- CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
- CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
- CONFIG.PCW_MIO_0_DIRECTION {inout} \
- CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_0_PULLUP {enabled} \
- CONFIG.PCW_MIO_0_SLEW {slow} \
- CONFIG.PCW_MIO_10_DIRECTION {inout} \
- CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_10_PULLUP {enabled} \
- CONFIG.PCW_MIO_10_SLEW {slow} \
- CONFIG.PCW_MIO_11_DIRECTION {inout} \
- CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_11_PULLUP {enabled} \
- CONFIG.PCW_MIO_11_SLEW {slow} \
- CONFIG.PCW_MIO_12_DIRECTION {inout} \
- CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_12_PULLUP {enabled} \
- CONFIG.PCW_MIO_12_SLEW {slow} \
- CONFIG.PCW_MIO_13_DIRECTION {inout} \
- CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_13_PULLUP {enabled} \
- CONFIG.PCW_MIO_13_SLEW {slow} \
- CONFIG.PCW_MIO_14_DIRECTION {inout} \
- CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_14_PULLUP {enabled} \
- CONFIG.PCW_MIO_14_SLEW {slow} \
- CONFIG.PCW_MIO_15_DIRECTION {inout} \
- CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_15_PULLUP {enabled} \
- CONFIG.PCW_MIO_15_SLEW {slow} \
- CONFIG.PCW_MIO_16_DIRECTION {out} \
- CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_16_PULLUP {enabled} \
- CONFIG.PCW_MIO_16_SLEW {fast} \
- CONFIG.PCW_MIO_17_DIRECTION {out} \
- CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_17_PULLUP {enabled} \
- CONFIG.PCW_MIO_17_SLEW {fast} \
- CONFIG.PCW_MIO_18_DIRECTION {out} \
- CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_18_PULLUP {enabled} \
- CONFIG.PCW_MIO_18_SLEW {fast} \
- CONFIG.PCW_MIO_19_DIRECTION {out} \
- CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_19_PULLUP {enabled} \
- CONFIG.PCW_MIO_19_SLEW {fast} \
- CONFIG.PCW_MIO_1_DIRECTION {out} \
- CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_1_PULLUP {enabled} \
- CONFIG.PCW_MIO_1_SLEW {slow} \
- CONFIG.PCW_MIO_20_DIRECTION {out} \
- CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_20_PULLUP {enabled} \
- CONFIG.PCW_MIO_20_SLEW {fast} \
- CONFIG.PCW_MIO_21_DIRECTION {out} \
- CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_21_PULLUP {enabled} \
- CONFIG.PCW_MIO_21_SLEW {fast} \
- CONFIG.PCW_MIO_22_DIRECTION {in} \
- CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_22_PULLUP {enabled} \
- CONFIG.PCW_MIO_22_SLEW {fast} \
- CONFIG.PCW_MIO_23_DIRECTION {in} \
- CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_23_PULLUP {enabled} \
- CONFIG.PCW_MIO_23_SLEW {fast} \
- CONFIG.PCW_MIO_24_DIRECTION {in} \
- CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_24_PULLUP {enabled} \
- CONFIG.PCW_MIO_24_SLEW {fast} \
- CONFIG.PCW_MIO_25_DIRECTION {in} \
- CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_25_PULLUP {enabled} \
- CONFIG.PCW_MIO_25_SLEW {fast} \
- CONFIG.PCW_MIO_26_DIRECTION {in} \
- CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_26_PULLUP {enabled} \
- CONFIG.PCW_MIO_26_SLEW {fast} \
- CONFIG.PCW_MIO_27_DIRECTION {in} \
- CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_27_PULLUP {enabled} \
- CONFIG.PCW_MIO_27_SLEW {fast} \
- CONFIG.PCW_MIO_28_DIRECTION {inout} \
- CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_28_PULLUP {enabled} \
- CONFIG.PCW_MIO_28_SLEW {fast} \
- CONFIG.PCW_MIO_29_DIRECTION {in} \
- CONFIG.PCW_MIO_29_IOTYPE {LVCMO
- CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_2_PULLUP {disablS 1.8V} \
- CONFIG.PCW_MIO_29_PULLUP {enabled} \
- CONFIG.PCW_MIO_29_SLEW {fast} \
- CONFIG.PCW_MIO_2_DIRECTION {inout} \
- CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_2_PULLUP {disabled} \
- CONFIG.PCW_MIO_2_SLEW {slow} \
- CONFIG.PCW_MIO_30_DIRECTION {out} \
- CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_30_PULLUP {enabled} \
- CONFIG.PCW_MIO_30_SLEW {fast} \
- CONFIG.PCW_MIO_31_DIRECTION {in} \
- CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_31_PULLUP {enabled} \
- CONFIG.PCW_MIO_31_SLEW {fast} \
- CONFIG.PCW_MIO_32_DIRECTION {inout} \
- CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_32_PULLUP {enabled} \
- CONFIG.PCW_MIO_32_SLEW {fast} \
- CONFIG.PCW_MIO_33_DIRECTION {inout} \
- CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_33_PULLUP {enabled} \
- CONFIG.PCW_MIO_33_SLEW {fast} \
- CONFIG.PCW_MIO_34_DIRECTION {inout} \
- CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_34_PULLUP {enabled} \
- CONFIG.PCW_MIO_34_SLEW {fast} \
- CONFIG.PCW_MIO_35_DIRECTION {inout} \
- CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_35_PULLUP {enabled} \
- CONFIG.PCW_MIO_35_SLEW {fast} \
- CONFIG.PCW_MIO_36_DIRECTION {in} \
- CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_36_PULLUP {enabled} \
- CONFIG.PCW_MIO_36_SLEW {fast} \
- CONFIG.PCW_MIO_37_DIRECTION {inout} \
- CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_37_PULLUP {enabled} \
- CONFIG.PCW_MIO_37_SLEW {fast} \
- CONFIG.PCW_MIO_38_DIRECTION {inout} \
- CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_38_PULLUP {enabled} \
- CONFIG.PCW_MIO_38_SLEW {fast} \
- CONFIG.PCW_MIO_39_DIRECTION {inout} \
- CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_39_PULLUP {enabled} \
- CONFIG.PCW_MIO_39_SLEW {fast} \
- CONFIG.PCW_MIO_3_DIRECTION {inout} \
- CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_3_PULLUP {disabled} \
- CONFIG.PCW_MIO_3_SLEW {slow} \
- CONFIG.PCW_MIO_40_DIRECTION {inout} \
- CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_40_PULLUP {enabled} \
- CONFIG.PCW_MIO_40_SLEW {slow} \
- CONFIG.PCW_MIO_41_DIRECTION {inout} \
- CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_41_PULLUP {enabled} \
- CONFIG.PCW_MIO_41_SLEW {slow} \
- CONFIG.PCW_MIO_42_DIRECTION {inout} \
- CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_42_PULLUP {enabled} \
- CONFIG.PCW_MIO_42_SLEW {slow} \
- CONFIG.PCW_MIO_43_DIRECTION {inout} \
- CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_43_PULLUP {enabled} \
- CONFIG.PCW_MIO_43_SLEW {slow} \
- CONFIG.PCW_MIO_44_DIRECTION {inout} \
- CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_44_PULLUP {enabled} \
- CONFIG.PCW_MIO_44_SLEW {slow} \
- CONFIG.PCW_MIO_45_DIRECTION {inout} \
- CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_45_PULLUP {enabled} \
- CONFIG.PCW_MIO_45_SLEW {slow} \
- CONFIG.PCW_MIO_46_DIRECTION {out} \
- CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_46_PULLUP {enabled} \
- CONFIG.PCW_MIO_46_SLEW {slow} \
- CONFIG.PCW_MIO_47_DIRECTION {in} \
- CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_47_PULLUP {enabled} \
- CONFIG.PCW_MIO_47_SLEW {slow} \
- CONFIG.PCW_MIO_48_DIRECTION {out} \
- CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_48_PULLUP {enabled} \
- CONFIG.PCW_MIO_48_SLEW {slow} \
- CONFIG.PCW_MIO_49_DIRECTION {in} \
- CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_49_PULLUP {enabled} \
- CONFIG.PCW_MIO_49_SLEW {slow} \
- CONFIG.PCW_MIO_4_DIRECTION {inout} \
- CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_4_PULLUP {disabled} \
- CONFIG.PCW_MIO_4_SLEW {slow} \
- CONFIG.PCW_MIO_50_DIRECTION {inout} \
- CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_50_PULLUP {enabled} \
- CONFIG.PCW_MIO_50_SLEW {slow} \
- CONFIG.PCW_MIO_51_DIRECTION {inout} \
- CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_51_PULLUP {enabled} \
- CONFIG.PCW_MIO_51_SLEW {slow} \
- CONFIG.PCW_MIO_52_DIRECTION {out} \
- CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_52_PULLUP {enabled} \
- CONFIG.PCW_MIO_52_SLEW {slow} \
- CONFIG.PCW_MIO_53_DIRECTION {inout} \
- CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
- CONFIG.PCW_MIO_53_PULLUP {enabled} \
- CONFIG.PCW_MIO_53_SLEW {slow} \
- CONFIG.PCW_MIO_5_DIRECTION {inout} \
- CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_5_PULLUP {disabled} \
- CONFIG.PCW_MIO_5_SLEW {slow} \
- CONFIG.PCW_MIO_6_DIRECTION {out} \
- CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_6_PULLUP {disabled} \
- CONFIG.PCW_MIO_6_SLEW {slow} \
- CONFIG.PCW_MIO_7_DIRECTION {out} \
- CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_7_PULLUP {disabled} \
- CONFIG.PCW_MIO_7_SLEW {slow} \
- CONFIG.PCW_MIO_8_DIRECTION {out} \
- CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_8_PULLUP {disabled} \
- CONFIG.PCW_MIO_8_SLEW {slow} \
- CONFIG.PCW_MIO_9_DIRECTION {inout} \
- CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_9_PULLUP {enabled} \
- CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
- CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
- CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
- CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
- CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
- CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
- CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
- CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
- CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
- CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
- CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
- CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
- CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
- CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
- CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
- CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
- CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
- CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
- CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
- CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
- CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
- CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
- CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
- CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
- CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART0_UART0_IO {EMIO} \
- CONFIG.PCW_UART1_BAUD_RATE {115200} \
- CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART1_UART1_IO {EMIO} \
- CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
- CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
- CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
- CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
- CONFIG.PCW_UIPARAM_DDR_AL {0} \
- CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
- CONFIG.PCW_UIPARAM_DDR_BL {8} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
- CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
- CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
- CONFIG.PCW_UIPARAM_DDR_CL {7} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
- CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
- CONFIG.PCW_UIPARAM_DDR_CWL {6} \
- CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
- CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
- CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
- CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
- CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
- CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
- CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
- CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
- CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
- CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
- CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
- CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
- CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
- CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
- CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
- CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
- CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
- CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
- CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
- CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
- CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
- CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
- CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
- CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
- CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
- CONFIG.PCW_USB0_RESET_ENABLE {1} \
- CONFIG.PCW_USB0_RESET_IO {MIO 46} \
- CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
- CONFIG.PCW_USB1_RESET_ENABLE {0} \
- CONFIG.PCW_USB_RESET_ENABLE {1} \
- CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
- CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_USE_AXI_NONSECURE {0} \
- CONFIG.PCW_USE_CROSS_TRIGGER {0} \
- CONFIG.PCW_USE_M_AXI_GP0 {1} \
- ] $processing_system7_0
-
- # Create instance: ps7_0_axi_periph, and set properties
- set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
- set_property -dict [ list \
- CONFIG.NUM_MI {15} \
- ] $ps7_0_axi_periph
-
- # Create instance: pwm_recorder_0, and set properties
- set pwm_recorder_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_0 ]
-
- # Create instance: pwm_recorder_1, and set properties
- set pwm_recorder_1 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_1 ]
-
- # Create instance: pwm_recorder_2, and set properties
- set pwm_recorder_2 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_2 ]
-
- # Create instance: pwm_recorder_3, and set properties
- set pwm_recorder_3 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_3 ]
-
- # Create instance: pwm_recorder_4, and set properties
- set pwm_recorder_4 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_4 ]
-
- # Create instance: pwm_recorder_5, and set properties
- set pwm_recorder_5 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_5 ]
-
- # Create instance: pwm_signal_out_0, and set properties
- set pwm_signal_out_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_0 ]
-
- # Create instance: pwm_signal_out_1, and set properties
- set pwm_signal_out_1 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_1 ]
-
- # Create instance: pwm_signal_out_2, and set properties
- set pwm_signal_out_2 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_2 ]
-
- # Create instance: pwm_signal_out_3, and set properties
- set pwm_signal_out_3 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_3 ]
-
- # Create instance: rst_ps7_0_50M, and set properties
- set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
-
- # Create interface connections
- connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports sws_4bits] [get_bd_intf_pins axi_gpio_sws/GPIO]
- connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports leds_4bits] [get_bd_intf_pins axi_gpio_leds/GPIO]
- connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports btns_4bits] [get_bd_intf_pins axi_gpio_btns/GPIO]
- connect_bd_intf_net -intf_net axi_gpio_3_GPIO [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_3/GPIO]
- connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
- connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
- connect_bd_intf_net -intf_net processing_system7_0_IIC_0 [get_bd_intf_ports I2C0] [get_bd_intf_pins processing_system7_0/IIC_0]
- connect_bd_intf_net -intf_net processing_system7_0_IIC_1 [get_bd_intf_ports I2C1] [get_bd_intf_pins processing_system7_0/IIC_1]
- connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
- connect_bd_intf_net -intf_net processing_system7_0_UART_0 [get_bd_intf_ports UART0] [get_bd_intf_pins processing_system7_0/UART_0]
- connect_bd_intf_net -intf_net processing_system7_0_UART_1 [get_bd_intf_ports UART1] [get_bd_intf_pins processing_system7_0/UART_1]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_sws/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_leds/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_btns/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins ps7_0_axi_periph/M04_AXI] [get_bd_intf_pins pwm_recorder_0/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M05_AXI [get_bd_intf_pins ps7_0_axi_periph/M05_AXI] [get_bd_intf_pins pwm_recorder_1/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M06_AXI [get_bd_intf_pins ps7_0_axi_periph/M06_AXI] [get_bd_intf_pins pwm_recorder_2/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M07_AXI [get_bd_intf_pins ps7_0_axi_periph/M07_AXI] [get_bd_intf_pins pwm_recorder_3/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M08_AXI [get_bd_intf_pins ps7_0_axi_periph/M08_AXI] [get_bd_intf_pins pwm_recorder_4/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M09_AXI [get_bd_intf_pins ps7_0_axi_periph/M09_AXI] [get_bd_intf_pins pwm_recorder_5/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M10_AXI [get_bd_intf_pins ps7_0_axi_periph/M10_AXI] [get_bd_intf_pins pwm_signal_out_0/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M11_AXI [get_bd_intf_pins ps7_0_axi_periph/M11_AXI] [get_bd_intf_pins pwm_signal_out_1/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M12_AXI [get_bd_intf_pins ps7_0_axi_periph/M12_AXI] [get_bd_intf_pins pwm_signal_out_2/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M13_AXI [get_bd_intf_pins ps7_0_axi_periph/M13_AXI] [get_bd_intf_pins pwm_signal_out_3/S_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M14_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M14_AXI]
-
- # Create port connections
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_btns/s_axi_aclk] [get_bd_pins axi_gpio_leds/s_axi_aclk] [get_bd_pins axi_gpio_sws/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
- connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
- connect_bd_net -net pwm_in_master_0_1 [get_bd_ports pwm_in_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
- connect_bd_net -net pwm_in_master_1_1 [get_bd_ports pwm_in_1] [get_bd_pins pwm_recorder_1/pwm_in_master]
- connect_bd_net -net pwm_in_master_2_1 [get_bd_ports pwm_in_2] [get_bd_pins pwm_recorder_2/pwm_in_master]
- connect_bd_net -net pwm_in_master_3_1 [get_bd_ports pwm_in_3] [get_bd_pins pwm_recorder_3/pwm_in_master]
- connect_bd_net -net pwm_in_master_4_1 [get_bd_ports pwm_in_4] [get_bd_pins pwm_recorder_4/pwm_in_master]
- connect_bd_net -net pwm_in_master_5_1 [get_bd_ports pwm_in_5] [get_bd_pins pwm_recorder_5/pwm_in_master]
- connect_bd_net -net pwm_signal_out_0_pwm_out_sm [get_bd_ports pwm_out_0] [get_bd_pins pwm_signal_out_0/pwm_out_sm]
- connect_bd_net -net pwm_signal_out_1_pwm_out_sm [get_bd_ports pwm_out_1] [get_bd_pins pwm_signal_out_1/pwm_out_sm]
- connect_bd_net -net pwm_signal_out_2_pwm_out_sm [get_bd_ports pwm_out_2] [get_bd_pins pwm_signal_out_2/pwm_out_sm]
- connect_bd_net -net pwm_signal_out_3_pwm_out_sm [get_bd_ports pwm_out_3] [get_bd_pins pwm_signal_out_3/pwm_out_sm]
- connect_bd_net -net rst_ps7_0_50M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_50M/interconnect_aresetn]
- connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_btns/s_axi_aresetn] [get_bd_pins axi_gpio_leds/s_axi_aresetn] [get_bd_pins axi_gpio_sws/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/M05_ARESETN] [get_bd_pins ps7_0_axi_periph/M06_ARESETN] [get_bd_pins ps7_0_axi_periph/M07_ARESETN] [get_bd_pins ps7_0_axi_periph/M08_ARESETN] [get_bd_pins ps7_0_axi_periph/M09_ARESETN] [get_bd_pins ps7_0_axi_periph/M10_ARESETN] [get_bd_pins ps7_0_axi_periph/M11_ARESETN] [get_bd_pins ps7_0_axi_periph/M12_ARESETN] [get_bd_pins ps7_0_axi_periph/M13_ARESETN] [get_bd_pins ps7_0_axi_periph/M14_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pwm_recorder_0/s_axi_aresetn] [get_bd_pins pwm_recorder_1/s_axi_aresetn] [get_bd_pins pwm_recorder_2/s_axi_aresetn] [get_bd_pins pwm_recorder_3/s_axi_aresetn] [get_bd_pins pwm_recorder_4/s_axi_aresetn] [get_bd_pins pwm_recorder_5/s_axi_aresetn] [get_bd_pins pwm_signal_out_0/s_axi_aresetn] [get_bd_pins pwm_signal_out_1/s_axi_aresetn] [get_bd_pins pwm_signal_out_2/s_axi_aresetn] [get_bd_pins pwm_signal_out_3/s_axi_aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
-
- # Create address segments
- create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_sws/S_AXI/Reg] SEG_axi_gpio_0_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_leds/S_AXI/Reg] SEG_axi_gpio_1_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_btns/S_AXI/Reg] SEG_axi_gpio_2_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x42800000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x76EA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_0/S_AXI/S_AXI_reg] SEG_pwm_recorder_0_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x76E80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_1/S_AXI/S_AXI_reg] SEG_pwm_recorder_1_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x76E60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_2/S_AXI/S_AXI_reg] SEG_pwm_recorder_2_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x76E40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_3/S_AXI/S_AXI_reg] SEG_pwm_recorder_3_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x76E20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_4/S_AXI/S_AXI_reg] SEG_pwm_recorder_4_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x76E00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_5/S_AXI/S_AXI_reg] SEG_pwm_recorder_5_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x79460000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_0/S_AXI/S_AXI_reg] SEG_pwm_signal_out_0_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x79440000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_1/S_AXI/S_AXI_reg] SEG_pwm_signal_out_1_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x79420000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_2/S_AXI/S_AXI_reg] SEG_pwm_signal_out_2_S_AXI_reg
- create_bd_addr_seg -range 0x00010000 -offset 0x79400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_3/S_AXI/S_AXI_reg] SEG_pwm_signal_out_3_S_AXI_reg
-
-
- # Restore current instance
- current_bd_instance $oldCurInst
-
- save_bd_design
- close_bd_design $design_name
+ set list_ips_missing ""
+ common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+ }
+
+ if { $bCheckIPsPassed != 1 } {
+ common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+ }
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+ set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+ set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+ set I2C0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C0 ]
+ set I2C1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C1 ]
+ set UART0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART0 ]
+ set UART1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART1 ]
+ set btns_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 btns_4bits ]
+ set leds_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 leds_4bits ]
+ set rgb_led [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rgb_led ]
+ set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ]
+
+ # Create ports
+ set pwm_in_0 [ create_bd_port -dir I pwm_in_0 ]
+ set pwm_in_1 [ create_bd_port -dir I pwm_in_1 ]
+ set pwm_in_2 [ create_bd_port -dir I pwm_in_2 ]
+ set pwm_in_3 [ create_bd_port -dir I pwm_in_3 ]
+ set pwm_in_4 [ create_bd_port -dir I pwm_in_4 ]
+ set pwm_in_5 [ create_bd_port -dir I pwm_in_5 ]
+ set pwm_out_0 [ create_bd_port -dir O pwm_out_0 ]
+ set pwm_out_1 [ create_bd_port -dir O pwm_out_1 ]
+ set pwm_out_2 [ create_bd_port -dir O pwm_out_2 ]
+ set pwm_out_3 [ create_bd_port -dir O pwm_out_3 ]
+
+ # Create instance: axi_gpio_3, and set properties
+ set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ]
+ set_property -dict [ list \
+ CONFIG.GPIO_BOARD_INTERFACE {rgb_led} \
+ CONFIG.USE_BOARD_FLOW {true} \
+ ] $axi_gpio_3
+
+ # Create instance: axi_gpio_btns, and set properties
+ set axi_gpio_btns [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_btns ]
+ set_property -dict [ list \
+ CONFIG.GPIO_BOARD_INTERFACE {btns_4bits} \
+ CONFIG.USE_BOARD_FLOW {true} \
+ ] $axi_gpio_btns
+
+ # Create instance: axi_gpio_leds, and set properties
+ set axi_gpio_leds [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_leds ]
+ set_property -dict [ list \
+ CONFIG.GPIO_BOARD_INTERFACE {leds_4bits} \
+ CONFIG.USE_BOARD_FLOW {true} \
+ ] $axi_gpio_leds
+
+ # Create instance: axi_gpio_sws, and set properties
+ set axi_gpio_sws [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sws ]
+ set_property -dict [ list \
+ CONFIG.GPIO_BOARD_INTERFACE {sws_4bits} \
+ CONFIG.USE_BOARD_FLOW {true} \
+ ] $axi_gpio_sws
+
+ # Create instance: axi_timer_0, and set properties
+ set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CLK0_FREQ {100000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+ CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
+ CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+ CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+ CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
+ CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
+ CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
+ CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
+ CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
+ CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
+ CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
+ CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
+ CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+ CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET_RESET_ENABLE {1} \
+ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_EN_4K_TIMER {0} \
+ CONFIG.PCW_EN_EMIO_I2C0 {1} \
+ CONFIG.PCW_EN_EMIO_I2C1 {1} \
+ CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_UART0 {1} \
+ CONFIG.PCW_EN_EMIO_UART1 {1} \
+ CONFIG.PCW_EN_ENET0 {1} \
+ CONFIG.PCW_EN_GPIO {1} \
+ CONFIG.PCW_EN_I2C0 {1} \
+ CONFIG.PCW_EN_I2C1 {1} \
+ CONFIG.PCW_EN_MODEM_UART0 {0} \
+ CONFIG.PCW_EN_QSPI {1} \
+ CONFIG.PCW_EN_SDIO0 {1} \
+ CONFIG.PCW_EN_UART0 {1} \
+ CONFIG.PCW_EN_UART1 {1} \
+ CONFIG.PCW_EN_USB0 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
+ CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
+ CONFIG.PCW_I2C0_I2C0_IO {EMIO} \
+ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
+ CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
+ CONFIG.PCW_I2C1_I2C1_IO {EMIO} \
+ CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_I2C_RESET_ENABLE {1} \
+ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+ CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+ CONFIG.PCW_MIO_0_DIRECTION {inout} \
+ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_0_PULLUP {enabled} \
+ CONFIG.PCW_MIO_0_SLEW {slow} \
+ CONFIG.PCW_MIO_10_DIRECTION {inout} \
+ CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_10_PULLUP {enabled} \
+ CONFIG.PCW_MIO_10_SLEW {slow} \
+ CONFIG.PCW_MIO_11_DIRECTION {inout} \
+ CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_11_PULLUP {enabled} \
+ CONFIG.PCW_MIO_11_SLEW {slow} \
+ CONFIG.PCW_MIO_12_DIRECTION {inout} \
+ CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_12_PULLUP {enabled} \
+ CONFIG.PCW_MIO_12_SLEW {slow} \
+ CONFIG.PCW_MIO_13_DIRECTION {inout} \
+ CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_13_PULLUP {enabled} \
+ CONFIG.PCW_MIO_13_SLEW {slow} \
+ CONFIG.PCW_MIO_14_DIRECTION {inout} \
+ CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_14_PULLUP {enabled} \
+ CONFIG.PCW_MIO_14_SLEW {slow} \
+ CONFIG.PCW_MIO_15_DIRECTION {inout} \
+ CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_15_PULLUP {enabled} \
+ CONFIG.PCW_MIO_15_SLEW {slow} \
+ CONFIG.PCW_MIO_16_DIRECTION {out} \
+ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_16_PULLUP {enabled} \
+ CONFIG.PCW_MIO_16_SLEW {fast} \
+ CONFIG.PCW_MIO_17_DIRECTION {out} \
+ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_17_PULLUP {enabled} \
+ CONFIG.PCW_MIO_17_SLEW {fast} \
+ CONFIG.PCW_MIO_18_DIRECTION {out} \
+ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_18_PULLUP {enabled} \
+ CONFIG.PCW_MIO_18_SLEW {fast} \
+ CONFIG.PCW_MIO_19_DIRECTION {out} \
+ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_19_PULLUP {enabled} \
+ CONFIG.PCW_MIO_19_SLEW {fast} \
+ CONFIG.PCW_MIO_1_DIRECTION {out} \
+ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_1_PULLUP {enabled} \
+ CONFIG.PCW_MIO_1_SLEW {slow} \
+ CONFIG.PCW_MIO_20_DIRECTION {out} \
+ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_20_PULLUP {enabled} \
+ CONFIG.PCW_MIO_20_SLEW {fast} \
+ CONFIG.PCW_MIO_21_DIRECTION {out} \
+ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_21_PULLUP {enabled} \
+ CONFIG.PCW_MIO_21_SLEW {fast} \
+ CONFIG.PCW_MIO_22_DIRECTION {in} \
+ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_22_PULLUP {enabled} \
+ CONFIG.PCW_MIO_22_SLEW {fast} \
+ CONFIG.PCW_MIO_23_DIRECTION {in} \
+ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_23_PULLUP {enabled} \
+ CONFIG.PCW_MIO_23_SLEW {fast} \
+ CONFIG.PCW_MIO_24_DIRECTION {in} \
+ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_24_PULLUP {enabled} \
+ CONFIG.PCW_MIO_24_SLEW {fast} \
+ CONFIG.PCW_MIO_25_DIRECTION {in} \
+ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_25_PULLUP {enabled} \
+ CONFIG.PCW_MIO_25_SLEW {fast} \
+ CONFIG.PCW_MIO_26_DIRECTION {in} \
+ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_26_PULLUP {enabled} \
+ CONFIG.PCW_MIO_26_SLEW {fast} \
+ CONFIG.PCW_MIO_27_DIRECTION {in} \
+ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_27_PULLUP {enabled} \
+ CONFIG.PCW_MIO_27_SLEW {fast} \
+ CONFIG.PCW_MIO_28_DIRECTION {inout} \
+ CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_28_PULLUP {enabled} \
+ CONFIG.PCW_MIO_28_SLEW {fast} \
+ CONFIG.PCW_MIO_29_DIRECTION {in} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_29_PULLUP {enabled} \
+ CONFIG.PCW_MIO_29_SLEW {fast} \
+ CONFIG.PCW_MIO_30_DIRECTION {out} \
+ CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_30_PULLUP {enabled} \
+ CONFIG.PCW_MIO_30_SLEW {fast} \
+ CONFIG.PCW_MIO_31_DIRECTION {in} \
+ CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_31_PULLUP {enabled} \
+ CONFIG.PCW_MIO_31_SLEW {fast} \
+ CONFIG.PCW_MIO_32_DIRECTION {inout} \
+ CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_32_PULLUP {enabled} \
+ CONFIG.PCW_MIO_32_SLEW {fast} \
+ CONFIG.PCW_MIO_33_DIRECTION {inout} \
+ CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_33_PULLUP {enabled} \
+ CONFIG.PCW_MIO_33_SLEW {fast} \
+ CONFIG.PCW_MIO_34_DIRECTION {inout} \
+ CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_34_PULLUP {enabled} \
+ CONFIG.PCW_MIO_34_SLEW {fast} \
+ CONFIG.PCW_MIO_35_DIRECTION {inout} \
+ CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_35_PULLUP {enabled} \
+ CONFIG.PCW_MIO_35_SLEW {fast} \
+ CONFIG.PCW_MIO_36_DIRECTION {in} \
+ CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_36_PULLUP {enabled} \
+ CONFIG.PCW_MIO_36_SLEW {fast} \
+ CONFIG.PCW_MIO_37_DIRECTION {inout} \
+ CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_37_PULLUP {enabled} \
+ CONFIG.PCW_MIO_37_SLEW {fast} \
+ CONFIG.PCW_MIO_38_DIRECTION {inout} \
+ CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_38_PULLUP {enabled} \
+ CONFIG.PCW_MIO_38_SLEW {fast} \
+ CONFIG.PCW_MIO_39_DIRECTION {inout} \
+ CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_39_PULLUP {enabled} \
+ CONFIG.PCW_MIO_39_SLEW {fast} \
+ CONFIG.PCW_MIO_3_DIRECTION {inout} \
+ CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_3_PULLUP {disabled} \
+ CONFIG.PCW_MIO_3_SLEW {slow} \
+ CONFIG.PCW_MIO_40_DIRECTION {inout} \
+ CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_40_PULLUP {enabled} \
+ CONFIG.PCW_MIO_40_SLEW {slow} \
+ CONFIG.PCW_MIO_41_DIRECTION {inout} \
+ CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_41_PULLUP {enabled} \
+ CONFIG.PCW_MIO_41_SLEW {slow} \
+ CONFIG.PCW_MIO_42_DIRECTION {inout} \
+ CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_42_PULLUP {enabled} \
+ CONFIG.PCW_MIO_42_SLEW {slow} \
+ CONFIG.PCW_MIO_43_DIRECTION {inout} \
+ CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_43_PULLUP {enabled} \
+ CONFIG.PCW_MIO_43_SLEW {slow} \
+ CONFIG.PCW_MIO_44_DIRECTION {inout} \
+ CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_44_PULLUP {enabled} \
+ CONFIG.PCW_MIO_44_SLEW {slow} \
+ CONFIG.PCW_MIO_45_DIRECTION {inout} \
+ CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_45_PULLUP {enabled} \
+ CONFIG.PCW_MIO_45_SLEW {slow} \
+ CONFIG.PCW_MIO_46_DIRECTION {out} \
+ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_46_PULLUP {enabled} \
+ CONFIG.PCW_MIO_46_SLEW {slow} \
+ CONFIG.PCW_MIO_47_DIRECTION {in} \
+ CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_47_PULLUP {enabled} \
+ CONFIG.PCW_MIO_47_SLEW {slow} \
+ CONFIG.PCW_MIO_48_DIRECTION {out} \
+ CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_48_PULLUP {enabled} \
+ CONFIG.PCW_MIO_48_SLEW {slow} \
+ CONFIG.PCW_MIO_49_DIRECTION {in} \
+ CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_49_PULLUP {enabled} \
+ CONFIG.PCW_MIO_49_SLEW {slow} \
+ CONFIG.PCW_MIO_4_DIRECTION {inout} \
+ CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_4_PULLUP {disabled} \
+ CONFIG.PCW_MIO_4_SLEW {slow} \
+ CONFIG.PCW_MIO_50_DIRECTION {inout} \
+ CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_50_PULLUP {enabled} \
+ CONFIG.PCW_MIO_50_SLEW {slow} \
+ CONFIG.PCW_MIO_51_DIRECTION {inout} \
+ CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_51_PULLUP {enabled} \
+ CONFIG.PCW_MIO_51_SLEW {slow} \
+ CONFIG.PCW_MIO_52_DIRECTION {out} \
+ CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_52_PULLUP {enabled} \
+ CONFIG.PCW_MIO_52_SLEW {slow} \
+ CONFIG.PCW_MIO_53_DIRECTION {inout} \
+ CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_53_PULLUP {enabled} \
+ CONFIG.PCW_MIO_53_SLEW {slow} \
+ CONFIG.PCW_MIO_5_DIRECTION {inout} \
+ CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_5_PULLUP {disabled} \
+ CONFIG.PCW_MIO_5_SLEW {slow} \
+ CONFIG.PCW_MIO_6_DIRECTION {out} \
+ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_6_PULLUP {disabled} \
+ CONFIG.PCW_MIO_6_SLEW {slow} \
+ CONFIG.PCW_MIO_7_DIRECTION {out} \
+ CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_7_PULLUP {disabled} \
+ CONFIG.PCW_MIO_7_SLEW {slow} \
+ CONFIG.PCW_MIO_8_DIRECTION {out} \
+ CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_8_PULLUP {disabled} \
+ CONFIG.PCW_MIO_8_SLEW {slow} \
+ CONFIG.PCW_MIO_9_DIRECTION {inout} \
+ CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_9_PULLUP {enabled} \
+ CONFIG.PCW_MIO_9_SLEW {slow} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
+ CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+ CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+ CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.221} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.222} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.217} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.244} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
+ CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+ CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+ CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+ CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+ CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+ CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+ CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+ CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+ CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
+ CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+ CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+ CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+ CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+ CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
+ CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART0_UART0_IO {EMIO} \
+ CONFIG.PCW_UART1_BAUD_RATE {115200} \
+ CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_UART1_IO {EMIO} \
+ CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+ CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+ CONFIG.PCW_UIPARAM_DDR_AL {0} \
+ CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+ CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_CL {7} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {18.8} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {18.8} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {18.8} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {18.8} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+ CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+ CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+ CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {22.8} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {27.9} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.4} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.050} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {22.8} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {27.9} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {22.9} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {29.4} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+ CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+ CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+ CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
+ CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+ CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
+ CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+ CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
+ CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+ CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+ CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_USB0_RESET_ENABLE {1} \
+ CONFIG.PCW_USB0_RESET_IO {MIO 46} \
+ CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+ CONFIG.PCW_USB1_RESET_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_ENABLE {1} \
+ CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_USE_AXI_NONSECURE {0} \
+ CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+ CONFIG.PCW_USE_M_AXI_GP0 {1} \
+ ] $processing_system7_0
+
+ # Create instance: ps7_0_axi_periph, and set properties
+ set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {15} \
+ ] $ps7_0_axi_periph
+
+ # Create instance: pwm_recorder_0, and set properties
+ set pwm_recorder_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_0 ]
+
+ # Create instance: pwm_recorder_1, and set properties
+ set pwm_recorder_1 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_1 ]
+
+ # Create instance: pwm_recorder_2, and set properties
+ set pwm_recorder_2 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_2 ]
+
+ # Create instance: pwm_recorder_3, and set properties
+ set pwm_recorder_3 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_3 ]
+
+ # Create instance: pwm_recorder_4, and set properties
+ set pwm_recorder_4 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_4 ]
+
+ # Create instance: pwm_recorder_5, and set properties
+ set pwm_recorder_5 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_5 ]
+
+ # Create instance: pwm_signal_out_0, and set properties
+ set pwm_signal_out_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_0 ]
+
+ # Create instance: pwm_signal_out_1, and set properties
+ set pwm_signal_out_1 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_1 ]
+
+ # Create instance: pwm_signal_out_2, and set properties
+ set pwm_signal_out_2 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_2 ]
+
+ # Create instance: pwm_signal_out_3, and set properties
+ set pwm_signal_out_3 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_3 ]
+
+ # Create instance: rst_ps7_0_50M, and set properties
+ set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports sws_4bits] [get_bd_intf_pins axi_gpio_sws/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports leds_4bits] [get_bd_intf_pins axi_gpio_leds/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports btns_4bits] [get_bd_intf_pins axi_gpio_btns/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_3_GPIO [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_3/GPIO]
+ connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+ connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_IIC_0 [get_bd_intf_ports I2C0] [get_bd_intf_pins processing_system7_0/IIC_0]
+ connect_bd_intf_net -intf_net processing_system7_0_IIC_1 [get_bd_intf_ports I2C1] [get_bd_intf_pins processing_system7_0/IIC_1]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_UART_0 [get_bd_intf_ports UART0] [get_bd_intf_pins processing_system7_0/UART_0]
+ connect_bd_intf_net -intf_net processing_system7_0_UART_1 [get_bd_intf_ports UART1] [get_bd_intf_pins processing_system7_0/UART_1]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_sws/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_leds/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_btns/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins ps7_0_axi_periph/M04_AXI] [get_bd_intf_pins pwm_recorder_0/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M05_AXI [get_bd_intf_pins ps7_0_axi_periph/M05_AXI] [get_bd_intf_pins pwm_recorder_1/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M06_AXI [get_bd_intf_pins ps7_0_axi_periph/M06_AXI] [get_bd_intf_pins pwm_recorder_2/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M07_AXI [get_bd_intf_pins ps7_0_axi_periph/M07_AXI] [get_bd_intf_pins pwm_recorder_3/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M08_AXI [get_bd_intf_pins ps7_0_axi_periph/M08_AXI] [get_bd_intf_pins pwm_recorder_4/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M09_AXI [get_bd_intf_pins ps7_0_axi_periph/M09_AXI] [get_bd_intf_pins pwm_recorder_5/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M10_AXI [get_bd_intf_pins ps7_0_axi_periph/M10_AXI] [get_bd_intf_pins pwm_signal_out_0/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M11_AXI [get_bd_intf_pins ps7_0_axi_periph/M11_AXI] [get_bd_intf_pins pwm_signal_out_1/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M12_AXI [get_bd_intf_pins ps7_0_axi_periph/M12_AXI] [get_bd_intf_pins pwm_signal_out_2/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M13_AXI [get_bd_intf_pins ps7_0_axi_periph/M13_AXI] [get_bd_intf_pins pwm_signal_out_3/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M14_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M14_AXI]
+
+ # Create port connections
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_btns/s_axi_aclk] [get_bd_pins axi_gpio_leds/s_axi_aclk] [get_bd_pins axi_gpio_sws/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
+ connect_bd_net -net pwm_in_master_0_1 [get_bd_ports pwm_in_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
+ connect_bd_net -net pwm_in_master_1_1 [get_bd_ports pwm_in_1] [get_bd_pins pwm_recorder_1/pwm_in_master]
+ connect_bd_net -net pwm_in_master_2_1 [get_bd_ports pwm_in_2] [get_bd_pins pwm_recorder_2/pwm_in_master]
+ connect_bd_net -net pwm_in_master_3_1 [get_bd_ports pwm_in_3] [get_bd_pins pwm_recorder_3/pwm_in_master]
+ connect_bd_net -net pwm_in_master_4_1 [get_bd_ports pwm_in_4] [get_bd_pins pwm_recorder_4/pwm_in_master]
+ connect_bd_net -net pwm_in_master_5_1 [get_bd_ports pwm_in_5] [get_bd_pins pwm_recorder_5/pwm_in_master]
+ connect_bd_net -net pwm_signal_out_0_pwm_out_sm [get_bd_ports pwm_out_0] [get_bd_pins pwm_signal_out_0/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_1_pwm_out_sm [get_bd_ports pwm_out_1] [get_bd_pins pwm_signal_out_1/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_2_pwm_out_sm [get_bd_ports pwm_out_2] [get_bd_pins pwm_signal_out_2/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_3_pwm_out_sm [get_bd_ports pwm_out_3] [get_bd_pins pwm_signal_out_3/pwm_out_sm]
+ connect_bd_net -net rst_ps7_0_50M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_50M/interconnect_aresetn]
+ connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_btns/s_axi_aresetn] [get_bd_pins axi_gpio_leds/s_axi_aresetn] [get_bd_pins axi_gpio_sws/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/M05_ARESETN] [get_bd_pins ps7_0_axi_periph/M06_ARESETN] [get_bd_pins ps7_0_axi_periph/M07_ARESETN] [get_bd_pins ps7_0_axi_periph/M08_ARESETN] [get_bd_pins ps7_0_axi_periph/M09_ARESETN] [get_bd_pins ps7_0_axi_periph/M10_ARESETN] [get_bd_pins ps7_0_axi_periph/M11_ARESETN] [get_bd_pins ps7_0_axi_periph/M12_ARESETN] [get_bd_pins ps7_0_axi_periph/M13_ARESETN] [get_bd_pins ps7_0_axi_periph/M14_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pwm_recorder_0/s_axi_aresetn] [get_bd_pins pwm_recorder_1/s_axi_aresetn] [get_bd_pins pwm_recorder_2/s_axi_aresetn] [get_bd_pins pwm_recorder_3/s_axi_aresetn] [get_bd_pins pwm_recorder_4/s_axi_aresetn] [get_bd_pins pwm_recorder_5/s_axi_aresetn] [get_bd_pins pwm_signal_out_0/s_axi_aresetn] [get_bd_pins pwm_signal_out_1/s_axi_aresetn] [get_bd_pins pwm_signal_out_2/s_axi_aresetn] [get_bd_pins pwm_signal_out_3/s_axi_aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
+
+ # Create address segments
+ create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_sws/S_AXI/Reg] SEG_axi_gpio_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_leds/S_AXI/Reg] SEG_axi_gpio_1_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_btns/S_AXI/Reg] SEG_axi_gpio_2_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x42800000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x76EA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_0/S_AXI/S_AXI_reg] SEG_pwm_recorder_0_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x76E80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_1/S_AXI/S_AXI_reg] SEG_pwm_recorder_1_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x76E60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_2/S_AXI/S_AXI_reg] SEG_pwm_recorder_2_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x76E40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_3/S_AXI/S_AXI_reg] SEG_pwm_recorder_3_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x76E20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_4/S_AXI/S_AXI_reg] SEG_pwm_recorder_4_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x76E00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_5/S_AXI/S_AXI_reg] SEG_pwm_recorder_5_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x79460000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_0/S_AXI/S_AXI_reg] SEG_pwm_signal_out_0_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x79440000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_1/S_AXI/S_AXI_reg] SEG_pwm_signal_out_1_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x79420000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_2/S_AXI/S_AXI_reg] SEG_pwm_signal_out_2_S_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x79400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_3/S_AXI/S_AXI_reg] SEG_pwm_signal_out_3_S_AXI_reg
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ save_bd_design
+ close_bd_design $design_name
+
}
# End of cr_bd_design_1()
cr_bd_design_1 ""
@@ -944,8 +939,8 @@ set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
- set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
- set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+ set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+ set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
@@ -953,7 +948,7 @@ set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
- create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+ create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {
@@ -969,8 +964,8 @@ current_run -synthesis [get_runs synth_1]
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
- set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
- set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+ set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+ set_property flow "Vivado Implementation 2018" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
@@ -978,16 +973,16 @@ set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+ create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
- create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+ create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {
@@ -995,25 +990,25 @@ if { $obj != "" } {
}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+ create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+ create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
- create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+ create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {
@@ -1021,7 +1016,7 @@ if { $obj != "" } {
}
# Create 'impl_1_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
- create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+ create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
if { $obj != "" } {
@@ -1029,7 +1024,7 @@ if { $obj != "" } {
}
# Create 'impl_1_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
- create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+ create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
if { $obj != "" } {
@@ -1037,52 +1032,52 @@ if { $obj != "" } {
}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
- create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+ create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
- create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+ create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+ create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+ create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+ create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
+ set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
- create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {
@@ -1090,7 +1085,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
- create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
if { $obj != "" } {
@@ -1098,7 +1093,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
- create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {
@@ -1106,7 +1101,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
- create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {
@@ -1114,7 +1109,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {
@@ -1122,7 +1117,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
- create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {
@@ -1130,7 +1125,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
- create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {
@@ -1138,7 +1133,7 @@ if { $obj != "" } {
}
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
- create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+ create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
if { $obj != "" } {
@@ -1146,7 +1141,7 @@ if { $obj != "" } {
}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
- create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+ create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
@@ -1154,7 +1149,7 @@ if { $obj != "" } {
}
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
- create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+ create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
if { $obj != "" } {
diff --git a/quad/xsdk_workspace/design_1_wrapper.hdf b/quad/xsdk_workspace/design_1_wrapper.hdf
new file mode 100644
index 0000000000000000000000000000000000000000..45c8988c37a8163f438ae440a25556a03b75d41a
Binary files /dev/null and b/quad/xsdk_workspace/design_1_wrapper.hdf differ
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/.project b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/.project
new file mode 100644
index 0000000000000000000000000000000000000000..e194aa4c441792d66065defa88cdc2a4ae083457
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/.project
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>design_1_wrapper_hw_platform_0</name>
+ <comment>Created by SDK v2018.3</comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ <nature>com.xilinx.sdk.hw.HwProject</nature>
+ </natures>
+ <filteredResources>
+ <filter>
+ <id>1556586164205</id>
+ <name></name>
+ <type>6</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.xml</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1556586164211</id>
+ <name></name>
+ <type>6</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.svd</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1556586164214</id>
+ <name></name>
+ <type>6</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.hwh</arguments>
+ </matcher>
+ </filter>
+ </filteredResources>
+</projectDescription>
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/board.xml b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/board.xml
new file mode 100644
index 0000000000000000000000000000000000000000..7e7e438e281bc135b54f93bbea822fb0dc233df9
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/board.xml
@@ -0,0 +1,994 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo-z7-20" display_name="Zybo Z7-20" url="http://www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Zybo Z7-20</description>
+<components>
+ <component name="part0" display_name="Zybo Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+
+ <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <description>HDMI DDC</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+ <description>HDMI Out</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JE1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JE2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JE3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JE4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JE7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JE8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JE9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JE10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 3 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JE</description>
+ </component>
+ <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+ </component>
+
+ <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI input (Requires Digilent's TMDS interface)</description>
+ <component_modes>
+ <component_mode name="HDMI_IN" display_name="HDMI In">
+ <interfaces>
+ <interface name="hdmi_in" order="0"/>
+ <interface name="hdmi_in_ddc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI in HPD (Connected to LD8)</description>
+ </component>
+ <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI Out (Requires Digilent's TMDS interface)</description>
+ </component>
+ <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI out HPD</description>
+ </component>
+
+
+
+
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+ <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+ <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+ <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+
+ <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+ <connection_map name="part0_hdmi_in_1" c1_st_index="14" c1_end_index="21" c2_st_index="0" c2_end_index="7"/>
+
+ <connection_map name="part0_hdmi_in_ddc" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+
+ <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+ <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="13" c1_end_index="13" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+ <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+ <connection_map name="part0_hdmi_out_1" c1_st_index="23" c1_end_index="30" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+
+ <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+ <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="39" c1_end_index="46" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="55" c1_end_index="62" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="63" c1_end_index="70" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_je" component1="part0" component2="je">
+ <connection_map name="part0_je_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/part0_pins.xml b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/part0_pins.xml
new file mode 100644
index 0000000000000000000000000000000000000000..e166d82bacf910e8a1005f6ad1d4d11013ff85d1
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/part0_pins.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z020clg400-1">
+<pins>
+ <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="K19"/>
+ <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+ <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="K17"/>
+
+ <pin index="13" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="W19"/>
+
+ <pin index="14" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="U18"/>
+ <pin index="15" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="U19"/>
+ <pin index="16" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="V20"/>
+ <pin index="17" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="T20"/>
+ <pin index="18" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="N20"/>
+ <pin index="19" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="W20"/>
+ <pin index="20" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="U20"/>
+ <pin index="21" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="P20"/>
+
+
+ <pin index="22" name ="hdmi_tx_hpd" iostandard="LVCMOS33" loc="E18"/>
+
+ <pin index="23" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="24" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="25" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="26" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="C20"/>
+ <pin index="27" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="B19"/>
+ <pin index="28" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="D20"/>
+ <pin index="29" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="B20"/>
+ <pin index="30" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="A20"/>
+
+ <pin index="31" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="32" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="Y19"/>
+
+
+
+ <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="Y12"/>
+ <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="T5"/>
+ <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="Y11"/>
+ <pin index="36" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="37" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F17"/>
+ <pin index="38" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="V16"/>
+
+
+ <pin index="39" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="40" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="41" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="42" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+ <pin index="43" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="44" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+ <pin index="45" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="46" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+
+ <pin index="47" name ="JB1" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="48" name ="JB2" iostandard="LVCMOS33" loc="W8"/>
+ <pin index="49" name ="JB3" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="50" name ="JB4" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="51" name ="JB7" iostandard="LVCMOS33" loc="Y7"/>
+ <pin index="52" name ="JB8" iostandard="LVCMOS33" loc="Y6"/>
+ <pin index="53" name ="JB9" iostandard="LVCMOS33" loc="V6"/>
+ <pin index="54" name ="JB10" iostandard="LVCMOS33" loc="W6"/>
+
+ <pin index="55" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="56" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="57" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="58" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="59" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="60" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+ <pin index="61" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="62" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+
+ <pin index="63" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="64" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="65" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="66" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="67" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="68" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="69" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="70" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+
+ <pin index="71" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="72" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="73" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="74" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="75" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="76" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="77" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="78" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/preset.xml b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/preset.xml
new file mode 100644
index 0000000000000000000000000000000000000000..3175792eabb3e41197094768dbd215eb487acf69
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/board/zybo-z7-20/preset.xml
@@ -0,0 +1,667 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="667"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="39"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="33.333333"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.221"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.222"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.217"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.244"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="32 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="22.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="27.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="22.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="29.4"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.050"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.044"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.035"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="22.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="27.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="22.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="29.4"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="533.333333"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/design_1_wrapper.bit b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/design_1_wrapper.bit
new file mode 100644
index 0000000000000000000000000000000000000000..1e025a59ad8a4f901f49fb22724141c867c509d6
Binary files /dev/null and b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/design_1_wrapper.bit differ
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.mdd b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.mdd
new file mode 100644
index 0000000000000000000000000000000000000000..2e60f72be1d8ce4186ee1a67c3e839c0fbec1275
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER pwm_recorder
+ OPTION supported_peripherals = (pwm_recorder);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = pwm_recorder;
+END DRIVER
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.tcl b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7b50311bcfa06dfc4793208ca68d23b4be3b56c9
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "pwm_recorder" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
+}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.c
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_recorder.h b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_recorder.h
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.h
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.mdd b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.mdd
new file mode 100644
index 0000000000000000000000000000000000000000..c3b8f3c47e5fef4aeb90c96e35c65c2e116f4239
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER pwm_signal_out
+ OPTION supported_peripherals = (pwm_signal_out);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = pwm_signal_out;
+END DRIVER
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.tcl b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..14022c201eb1ec1e160ecca813014d8288c4b273
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "pwm_signal_out" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
+}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.c
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_signal_out.h b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_signal_out.h
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.h
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.c
similarity index 69%
rename from quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.c
index 2c7ad97ad33b532925df749643c5395076b72cfa..d06de5bb8b79ceb224f9f1b49058c17496705a77 100644
--- a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.c
@@ -1,82 +1,66 @@
- /******************************************************************************
- *
- * (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
- *
- * This file contains confidential and proprietary information of Xilinx, Inc.
- * and is protected under U.S. and international copyright and other
- * intellectual property laws.
- *
- * DISCLAIMER
- * This disclaimer is not a license and does not grant any rights to the
- * materials distributed herewith. Except as otherwise provided in a valid
- * license issued to you by Xilinx, and to the maximum extent permitted by
- * applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND WITH ALL
- * FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
- * IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
- * MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
- * and (2) Xilinx shall not be liable (whether in contract or tort, including
- * negligence, or under any other theory of liability) for any loss or damage
- * of any kind or nature related to, arising under or in connection with these
- * materials, including for any direct, or any indirect, special, incidental,
- * or consequential loss or damage (including loss of data, profits, goodwill,
- * or any type of loss or damage suffered as a result of any action brought by
- * a third party) even if such damage or loss was reasonably foreseeable or
- * Xilinx had been advised of the possibility of the same.
- *
- * CRITICAL APPLICATIONS
- * Xilinx products are not designed or intended to be fail-safe, or for use in
- * any application requiring fail-safe performance, such as life-support or
- * safety devices or systems, Class III medical devices, nuclear facilities,
- * applications related to the deployment of airbags, or any other applications
- * that could lead to death, personal injury, or severe property or
- * environmental damage (individually and collectively, \"Critical
- * Applications\"). Customer assumes the sole risk and liability of any use of
- * Xilinx products in Critical Applications, subject only to applicable laws
- * and regulations governing limitations on product liability.
- *
- * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
- * AT ALL TIMES.
- *
- ******************************************************************************/
- /****************************************************************************/
- /**
- *
- * @file ps7_init.c
- *
- * This file is automatically generated
- *
- *****************************************************************************/
+/******************************************************************************
+*
+* (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
+* otherwise to promote the sale, use or other dealings in this Software without prior written
+* authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
- #include "ps7_init.h"
+#include "ps7_init.h"
-unsigned long ps7_pll_init_data_1_0[] = {
+unsigned long ps7_pll_init_data_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: PLL SLCR REGISTERS
// .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000110[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
// .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -138,23 +122,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
// .. .. FINISH: ARM PLL INIT
// .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000114[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
// .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -213,17 +197,17 @@ unsigned long ps7_pll_init_data_1_0[] = {
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
// .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -267,7 +251,7 @@ unsigned long ps7_pll_init_data_1_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -276,27 +260,27 @@ unsigned long ps7_pll_init_data_1_0[] = {
//
};
-unsigned long ps7_clock_init_data_1_0[] = {
+unsigned long ps7_clock_init_data_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: CLOCK CONTROL SLCR REGISTERS
// .. CLKACT = 0x1
// .. ==> 0XF8000128[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
// .. CLKACT = 0x1
// .. ==> 0XF8000138[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -353,126 +337,95 @@ unsigned long ps7_clock_init_data_1_0[] = {
// .. SRCSEL = 0x0
// .. ==> 0XF8000154[5:4] = 0x00000000U
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x3
- // .. ==> 0XF8000180[5:4] = 0x00000003U
- // .. ==> MASK : 0x00000030U VAL : 0x00000030U
- // .. DIVISOR0 = 0x6
- // .. ==> 0XF8000180[13:8] = 0x00000006U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000600U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
- // .. SRCSEL = 0x2
- // .. ==> 0XF8000190[5:4] = 0x00000002U
- // .. ==> MASK : 0x00000030U VAL : 0x00000020U
- // .. DIVISOR0 = 0x35
- // .. ==> 0XF8000190[13:8] = 0x00000035U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003500U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000190[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF80001A0[13:8] = 0x0000000AU
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF8000154[13:8] = 0x0000000AU
// .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
// .. START: THIS SHOULD BE BLANK
@@ -482,7 +435,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -491,7 +444,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
//
};
-unsigned long ps7_ddr_init_data_1_0[] = {
+unsigned long ps7_ddr_init_data_3_0[] = {
// START: top
// .. START: DDR INITIALIZATION
// .. .. START: LOCK DDR
@@ -522,32 +475,17 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. ..
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
// .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
// .. .. ==> 0XF8006004[13:12] = 0x00000001U
// .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
// .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
// .. .. ==> 0XF8006004[18:14] = 0x00000000U
// .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U),
// .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
// .. .. ==> 0XF8006008[10:0] = 0x0000000FU
// .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
@@ -581,29 +519,29 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
// .. ..
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
// .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
// .. .. ==> 0XF8006014[20:14] = 0x00000010U
// .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
// .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
// .. .. reg_ddrc_powerdown_to_x32 = 0x6
// .. .. ==> 0XF8006018[9:5] = 0x00000006U
// .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
// .. .. reg_ddrc_t_ras_min = 0x13
// .. .. ==> 0XF8006018[26:22] = 0x00000013U
// .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
@@ -611,30 +549,30 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> 0XF8006018[31:28] = 0x00000004U
// .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
// .. .. reg_ddrc_write_latency = 0x5
// .. .. ==> 0XF800601C[4:0] = 0x00000005U
// .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
// .. .. reg_ddrc_rd2wr = 0x7
// .. .. ==> 0XF800601C[9:5] = 0x00000007U
// .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
// .. .. reg_ddrc_pad_pd = 0x0
// .. .. ==> 0XF800601C[22:20] = 0x00000000U
// .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
// .. .. reg_ddrc_t_rcd = 0x7
// .. .. ==> 0XF800601C[31:28] = 0x00000007U
// .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
// .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
// .. .. reg_ddrc_t_ccd = 0x4
// .. .. ==> 0XF8006020[4:2] = 0x00000004U
// .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
@@ -650,13 +588,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. reg_ddrc_refresh_to_x32 = 0x8
// .. .. ==> 0XF8006020[20:16] = 0x00000008U
// .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
// .. .. reg_ddrc_mobile = 0x0
// .. .. ==> 0XF8006020[22:22] = 0x00000000U
// .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
// .. .. ==> 0XF8006020[23:23] = 0x00000000U
// .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
// .. .. reg_ddrc_read_latency = 0x7
@@ -668,20 +603,14 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. reg_ddrc_dis_pad_pd = 0x0
// .. .. ==> 0XF8006020[30:30] = 0x00000000U
// .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
// .. .. reg_ddrc_en_2t_timing_mode = 0x0
// .. .. ==> 0XF8006024[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. reg_ddrc_prefer_write = 0x0
// .. .. ==> 0XF8006024[1:1] = 0x00000000U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
// .. .. reg_ddrc_mr_wr = 0x0
// .. .. ==> 0XF8006024[6:6] = 0x00000000U
// .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
@@ -701,7 +630,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> 0XF8006024[27:27] = 0x00000000U
// .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
// .. .. reg_ddrc_final_wait_x32 = 0x7
// .. .. ==> 0XF8006028[6:0] = 0x00000007U
// .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
@@ -721,20 +650,20 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
// .. .. reg_ddrc_emr = 0x4
// .. .. ==> 0XF8006030[31:16] = 0x00000004U
// .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
// .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
// .. .. reg_ddrc_burst_rdwr = 0x4
// .. .. ==> 0XF8006034[3:0] = 0x00000004U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x101
- // .. .. ==> 0XF8006034[13:4] = 0x00000101U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
// .. .. reg_ddrc_post_cke_x1024 = 0x1
// .. .. ==> 0XF8006034[25:16] = 0x00000001U
// .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
@@ -742,27 +671,15 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> 0XF8006034[28:28] = 0x00000000U
// .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
// .. .. reg_ddrc_force_low_pri_n = 0x0
// .. .. ==> 0XF8006038[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. reg_ddrc_dis_dq = 0x0
// .. .. ==> 0XF8006038[1:1] = 0x00000000U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
// .. .. reg_ddrc_addrmap_bank_b0 = 0x7
// .. .. ==> 0XF800603C[3:0] = 0x00000007U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
@@ -821,26 +738,14 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. reg_ddrc_addrmap_row_b13 = 0x6
// .. .. ==> 0XF8006044[19:16] = 0x00000006U
// .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
// .. .. reg_ddrc_addrmap_row_b15 = 0xf
// .. .. ==> 0XF8006044[27:24] = 0x0000000FU
// .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
// .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
// .. .. reg_phy_rd_local_odt = 0x0
// .. .. ==> 0XF8006048[13:12] = 0x00000000U
// .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
@@ -850,20 +755,14 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. reg_phy_idle_local_odt = 0x3
// .. .. ==> 0XF8006048[17:16] = 0x00000003U
// .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
// .. .. reg_phy_rd_cmd_to_data = 0x0
// .. .. ==> 0XF8006050[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
@@ -896,17 +795,11 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
// .. ..
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
// .. .. reg_ddrc_dis_dll_calib = 0x0
// .. .. ==> 0XF8006058[16:16] = 0x00000000U
// .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
// .. .. reg_ddrc_rd_odt_delay = 0x3
// .. .. ==> 0XF800605C[3:0] = 0x00000003U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
@@ -971,14 +864,43 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
// .. ..
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
// .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
// .. .. reg_ddrc_dis_auto_zq = 0x0
// .. .. ==> 0XF80060A4[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -996,14 +918,14 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
// .. ..
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
// .. .. deeppowerdown_en = 0x0
// .. .. ==> 0XF80060AC[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -1035,17 +957,11 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
// .. ..
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
// .. .. reg_ddrc_skip_ocd = 0x1
// .. .. ==> 0XF80060B4[9:9] = 0x00000001U
// .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
// .. .. reg_ddrc_dfi_t_rddata_en = 0x6
// .. .. ==> 0XF80060B8[4:0] = 0x00000006U
// .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
@@ -1057,681 +973,622 @@ unsigned long ps7_ddr_init_data_1_0[] = {
// .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
// .. ..
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. FINISH: DDR INITIALIZATION
- // .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // ..
EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. CORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // ..
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. UNCORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. STAT_NUM_CORR_ERR = 0x0
- // .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. STAT_NUM_UNCORR_ERR = 0x0
- // .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // ..
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. reg_ddrc_ecc_mode = 0x0
- // .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. reg_ddrc_dis_scrub = 0x1
- // .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // ..
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. reg_phy_dif_on = 0x0
- // .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. reg_phy_dif_off = 0x0
- // .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x92
- // .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF800612C[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF8006130[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9b
+ // .. .. ==> 0XF8006134[19:10] = 0x0000009BU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa2
+ // .. .. ==> 0XF8006138[19:10] = 0x000000A2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x73
+ // .. .. ==> 0XF8006160[9:0] = 0x00000073U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf0
+ // .. .. ==> 0XF8006170[10:0] = 0x000000F0U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf7
+ // .. .. ==> 0XF8006174[10:0] = 0x000000F7U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. reg_phy_loopback = 0x0
- // .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_phy_bl2 = 0x0
- // .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_at_spd_atpg = 0x0
- // .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_bist_enable = 0x0
- // .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_bist_force_err = 0x0
- // .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_bist_mode = 0x0
- // .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reg_phy_invert_clkout = 0x1
- // .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reg_phy_sel_logic = 0x0
- // .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_ratio = 0x100
- // .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. reg_phy_ctrl_slave_force = 0x0
- // .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. reg_phy_use_rank0_delays = 0x1
- // .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. reg_phy_lpddr = 0x0
- // .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. reg_phy_cmd_latency = 0x0
- // .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. reg_phy_int_lpbk = 0x0
- // .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. reg_phy_wr_rl_delay = 0x2
- // .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. reg_phy_rd_rl_delay = 0x4
- // .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. reg_phy_dll_lock_diff = 0xf
- // .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. reg_phy_use_wr_level = 0x1
- // .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. reg_phy_use_rd_data_eye_level = 0x1
- // .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reg_phy_dis_calib_rst = 0x0
- // .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. reg_arb_page_addr_mask = 0x0
- // .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. reg_ddrc_lpddr2 = 0x0
- // .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_ddrc_per_bank_refresh = 0x0
- // .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_derate_enable = 0x0
- // .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_ddrc_mr4_margin = 0x0
- // .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. reg_ddrc_mr4_read_interval = 0x0
- // .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. reg_ddrc_t_mrw = 0x5
- // .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // ..
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. START: POLL ON DCI STATUS
- // .. DONE = 1
- // .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. FINISH: POLL ON DCI STATUS
- // .. START: UNLOCK DDR
- // .. reg_ddrc_soft_rstb = 0x1
- // .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_ddrc_powerdown_en = 0x0
- // .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_data_bus_width = 0x0
- // .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. reg_ddrc_burst8_refresh = 0x0
- // .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. reg_ddrc_rdwr_idle_gap = 1
- // .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. reg_ddrc_dis_rd_bypass = 0x0
- // .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. reg_ddrc_dis_act_bypass = 0x0
- // .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. reg_ddrc_dis_auto_refresh = 0x0
- // .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // ..
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. FINISH: UNLOCK DDR
- // .. START: CHECK DDR STATUS
- // .. ddrc_reg_operating_mode = 1
- // .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // ..
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. FINISH: CHECK DDR STATUS
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
// FINISH: top
//
EMIT_EXIT(),
@@ -1739,45 +1596,31 @@ unsigned long ps7_ddr_init_data_1_0[] = {
//
};
-unsigned long ps7_mio_init_data_1_0[] = {
+unsigned long ps7_mio_init_data_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
// .. FINISH: OCM REMAPPING
// .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B40[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x0
// .. ==> 0XF8000B40[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B40[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x0
// .. ==> 0XF8000B40[4:4] = 0x00000000U
// .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
+ // .. DCI_TYPE = 0x0
// .. ==> 0XF8000B40[6:5] = 0x00000000U
// .. ==> MASK : 0x00000060U VAL : 0x00000000U
// .. IBUF_DISABLE_MODE = 0x0
@@ -1794,19 +1637,19 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B44[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x0
// .. ==> 0XF8000B44[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B44[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x0
// .. ==> 0XF8000B44[4:4] = 0x00000000U
// .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
+ // .. DCI_TYPE = 0x0
// .. ==> 0XF8000B44[6:5] = 0x00000000U
// .. ==> MASK : 0x00000060U VAL : 0x00000000U
// .. IBUF_DISABLE_MODE = 0x0
@@ -1823,19 +1666,19 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B48[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x1
// .. ==> 0XF8000B48[2:1] = 0x00000001U
// .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B48[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B48[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
+ // .. DCI_TYPE = 0x3
// .. ==> 0XF8000B48[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -1852,19 +1695,19 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B4C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x1
// .. ==> 0XF8000B4C[2:1] = 0x00000001U
// .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B4C[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B4C[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
+ // .. DCI_TYPE = 0x3
// .. ==> 0XF8000B4C[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -1881,19 +1724,19 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B50[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x2
// .. ==> 0XF8000B50[2:1] = 0x00000002U
// .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B50[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B50[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
+ // .. DCI_TYPE = 0x3
// .. ==> 0XF8000B50[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -1910,19 +1753,19 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B54[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x2
// .. ==> 0XF8000B54[2:1] = 0x00000002U
// .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B54[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B54[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
+ // .. DCI_TYPE = 0x3
// .. ==> 0XF8000B54[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -1939,19 +1782,19 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
+ // .. reserved_INP_POWER = 0x0
// .. ==> 0XF8000B58[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x0
// .. ==> 0XF8000B58[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
+ // .. DCI_UPDATE_B = 0x0
// .. ==> 0XF8000B58[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x0
// .. ==> 0XF8000B58[4:4] = 0x00000000U
// .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
+ // .. DCI_TYPE = 0x0
// .. ==> 0XF8000B58[6:5] = 0x00000000U
// .. ==> MASK : 0x00000060U VAL : 0x00000000U
// .. IBUF_DISABLE_MODE = 0x0
@@ -1968,86 +1811,86 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B5C[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B5C[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
- // .. GTL = 0x0
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B5C[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B5C[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
// .. ==> 0XF8000B5C[26:24] = 0x00000000U
// .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
+ // .. reserved_RTERM = 0x0
// .. ==> 0XF8000B5C[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x00D6861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B60[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B60[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x6
// .. ==> 0XF8000B60[18:14] = 0x00000006U
// .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
+ // .. reserved_SLEW_N = 0x1f
// .. ==> 0XF8000B60[23:19] = 0x0000001FU
// .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
+ // .. reserved_GTL = 0x0
// .. ==> 0XF8000B60[26:24] = 0x00000000U
// .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
+ // .. reserved_RTERM = 0x0
// .. ==> 0XF8000B60[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B64[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B64[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x6
// .. ==> 0XF8000B64[18:14] = 0x00000006U
// .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
+ // .. reserved_SLEW_N = 0x1f
// .. ==> 0XF8000B64[23:19] = 0x0000001FU
// .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
+ // .. reserved_GTL = 0x0
// .. ==> 0XF8000B64[26:24] = 0x00000000U
// .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
+ // .. reserved_RTERM = 0x0
// .. ==> 0XF8000B64[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B68[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B68[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
- // .. GTL = 0x0
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B68[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B68[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
// .. ==> 0XF8000B68[26:24] = 0x00000000U
// .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
+ // .. reserved_RTERM = 0x0
// .. ==> 0XF8000B68[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00D6861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
// .. VREF_INT_EN = 0x0
// .. ==> 0XF8000B6C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2057,38 +1900,38 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. VREF_EXT_EN = 0x3
// .. ==> 0XF8000B6C[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
+ // .. reserved_VREF_PULLUP_EN = 0x0
// .. ==> 0XF8000B6C[8:7] = 0x00000000U
// .. ==> MASK : 0x00000180U VAL : 0x00000000U
// .. REFIO_EN = 0x1
// .. ==> 0XF8000B6C[9:9] = 0x00000001U
// .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
+ // .. reserved_REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
// .. ==> 0XF8000B6C[12:12] = 0x00000000U
// .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
// .. ==> 0XF8000B6C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
+ // .. reserved_CKE_PULLUP_EN = 0x0
// .. ==> 0XF8000B6C[14:14] = 0x00000000U
// .. ==> MASK : 0x00004000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
// .. .. START: ASSERT RESET
// .. .. RESET = 1
// .. .. ==> 0XF8000B70[0:0] = 0x00000001U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
// .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
// .. .. FINISH: ASSERT RESET
// .. .. START: DEASSERT RESET
// .. .. RESET = 0
// .. .. ==> 0XF8000B70[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
+ // .. .. reserved_VRN_OUT = 0x1
// .. .. ==> 0XF8000B70[5:5] = 0x00000001U
// .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
// .. ..
@@ -2100,16 +1943,16 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. .. ENABLE = 0x1
// .. .. ==> 0XF8000B70[1:1] = 0x00000001U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
+ // .. .. reserved_VRP_TRI = 0x0
// .. .. ==> 0XF8000B70[2:2] = 0x00000000U
// .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
+ // .. .. reserved_VRN_TRI = 0x0
// .. .. ==> 0XF8000B70[3:3] = 0x00000000U
// .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
+ // .. .. reserved_VRP_OUT = 0x0
// .. .. ==> 0XF8000B70[4:4] = 0x00000000U
// .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
+ // .. .. reserved_VRN_OUT = 0x1
// .. .. ==> 0XF8000B70[5:5] = 0x00000001U
// .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
// .. .. NREF_OPT1 = 0x0
@@ -2122,34 +1965,34 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. .. ==> 0XF8000B70[13:11] = 0x00000001U
// .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
// .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
// .. .. PREF_OPT2 = 0x0
// .. .. ==> 0XF8000B70[19:17] = 0x00000000U
// .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
// .. .. UPDATE_CONTROL = 0x0
// .. .. ==> 0XF8000B70[20:20] = 0x00000000U
// .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
+ // .. .. reserved_INIT_COMPLETE = 0x0
// .. .. ==> 0XF8000B70[21:21] = 0x00000000U
// .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
+ // .. .. reserved_TST_CLK = 0x0
// .. .. ==> 0XF8000B70[22:22] = 0x00000000U
// .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
+ // .. .. reserved_TST_HLN = 0x0
// .. .. ==> 0XF8000B70[23:23] = 0x00000000U
// .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
+ // .. .. reserved_TST_HLP = 0x0
// .. .. ==> 0XF8000B70[24:24] = 0x00000000U
// .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
+ // .. .. reserved_TST_RST = 0x0
// .. .. ==> 0XF8000B70[25:25] = 0x00000000U
// .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
+ // .. .. reserved_INT_DCI_EN = 0x0
// .. .. ==> 0XF8000B70[26:26] = 0x00000000U
// .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
// .. FINISH: DDRIOB SETTINGS
// .. START: MIO PROGRAMMING
// .. TRI_ENABLE = 0
@@ -2173,14 +2016,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000700[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000700[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000704[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2196,20 +2039,20 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000704[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000704[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000704[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000708[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2225,9 +2068,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000708[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000708[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -2238,7 +2081,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000708[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800070C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2254,9 +2097,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF800070C[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF800070C[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -2267,7 +2110,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF800070C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000710[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2283,9 +2126,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000710[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000710[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -2296,7 +2139,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000710[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000714[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2312,9 +2155,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000714[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000714[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -2325,7 +2168,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000714[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000718[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2341,9 +2184,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000718[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000718[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -2354,7 +2197,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000718[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800071C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2399,9 +2242,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000720[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000720[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -2412,7 +2255,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000720[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000724[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2434,14 +2277,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000724[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000724[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000728[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2454,9 +2297,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000728[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000728[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -2470,7 +2313,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000728[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800072C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2483,9 +2326,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF800072C[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF800072C[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -2499,7 +2342,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF800072C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000730[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2512,9 +2355,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000730[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000730[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -2528,7 +2371,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000730[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000734[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2541,9 +2384,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000734[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000734[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -2557,7 +2400,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> 0XF8000734[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000738[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2579,14 +2422,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000738[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000738[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800073C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2608,14 +2451,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 3
// .. ==> 0XF800073C[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800073C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000740[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2634,17 +2477,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000740[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000740[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000744[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2663,17 +2506,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000744[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000744[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000748[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2692,17 +2535,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000748[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000748[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800074C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2721,17 +2564,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF800074C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800074C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000750[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2750,17 +2593,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000750[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000750[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000754[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2779,17 +2622,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000754[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000754[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000758[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -2808,17 +2651,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000758[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000758[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000758[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800075C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -2837,17 +2680,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF800075C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800075C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800075C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000760[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -2866,17 +2709,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000760[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000760[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000760[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000764[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -2895,17 +2738,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000764[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000764[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000764[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000768[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -2924,17 +2767,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF8000768[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000768[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000768[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800076C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -2953,17 +2796,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. Speed = 1
// .. ==> 0XF800076C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800076C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800076C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000770[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2985,14 +2828,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000770[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000770[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000770[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000774[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -3014,14 +2857,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000774[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000774[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000774[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000778[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3043,14 +2886,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000778[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000778[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000778[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800077C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -3072,14 +2915,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800077C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800077C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800077C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000780[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3101,14 +2944,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000780[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000780[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000780[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000784[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3130,14 +2973,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000784[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000784[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000784[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000788[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3159,14 +3002,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000788[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000788[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000788[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800078C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3188,14 +3031,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800078C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800078C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800078C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000790[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -3217,14 +3060,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000790[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000790[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000790[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000794[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3246,14 +3089,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000794[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000794[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000794[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000798[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3275,14 +3118,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000798[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000798[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000798[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800079C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3304,14 +3147,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800079C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800079C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800079C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3326,21 +3169,21 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
// .. L3_SEL = 4
// .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3356,20 +3199,20 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A4[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A8[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3385,20 +3228,20 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A8[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007AC[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3414,20 +3257,20 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007AC[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007AC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007AC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007AC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3443,20 +3286,20 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007B0[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3472,37 +3315,49 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007B4[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B8[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007B8[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
// .. TRI_ENABLE = 1
// .. ==> 0XF80007BC[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -3512,14 +3367,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007BC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007BC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007C0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3532,26 +3387,26 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF80007C0[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007C0[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007C0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007C4[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -3561,26 +3416,26 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF80007C4[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007C4[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007C4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007C8[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -3599,17 +3454,17 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007C8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007CC[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -3628,14 +3483,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007CC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007CC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007D0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3657,14 +3512,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007D0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007D0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007D4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3686,26 +3541,29 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007D4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007D4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+ // .. SDIO0_WP_SEL = 55
+ // .. ==> 0XF8000830[5:0] = 0x00000037U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
// .. SDIO0_CD_SEL = 47
// .. ==> 0XF8000830[21:16] = 0x0000002FU
// .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
// ..
- EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
// .. FINISH: MIO PROGRAMMING
// .. START: LOCK IT BACK
// .. LOCK_KEY = 0X767B
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -3714,14 +3572,14 @@ unsigned long ps7_mio_init_data_1_0[] = {
//
};
-unsigned long ps7_peripherals_init_data_1_0[] = {
+unsigned long ps7_peripherals_init_data_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
// .. IBUF_DISABLE_MODE = 0x1
@@ -3762,7 +3620,7 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
@@ -3772,11 +3630,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // .. CD = 0x7c
+ // .. ==> 0XE0001018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
// ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -3806,12 +3664,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
@@ -3828,17 +3680,17 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
// .. BDIV = 0x6
// .. ==> 0XE0000034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0000018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // .. CD = 0x7c
+ // .. ==> 0XE0000018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
// ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
// .. STPBRK = 0x0
// .. ==> 0XE0000000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -3868,12 +3720,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0000004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
@@ -3890,8 +3736,15 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> 0XE0000004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
// .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
// .. START: PL POWER ON RESET REGISTERS
// .. PCFG_POR_CNT_4K = 0
// .. ==> 0XF8007000[29:29] = 0x00000000U
@@ -3919,141 +3772,91 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. .. START: NOR CS1 BASE ADDRESS
// .. .. FINISH: NOR CS1 BASE ADDRESS
// .. .. START: USB RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x0
- // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. ..
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
// .. .. FINISH: USB RESET
// .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
// .. .. .. START: DIR MODE BANK 0
// .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. FINISH: DIR MODE BANK 1
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
// .. .. .. START: OUTPUT ENABLE BANK 0
// .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: I2C RESET
+ // .. .. FINISH: NOR CHIP SELECT
// .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
// FINISH: top
//
@@ -4062,139 +3865,78 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
//
};
-unsigned long ps7_post_config_1_0[] = {
+unsigned long ps7_post_config_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 1
- // .. reserved_3 = 127
- // .. ==> 0XF8000240[31:25] = 0x0000007FU
- // .. ==> MASK : 0xFE000000U VAL : 0xFE000000U
- // .. FPGA_ACP_RST = 1
- // .. ==> 0XF8000240[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. FPGA_AXDS3_RST = 1
- // .. ==> 0XF8000240[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. FPGA_AXDS2_RST = 1
- // .. ==> 0XF8000240[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. FPGA_AXDS1_RST = 1
- // .. ==> 0XF8000240[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. FPGA_AXDS0_RST = 1
- // .. ==> 0XF8000240[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. reserved_2 = 3
- // .. ==> 0XF8000240[19:18] = 0x00000003U
- // .. ==> MASK : 0x000C0000U VAL : 0x000C0000U
- // .. FSSW1_FPGA_RST = 1
- // .. ==> 0XF8000240[17:17] = 0x00000001U
- // .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. FSSW0_FPGA_RST = 1
- // .. ==> 0XF8000240[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reserved_1 = 15
- // .. ==> 0XF8000240[15:14] = 0x0000000FU
- // .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. FPGA_FMSW1_RST = 1
- // .. ==> 0XF8000240[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. FPGA_FMSW0_RST = 1
- // .. ==> 0XF8000240[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. FPGA_DMA3_RST = 1
- // .. ==> 0XF8000240[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. FPGA_DMA2_RST = 1
- // .. ==> 0XF8000240[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. FPGA_DMA1_RST = 1
- // .. ==> 0XF8000240[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. FPGA_DMA0_RST = 1
- // .. ==> 0XF8000240[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. reserved = 15
- // .. ==> 0XF8000240[7:4] = 0x0000000FU
- // .. ==> MASK : 0x000000F0U VAL : 0x000000F0U
- // .. FPGA3_OUT_RST = 1
- // .. ==> 0XF8000240[3:3] = 0x00000001U
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
// .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. FPGA2_OUT_RST = 1
- // .. ==> 0XF8000240[2:2] = 0x00000001U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. FPGA1_OUT_RST = 1
- // .. ==> 0XF8000240[1:1] = 0x00000001U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. FPGA0_OUT_RST = 1
- // .. ==> 0XF8000240[0:0] = 0x00000001U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
- // .. FINISH: FPGA RESETS TO 1
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
// .. START: FPGA RESETS TO 0
// .. reserved_3 = 0
// .. ==> 0XF8000240[31:25] = 0x00000000U
// .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
+ // .. reserved_FPGA_ACP_RST = 0
// .. ==> 0XF8000240[24:24] = 0x00000000U
// .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
+ // .. reserved_FPGA_AXDS3_RST = 0
// .. ==> 0XF8000240[23:23] = 0x00000000U
// .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
+ // .. reserved_FPGA_AXDS2_RST = 0
// .. ==> 0XF8000240[22:22] = 0x00000000U
// .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
+ // .. reserved_FPGA_AXDS1_RST = 0
// .. ==> 0XF8000240[21:21] = 0x00000000U
// .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
+ // .. reserved_FPGA_AXDS0_RST = 0
// .. ==> 0XF8000240[20:20] = 0x00000000U
// .. ==> MASK : 0x00100000U VAL : 0x00000000U
// .. reserved_2 = 0
// .. ==> 0XF8000240[19:18] = 0x00000000U
// .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
+ // .. reserved_FSSW1_FPGA_RST = 0
// .. ==> 0XF8000240[17:17] = 0x00000000U
// .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
+ // .. reserved_FSSW0_FPGA_RST = 0
// .. ==> 0XF8000240[16:16] = 0x00000000U
// .. ==> MASK : 0x00010000U VAL : 0x00000000U
// .. reserved_1 = 0
// .. ==> 0XF8000240[15:14] = 0x00000000U
// .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
+ // .. reserved_FPGA_FMSW1_RST = 0
// .. ==> 0XF8000240[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
+ // .. reserved_FPGA_FMSW0_RST = 0
// .. ==> 0XF8000240[12:12] = 0x00000000U
// .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
+ // .. reserved_FPGA_DMA3_RST = 0
// .. ==> 0XF8000240[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
+ // .. reserved_FPGA_DMA2_RST = 0
// .. ==> 0XF8000240[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
+ // .. reserved_FPGA_DMA1_RST = 0
// .. ==> 0XF8000240[9:9] = 0x00000000U
// .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
+ // .. reserved_FPGA_DMA0_RST = 0
// .. ==> 0XF8000240[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. reserved = 0
@@ -4224,13 +3966,15 @@ unsigned long ps7_post_config_1_0[] = {
// .. .. FINISH: AFI2 REGISTERS
// .. .. START: AFI3 REGISTERS
// .. .. FINISH: AFI3 REGISTERS
+ // .. .. START: AFI2 SECURE REGISTER
+ // .. .. FINISH: AFI2 SECURE REGISTER
// .. FINISH: AFI REGISTERS
// .. START: LOCK IT BACK
// .. LOCK_KEY = 0X767B
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -4239,6 +3983,38 @@ unsigned long ps7_post_config_1_0[] = {
//
};
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
// .. START: SLCR SETTINGS
@@ -4246,27 +4022,27 @@ unsigned long ps7_pll_init_data_2_0[] = {
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: PLL SLCR REGISTERS
// .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000110[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
// .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -4328,23 +4104,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
// .. .. FINISH: ARM PLL INIT
// .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000114[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
// .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -4403,17 +4179,17 @@ unsigned long ps7_pll_init_data_2_0[] = {
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
// .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -4457,7 +4233,7 @@ unsigned long ps7_pll_init_data_2_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -4473,20 +4249,20 @@ unsigned long ps7_clock_init_data_2_0[] = {
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: CLOCK CONTROL SLCR REGISTERS
// .. CLKACT = 0x1
// .. ==> 0XF8000128[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
// .. CLKACT = 0x1
// .. ==> 0XF8000138[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -4541,128 +4317,97 @@ unsigned long ps7_clock_init_data_2_0[] = {
// .. ==> 0XF8000154[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x3
- // .. ==> 0XF8000180[5:4] = 0x00000003U
- // .. ==> MASK : 0x00000030U VAL : 0x00000030U
- // .. DIVISOR0 = 0x6
- // .. ==> 0XF8000180[13:8] = 0x00000006U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000600U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
- // .. SRCSEL = 0x2
- // .. ==> 0XF8000190[5:4] = 0x00000002U
- // .. ==> MASK : 0x00000030U VAL : 0x00000020U
- // .. DIVISOR0 = 0x35
- // .. ==> 0XF8000190[13:8] = 0x00000035U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003500U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000190[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF80001A0[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF8000154[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
// ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
// .. START: THIS SHOULD BE BLANK
@@ -4672,7 +4417,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -4712,9 +4457,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. ..
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
// .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
// .. .. reg_ddrc_active_ranks = 0x1
// .. .. ==> 0XF8006004[13:12] = 0x00000001U
// .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
@@ -4737,7 +4482,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. ==> 0XF8006004[28:28] = 0x00000000U
// .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
// .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
// .. .. ==> 0XF8006008[10:0] = 0x0000000FU
// .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
@@ -4771,29 +4516,29 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
// .. ..
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
// .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
// .. .. ==> 0XF8006014[20:14] = 0x00000010U
// .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
// .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
// .. .. reg_ddrc_powerdown_to_x32 = 0x6
// .. .. ==> 0XF8006018[9:5] = 0x00000006U
// .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
// .. .. reg_ddrc_t_ras_min = 0x13
// .. .. ==> 0XF8006018[26:22] = 0x00000013U
// .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
@@ -4801,30 +4546,30 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. ==> 0XF8006018[31:28] = 0x00000004U
// .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
// .. .. reg_ddrc_write_latency = 0x5
// .. .. ==> 0XF800601C[4:0] = 0x00000005U
// .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
// .. .. reg_ddrc_rd2wr = 0x7
// .. .. ==> 0XF800601C[9:5] = 0x00000007U
// .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
// .. .. reg_ddrc_pad_pd = 0x0
// .. .. ==> 0XF800601C[22:20] = 0x00000000U
// .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
// .. .. reg_ddrc_t_rcd = 0x7
// .. .. ==> 0XF800601C[31:28] = 0x00000007U
// .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
// .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
// .. .. reg_ddrc_t_ccd = 0x4
// .. .. ==> 0XF8006020[4:2] = 0x00000004U
// .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
@@ -4911,20 +4656,20 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
// .. .. reg_ddrc_emr = 0x4
// .. .. ==> 0XF8006030[31:16] = 0x00000004U
// .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
// .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
// .. .. reg_ddrc_burst_rdwr = 0x4
// .. .. ==> 0XF8006034[3:0] = 0x00000004U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x101
- // .. .. ==> 0XF8006034[13:4] = 0x00000101U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
// .. .. reg_ddrc_post_cke_x1024 = 0x1
// .. .. ==> 0XF8006034[25:16] = 0x00000001U
// .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
@@ -4932,7 +4677,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. ==> 0XF8006034[28:28] = 0x00000000U
// .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
// .. .. reg_ddrc_force_low_pri_n = 0x0
// .. .. ==> 0XF8006038[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -5011,14 +4756,14 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. reg_ddrc_addrmap_row_b13 = 0x6
// .. .. ==> 0XF8006044[19:16] = 0x00000006U
// .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
// .. .. reg_ddrc_addrmap_row_b15 = 0xf
// .. .. ==> 0XF8006044[27:24] = 0x0000000FU
// .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
// .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
// .. .. reg_ddrc_rank0_rd_odt = 0x0
// .. .. ==> 0XF8006048[2:0] = 0x00000000U
// .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
@@ -5197,795 +4942,787 @@ unsigned long ps7_ddr_init_data_2_0[] = {
// .. .. ==> 0XF800607C[19:16] = 0x00000003U
// .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
// .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF800612C[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
// .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF8006130[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
// .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9b
+ // .. .. ==> 0XF8006134[19:10] = 0x0000009BU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U
// .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa2
+ // .. .. ==> 0XF8006138[19:10] = 0x000000A2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U
// .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. FINISH: DDR INITIALIZATION
- // .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. CORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. UNCORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. STAT_NUM_CORR_ERR = 0x0
- // .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. STAT_NUM_UNCORR_ERR = 0x0
- // .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. reg_ddrc_ecc_mode = 0x0
- // .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. reg_ddrc_dis_scrub = 0x1
- // .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. reg_phy_dif_on = 0x0
- // .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. reg_phy_dif_off = 0x0
- // .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x92
- // .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x73
+ // .. .. ==> 0XF8006160[9:0] = 0x00000073U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf0
+ // .. .. ==> 0XF8006170[10:0] = 0x000000F0U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf7
+ // .. .. ==> 0XF8006174[10:0] = 0x000000F7U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. reg_phy_loopback = 0x0
- // .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_phy_bl2 = 0x0
- // .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_at_spd_atpg = 0x0
- // .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_bist_enable = 0x0
- // .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_bist_force_err = 0x0
- // .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_bist_mode = 0x0
- // .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reg_phy_invert_clkout = 0x1
- // .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reg_phy_sel_logic = 0x0
- // .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_ratio = 0x100
- // .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. reg_phy_ctrl_slave_force = 0x0
- // .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. reg_phy_use_rank0_delays = 0x1
- // .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. reg_phy_lpddr = 0x0
- // .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. reg_phy_cmd_latency = 0x0
- // .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. reg_phy_int_lpbk = 0x0
- // .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. reg_phy_wr_rl_delay = 0x2
- // .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. reg_phy_rd_rl_delay = 0x4
- // .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. reg_phy_dll_lock_diff = 0xf
- // .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. reg_phy_use_wr_level = 0x1
- // .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. reg_phy_use_rd_data_eye_level = 0x1
- // .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reg_phy_dis_calib_rst = 0x0
- // .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // ..
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. reg_arb_page_addr_mask = 0x0
- // .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. reg_ddrc_lpddr2 = 0x0
- // .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_ddrc_per_bank_refresh = 0x0
- // .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_derate_enable = 0x0
- // .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_ddrc_mr4_margin = 0x0
- // .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // ..
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. reg_ddrc_mr4_read_interval = 0x0
- // .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. reg_ddrc_t_mrw = 0x5
- // .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // ..
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. START: POLL ON DCI STATUS
- // .. DONE = 1
- // .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. FINISH: POLL ON DCI STATUS
- // .. START: UNLOCK DDR
- // .. reg_ddrc_soft_rstb = 0x1
- // .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_ddrc_powerdown_en = 0x0
- // .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_data_bus_width = 0x0
- // .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. reg_ddrc_burst8_refresh = 0x0
- // .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. reg_ddrc_rdwr_idle_gap = 1
- // .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. reg_ddrc_dis_rd_bypass = 0x0
- // .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. reg_ddrc_dis_act_bypass = 0x0
- // .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. reg_ddrc_dis_auto_refresh = 0x0
- // .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // ..
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. FINISH: UNLOCK DDR
- // .. START: CHECK DDR STATUS
- // .. ddrc_reg_operating_mode = 1
- // .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // ..
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. FINISH: CHECK DDR STATUS
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
// FINISH: top
//
EMIT_EXIT(),
@@ -6000,23 +5737,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
// .. FINISH: OCM REMAPPING
// .. START: DDRIOB SETTINGS
// .. INP_POWER = 0x0
@@ -6222,18 +5945,18 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B5C[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B5C[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B5C[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B5C[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
// .. GTL = 0x0
// .. ==> 0XF8000B5C[26:24] = 0x00000000U
// .. ==> MASK : 0x07000000U VAL : 0x00000000U
@@ -6241,13 +5964,13 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000B5C[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x00D6861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B60[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B60[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
// .. SLEW_P = 0x6
// .. ==> 0XF8000B60[18:14] = 0x00000006U
// .. ==> MASK : 0x0007C000U VAL : 0x00018000U
@@ -6261,13 +5984,13 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000B60[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B64[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B64[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
// .. SLEW_P = 0x6
// .. ==> 0XF8000B64[18:14] = 0x00000006U
// .. ==> MASK : 0x0007C000U VAL : 0x00018000U
@@ -6281,19 +6004,19 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000B64[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B68[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B68[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B68[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B68[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
// .. GTL = 0x0
// .. ==> 0XF8000B68[26:24] = 0x00000000U
// .. ==> MASK : 0x07000000U VAL : 0x00000000U
@@ -6301,7 +6024,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000B68[31:27] = 0x00000000U
// .. ==> MASK : 0xF8000000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00D6861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
// .. VREF_INT_EN = 0x0
// .. ==> 0XF8000B6C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6317,9 +6040,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. REFIO_EN = 0x1
// .. ==> 0XF8000B6C[9:9] = 0x00000001U
// .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
// .. REFIO_PULLUP_EN = 0x0
// .. ==> 0XF8000B6C[12:12] = 0x00000000U
// .. ==> MASK : 0x00001000U VAL : 0x00000000U
@@ -6330,7 +6053,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000B6C[14:14] = 0x00000000U
// .. ==> MASK : 0x00004000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E60U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
// .. .. START: ASSERT RESET
// .. .. RESET = 1
// .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -6430,14 +6153,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000700[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000700[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000704[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6453,20 +6176,20 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000704[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000704[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000704[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000708[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6482,9 +6205,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000708[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000708[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -6495,7 +6218,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000708[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800070C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6511,9 +6234,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF800070C[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF800070C[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -6524,7 +6247,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF800070C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000710[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6540,9 +6263,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000710[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000710[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -6553,7 +6276,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000710[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000714[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6569,9 +6292,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000714[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000714[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -6582,7 +6305,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000714[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000718[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6598,9 +6321,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000718[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000718[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -6611,7 +6334,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000718[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800071C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6656,9 +6379,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000720[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000720[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -6669,7 +6392,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000720[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000724[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6691,14 +6414,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000724[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000724[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000728[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6711,9 +6434,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000728[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000728[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -6727,7 +6450,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000728[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800072C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6740,9 +6463,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF800072C[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF800072C[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -6756,7 +6479,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF800072C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000730[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6769,9 +6492,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000730[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000730[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -6785,7 +6508,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000730[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000734[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6798,9 +6521,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000734[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000734[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -6814,7 +6537,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. ==> 0XF8000734[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000738[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6836,14 +6559,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000738[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000738[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800073C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6865,14 +6588,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 3
// .. ==> 0XF800073C[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800073C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000740[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6891,17 +6614,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000740[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000740[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000744[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6920,17 +6643,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000744[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000744[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000748[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6949,17 +6672,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000748[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000748[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800074C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6978,17 +6701,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF800074C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800074C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000750[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7007,17 +6730,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000750[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000750[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000754[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7036,17 +6759,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000754[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000754[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000758[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7065,17 +6788,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000758[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000758[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000758[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800075C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7094,17 +6817,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF800075C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800075C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800075C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000760[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7123,17 +6846,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000760[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000760[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000760[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000764[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7152,17 +6875,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000764[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000764[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000764[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000768[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7181,17 +6904,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF8000768[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000768[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000768[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800076C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7210,17 +6933,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. Speed = 1
// .. ==> 0XF800076C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800076C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800076C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000770[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7242,14 +6965,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000770[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000770[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000770[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000774[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7271,14 +6994,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000774[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000774[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000774[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000778[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7300,14 +7023,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000778[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000778[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000778[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800077C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7329,14 +7052,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800077C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800077C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800077C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000780[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7358,14 +7081,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000780[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000780[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000780[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000784[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7387,14 +7110,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000784[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000784[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000784[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000788[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7416,14 +7139,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000788[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000788[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000788[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800078C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7445,14 +7168,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800078C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800078C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800078C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000790[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7474,14 +7197,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000790[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000790[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000790[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000794[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7503,14 +7226,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000794[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000794[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000794[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000798[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7532,14 +7255,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000798[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000798[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000798[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800079C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7561,14 +7284,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800079C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800079C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800079C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7584,20 +7307,20 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A0[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7613,20 +7336,20 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A4[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A8[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7642,20 +7365,20 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A8[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007AC[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7671,20 +7394,20 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007AC[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007AC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007AC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007AC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7700,20 +7423,20 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007B0[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7729,37 +7452,49 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007B4[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B8[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007B8[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
// .. TRI_ENABLE = 1
// .. ==> 0XF80007BC[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -7769,14 +7504,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007BC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007BC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007C0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7789,26 +7524,26 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF80007C0[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007C0[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007C0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007C4[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -7818,26 +7553,26 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF80007C4[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007C4[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007C4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007C8[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -7856,17 +7591,17 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007C8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007CC[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -7885,14 +7620,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007CC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007CC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007D0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7914,14 +7649,14 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007D0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007D0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007D4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -7943,26 +7678,29 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007D4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007D4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+ // .. SDIO0_WP_SEL = 55
+ // .. ==> 0XF8000830[5:0] = 0x00000037U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
// .. SDIO0_CD_SEL = 47
// .. ==> 0XF8000830[21:16] = 0x0000002FU
// .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
// ..
- EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
// .. FINISH: MIO PROGRAMMING
// .. START: LOCK IT BACK
// .. LOCK_KEY = 0X767B
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -7978,7 +7716,7 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
// .. IBUF_DISABLE_MODE = 0x1
@@ -8019,7 +7757,7 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
@@ -8029,11 +7767,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // .. CD = 0x7c
+ // .. ==> 0XE0001018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
// ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -8091,11 +7829,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0000018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // .. CD = 0x7c
+ // .. ==> 0XE0000018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
// ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
// .. STPBRK = 0x0
// .. ==> 0XE0000000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -8183,141 +7921,91 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. .. START: NOR CS1 BASE ADDRESS
// .. .. FINISH: NOR CS1 BASE ADDRESS
// .. .. START: USB RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x0
- // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. ..
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
// .. .. FINISH: USB RESET
// .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
// .. .. .. START: DIR MODE BANK 0
// .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. FINISH: DIR MODE BANK 1
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
// .. .. .. START: OUTPUT ENABLE BANK 0
// .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: I2C RESET
+ // .. .. FINISH: NOR CHIP SELECT
// .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
// FINISH: top
//
@@ -8333,7 +8021,7 @@ unsigned long ps7_post_config_2_0[] = {
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: ENABLING LEVEL SHIFTER
// .. USER_INP_ICT_EN_0 = 3
@@ -8345,73 +8033,6 @@ unsigned long ps7_post_config_2_0[] = {
// ..
EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
// .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 1
- // .. reserved_3 = 127
- // .. ==> 0XF8000240[31:25] = 0x0000007FU
- // .. ==> MASK : 0xFE000000U VAL : 0xFE000000U
- // .. FPGA_ACP_RST = 1
- // .. ==> 0XF8000240[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. FPGA_AXDS3_RST = 1
- // .. ==> 0XF8000240[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. FPGA_AXDS2_RST = 1
- // .. ==> 0XF8000240[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. FPGA_AXDS1_RST = 1
- // .. ==> 0XF8000240[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. FPGA_AXDS0_RST = 1
- // .. ==> 0XF8000240[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. reserved_2 = 3
- // .. ==> 0XF8000240[19:18] = 0x00000003U
- // .. ==> MASK : 0x000C0000U VAL : 0x000C0000U
- // .. FSSW1_FPGA_RST = 1
- // .. ==> 0XF8000240[17:17] = 0x00000001U
- // .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. FSSW0_FPGA_RST = 1
- // .. ==> 0XF8000240[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reserved_1 = 15
- // .. ==> 0XF8000240[15:14] = 0x0000000FU
- // .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. FPGA_FMSW1_RST = 1
- // .. ==> 0XF8000240[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. FPGA_FMSW0_RST = 1
- // .. ==> 0XF8000240[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. FPGA_DMA3_RST = 1
- // .. ==> 0XF8000240[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. FPGA_DMA2_RST = 1
- // .. ==> 0XF8000240[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. FPGA_DMA1_RST = 1
- // .. ==> 0XF8000240[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. FPGA_DMA0_RST = 1
- // .. ==> 0XF8000240[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. reserved = 15
- // .. ==> 0XF8000240[7:4] = 0x0000000FU
- // .. ==> MASK : 0x000000F0U VAL : 0x000000F0U
- // .. FPGA3_OUT_RST = 1
- // .. ==> 0XF8000240[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. FPGA2_OUT_RST = 1
- // .. ==> 0XF8000240[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. FPGA1_OUT_RST = 1
- // .. ==> 0XF8000240[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. FPGA0_OUT_RST = 1
- // .. ==> 0XF8000240[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
- // .. FINISH: FPGA RESETS TO 1
// .. START: FPGA RESETS TO 0
// .. reserved_3 = 0
// .. ==> 0XF8000240[31:25] = 0x00000000U
@@ -8494,7 +8115,7 @@ unsigned long ps7_post_config_2_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -8503,34 +8124,66 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_pll_init_data_3_0[] = {
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: PLL SLCR REGISTERS
// .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000110[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
// .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -8592,23 +8245,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
// .. .. FINISH: ARM PLL INIT
// .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000114[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
// .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -8667,17 +8320,17 @@ unsigned long ps7_pll_init_data_3_0[] = {
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
// .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
// .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
// .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
@@ -8721,7 +8374,7 @@ unsigned long ps7_pll_init_data_3_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -8730,27 +8383,27 @@ unsigned long ps7_pll_init_data_3_0[] = {
//
};
-unsigned long ps7_clock_init_data_3_0[] = {
+unsigned long ps7_clock_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: CLOCK CONTROL SLCR REGISTERS
// .. CLKACT = 0x1
// .. ==> 0XF8000128[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
// .. CLKACT = 0x1
// .. ==> 0XF8000138[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -8807,126 +8460,95 @@ unsigned long ps7_clock_init_data_3_0[] = {
// .. SRCSEL = 0x0
// .. ==> 0XF8000154[5:4] = 0x00000000U
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x3
- // .. ==> 0XF8000180[5:4] = 0x00000003U
- // .. ==> MASK : 0x00000030U VAL : 0x00000030U
- // .. DIVISOR0 = 0x6
- // .. ==> 0XF8000180[13:8] = 0x00000006U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000600U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
- // .. SRCSEL = 0x2
- // .. ==> 0XF8000190[5:4] = 0x00000002U
- // .. ==> MASK : 0x00000030U VAL : 0x00000020U
- // .. DIVISOR0 = 0x35
- // .. ==> 0XF8000190[13:8] = 0x00000035U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003500U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000190[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF80001A0[13:8] = 0x0000000AU
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF8000154[13:8] = 0x0000000AU
// .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
// .. START: THIS SHOULD BE BLANK
@@ -8936,7 +8558,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -8945,7 +8567,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
//
};
-unsigned long ps7_ddr_init_data_3_0[] = {
+unsigned long ps7_ddr_init_data_1_0[] = {
// START: top
// .. START: DDR INITIALIZATION
// .. .. START: LOCK DDR
@@ -8976,17 +8598,32 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. ..
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
// .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
// .. .. ==> 0XF8006004[13:12] = 0x00000001U
// .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
// .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
// .. .. ==> 0XF8006004[18:14] = 0x00000000U
// .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
// .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
// .. .. ==> 0XF8006008[10:0] = 0x0000000FU
// .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
@@ -9020,29 +8657,29 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
// .. ..
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
// .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
// .. .. ==> 0XF8006014[20:14] = 0x00000010U
// .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
// .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
// .. .. reg_ddrc_powerdown_to_x32 = 0x6
// .. .. ==> 0XF8006018[9:5] = 0x00000006U
// .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
// .. .. reg_ddrc_t_ras_min = 0x13
// .. .. ==> 0XF8006018[26:22] = 0x00000013U
// .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
@@ -9050,30 +8687,30 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006018[31:28] = 0x00000004U
// .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
// .. .. reg_ddrc_write_latency = 0x5
// .. .. ==> 0XF800601C[4:0] = 0x00000005U
// .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
// .. .. reg_ddrc_rd2wr = 0x7
// .. .. ==> 0XF800601C[9:5] = 0x00000007U
// .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
// .. .. reg_ddrc_pad_pd = 0x0
// .. .. ==> 0XF800601C[22:20] = 0x00000000U
// .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
// .. .. reg_ddrc_t_rcd = 0x7
// .. .. ==> 0XF800601C[31:28] = 0x00000007U
// .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
// .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
// .. .. reg_ddrc_t_ccd = 0x4
// .. .. ==> 0XF8006020[4:2] = 0x00000004U
// .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
@@ -9089,10 +8726,13 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_ddrc_refresh_to_x32 = 0x8
// .. .. ==> 0XF8006020[20:16] = 0x00000008U
// .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
// .. .. reg_ddrc_mobile = 0x0
// .. .. ==> 0XF8006020[22:22] = 0x00000000U
// .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. reg_ddrc_clock_stop_en = 0x0
// .. .. ==> 0XF8006020[23:23] = 0x00000000U
// .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
// .. .. reg_ddrc_read_latency = 0x7
@@ -9104,14 +8744,20 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_ddrc_dis_pad_pd = 0x0
// .. .. ==> 0XF8006020[30:30] = 0x00000000U
// .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
// .. .. reg_ddrc_en_2t_timing_mode = 0x0
// .. .. ==> 0XF8006024[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. reg_ddrc_prefer_write = 0x0
// .. .. ==> 0XF8006024[1:1] = 0x00000000U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
// .. .. reg_ddrc_mr_wr = 0x0
// .. .. ==> 0XF8006024[6:6] = 0x00000000U
// .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
@@ -9131,7 +8777,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006024[27:27] = 0x00000000U
// .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
// .. .. reg_ddrc_final_wait_x32 = 0x7
// .. .. ==> 0XF8006028[6:0] = 0x00000007U
// .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
@@ -9151,20 +8797,20 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
// .. .. reg_ddrc_emr = 0x4
// .. .. ==> 0XF8006030[31:16] = 0x00000004U
// .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
// .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
// .. .. reg_ddrc_burst_rdwr = 0x4
// .. .. ==> 0XF8006034[3:0] = 0x00000004U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x101
- // .. .. ==> 0XF8006034[13:4] = 0x00000101U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
// .. .. reg_ddrc_post_cke_x1024 = 0x1
// .. .. ==> 0XF8006034[25:16] = 0x00000001U
// .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
@@ -9172,15 +8818,27 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006034[28:28] = 0x00000000U
// .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
// .. .. reg_ddrc_force_low_pri_n = 0x0
// .. .. ==> 0XF8006038[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. reg_ddrc_dis_dq = 0x0
// .. .. ==> 0XF8006038[1:1] = 0x00000000U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
// .. .. reg_ddrc_addrmap_bank_b0 = 0x7
// .. .. ==> 0XF800603C[3:0] = 0x00000007U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
@@ -9239,14 +8897,26 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_ddrc_addrmap_row_b13 = 0x6
// .. .. ==> 0XF8006044[19:16] = 0x00000006U
// .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
// .. .. reg_ddrc_addrmap_row_b15 = 0xf
// .. .. ==> 0XF8006044[27:24] = 0x0000000FU
// .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
// .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
// .. .. reg_phy_rd_local_odt = 0x0
// .. .. ==> 0XF8006048[13:12] = 0x00000000U
// .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
@@ -9256,8 +8926,20 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_idle_local_odt = 0x3
// .. .. ==> 0XF8006048[17:16] = 0x00000003U
// .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
// .. .. reg_phy_rd_cmd_to_data = 0x0
// .. .. ==> 0XF8006050[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
@@ -9290,11 +8972,17 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
// .. ..
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
// .. .. reg_ddrc_dis_dll_calib = 0x0
// .. .. ==> 0XF8006058[16:16] = 0x00000000U
// .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
// .. .. reg_ddrc_rd_odt_delay = 0x3
// .. .. ==> 0XF800605C[3:0] = 0x00000003U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
@@ -9359,43 +9047,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
// .. ..
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
// .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
// .. .. reg_ddrc_dis_auto_zq = 0x0
// .. .. ==> 0XF80060A4[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -9413,14 +9072,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
// .. ..
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
// .. .. deeppowerdown_en = 0x0
// .. .. ==> 0XF80060AC[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -9452,11 +9111,17 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
// .. ..
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
// .. .. reg_ddrc_skip_ocd = 0x1
// .. .. ==> 0XF80060B4[9:9] = 0x00000001U
// .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
// .. .. reg_ddrc_dfi_t_rddata_en = 0x6
// .. .. ==> 0XF80060B8[4:0] = 0x00000006U
// .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
@@ -9468,16 +9133,6 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
// .. ..
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
// .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
// .. .. ==> 0XF80060C4[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -9535,6 +9190,12 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_wrlvl_inc_mode = 0x0
// .. .. ==> 0XF8006118[3:3] = 0x00000000U
// .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. .. reg_phy_bist_shift_dq = 0x0
// .. .. ==> 0XF8006118[14:6] = 0x00000000U
// .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
@@ -9545,7 +9206,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006118[30:24] = 0x00000040U
// .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
// .. .. reg_phy_data_slice_in_use = 0x1
// .. .. ==> 0XF800611C[0:0] = 0x00000001U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -9558,6 +9219,12 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_wrlvl_inc_mode = 0x0
// .. .. ==> 0XF800611C[3:3] = 0x00000000U
// .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. .. reg_phy_bist_shift_dq = 0x0
// .. .. ==> 0XF800611C[14:6] = 0x00000000U
// .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
@@ -9568,7 +9235,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF800611C[30:24] = 0x00000040U
// .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
// .. .. reg_phy_data_slice_in_use = 0x1
// .. .. ==> 0XF8006120[0:0] = 0x00000001U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -9581,6 +9248,12 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_wrlvl_inc_mode = 0x0
// .. .. ==> 0XF8006120[3:3] = 0x00000000U
// .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. .. reg_phy_bist_shift_dq = 0x0
// .. .. ==> 0XF8006120[14:6] = 0x00000000U
// .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
@@ -9591,7 +9264,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006120[30:24] = 0x00000040U
// .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
// .. .. reg_phy_data_slice_in_use = 0x1
// .. .. ==> 0XF8006124[0:0] = 0x00000001U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -9604,6 +9277,12 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_wrlvl_inc_mode = 0x0
// .. .. ==> 0XF8006124[3:3] = 0x00000000U
// .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. .. reg_phy_bist_shift_dq = 0x0
// .. .. ==> 0XF8006124[14:6] = 0x00000000U
// .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
@@ -9614,39 +9293,39 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006124[30:24] = 0x00000040U
// .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
// .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
// .. .. reg_phy_wrlvl_init_ratio = 0x0
// .. .. ==> 0XF800612C[9:0] = 0x00000000U
// .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF800612C[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
// .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U),
// .. .. reg_phy_wrlvl_init_ratio = 0x0
// .. .. ==> 0XF8006130[9:0] = 0x00000000U
// .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF8006130[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
// .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U),
// .. .. reg_phy_wrlvl_init_ratio = 0x0
// .. .. ==> 0XF8006134[9:0] = 0x00000000U
// .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9b
+ // .. .. ==> 0XF8006134[19:10] = 0x0000009BU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U
// .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U),
// .. .. reg_phy_wrlvl_init_ratio = 0x0
// .. .. ==> 0XF8006138[9:0] = 0x00000000U
// .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa2
+ // .. .. ==> 0XF8006138[19:10] = 0x000000A2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U
// .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U),
// .. .. reg_phy_rd_dqs_slave_ratio = 0x35
// .. .. ==> 0XF8006140[9:0] = 0x00000035U
// .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
@@ -9691,9 +9370,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
// .. .. reg_phy_wr_dqs_slave_force = 0x0
// .. .. ==> 0XF8006154[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
@@ -9701,10 +9380,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006154[19:11] = 0x00000000U
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
// .. .. reg_phy_wr_dqs_slave_force = 0x0
// .. .. ==> 0XF8006158[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
@@ -9712,7 +9391,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006158[19:11] = 0x00000000U
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU),
// .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
// .. .. ==> 0XF800615C[9:0] = 0x0000007CU
// .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
@@ -9724,9 +9403,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x73
+ // .. .. ==> 0XF8006160[9:0] = 0x00000073U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U
// .. .. reg_phy_wr_dqs_slave_force = 0x0
// .. .. ==> 0XF8006160[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
@@ -9734,10 +9413,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006160[19:11] = 0x00000000U
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
// .. .. reg_phy_fifo_we_in_force = 0x0
// .. .. ==> 0XF8006168[11:11] = 0x00000000U
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
@@ -9745,10 +9424,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006168[20:12] = 0x00000000U
// .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
// .. .. reg_phy_fifo_we_in_force = 0x0
// .. .. ==> 0XF800616C[11:11] = 0x00000000U
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
@@ -9756,10 +9435,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF800616C[20:12] = 0x00000000U
// .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf0
+ // .. .. ==> 0XF8006170[10:0] = 0x000000F0U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U
// .. .. reg_phy_fifo_we_in_force = 0x0
// .. .. ==> 0XF8006170[11:11] = 0x00000000U
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
@@ -9767,10 +9446,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006170[20:12] = 0x00000000U
// .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf7
+ // .. .. ==> 0XF8006174[10:0] = 0x000000F7U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U
// .. .. reg_phy_fifo_we_in_force = 0x0
// .. .. ==> 0XF8006174[11:11] = 0x00000000U
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
@@ -9778,10 +9457,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006174[20:12] = 0x00000000U
// .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
// .. .. reg_phy_wr_data_slave_force = 0x0
// .. .. ==> 0XF800617C[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
@@ -9789,10 +9468,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF800617C[19:11] = 0x00000000U
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
// .. .. reg_phy_wr_data_slave_force = 0x0
// .. .. ==> 0XF8006180[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
@@ -9800,7 +9479,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006180[19:11] = 0x00000000U
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU),
// .. .. reg_phy_wr_data_slave_ratio = 0xbc
// .. .. ==> 0XF8006184[9:0] = 0x000000BCU
// .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
@@ -9812,9 +9491,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U
// .. .. reg_phy_wr_data_slave_force = 0x0
// .. .. ==> 0XF8006188[10:10] = 0x00000000U
// .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
@@ -9822,7 +9501,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF8006188[19:11] = 0x00000000U
// .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. reg_phy_bl2 = 0x0
// .. .. ==> 0XF8006190[1:1] = 0x00000000U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -9841,6 +9523,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_invert_clkout = 0x1
// .. .. ==> 0XF8006190[7:7] = 0x00000001U
// .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. .. reg_phy_sel_logic = 0x0
// .. .. ==> 0XF8006190[9:9] = 0x00000000U
// .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
@@ -9853,14 +9538,20 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_phy_ctrl_slave_delay = 0x0
// .. .. ==> 0XF8006190[27:21] = 0x00000000U
// .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
// .. .. reg_phy_lpddr = 0x0
// .. .. ==> 0XF8006190[29:29] = 0x00000000U
// .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
// .. .. reg_phy_cmd_latency = 0x0
// .. .. ==> 0XF8006190[30:30] = 0x00000000U
// .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
// .. .. reg_phy_wr_rl_delay = 0x2
// .. .. ==> 0XF8006194[4:0] = 0x00000002U
// .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
@@ -9904,8 +9595,11 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_arb_dis_page_match_wr_portn = 0x0
// .. .. ==> 0XF8006208[18:18] = 0x00000000U
// .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
// .. .. reg_arb_pri_wr_portn = 0x3ff
// .. .. ==> 0XF800620C[9:0] = 0x000003FFU
// .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
@@ -9918,8 +9612,11 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_arb_dis_page_match_wr_portn = 0x0
// .. .. ==> 0XF800620C[18:18] = 0x00000000U
// .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
// .. .. reg_arb_pri_wr_portn = 0x3ff
// .. .. ==> 0XF8006210[9:0] = 0x000003FFU
// .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
@@ -9932,8 +9629,11 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_arb_dis_page_match_wr_portn = 0x0
// .. .. ==> 0XF8006210[18:18] = 0x00000000U
// .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
// .. .. reg_arb_pri_wr_portn = 0x3ff
// .. .. ==> 0XF8006214[9:0] = 0x000003FFU
// .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
@@ -9946,8 +9646,11 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_arb_dis_page_match_wr_portn = 0x0
// .. .. ==> 0XF8006214[18:18] = 0x00000000U
// .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
// .. .. reg_arb_pri_rd_portn = 0x3ff
// .. .. ==> 0XF8006218[9:0] = 0x000003FFU
// .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
@@ -10019,6 +9722,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. reg_ddrc_lpddr2 = 0x0
// .. .. ==> 0XF80062A8[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
// .. .. reg_ddrc_derate_enable = 0x0
// .. .. ==> 0XF80062A8[2:2] = 0x00000000U
// .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
@@ -10026,7 +9732,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> 0XF80062A8[11:4] = 0x00000000U
// .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
// .. .. reg_ddrc_mr4_read_interval = 0x0
// .. .. ==> 0XF80062AC[31:0] = 0x00000000U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
@@ -10043,14 +9749,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
// .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
// .. ..
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
// .. .. reg_ddrc_dev_zqinit_x32 = 0x12
// .. .. ==> 0XF80062B4[17:8] = 0x00000012U
// .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
// .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
// .. .. START: POLL ON DCI STATUS
// .. .. DONE = 1
// .. .. ==> 0XF8000B74[13:13] = 0x00000001U
@@ -10101,36 +9807,31 @@ unsigned long ps7_ddr_init_data_3_0[] = {
//
};
-unsigned long ps7_mio_init_data_3_0[] = {
+unsigned long ps7_mio_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B00[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
// .. FINISH: OCM REMAPPING
// .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x0
// .. ==> 0XF8000B40[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B40[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x0
// .. ==> 0XF8000B40[4:4] = 0x00000000U
// .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
+ // .. DCR_TYPE = 0x0
// .. ==> 0XF8000B40[6:5] = 0x00000000U
// .. ==> MASK : 0x00000060U VAL : 0x00000000U
// .. IBUF_DISABLE_MODE = 0x0
@@ -10146,17 +9847,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B40[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFEU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x0
// .. ==> 0XF8000B44[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B44[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x0
// .. ==> 0XF8000B44[4:4] = 0x00000000U
// .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
+ // .. DCR_TYPE = 0x0
// .. ==> 0XF8000B44[6:5] = 0x00000000U
// .. ==> MASK : 0x00000060U VAL : 0x00000000U
// .. IBUF_DISABLE_MODE = 0x0
@@ -10172,17 +9876,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B44[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFEU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x1
// .. ==> 0XF8000B48[2:1] = 0x00000001U
// .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B48[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B48[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
+ // .. DCR_TYPE = 0x3
// .. ==> 0XF8000B48[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -10198,17 +9905,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B48[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFEU ,0x00000672U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x1
// .. ==> 0XF8000B4C[2:1] = 0x00000001U
// .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B4C[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B4C[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
+ // .. DCR_TYPE = 0x3
// .. ==> 0XF8000B4C[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -10224,17 +9934,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B4C[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFEU ,0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x2
// .. ==> 0XF8000B50[2:1] = 0x00000002U
// .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B50[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B50[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
+ // .. DCR_TYPE = 0x3
// .. ==> 0XF8000B50[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -10250,17 +9963,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B50[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFEU ,0x00000674U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x2
// .. ==> 0XF8000B54[2:1] = 0x00000002U
// .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B54[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x1
// .. ==> 0XF8000B54[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
+ // .. DCR_TYPE = 0x3
// .. ==> 0XF8000B54[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
// .. IBUF_DISABLE_MODE = 0
@@ -10276,17 +9992,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B54[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFEU ,0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. INP_TYPE = 0x0
// .. ==> 0XF8000B58[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
+ // .. DCI_UPDATE = 0x0
// .. ==> 0XF8000B58[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. TERM_EN = 0x0
// .. ==> 0XF8000B58[4:4] = 0x00000000U
// .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
+ // .. DCR_TYPE = 0x0
// .. ==> 0XF8000B58[6:5] = 0x00000000U
// .. ==> MASK : 0x00000060U VAL : 0x00000000U
// .. IBUF_DISABLE_MODE = 0x0
@@ -10302,7 +10021,87 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000B58[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFEU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B5C[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B5C[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B60[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B60[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B64[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B64[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B68[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B68[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
// .. VREF_INT_EN = 0x0
// .. ==> 0XF8000B6C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10312,24 +10111,42 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. VREF_EXT_EN = 0x3
// .. ==> 0XF8000B6C[6:5] = 0x00000003U
// .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
// .. REFIO_EN = 0x1
// .. ==> 0XF8000B6C[9:9] = 0x00000001U
// .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000B6C, 0x0000027FU ,0x00000260U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
// .. .. START: ASSERT RESET
// .. .. RESET = 1
// .. .. ==> 0XF8000B70[0:0] = 0x00000001U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
// .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
// .. .. FINISH: ASSERT RESET
// .. .. START: DEASSERT RESET
// .. .. RESET = 0
// .. .. ==> 0XF8000B70[0:0] = 0x00000000U
// .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
// .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000000U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
// .. .. FINISH: DEASSERT RESET
// .. .. RESET = 0x1
// .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -10337,6 +10154,18 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. .. ENABLE = 0x1
// .. .. ==> 0XF8000B70[1:1] = 0x00000001U
// .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
// .. .. NREF_OPT1 = 0x0
// .. .. ==> 0XF8000B70[7:6] = 0x00000000U
// .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
@@ -10346,14 +10175,35 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. .. NREF_OPT4 = 0x1
// .. .. ==> 0XF8000B70[13:11] = 0x00000001U
// .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
// .. .. PREF_OPT2 = 0x0
// .. .. ==> 0XF8000B70[19:17] = 0x00000000U
// .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
// .. .. UPDATE_CONTROL = 0x0
// .. .. ==> 0XF8000B70[20:20] = 0x00000000U
// .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
// .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x001E3FC3U ,0x00000803U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
// .. FINISH: DDRIOB SETTINGS
// .. START: MIO PROGRAMMING
// .. TRI_ENABLE = 0
@@ -10377,14 +10227,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000700[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000700[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000704[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10400,20 +10250,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000704[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000704[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000704[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000708[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10429,9 +10279,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000708[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000708[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -10442,7 +10292,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000708[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800070C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10458,9 +10308,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF800070C[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF800070C[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -10471,7 +10321,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF800070C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000710[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10487,9 +10337,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000710[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000710[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -10500,7 +10350,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000710[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000714[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10516,9 +10366,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000714[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000714[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -10529,7 +10379,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000714[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000718[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10545,9 +10395,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000718[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000718[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -10558,7 +10408,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000718[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800071C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10603,9 +10453,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 0
// .. ==> 0XF8000720[7:5] = 0x00000000U
// .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000720[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
@@ -10616,7 +10466,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000720[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000724[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10638,14 +10488,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000724[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000724[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000728[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10658,9 +10508,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000728[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000728[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -10674,7 +10524,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000728[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800072C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10687,9 +10537,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF800072C[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF800072C[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -10703,7 +10553,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF800072C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000730[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10716,9 +10566,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000730[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000730[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -10732,7 +10582,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000730[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000734[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10745,9 +10595,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000734[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF8000734[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -10761,7 +10611,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> 0XF8000734[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000738[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10783,14 +10633,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 3
// .. ==> 0XF8000738[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000738[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800073C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10812,14 +10662,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 3
// .. ==> 0XF800073C[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800073C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000740[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10838,17 +10688,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000740[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000740[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000744[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10867,17 +10717,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000744[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000744[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000748[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10896,17 +10746,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000748[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000748[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800074C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10925,17 +10775,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF800074C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800074C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000750[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10954,17 +10804,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000750[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000750[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000754[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10983,17 +10833,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000754[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000754[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000758[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11012,17 +10862,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000758[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000758[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000758[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800075C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11041,17 +10891,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF800075C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800075C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800075C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000760[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11070,17 +10920,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000760[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000760[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000760[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000764[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11099,17 +10949,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000764[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000764[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000764[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000768[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11128,17 +10978,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF8000768[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000768[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000768[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800076C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11157,17 +11007,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. Speed = 1
// .. ==> 0XF800076C[8:8] = 0x00000001U
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800076C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800076C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000770[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11189,14 +11039,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000770[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000770[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000770[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000774[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11218,14 +11068,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000774[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000774[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000774[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000778[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11247,14 +11097,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000778[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000778[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000778[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF800077C[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11276,14 +11126,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800077C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800077C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800077C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000780[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11305,14 +11155,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000780[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000780[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000780[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000784[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11334,14 +11184,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000784[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000784[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000784[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000788[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11363,14 +11213,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000788[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000788[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000788[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800078C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11392,14 +11242,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF800078C[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF800078C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800078C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 1
// .. ==> 0XF8000790[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11421,14 +11271,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000790[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000790[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000790[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000794[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11450,14 +11300,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000794[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000794[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000794[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000798[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11479,14 +11329,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF8000798[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000798[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000798[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF800079C[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11507,15 +11357,15 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. ==> MASK : 0x00000100U VAL : 0x00000100U
// .. IO_Type = 1
// .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800079C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF800079C[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11531,20 +11381,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A0[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11560,20 +11410,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A4[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007A8[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11589,20 +11439,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007A8[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007A8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007A8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007AC[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11618,20 +11468,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007AC[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007AC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007AC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007AC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11647,20 +11497,20 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007B0[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11676,37 +11526,49 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L3_SEL = 4
// .. ==> 0XF80007B4[7:5] = 0x00000004U
// .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007B8[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007B8[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007B8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007B8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
// .. TRI_ENABLE = 1
// .. ==> 0XF80007BC[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
@@ -11716,14 +11578,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007BC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007BC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007C0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11736,26 +11598,26 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF80007C0[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007C0[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007C0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007C4[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -11765,26 +11627,26 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF80007C4[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
// .. Speed = 0
// .. ==> 0XF80007C4[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 1
// .. ==> 0XF80007C4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007C8[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -11803,17 +11665,17 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007C8[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007C8[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. L0_SEL = 0
// .. ==> 0XF80007CC[1:1] = 0x00000000U
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
@@ -11832,14 +11694,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007CC[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007CC[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007D0[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11861,14 +11723,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007D0[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007D0[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
// .. TRI_ENABLE = 0
// .. ==> 0XF80007D4[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11890,26 +11752,29 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. IO_Type = 1
// .. ==> 0XF80007D4[11:9] = 0x00000001U
// .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF80007D4[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+ // .. SDIO0_WP_SEL = 55
+ // .. ==> 0XF8000830[5:0] = 0x00000037U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
// .. SDIO0_CD_SEL = 47
// .. ==> 0XF8000830[21:16] = 0x0000002FU
// .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
// ..
- EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
// .. FINISH: MIO PROGRAMMING
// .. START: LOCK IT BACK
// .. LOCK_KEY = 0X767B
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -11918,14 +11783,14 @@ unsigned long ps7_mio_init_data_3_0[] = {
//
};
-unsigned long ps7_peripherals_init_data_3_0[] = {
+unsigned long ps7_peripherals_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
// .. IBUF_DISABLE_MODE = 0x1
@@ -11966,7 +11831,7 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
@@ -11976,11 +11841,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // .. CD = 0x7c
+ // .. ==> 0XE0001018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
// ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -12010,6 +11875,12 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
@@ -12026,17 +11897,17 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. BDIV = 0x6
// .. ==> 0XE0000034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0000018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // .. CD = 0x7c
+ // .. ==> 0XE0000018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
// ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
// .. STPBRK = 0x0
// .. ==> 0XE0000000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -12066,6 +11937,12 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0000004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0000004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0000004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
@@ -12082,7 +11959,7 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> 0XE0000004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
@@ -12118,141 +11995,91 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. .. START: NOR CS1 BASE ADDRESS
// .. .. FINISH: NOR CS1 BASE ADDRESS
// .. .. START: USB RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x0
- // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. ..
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
// .. .. FINISH: USB RESET
// .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
// .. .. .. START: DIR MODE BANK 0
// .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. FINISH: DIR MODE BANK 1
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
// .. .. .. START: OUTPUT ENABLE BANK 0
// .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: I2C RESET
+ // .. .. FINISH: NOR CHIP SELECT
// .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
// FINISH: top
//
@@ -12261,145 +12088,72 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
//
};
-unsigned long ps7_post_config_3_0[] = {
+unsigned long ps7_post_config_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
// ..
EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
// .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 1
- // .. reserved_3 = 127
- // .. ==> 0XF8000240[31:25] = 0x0000007FU
- // .. ==> MASK : 0xFE000000U VAL : 0xFE000000U
- // .. reserved_FPGA_ACP_RST = 1
- // .. ==> 0XF8000240[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. reserved_FPGA_AXDS3_RST = 1
- // .. ==> 0XF8000240[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. reserved_FPGA_AXDS2_RST = 1
- // .. ==> 0XF8000240[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. reserved_FPGA_AXDS1_RST = 1
- // .. ==> 0XF8000240[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. reserved_FPGA_AXDS0_RST = 1
- // .. ==> 0XF8000240[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. reserved_2 = 3
- // .. ==> 0XF8000240[19:18] = 0x00000003U
- // .. ==> MASK : 0x000C0000U VAL : 0x000C0000U
- // .. reserved_FSSW1_FPGA_RST = 1
- // .. ==> 0XF8000240[17:17] = 0x00000001U
- // .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. reserved_FSSW0_FPGA_RST = 1
- // .. ==> 0XF8000240[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reserved_1 = 15
- // .. ==> 0XF8000240[15:14] = 0x0000000FU
- // .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. reserved_FPGA_FMSW1_RST = 1
- // .. ==> 0XF8000240[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. reserved_FPGA_FMSW0_RST = 1
- // .. ==> 0XF8000240[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. reserved_FPGA_DMA3_RST = 1
- // .. ==> 0XF8000240[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. reserved_FPGA_DMA2_RST = 1
- // .. ==> 0XF8000240[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. reserved_FPGA_DMA1_RST = 1
- // .. ==> 0XF8000240[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_FPGA_DMA0_RST = 1
- // .. ==> 0XF8000240[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. reserved = 15
- // .. ==> 0XF8000240[7:4] = 0x0000000FU
- // .. ==> MASK : 0x000000F0U VAL : 0x000000F0U
- // .. FPGA3_OUT_RST = 1
- // .. ==> 0XF8000240[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. FPGA2_OUT_RST = 1
- // .. ==> 0XF8000240[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. FPGA1_OUT_RST = 1
- // .. ==> 0XF8000240[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. FPGA0_OUT_RST = 1
- // .. ==> 0XF8000240[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
- // .. FINISH: FPGA RESETS TO 1
// .. START: FPGA RESETS TO 0
// .. reserved_3 = 0
// .. ==> 0XF8000240[31:25] = 0x00000000U
// .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
+ // .. FPGA_ACP_RST = 0
// .. ==> 0XF8000240[24:24] = 0x00000000U
// .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
+ // .. FPGA_AXDS3_RST = 0
// .. ==> 0XF8000240[23:23] = 0x00000000U
// .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
+ // .. FPGA_AXDS2_RST = 0
// .. ==> 0XF8000240[22:22] = 0x00000000U
// .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
+ // .. FPGA_AXDS1_RST = 0
// .. ==> 0XF8000240[21:21] = 0x00000000U
// .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
+ // .. FPGA_AXDS0_RST = 0
// .. ==> 0XF8000240[20:20] = 0x00000000U
// .. ==> MASK : 0x00100000U VAL : 0x00000000U
// .. reserved_2 = 0
// .. ==> 0XF8000240[19:18] = 0x00000000U
// .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
+ // .. FSSW1_FPGA_RST = 0
// .. ==> 0XF8000240[17:17] = 0x00000000U
// .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
+ // .. FSSW0_FPGA_RST = 0
// .. ==> 0XF8000240[16:16] = 0x00000000U
// .. ==> MASK : 0x00010000U VAL : 0x00000000U
// .. reserved_1 = 0
// .. ==> 0XF8000240[15:14] = 0x00000000U
// .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
+ // .. FPGA_FMSW1_RST = 0
// .. ==> 0XF8000240[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
+ // .. FPGA_FMSW0_RST = 0
// .. ==> 0XF8000240[12:12] = 0x00000000U
// .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
+ // .. FPGA_DMA3_RST = 0
// .. ==> 0XF8000240[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
+ // .. FPGA_DMA2_RST = 0
// .. ==> 0XF8000240[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
+ // .. FPGA_DMA1_RST = 0
// .. ==> 0XF8000240[9:9] = 0x00000000U
// .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
+ // .. FPGA_DMA0_RST = 0
// .. ==> 0XF8000240[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. reserved = 0
@@ -12435,7 +12189,7 @@ unsigned long ps7_post_config_3_0[] = {
// .. ==> 0XF8000004[15:0] = 0x0000767BU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
// ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
// .. FINISH: LOCK IT BACK
// FINISH: top
//
@@ -12444,6 +12198,38 @@ unsigned long ps7_post_config_3_0[] = {
//
};
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
#include "xil_io.h"
#define PS7_MASK_POLL_TIME 100000000
@@ -12475,14 +12261,14 @@ ps7GetSiliconVersion () {
}
void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
+ volatile unsigned long *addr = (volatile unsigned long*) add;
*addr = ( val & mask ) | ( *addr & ~mask);
//xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
}
int mask_poll(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
+ volatile unsigned long *addr = (volatile unsigned long*) add;
int i = 0;
while (!(*addr & mask)) {
if (i == PS7_MASK_POLL_TIME) {
@@ -12495,7 +12281,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
}
unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
+ volatile unsigned long *addr = (volatile unsigned long*) add;
unsigned long val = (*addr & mask);
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
return val;
@@ -12564,6 +12350,14 @@ ps7_config(unsigned long * ps7_config_init)
i++;
}
break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
default:
finish = PS7_INIT_CORRUPT;
break;
@@ -12597,13 +12391,34 @@ ps7_post_config()
return PS7_INIT_SUCCESS;
}
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+
int
ps7_init()
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
//int pcw_ver = 0;
-
+
if (si_ver == PCW_SILICON_VERSION_1) {
ps7_mio_init_data = ps7_mio_init_data_1_0;
ps7_pll_init_data = ps7_pll_init_data_1_0;
@@ -12630,7 +12445,7 @@ ps7_init()
}
// MIO init
- int ret = ps7_config (ps7_mio_init_data);
+ ret = ps7_config (ps7_mio_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
// PLL init
@@ -12646,6 +12461,7 @@ ps7_init()
if (ret != PS7_INIT_SUCCESS) return ret;
+
// Peripherals init
ret = ps7_config (ps7_peripherals_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
@@ -12653,3 +12469,48 @@ ps7_init()
return PS7_INIT_SUCCESS;
}
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+
+
+
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.h b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.h
similarity index 50%
rename from quad/xsdk_workspace/zybo_fsbl/src/ps7_init.h
rename to quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.h
index d63682e6a8d848399e05e9962eb7473e84e4a954..60b56c6ed45112aab04e1e89334f2e930d52fe9f 100644
--- a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.h
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.h
@@ -1,42 +1,28 @@
-
/******************************************************************************
*
-* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
@@ -50,6 +36,9 @@
*
*****************************************************************************/
+
+
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -73,17 +62,16 @@ extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
-
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-
-
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
@@ -104,36 +92,48 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10159000
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158730
#define QSPI_FREQ 200000000
-#define SMC_FREQ 100000000
+#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
-#define ENET1_FREQ 125000000
+#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 166666666
-#define I2C_FREQ 108333336
-#define WDT_FREQ 133333333
+#define UART_FREQ 100000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
-#define CAN_FREQ 100000000
+#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
-#define TPIU_FREQ 0
+#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 175000000
-#define FPGA2_FREQ 12288000
-#define FPGA3_FREQ 100000000
-#define C_CPU_REF_CLK_FREQ_HZ 50000000
+#define FPGA1_FREQ 10000000
+#define FPGA2_FREQ 10000000
+#define FPGA3_FREQ 10000000
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
+int ps7_debug();
char* getPS7MessageInfo(unsigned key);
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
+
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.html b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.html
new file mode 100644
index 0000000000000000000000000000000000000000..95f925c3c9b9703e1881adfd491f52db7f1398ee
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.html
@@ -0,0 +1,141887 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="content-type" content="text/html;charset=UTF-8">
+<title>Zynq PS configuration detail</title>
+<style type="text/css">.sitename { background-color: #EEE;border:2px ridge #FFCF01;color: #B20838; font-size:22px; font-style:oblique; font-weight:bold;margin:0px 0px 10px 0px;padding:5px 0px; text-align:center; z-index: 3; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.navpath {color: #FFCF01; font-size:8px;padding: 7px 2px 2px 11px; text-transform: capitalize; z-index:2;}.navbar { background-color: #B20838; background-color: #EE3424;color: #fff;border: 1px solid #000; border-left: 0px solid #000; border-right: 0px solid #000; font-family: arial, sans-serif; font-weight: bold;height:50px; letter-spacing: 2px; text-transform: uppercase;position:fixed;top:0px;left:0px;right:0px; z-index: 0; /* -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px; */}.navlink_container { text-align:center;position: absolute;bottom:-1px;}.navbar a {color: #FFF;}.navbar a:hover {color: #EC891D;}.navbar ul { margin-left: 0px;height: 70px;overflow: hidden;}.navbar li { background-color: #B20838;padding: 4px 400px 4px 400px;float: left; font-size:24px;width: 800px;}.navbar li:hover { background-color: #000;color: #eee;}.navbar li#last { padding-right: 10px; border-right: 1px solid #050505; background-image: none;}.nav_splash {width: 80%;float:right; z-index: 0;}.search_form {position:fixed;top:25px;right:5px; z-index:2;}.action_tray {padding:5px;position: fixed;top: 57px;width: 210px;}.action_tray_header { text-align: center; background-color: #DDD;border: 2px groove #FFCF01; margin-bottom: 10px; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.action_tray_header:hover { background-color: #eee;}.action_container {padding:10px 5px; text-align: center;}.action { background-color: #FFF;border: 1px outset #B20838;padding: 5px 0px; font-weight:bolder; margin-bottom: 2px; -moz-border-radius: 7px; -webkit-border-radius: 7px; -khtml-border-radius: 7px; border-radius: 7px; text-transform:uppercase;color: #B20838; }.action:hover {border: 1px inset #000; background-color: #FFCF01;color: #000;}.content_container { background-color:#fff;border: 0px solid #000; border-left: 1px solid #000;color: #000;overflow:auto;padding: 10px;position:fixed;left: 224px;top: 52px;right: 0px;bottom:0px; text-align: left; padding-right:25px; z-index:1;}.SelectButtons { background-color:white; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 10px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.viewButtons { background-color:#F3F781; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 0px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.db_selector {margin:10px 0px 10px 0px;}.db_selector_title { background-color: #00FFFF;border: 1px solid #000; margin-bottom:5px; font-weight:bold;padding:5px 3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select { background-color: #FFEFC0; font-weight:bolder;padding:3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select:hover { background-color: #AFEFF0; }</style>
+<script type="text/javascript" language="JavaScript">function ChangeSilRegLink(id) { var ver=document.getElementById(id).value; if (ver == "Silicon3.0") { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_3_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_3_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_3_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_3_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_3_0"; window.location = '#ps7_mio_init_data_3_0'; } else if (ver == "Silicon2.0") { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_2_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_2_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_2_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_2_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_2_0"; window.location = '#ps7_mio_init_data_2_0'; } else { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_1_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_1_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_1_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_1_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_1_0"; window.location = '#ps7_mio_init_data_1_0'; }}</script>
+<body>
+<DIV class="navbar">
+<DIV class="navlink_container">
+<A id="Summary" href="#">
+<li>
+<DIV class="navlink">Zynq PS Register Summary Viewer
+</DIV>
+</li>
+</A>
+</DIV>
+</DIV>
+<DIV class="action_tray">
+<A id="Report" href="#">
+<DIV class="sitename">Zynq PS7 Summary Report
+</DIV>
+</A>
+<DIV class="viewButtons">User Configurations
+</DIV>
+<DIV class="viewButtons">
+<A id="MIO_Configurations" href="#ZynqPerTab">
+<DIV class="viewButtonHalf">MIO Configurations
+</DIV>
+</A>
+<HR class="action_separator">
+<A id="CLK_Configurations" href="#ClockInfoTab">
+<DIV class="viewButtonHalf">CLK Configurations
+</DIV>
+</A>
+<HR class="action_separator">
+<A id="DDR_Configurations" href="#DDRInfoTab">
+<DIV class="viewButtonHalf">DDR Configurations
+</DIV>
+</A>
+<HR class="action_separator">
+<A id="SMC_Configurations" href="#SMCInfoTab">
+<DIV class="viewButtonHalf">SMC Configurations
+</DIV>
+</A>
+</DIV>
+<DIV class="db_selector">
+<DIV class="db_selector_title">Select Version:
+<select id="db_selection" class="db_selection" onChange="ChangeSilRegLink(this.id)" width="210" style="width: 210px">
+<option value="Silicon3.0">Silicon 3.0</option>
+<option value="Silicon2.0">Silicon 2.0</option>
+<option value="Silicon1.0">Silicon 1.0</option>
+</select>
+</DIV>
+</DIV>
+<DIV class="viewButtons">Zynq Register View
+</DIV>
+<DIV class="action_container">
+<A id="MIO_Registers" href="#ps7_mio_init_data_3_0">
+<DIV class="action">MIO Registers
+</DIV>
+</A>
+<A id="PLL_Registers" href="#ps7_pll_init_data_3_0">
+<DIV class="action">PLL Registers
+</DIV>
+</A>
+<A id="Clock_Registers" href="#ps7_clock_init_data_3_0">
+<DIV class="action">Clock Registers
+</DIV>
+</A>
+<A id="DDR_Registers" href="#ps7_ddr_init_data_3_0">
+<DIV class="action">DDR Registers
+</DIV>
+</A>
+<A id="Peri_Registers" href="#ps7_peripherals_init_data_3_0">
+<DIV class="action">Peripherals Registers
+</DIV>
+</A>
+</DIV>
+<DIV class="content_container">This design is targeted for xc7z020 board (part number: xc7z020clg400-1)
+
+<br>
+<H1>Zynq Design Summary</H1>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Device</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+xc7z020
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>SpeedGrade</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+-1
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Part</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+xc7z020clg400-1
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Description</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+Zynq PS Configuration Report with register details
+</TD>
+</TR>
+<TR valign="top">
+<TD width=20% BGCOLOR=#C0C0FF>
+<B>Vendor</B>
+</TD>
+<TD width=80% BGCOLOR=#E6E6E6>
+Xilinx
+</TD>
+</TR>
+</TABLE>
+<H2><a name="ZynqPerTab">MIO Table View</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>MIO Pin</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Peripheral</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Signal</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>IO Type</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Speed</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Pullup</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0FF>
+<B>Direction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_ss_b
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_io[3]/HOLD_B
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi0_sclk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[7]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Quad SPI Flash
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+qspi_fbclk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[9]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[10]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[11]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[12]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[13]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[14]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[15]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 3.3V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tx_clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+txd[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tx_ctl
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rx_clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rxd[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+rx_ctl
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[4]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+dir
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+stp
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+nxt
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 33</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 34</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 35</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 36</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 37</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[5]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[6]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 39</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[7]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+fast
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+clk
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 41</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+cmd
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 42</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[0]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 43</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[1]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[2]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 45</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+data[3]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 46</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+USB Reset
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+reset
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 47</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+SD 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+cd
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+in
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[48]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 49</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[49]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[50]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 51</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+GPIO
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+gpio[51]
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 52</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+mdc
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+out
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>MIO 53</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enet 0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+mdio
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+LVCMOS 1.8V
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+slow
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+enabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+inout
+</TD>
+</TR>
+</TABLE>
+<H2><a name="DDRInfoTab">DDR Memory information</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Parameter name</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Value</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Enable DDR</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Enable DDR Controller of Zynq PS
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Memory Part</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+MT41K256M16 RE-125
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DRAM bus width</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+32 Bit
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ECC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Disabled
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+ECC is supported only for data width of 16-bit
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>BURST Length (lppdr only)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+8
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Internal Vref</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Operating Frequency (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+533.333333
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>HIGH temperature</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Normal (0-85)
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the operating temparature
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DRAM IC bus width</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+16 Bits
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the width of the DRAM chip
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DRAM Device Capacity</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+4096 MBits
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Speed Bin</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+DDR3_1066F
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Speed Bin
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>BANK Address Count</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+3
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ROW Address Count</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+15
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Row address for ACTIVE commands
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>COLUMN Address Count</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Row address for READ/WRITE commands
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>CAS Latency</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+7
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>CAS Write Latency</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+6
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Select the CAS Write Latency
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RAS to CAS Delay</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+7
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RECHARGE Time</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+7
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>tRC (ns )</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+48.75
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Row cycle time tRC (ns)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>tRASmin ( ns )</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+35.0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>tFAW</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+40.0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+It restricts the number of activates that can be done within a certain window of time
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ADDITIVE Latency</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Write levelling</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Read gate</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Read gate</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+1
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [0] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+-0.050
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [1] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+-0.044
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [2] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+-0.035
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>DQS to Clock delay [3] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+-0.100
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The daly difference of each DQS path delay subtracted from the clock path delay
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [0] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.221
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [1] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.222
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [2] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.217
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>Board delay [3] (ns)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+0.244
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+</TD>
+</TR>
+</TABLE>
+<H2><a name="ClockInfoTab">PS Clocks information</a></H2>
+<H2><a name="ClockInfoTab">PS Reference Clock : 33.333333</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Peripheral</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>PLL source</B>
+</TD>
+<TD width=10% BGCOLOR=#E0F8F7>
+<B>Frequency (MHz)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>CPU 6x Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+ARM PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+666.666687
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>QSPI Flash Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+200.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ENET0 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+125.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>SDIO Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+50.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>UART Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+100.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>UART Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+100.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA0 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+100.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA1 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA2 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10.000000
+</TD>
+</TR>
+<TR valign="top">
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>FPGA3 Freq (MHz)</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+IO PLL
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+10.000000
+</TD>
+</TR>
+</TABLE>
+<H2><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CFG">
+ARM_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_CLK_CTRL">
+ARM_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CFG">
+DDR_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_CLK_CTRL">
+DDR_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CFG">
+IO_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PLL SLCR REGISTERS</H1>
+<H1>ARM PLL INIT</H1>
+<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fa</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fa000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CFG@0XF8000110</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fa220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the CPU clock source.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_6OR4XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_6x4x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_3OR2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_3x2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_1x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_PERI_CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_CLK_CTRL@0XF8000120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1f003f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1f000200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR PLL INIT</H1>
+<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CFG@0XF8000114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12c220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_3x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_3x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_2x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_CLK_CTRL@0XF8000124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff00003</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c200003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>IO PLL INIT</H1>
+<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>145</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>145000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CFG@0XF8000118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1452c0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DCI_CLK_CTRL">
+DCI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_RCLK_CTRL">
+GEM0_RCLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Rx Clock and Rx Signals Select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_CLK_CTRL">
+GEM0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LQSPI_CLK_CTRL">
+LQSPI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SDIO_CLK_CTRL">
+SDIO_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#UART_CLK_CTRL">
+UART_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PCAP_CLK_CTRL">
+PCAP_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA0_CLK_CTRL">
+FPGA0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CLK_621_TRUE">
+CLK_621_TRUE
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#APER_CLK_CTRL">
+APER_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CLOCK CONTROL SLCR REGISTERS</H1>
+<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control - 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DCI_CLK_CTRL@0XF8000128</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>700f01</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DCI clock control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_RCLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controler 0 Rx Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_RCLK_CTRL@0XF8000138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>11</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Rx Clock and Rx Signals Select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controller 0 Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>First divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Second divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_CLK_CTRL@0XF8000140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f71</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>100801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Controller Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for Quad SPI Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LQSPI_CLK_CTRL@0XF800014C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 0 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 1 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SDIO_CLK_CTRL@0XF8000150</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1401</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 Reference clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for UART Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>UART_CLK_CTRL@0XF8000154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>a03</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>TRACE CLOCK</H1>
+<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCAP_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PCAP_CLK_CTRL@0XF8000168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA0_CLK_CTRL@0XF8000170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200500</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CLK_621_TRUE@0XF80001C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>APER_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DMA_CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DMA controller AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 0 AMBA Clock 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GPIO_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GPIO AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SMC_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SMC AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>APER_CLK_CTRL@0XF800012C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffcccd</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc044d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>THIS SHOULD BE BLANK</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Two_rank_cfg">
+Two_rank_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#HPR_reg">
+HPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LPR_reg">
+LPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#WR_reg">
+WR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>WR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg0">
+DRAM_param_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg1">
+DRAM_param_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg2">
+DRAM_param_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg3">
+DRAM_param_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg4">
+DRAM_param_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_init_param">
+DRAM_init_param
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_reg">
+DRAM_EMR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_MR_reg">
+DRAM_EMR_MR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_burst8_rdwr">
+DRAM_burst8_rdwr
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_disable_DQ">
+DRAM_disable_DQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_bank">
+DRAM_addr_map_bank
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_col">
+DRAM_addr_map_col
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_row">
+DRAM_addr_map_row
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_ODT_reg">
+DRAM_ODT_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_cmd_timeout_rddata_cpt">
+phy_cmd_timeout_rddata_cpt
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DLL_calib">
+DLL_calib
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DLL calibration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ODT_delay_hold">
+ODT_delay_hold
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg1">
+ctrl_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg2">
+ctrl_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg3">
+ctrl_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg4">
+ctrl_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg5">
+ctrl_reg5
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg6">
+ctrl_reg6
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ">
+CHE_T_ZQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ_Short_Interval_Reg">
+CHE_T_ZQ_Short_Interval_Reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#deep_pwrdwn_reg">
+deep_pwrdwn_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2c">
+reg_2c
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2d">
+reg_2d
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc Debug</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#dfi_timing">
+dfi_timing
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DFI timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_CONTROL_REG_OFFSET">
+CHE_ECC_CONTROL_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
+CHE_CORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error correction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_STATS_REG_OFFSET">
+CHE_ECC_STATS_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error count</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ECC_scrub">
+ECC_scrub
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rcvr_enable">
+phy_rcvr_enable
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_64">
+reg_64
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_65">
+reg_65
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#page_mask">
+page_mask
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Page mask</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl0">
+lpddr_ctrl0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl1">
+lpddr_ctrl1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl2">
+lpddr_ctrl2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl3">
+lpddr_ctrl3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>DDR INITIALIZATION</H1>
+<H1>LOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Two_rank_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_nom_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_reg_ddrc_active_ranks</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Two_rank_cfg@0XF8006004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1082</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>HPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>HPR_reg@0XF8006008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c0780f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LPR_reg@0XF800600C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2001001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>WR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>WR_reg@0XF8006010</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>14001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>WR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2840</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_selfref_gap_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fc000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg0@0XF8006014</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4285b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_faw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>240000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cke</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg1@0XF8006018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>44e458d3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_write_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_xp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tXP: Minimum time after power down exit to any operation. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rcd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg2@0XF800601C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7282bce5</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ccd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mobile</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 device. 1: LPDDR2 device.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_dfi_dram_clk_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_read_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_mode_ddr1_ddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: disable the pad power down feature 0: Enable the pad power down feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg3@0XF8006020</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fdffffc</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>270872d0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_2t_timing_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: DDRC will use 2T timing 0: DDRC will use 1T timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_prefer_write</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: Bank selector prefers writes over reads</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_addr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fffe00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_mr_wr_busy</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates whether the Mode register operation is read or write 0: write 1: read</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_rdata_valid</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg4@0XF8006024</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffc3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_init_param</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_final_wait_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_ocd_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_init_param@0XF8006028</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2007</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_reg@0XF800602C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_MR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_MR_reg@0XF8006030</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40b30</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_burst8_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16d0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burstchop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_burst8_rdwr@0XF8006034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>13ff3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>116d4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_disable_DQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_force_low_pri_n</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_disable_DQ@0XF8006038</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_bank@0XF800603C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>777</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_col</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b9</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_col@0XF8006040</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fff00000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_row</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b2_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_row@0XF8006044</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f666666</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_ODT_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_idle_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_reg_ddrc_rank0_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_reg_ddrc_rank0_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_ODT_reg@0XF8006048</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c008</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_cmd_timeout_rddata_cpt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_we_to_re_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_fixed_re</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_phy_ctrl_rstn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_clk_stall_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: stall clock, for DLL aging control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff0f8fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77010800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DLL_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dll_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DLL_calib@0XF8006058</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DLL calibration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ODT_delay_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ODT_delay_hold@0XF800605C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pageclose</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_num_entries</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_auto_pre_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_update_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_wc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable Write Combine: 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_collision_page_opt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_selfref_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg1@0XF8006060</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>17ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_go2critical_hysteresis</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_go2critical_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg2@0XF8006064</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wrlvl_ww</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdlvl_rr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_wlmrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>280000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg3@0XF8006068</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>284141</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg4@0XF800606C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1610</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg5">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg5</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksrx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckesr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg5@0XF8006078</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>466111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 5</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg6">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg6</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckcsx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg6@0XF800607C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>32222</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 6</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_zq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ddr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mod</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register set command update delay (minimum d'128)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_long_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_short_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ@0XF80060A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10200802</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ_Short_Interval_Reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>t_zq_short_interval_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dram_rstn_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>69</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6900000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>690cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deep_pwrdwn_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_to_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>deep_pwrdwn_reg@0XF80060AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_wrlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_rdlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_twrlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_trdlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_wr_level_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_data_eye_train</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2c@0XF80060B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1cffffff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_skip_ocd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2d@0XF80060B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc Debug</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_timing</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_rddata_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>dfi_timing@0XF80060B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200066</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DFI timing</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_CONTROL_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Uncorrectable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Correctable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error clear</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_CORRECTED_BIT_NUM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error correction</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNCORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_STATS_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_CORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_UNCORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error count</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ecc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ECC_scrub@0XF80060F4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rcvr_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_on</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_off</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rcvr_enable@0XF8006114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF800611C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffcf</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF800612C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006130</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006134</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>26c00</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006144</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006148</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF800614C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006158</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF800615C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006160</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF800616C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006174</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF800617C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006180</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006184</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bc</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006188</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_64</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved for future Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_at_spd_atpg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_force_err</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_invert_clkout</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_sel_logic</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_lpddr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3. 1: LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_cmd_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set to 1, command comes to phy_ctrl through a flop.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_64@0XF8006190</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>6ffffefe</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40080</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_65</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dll_lock_diff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_wr_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_data_eye_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_calib_rst</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_65@0XF8006194</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc82</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>page_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_page_addr_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>page_mask@0XF8006204</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Page mask</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006208</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF800620C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006210</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006214</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>703ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006218</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF800621C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006220</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006224</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_derate_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl0@0XF80062A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff5</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_read_interval</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Interval between two MR4 reads, USED to derate the timing parameters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl1@0XF80062AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_min_stable_clock_x1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_idle_after_reset_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>120</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Idle time after the reset command, tINIT4. Units: 32 clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl2@0XF80062B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5125</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_auto_init_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dev_zqinit_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl3@0XF80062B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12a8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>POLL ON DCI STATUS</H1>
+<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B74</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DONE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI done signal</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UNLOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK DDR STATUS</H1>
+<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_sts_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006054</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_operating_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_sts_reg@0XF8006054</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR0">
+DDRIOB_ADDR0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for A[14:0], CKE and DRST_B</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR1">
+DDRIOB_ADDR1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_CLOCK">
+DDRIOB_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_ADDR">
+DDRIOB_DRIVE_SLEW_ADDR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for Address and Command pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DATA">
+DDRIOB_DRIVE_SLEW_DATA
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for DQ pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DIFF">
+DDRIOB_DRIVE_SLEW_DIFF
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for DQS pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
+DDRIOB_DRIVE_SLEW_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive and Slew controls for Clock pins of the DDR Interface</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DDR_CTRL">
+DDRIOB_DDR_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_00">
+MIO_PIN_00
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_01">
+MIO_PIN_01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_02">
+MIO_PIN_02
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_03">
+MIO_PIN_03
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_04">
+MIO_PIN_04
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_05">
+MIO_PIN_05
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_06">
+MIO_PIN_06
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_07">
+MIO_PIN_07
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_08">
+MIO_PIN_08
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_09">
+MIO_PIN_09
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_10">
+MIO_PIN_10
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_11">
+MIO_PIN_11
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_12">
+MIO_PIN_12
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_13">
+MIO_PIN_13
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_14">
+MIO_PIN_14
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_15">
+MIO_PIN_15
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_16">
+MIO_PIN_16
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_17">
+MIO_PIN_17
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_18">
+MIO_PIN_18
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_19">
+MIO_PIN_19
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_20">
+MIO_PIN_20
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_21">
+MIO_PIN_21
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_22">
+MIO_PIN_22
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_23">
+MIO_PIN_23
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_24">
+MIO_PIN_24
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_25">
+MIO_PIN_25
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_26">
+MIO_PIN_26
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_27">
+MIO_PIN_27
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_28">
+MIO_PIN_28
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_29">
+MIO_PIN_29
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_30">
+MIO_PIN_30
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_31">
+MIO_PIN_31
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_32">
+MIO_PIN_32
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_33">
+MIO_PIN_33
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_34">
+MIO_PIN_34
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_35">
+MIO_PIN_35
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_36">
+MIO_PIN_36
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_37">
+MIO_PIN_37
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_38">
+MIO_PIN_38
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_39">
+MIO_PIN_39
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_40">
+MIO_PIN_40
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_41">
+MIO_PIN_41
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_42">
+MIO_PIN_42
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_43">
+MIO_PIN_43
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_44">
+MIO_PIN_44
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_45">
+MIO_PIN_45
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_46">
+MIO_PIN_46
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_47">
+MIO_PIN_47
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_48">
+MIO_PIN_48
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_49">
+MIO_PIN_49
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_50">
+MIO_PIN_50
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_51">
+MIO_PIN_51
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_52">
+MIO_PIN_52
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_53">
+MIO_PIN_53
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SD0_WP_CD_SEL">
+SD0_WP_CD_SEL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>OCM REMAPPING</H1>
+<H1>DDRIOB SETTINGS</H1>
+<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR0@0XF8000B40</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for A[14:0], CKE and DRST_B</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR1@0XF8000B44</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE_B</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enable: 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_CLOCK@0XF8000B58</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_ADDR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>18c068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for Address and Command pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DATA</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for DQ pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DIFF</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for DQS pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Drive and Slew controls for Clock pins of the DDR Interface</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DDR_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_INT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF internal generator</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_EXT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VREF_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_REFIO_TEST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_REFIO_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_DRST_B_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_CKE_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>260</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialize flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialize flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialize flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRP_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRN_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRP_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Calibration. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UPDATE_CONTROL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Mode. Use the values in the Calibration Table.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INIT_COMPLETE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_CLK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_HLN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_HLP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_TST_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_INT_DCI_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7feffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>823</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB DCI Config</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MIO PROGRAMMING</H1>
+<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_00</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables Pullup on IO Buffer pin 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_00@0XF8000700</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_01@0XF8000704</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_02</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_02@0XF8000708</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_03</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_03@0XF800070C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_04</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_04@0XF8000710</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_05</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_05@0XF8000714</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_06</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_06@0XF8000718</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_07</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_07@0XF800071C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_08</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_08@0XF8000720</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_09</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_09@0XF8000724</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_10@0XF8000728</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_11@0XF800072C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_12@0XF8000730</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_13@0XF8000734</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_14@0XF8000738</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_15@0XF800073C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_16@0XF8000740</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_17</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_17@0XF8000744</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_18</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_18@0XF8000748</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_19</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_19@0XF800074C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_20@0XF8000750</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_21</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_21@0XF8000754</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_22</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_22@0XF8000758</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_23</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_23@0XF800075C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_24@0XF8000760</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_25</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_25@0XF8000764</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_26</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_26@0XF8000768</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_27</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_27@0XF800076C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_28@0XF8000770</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_29</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_29@0XF8000774</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_30@0XF8000778</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_31</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_31@0XF800077C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_32@0XF8000780</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_33</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_33@0XF8000784</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_34</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_34@0XF8000788</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_35@0XF800078C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_36</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_36@0XF8000790</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_37@0XF8000794</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_38</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_38@0XF8000798</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_39</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_39@0XF800079C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_40@0XF80007A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_41@0XF80007A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_42</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_42@0XF80007A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_43</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_43@0XF80007AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_44</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_44@0XF80007B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_45</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_45@0XF80007B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_46</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_46@0XF80007B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_47</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_47@0XF80007BC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_48</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_48@0XF80007C0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_49</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_49@0XF80007C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_50</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_50@0XF80007C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_51</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_51@0XF80007CC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_52</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_52@0XF80007D0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_53</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULLUP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_53@0XF80007D4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SD0_WP_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_WP_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>37</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2f0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SD0_WP_CD_SEL@0XF8000830</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f003f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2f0037</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Divider Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Generator Register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Divider Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Generator Register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Config_reg">
+Config_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CTRL">
+CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DIRM_1">
+DIRM_1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A244</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Direction mode (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#OEN_1">
+OEN_1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A248</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Output enable (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SRAM/NOR SET OPMODE</H1>
+<H1>UART REGISTERS</H1>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0001034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud Rate Divider Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0001018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud Rate Generator Register.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0001000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0001004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0000034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud Rate Divider Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0000018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud Rate Generator Register.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0000000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>QSPI REGISTERS</H1>
+<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Config_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Holdb_dr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Config_reg@0XE000D000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PL POWER ON RESET REGISTERS</H1>
+<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCFG_POR_CNT_4K</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CTRL@0XF8007000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
+<H1>NAND SET CYCLE</H1>
+<H1>OPMODE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>SRAM/NOR CS0 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS0 BASE ADDRESS</H1>
+<H1>SRAM/NOR CS1 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS1 BASE ADDRESS</H1>
+<H1>USB RESET</H1>
+<H1>USB0 RESET</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>DIR MODE BANK 1</H1>
+<H2><a name="DIRM_1">Register (<A href=#mod___slcr> slcr </A>)DIRM_1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIRM_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A244</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIRECTION_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as DIRM_0[DIRECTION_0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DIRM_1@0XE000A244</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Direction mode (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+<H1>OUTPUT ENABLE BANK 1</H1>
+<H2><a name="OEN_1">Register (<A href=#mod___slcr> slcr </A>)OEN_1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OEN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A248</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OP_ENABLE_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as OEN_0[OP_ENABLE_0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>OEN_1@0XE000A248</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Output enable (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
+<H1>ADD 1 MS DELAY</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
+<H1>ENET RESET</H1>
+<H1>I2C RESET</H1>
+<H1>NOR CHIP SELECT</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LVL_SHFTR_EN">
+LVL_SHFTR_EN
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA_RST_CTRL">
+FPGA_RST_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING LEVEL SHIFTER</H1>
+<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LVL_SHFTR_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_INP_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PL to PS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_OUT_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PS to PL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_INP_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PL to PS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_LVL_OUT_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level shifter enable to drive signals from PS to PL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LVL_SHFTR_EN@0XF8000900</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>FPGA RESETS TO 0</H1>
+<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_RST_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_ACP_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_AXDS0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FSSW1_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FSSW0_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_FMSW1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_FMSW0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_FPGA_DMA0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Do not modify.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA3_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA2_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA1_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA_RST_CTRL@0XF8000240</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>AFI REGISTERS</H1>
+<H1>AFI0 REGISTERS</H1>
+<H1>AFI1 REGISTERS</H1>
+<H1>AFI2 REGISTERS</H1>
+<H1>AFI3 REGISTERS</H1>
+<H1>AFI2 SECURE REGISTER</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_3_0">ps7_debug_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_3_0">ps7_debug_3_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>CROSS TRIGGER CONFIGURATIONS</H1>
+<H1>UNLOCKING CTI REGISTERS</H1>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8898FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8899FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8809FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING CTI MODULES AND CHANNELS</H1>
+<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
+</TABLE>
+<P>
+</body>
+</head>
+</body>
+</html>
+<H2><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CFG">
+ARM_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_CLK_CTRL">
+ARM_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CFG">
+DDR_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_CLK_CTRL">
+DDR_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CFG">
+IO_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PLL SLCR REGISTERS</H1>
+<H1>ARM PLL INIT</H1>
+<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fa</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fa000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CFG@0XF8000110</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fa220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the CPU clock source.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_6OR4XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_6x4x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_3OR2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_3x2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU_1x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_PERI_CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_CLK_CTRL@0XF8000120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1f003f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1f000200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR PLL INIT</H1>
+<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CFG@0XF8000114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12c220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_3x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR_2x Clock control: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_3x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Frequency divisor for the ddr_2x clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_CLK_CTRL@0XF8000124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff00003</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c200003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>IO PLL INIT</H1>
+<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>145</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>145000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CFG@0XF8000118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1452c0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL lock status: 0: not locked, 1: locked</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DCI_CLK_CTRL">
+DCI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_RCLK_CTRL">
+GEM0_RCLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Rx Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_CLK_CTRL">
+GEM0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LQSPI_CLK_CTRL">
+LQSPI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SDIO_CLK_CTRL">
+SDIO_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#UART_CLK_CTRL">
+UART_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PCAP_CLK_CTRL">
+PCAP_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA0_CLK_CTRL">
+FPGA0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CLK_621_TRUE">
+CLK_621_TRUE
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#APER_CLK_CTRL">
+APER_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CLOCK CONTROL SLCR REGISTERS</H1>
+<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control - 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DCI_CLK_CTRL@0XF8000128</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>700f01</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DCI clock control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_RCLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controler 0 Rx Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_RCLK_CTRL@0XF8000138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>11</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Rx Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ethernet Controller 0 Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>First divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Second divisor for Ethernet controller 0 source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_CLK_CTRL@0XF8000140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f71</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>100801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>GigE 0 Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI Controller Reference Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for Quad SPI Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LQSPI_CLK_CTRL@0XF800014C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Quad SPI Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 0 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Controller 1 Clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SDIO_CLK_CTRL@0XF8000150</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1401</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 Reference clock control. 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor for UART Controller source clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>UART_CLK_CTRL@0XF8000154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>a03</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>TRACE CLOCK</H1>
+<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCAP_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PCAP_CLK_CTRL@0XF8000168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PCAP Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA0_CLK_CTRL@0XF8000170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200500</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PL Clock 0 Output control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the CPU clock ration: 0: 4:2:1 1: 6:2:1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CLK_621_TRUE@0XF80001C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CPU Clock Ratio Mode select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>APER_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DMA_CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DMA controller AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 0 AMBA Clock 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO controller 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GPIO_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GPIO AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Quad SPI AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SMC_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SMC AMBA Clock control 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>APER_CLK_CTRL@0XF800012C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffcccd</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc044d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>THIS SHOULD BE BLANK</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Two_rank_cfg">
+Two_rank_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#HPR_reg">
+HPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LPR_reg">
+LPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#WR_reg">
+WR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>WR Queue control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg0">
+DRAM_param_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg1">
+DRAM_param_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg2">
+DRAM_param_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg3">
+DRAM_param_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg4">
+DRAM_param_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_init_param">
+DRAM_init_param
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_reg">
+DRAM_EMR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_MR_reg">
+DRAM_EMR_MR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_burst8_rdwr">
+DRAM_burst8_rdwr
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_disable_DQ">
+DRAM_disable_DQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_bank">
+DRAM_addr_map_bank
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_col">
+DRAM_addr_map_col
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_row">
+DRAM_addr_map_row
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_ODT_reg">
+DRAM_ODT_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_cmd_timeout_rddata_cpt">
+phy_cmd_timeout_rddata_cpt
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DLL_calib">
+DLL_calib
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DLL calibration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ODT_delay_hold">
+ODT_delay_hold
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg1">
+ctrl_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg2">
+ctrl_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg3">
+ctrl_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg4">
+ctrl_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg5">
+ctrl_reg5
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg6">
+ctrl_reg6
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_REFRESH_TIMER01">
+CHE_REFRESH_TIMER01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ">
+CHE_T_ZQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ_Short_Interval_Reg">
+CHE_T_ZQ_Short_Interval_Reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc parameters</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#deep_pwrdwn_reg">
+deep_pwrdwn_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2c">
+reg_2c
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2d">
+reg_2d
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc Debug</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#dfi_timing">
+dfi_timing
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DFI timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_CONTROL_REG_OFFSET">
+CHE_ECC_CONTROL_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
+CHE_CORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error correction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_STATS_REG_OFFSET">
+CHE_ECC_STATS_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error count</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ECC_scrub">
+ECC_scrub
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rcvr_enable">
+phy_rcvr_enable
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config0">
+PHY_Config0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config1">
+PHY_Config1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config2">
+PHY_Config2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config3">
+PHY_Config3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio0">
+phy_init_ratio0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio1">
+phy_init_ratio1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio2">
+phy_init_ratio2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio3">
+phy_init_ratio3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg0">
+phy_rd_dqs_cfg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg1">
+phy_rd_dqs_cfg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg2">
+phy_rd_dqs_cfg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg3">
+phy_rd_dqs_cfg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg0">
+phy_wr_dqs_cfg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg1">
+phy_wr_dqs_cfg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg2">
+phy_wr_dqs_cfg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg3">
+phy_wr_dqs_cfg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg0">
+phy_we_cfg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg1">
+phy_we_cfg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg2">
+phy_we_cfg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg3">
+phy_we_cfg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY FIFO write enable configuration for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv0">
+wr_data_slv0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv1">
+wr_data_slv1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv2">
+wr_data_slv2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv3">
+wr_data_slv3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio config for data slice 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_64">
+reg_64
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_65">
+reg_65
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#page_mask">
+page_mask
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Page mask</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port0">
+axi_priority_wr_port0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port1">
+axi_priority_wr_port1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port2">
+axi_priority_wr_port2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port3">
+axi_priority_wr_port3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port0">
+axi_priority_rd_port0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port1">
+axi_priority_rd_port1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port2">
+axi_priority_rd_port2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port3">
+axi_priority_rd_port3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl0">
+lpddr_ctrl0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl1">
+lpddr_ctrl1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl2">
+lpddr_ctrl2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl3">
+lpddr_ctrl3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>DDR INITIALIZATION</H1>
+<H1>LOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Two_rank_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_nom_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_active_ranks</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_block</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_diff_rank_rd_2cycle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_open_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_4bank_ram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Two_rank_cfg@0XF8006004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81082</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Two Rank Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>HPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>HPR_reg@0XF8006008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c0780f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>HPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LPR_reg@0XF800600C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2001001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>WR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>WR_reg@0XF8006010</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>14001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>WR Queue control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2840</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_selfref_gap_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fc000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg0@0XF8006014</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4285b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_faw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>240000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cke</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg1@0XF8006018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>44e458d3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_write_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_xp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tXP: Minimum time after power down exit to any operation. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rcd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg2@0XF800601C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7282bce5</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ccd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_sdram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: sdram device 0: non-sdram device</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mobile</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 device. 1: LPDDR2 device.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_clock_stop_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_read_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_mode_ddr1_ddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: disable the pad power down feature 0: Enable the pad power down feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg3@0XF8006020</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffffc</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>272872d0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_2t_timing_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: DDRC will use 2T timing 0: DDRC will use 1T timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_prefer_write</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: Bank selector prefers writes over reads</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_rank_rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_addr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fffe00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_mr_wr_busy</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates whether the Mode register operation is read or write 0: write 1: read</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_rdata_valid</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg4@0XF8006024</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_init_param</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_final_wait_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_ocd_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_init_param@0XF8006028</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2007</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Initialization Parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_reg@0XF800602C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR2, EMR3 access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_MR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_MR_reg@0XF8006030</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40b30</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR, MR access</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_burst8_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16d0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burstchop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_burst8_rdwr@0XF8006034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>13ff3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>116d4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Burst 8 read/write</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_disable_DQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_force_low_pri_n</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_debug_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq0_wait_t</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_disable_DQ@0XF8006038</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fc3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Disable DQ</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_bank@0XF800603C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>777</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Row/Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_col</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b9</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_col@0XF8006040</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fff00000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_row</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b2_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_row@0XF8006044</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f666666</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Select DRAM row address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_ODT_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_idle_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_ODT_reg@0XF8006048</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c248</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM ODT control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_cmd_timeout_rddata_cpt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_we_to_re_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_fixed_re</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_phy_ctrl_rstn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_clk_stall_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: stall clock, for DLL aging control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff0f8fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77010800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY command time out and read data capture FIFO</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DLL_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dll_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DLL_calib@0XF8006058</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>101</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DLL calibration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ODT_delay_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ODT_delay_hold@0XF800605C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ODT delay and ODT hold</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pageclose</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_num_entries</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_auto_pre_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_update_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_wc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable Write Combine: 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_collision_page_opt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_selfref_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg1@0XF8006060</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>17ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_go2critical_hysteresis</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_go2critical_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg2@0XF8006064</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wrlvl_ww</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdlvl_rr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_wlmrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>280000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg3@0XF8006068</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>284141</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg4@0XF800606C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1610</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg5">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg5</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006078</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_dram_clk_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cksrx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckesr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg5@0XF8006078</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>466111</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 5</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg6">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg6</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800607C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpde</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckdpdx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ckcsx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg6@0XF800607C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>32222</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 6</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_REFRESH_TIMER01">Register (<A href=#mod___slcr> slcr </A>)CHE_REFRESH_TIMER01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer0_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer1_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01@0XF80060A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_zq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ddr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mod</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_long_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_short_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ@0XF80060A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10200802</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ZQ parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ_Short_Interval_Reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>t_zq_short_interval_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dram_rstn_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>69</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6900000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>690cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc parameters</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deep_pwrdwn_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_to_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>deep_pwrdwn_reg@0XF80060AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Deep powerdown (LPDDR2)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_wrlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_rdlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_twrlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_trdlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_wr_level_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_data_eye_train</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2c@0XF80060B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1cffffff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_2t_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_skip_ocd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pre_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2d@0XF80060B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc Debug</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_timing</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_rddata_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>dfi_timing@0XF80060B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200066</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DFI timing</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_CONTROL_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Uncorrectable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Correctable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error clear</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_CORRECTED_BIT_NUM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error correction</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNCORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC unrecoverable error status</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_STATS_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_CORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_UNCORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error count</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ecc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ECC_scrub@0XF80060F4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC mode/scrub</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rcvr_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_on</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_off</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rcvr_enable@0XF8006114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config0">Register (<A href=#mod___slcr> slcr </A>)PHY_Config0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config0@0XF8006118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config1">Register (<A href=#mod___slcr> slcr </A>)PHY_Config1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config1@0XF800611C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config2">Register (<A href=#mod___slcr> slcr </A>)PHY_Config2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config2@0XF8006120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config3">Register (<A href=#mod___slcr> slcr </A>)PHY_Config3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config3@0XF8006124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio0">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio0@0XF800612C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio1">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio1@0XF8006130</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio2">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio2@0XF8006134</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>26c00</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio3">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio3@0XF8006138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg0@0XF8006140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg1@0XF8006144</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg2@0XF8006148</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg3@0XF800614C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg0@0XF8006154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg1@0XF8006158</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg2@0XF800615C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg3@0XF8006160</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg0@0XF8006168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg1@0XF800616C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg2@0XF8006170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg3@0XF8006174</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY FIFO write enable configuration for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv0">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv0@0XF800617C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv1">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv1@0XF8006180</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv2">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv2@0XF8006184</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bc</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv3">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv3@0XF8006188</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio config for data slice 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_64</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Loopback testing. 1: enable, 0: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved for future Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_at_spd_atpg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_force_err</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_invert_clkout</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_all_dq_mpr_rd_resp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_sel_logic</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rank0_delays</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_lpddr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3. 1: LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_cmd_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set to 1, command comes to phy_ctrl through a flop.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_int_lpbk</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_64@0XF8006190</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10040080</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_65</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dll_lock_diff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_wr_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_data_eye_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_calib_rst</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_65@0XF8006194</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc82</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>page_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_page_addr_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>page_mask@0XF8006204</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Page mask</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port0">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port0@0XF8006208</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port1">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port1@0XF800620C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port2">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port2@0XF8006210</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port3">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port3@0XF8006214</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port0">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port0@0XF8006218</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port1">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port1@0XF800621C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 1.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port2">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port2@0XF8006220</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 2.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port3">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port3@0XF8006224</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 3.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_per_bank_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_derate_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl0@0XF80062A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_read_interval</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Interval between two MR4 reads, USED to derate the timing parameters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl1@0XF80062AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_min_stable_clock_x1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_idle_after_reset_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>120</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Idle time after the reset command, tINIT4. Units: 32 clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl2@0XF80062B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5125</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_auto_init_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dev_zqinit_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl3@0XF80062B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12a8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>POLL ON DCI STATUS</H1>
+<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B74</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DONE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI done signal</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UNLOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK DDR STATUS</H1>
+<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_sts_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006054</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_operating_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_sts_reg@0XF8006054</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR0">
+DDRIOB_ADDR0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Address 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR1">
+DDRIOB_ADDR1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Address 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_CLOCK">
+DDRIOB_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_ADDR">
+DDRIOB_DRIVE_SLEW_ADDR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Address</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DATA">
+DDRIOB_DRIVE_SLEW_DATA
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Data</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DIFF">
+DDRIOB_DRIVE_SLEW_DIFF
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Diff</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
+DDRIOB_DRIVE_SLEW_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Slew for Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DDR_CTRL">
+DDRIOB_DDR_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_00">
+MIO_PIN_00
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_01">
+MIO_PIN_01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_02">
+MIO_PIN_02
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_03">
+MIO_PIN_03
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_04">
+MIO_PIN_04
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_05">
+MIO_PIN_05
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_06">
+MIO_PIN_06
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_07">
+MIO_PIN_07
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_08">
+MIO_PIN_08
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_09">
+MIO_PIN_09
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_10">
+MIO_PIN_10
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_11">
+MIO_PIN_11
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_12">
+MIO_PIN_12
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_13">
+MIO_PIN_13
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_14">
+MIO_PIN_14
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_15">
+MIO_PIN_15
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_16">
+MIO_PIN_16
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_17">
+MIO_PIN_17
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_18">
+MIO_PIN_18
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_19">
+MIO_PIN_19
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_20">
+MIO_PIN_20
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_21">
+MIO_PIN_21
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_22">
+MIO_PIN_22
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_23">
+MIO_PIN_23
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_24">
+MIO_PIN_24
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_25">
+MIO_PIN_25
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_26">
+MIO_PIN_26
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_27">
+MIO_PIN_27
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_28">
+MIO_PIN_28
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_29">
+MIO_PIN_29
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_30">
+MIO_PIN_30
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_31">
+MIO_PIN_31
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_32">
+MIO_PIN_32
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_33">
+MIO_PIN_33
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_34">
+MIO_PIN_34
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_35">
+MIO_PIN_35
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_36">
+MIO_PIN_36
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_37">
+MIO_PIN_37
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_38">
+MIO_PIN_38
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_39">
+MIO_PIN_39
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_40">
+MIO_PIN_40
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_41">
+MIO_PIN_41
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_42">
+MIO_PIN_42
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_43">
+MIO_PIN_43
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_44">
+MIO_PIN_44
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_45">
+MIO_PIN_45
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_46">
+MIO_PIN_46
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_47">
+MIO_PIN_47
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_48">
+MIO_PIN_48
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_49">
+MIO_PIN_49
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_50">
+MIO_PIN_50
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_51">
+MIO_PIN_51
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_52">
+MIO_PIN_52
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_53">
+MIO_PIN_53
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SD0_WP_CD_SEL">
+SD0_WP_CD_SEL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>OCM REMAPPING</H1>
+<H1>DDRIOB SETTINGS</H1>
+<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR0@0XF8000B40</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Address 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR1@0XF8000B44</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Address 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_CLOCK@0XF8000B58</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Clock Output</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_ADDR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>18c068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Address</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DATA</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Data</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DIFF</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Diff</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Slew for Clock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DDR_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_INT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF internal generator</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_EXT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_TEST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRST_B_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0: no pull-up 1: enable pull-up</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CKE_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0: no pull-up 1: enable pull-up</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>260</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Buffer Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 if any iob's use a terminate type, or if dci test block used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UPDATE_CONTROL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INIT_COMPLETE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>test Internal to IO bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_CLK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate DCI clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRN)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRP)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate Reset</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INT_DCI_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Need explanation here</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>823</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MIO PROGRAMMING</H1>
+<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_00</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high. 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up on IO Buffer pin 0: disable 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_00@0XF8000700</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 0 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_01@0XF8000704</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 1 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_02</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_02@0XF8000708</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 2 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_03</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_03@0XF800070C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 3 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_04</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_04@0XF8000710</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 4 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_05</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_05@0XF8000714</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 5 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_06</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_06@0XF8000718</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 6 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_07</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_07@0XF800071C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 7 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_08</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_08@0XF8000720</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 8 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_09</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_09@0XF8000724</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 9 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_10@0XF8000728</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 10 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_11@0XF800072C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 11 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_12@0XF8000730</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 12 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_13@0XF8000734</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 13 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_14@0XF8000738</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 14 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_15@0XF800073C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 15 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_16@0XF8000740</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 16 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_17</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_17@0XF8000744</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 17 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_18</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_18@0XF8000748</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 18 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_19</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_19@0XF800074C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 19 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_20@0XF8000750</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 20 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_21</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_21@0XF8000754</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 21 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_22</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_22@0XF8000758</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 22 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_23</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_23@0XF800075C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 23 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_24@0XF8000760</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 24 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_25</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_25@0XF8000764</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 25 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_26</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_26@0XF8000768</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 26 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_27</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_27@0XF800076C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 27 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_28@0XF8000770</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 28 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_29</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_29@0XF8000774</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 29 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_30@0XF8000778</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 30 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_31</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_31@0XF800077C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 31 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_32@0XF8000780</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 32 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_33</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_33@0XF8000784</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 33 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_34</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_34@0XF8000788</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 34 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_35@0XF800078C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 35 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_36</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_36@0XF8000790</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 36 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_37@0XF8000794</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 37 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_38</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_38@0XF8000798</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 38 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_39</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_39@0XF800079C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 39 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_40@0XF80007A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 40 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_41@0XF80007A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 41 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_42</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_42@0XF80007A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 42 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_43</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_43@0XF80007AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 43 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_44</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_44@0XF80007B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 44 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_45</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_45@0XF80007B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 45 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_46</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_46@0XF80007B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 46 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_47</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_47@0XF80007BC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 47 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_48</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_48@0XF80007C0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 48 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_49</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_49@0XF80007C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 49 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_50</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_50@0XF80007C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 50 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_51</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_51@0XF80007CC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 51 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_52</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_52@0XF80007D0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 52 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_53</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[Speed]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[IO_Type]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_53@0XF80007D4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Pin 53 Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SD0_WP_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_WP_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>37</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2f0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SD0_WP_CD_SEL@0XF8000830</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f003f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2f0037</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO 0 WP CD select</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider register.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Config_reg">
+Config_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CTRL">
+CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DIRM_1">
+DIRM_1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A244</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Direction mode (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#OEN_1">
+OEN_1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A248</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Output enable (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 15:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for Data 31:16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 1:0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR IOB Config for DQS 3:2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SRAM/NOR SET OPMODE</H1>
+<H1>UART REGISTERS</H1>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0001034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0001018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud rate divider register.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break: 0: start break transmission, 1: stop break transmission.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable: 0: enable transmitter, 0: disable transmitter</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0001000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IRMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UCLKEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0001004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0000034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0000018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud rate divider register.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break: 0: start break transmission, 1: stop break transmission.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable: 0: enable transmitter, 0: disable transmitter</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable: 0: disable, 1: enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0000000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IRMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UCLKEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>QSPI REGISTERS</H1>
+<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Config_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Holdb_dr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Config_reg@0XE000D000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PL POWER ON RESET REGISTERS</H1>
+<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCFG_POR_CNT_4K</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CTRL@0XF8007000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
+<H1>NAND SET CYCLE</H1>
+<H1>OPMODE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>SRAM/NOR CS0 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS0 BASE ADDRESS</H1>
+<H1>SRAM/NOR CS1 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS1 BASE ADDRESS</H1>
+<H1>USB RESET</H1>
+<H1>USB0 RESET</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>DIR MODE BANK 1</H1>
+<H2><a name="DIRM_1">Register (<A href=#mod___slcr> slcr </A>)DIRM_1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIRM_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A244</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIRECTION_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as DIRM_0[DIRECTION_0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DIRM_1@0XE000A244</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Direction mode (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+<H1>OUTPUT ENABLE BANK 1</H1>
+<H2><a name="OEN_1">Register (<A href=#mod___slcr> slcr </A>)OEN_1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OEN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A248</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OP_ENABLE_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as OEN_0[OP_ENABLE_0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>OEN_1@0XE000A248</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Output enable (GPIO Bank1, MIO)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
+<H1>ADD 1 MS DELAY</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
+<H1>ENET RESET</H1>
+<H1>I2C RESET</H1>
+<H1>NOR CHIP SELECT</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LVL_SHFTR_EN">
+LVL_SHFTR_EN
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA_RST_CTRL">
+FPGA_RST_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING LEVEL SHIFTER</H1>
+<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LVL_SHFTR_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LVL_SHFTR_EN@0XF8000900</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>FPGA RESETS TO 0</H1>
+<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_RST_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_ACP_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW1_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW0_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA3_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA2_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA1_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA_RST_CTRL@0XF8000240</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>AFI REGISTERS</H1>
+<H1>AFI0 REGISTERS</H1>
+<H1>AFI1 REGISTERS</H1>
+<H1>AFI2 REGISTERS</H1>
+<H1>AFI3 REGISTERS</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_2_0">ps7_debug_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_2_0">ps7_debug_2_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>CROSS TRIGGER CONFIGURATIONS</H1>
+<H1>UNLOCKING CTI REGISTERS</H1>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8898FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8899FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8809FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING CTI MODULES AND CHANNELS</H1>
+<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
+</TABLE>
+<P>
+</body>
+</head>
+</body>
+</html>
+<H2><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CFG">
+ARM_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_PLL_CTRL">
+ARM_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ARM_CLK_CTRL">
+ARM_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CORTEX A9 Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CFG">
+DDR_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_PLL_CTRL">
+DDR_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDR_CLK_CTRL">
+DDR_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CFG">
+IO_PLL_CFG
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#IO_PLL_CTRL">
+IO_PLL_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PLL SLCR REGISTERS</H1>
+<H1>ARM PLL INIT</H1>
+<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000110</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fa</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fa000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CFG@0XF8000110</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fa220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_PLL_CTRL@0XF8000100</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ARM PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ARM_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_6OR4XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_3OR2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CPU_PERI_CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ARM_CLK_CTRL@0XF8000120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1f003f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1f000200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CORTEX A9 Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR PLL INIT</H1>
+<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CFG@0XF8000114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12c220</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000104</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_PLL_CTRL@0XF8000104</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_3XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor value for the ddr_3xclk</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDR_2XCLK_DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDR_CLK_CTRL@0XF8000124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff00003</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c200003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDR Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>IO PLL INIT</H1>
+<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CFG</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_CP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_CNT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>145</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>145000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CFG@0XF8000118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1452c0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UPDATE FB_DIV</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_FDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7f000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1e000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>BY PASS PLL</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK PLL STATUS</H1>
+<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800010C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PLL_STATUS@0XF800010C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>REMOVE PLL BY PASS</H1>
+<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_PLL_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000108</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PLL_BYPASS_FORCE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>IO_PLL_CTRL@0XF8000108</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>IO PLL Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DCI_CLK_CTRL">
+DCI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI clock control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_RCLK_CTRL">
+GEM0_RCLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 0 RX Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#GEM0_CLK_CTRL">
+GEM0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 0 Ref Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LQSPI_CLK_CTRL">
+LQSPI_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Linear Quad-SPI Reference Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SDIO_CLK_CTRL">
+SDIO_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO Reference Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#UART_CLK_CTRL">
+UART_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Reference Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PCAP_CLK_CTRL">
+PCAP_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PCAP 2X Clock Contol</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA0_CLK_CTRL">
+FPGA0_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA 0 Output Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CLK_621_TRUE">
+CLK_621_TRUE
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>6:2:1 ratio clock, if set</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#APER_CLK_CTRL">
+APER_CLK_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CLOCK CONTROL SLCR REGISTERS</H1>
+<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000128</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DCI_CLK_CTRL@0XF8000128</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>700f01</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DCI clock control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_RCLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_RCLK_CTRL@0XF8000138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>11</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Gigabit Ethernet MAC 0 RX Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>GEM0_CLK_CTRL@0XF8000140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f71</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>100801</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Gigabit Ethernet MAC 0 Ref Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800014C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LQSPI_CLK_CTRL@0XF800014C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Linear Quad-SPI Reference Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000150</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SDIO_CLK_CTRL@0XF8000150</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1401</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO Reference Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>UART_CLK_CTRL@0XF8000154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f33</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>a03</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Reference Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>TRACE CLOCK</H1>
+<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCAP_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clock active 0 - Clock is disabled 1 - Clock is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PCAP_CLK_CTRL@0XF8000168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f31</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>501</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PCAP 2X Clock Contol</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SRCSEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>500</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIVISOR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA0_CLK_CTRL@0XF8000170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f03f30</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200500</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA 0 Output Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80001C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLK_621_TRUE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CLK_621_TRUE@0XF80001C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>6:2:1 ratio clock, if set</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>APER_CLK_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800012C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DMA_CPU_2XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USB1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GEM1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SPI1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CAN1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>I2C1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART0_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UART1_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GPIO_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LQSPI_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SMC_CPU_1XCLKACT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>APER_CLK_CTRL@0XF800012C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffcccd</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc044d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AMBA Peripheral Clock Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>THIS SHOULD BE BLANK</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Two_rank_cfg">
+Two_rank_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Two rank configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#HPR_reg">
+HPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>HPR Queue control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LPR_reg">
+LPR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPR Queue control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#WR_reg">
+WR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>WR Queue control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg0">
+DRAM_param_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg1">
+DRAM_param_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg2">
+DRAM_param_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg3">
+DRAM_param_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_param_reg4">
+DRAM_param_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Parameters register 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_init_param">
+DRAM_init_param
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM initialization parameters register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_reg">
+DRAM_EMR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR2, EMR3 access register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_EMR_MR_reg">
+DRAM_EMR_MR_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM EMR, MR access register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_burst8_rdwr">
+DRAM_burst8_rdwr
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM burst 8 read/write register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_disable_DQ">
+DRAM_disable_DQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM Disable DQ register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_bank">
+DRAM_addr_map_bank
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as DRAM bank address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_col">
+DRAM_addr_map_col
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as DRAM column address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_addr_map_row">
+DRAM_addr_map_row
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as DRAM row address bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DRAM_ODT_reg">
+DRAM_ODT_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ODT register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_cmd_timeout_rddata_cpt">
+phy_cmd_timeout_rddata_cpt
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY command time out and read data capture FIFO register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DLL_calib">
+DLL_calib
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DLL calibration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ODT_delay_hold">
+ODT_delay_hold
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ODT delay and ODT hold register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg1">
+ctrl_reg1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg2">
+ctrl_reg2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg3">
+ctrl_reg3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ctrl_reg4">
+ctrl_reg4
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller register 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_REFRESH_TIMER01">
+CHE_REFRESH_TIMER01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ">
+CHE_T_ZQ
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ parameters register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_T_ZQ_Short_Interval_Reg">
+CHE_T_ZQ_Short_Interval_Reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc parameters register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#deep_pwrdwn_reg">
+deep_pwrdwn_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Deep powerdown register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2c">
+reg_2c
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_2d">
+reg_2d
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Misc Debug register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#dfi_timing">
+dfi_timing
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DFI timing register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_CONTROL_REG_OFFSET">
+CHE_ECC_CONTROL_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error clear register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
+CHE_CORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error correction register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC unrecoverable error status register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CHE_ECC_STATS_REG_OFFSET">
+CHE_ECC_STATS_REG_OFFSET
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC error count register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ECC_scrub">
+ECC_scrub
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ECC mode/scrub register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rcvr_enable">
+phy_rcvr_enable
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#PHY_Config">
+PHY_Config
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_init_ratio">
+phy_init_ratio
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_rd_dqs_cfg">
+phy_rd_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_wr_dqs_cfg">
+phy_wr_dqs_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#phy_we_cfg">
+phy_we_cfg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#wr_data_slv">
+wr_data_slv
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_64">
+reg_64
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control register (2)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#reg_65">
+reg_65
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Training control register (3)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#page_mask">
+page_mask
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Page mask register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_wr_port">
+axi_priority_wr_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#axi_priority_rd_port">
+axi_priority_rd_port
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl0">
+lpddr_ctrl0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 0 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl1">
+lpddr_ctrl1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 1 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl2">
+lpddr_ctrl2
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 2 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#lpddr_ctrl3">
+lpddr_ctrl3
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>LPDDR2 Control 3 Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#ddrc_ctrl">
+ddrc_ctrl
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>DDR INITIALIZATION</H1>
+<H1>LOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Two_rank_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_nom_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>82</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_active_ranks</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_block</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_diff_rank_rd_2cycle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_cs_bit1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_open_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_4bank_ram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Two_rank_cfg@0XF8006004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81082</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Two rank configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>HPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_hpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>HPR_reg@0XF8006008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c0780f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>HPR Queue control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LPR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800600C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LPR_reg@0XF800600C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2001001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPR Queue control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>WR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006010</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_min_non_critical_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_xact_run_length</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_w_max_starve_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>WR_reg@0XF8006010</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>14001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>WR Queue control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006014</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rfc_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2840</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_selfref_gap_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fc000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg0@0XF8006014</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4285b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_faw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>240000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ras_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4c00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_cke</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg1@0XF8006018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>44e458d3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800601C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_write_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr2rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_xp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tXP: Minimum time after power down exit to any operation. DRAM RELATED.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd2pre</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2800000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rcd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg2@0XF800601C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7282bce5</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006020</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_ccd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_rp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_to_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_sdram</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = sdram device 0 = non-sdram device</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mobile</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_clock_stop_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_read_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_mode_ddr1_ddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pad_pd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = disable the pad power down feature 0 = Enable the pad power down feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg3@0XF8006020</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffffc</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>272872d0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_param_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006024</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_en_2t_timing_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = DDRC will use 2T timing 0 = DDRC will use 1T timing</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_prefer_write</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Bank selector prefers writes over reads</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_rank_rd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_wr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_addr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fffe00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_mr_wr_busy</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates whether the Mode register operation is read or write 1 = read 0 = write</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr_rdata_valid</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_param_reg4@0XF8006024</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Parameters register 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_init_param</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006028</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_final_wait_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_ocd_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_init_param@0XF8006028</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2007</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM initialization parameters register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800602C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_reg@0XF800602C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR2, EMR3 access register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_EMR_MR_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006030</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b30</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_emr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_EMR_MR_reg@0XF8006030</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40b30</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM EMR, MR access register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_burst8_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst_rdwr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pre_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16d0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_post_cke_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burstchop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_burst8_rdwr@0XF8006034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>13ff3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>116d4</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM burst 8 read/write register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_disable_DQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006038</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_force_low_pri_n</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_debug_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_level_start</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq0_wait_t</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not Applicable in this PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_disable_DQ@0XF8006038</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fc3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM Disable DQ register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_bank</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800603C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_bank_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_bank@0XF800603C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>777</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Selects the address bits used as DRAM bank address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_col</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006040</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b9</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_col_b11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_col@0XF8006040</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>fff00000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Selects the address bits used as DRAM column address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_addr_map_row</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006044</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b2_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_addrmap_row_b15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_addr_map_row@0XF8006044</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f666666</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Selects the address bits used as DRAM row address bits</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRAM_ODT_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006048</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank0_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank1_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_idle_local_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank2_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_rd_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rank3_wr_odt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DRAM_ODT_reg@0XF8006048</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3c248</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DRAM ODT register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_cmd_timeout_rddata_cpt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006050</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_cmd_to_data</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Not used in DFI PHY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_we_to_re_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_disable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_fixed_re</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_phy_ctrl_rstn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_clk_stall_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = stall clock, for DLL aging control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_num_of_dq0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>70000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff0f8fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>77010800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY command time out and read data capture FIFO register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DLL_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006058</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dll_calib_to_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused in DFI Controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_dll_calib</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DLL_calib@0XF8006058</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>101</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DLL calibration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ODT_delay_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800605C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rd_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Unused</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wr_odt_hold</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ODT_delay_hold@0XF800605C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5003</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ODT delay and ODT hold register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006060</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_pageclose</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpr_num_entries</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_auto_pre_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_refresh_update_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_wc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When 1, disable Write Combine</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_collision_page_opt</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_selfref_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg1@0XF8006060</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>17ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3e</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006064</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_go2critical_hysteresis</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_go2critical_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg2@0XF8006064</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006068</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_wrlvl_ww</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdlvl_rr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_wlmrd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>280000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg3@0XF8006068</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>284141</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ctrl_reg4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800606C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_min_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_t_ctrlupd_interval_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ctrl_reg4@0XF800606C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1610</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Controller register 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_REFRESH_TIMER01">Register (<A href=#mod___slcr> slcr </A>)CHE_REFRESH_TIMER01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer0_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>refresh_timer1_start_value_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01@0XF80060A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>CHE_REFRESH_TIMER01</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_zq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ddr3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mod</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_long_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_zq_short_nop</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ@0XF80060A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10200802</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ZQ parameters register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_T_ZQ_Short_Interval_Reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>t_zq_short_interval_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dram_rstn_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>69</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6900000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>690cb73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc parameters register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deep_pwrdwn_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>deeppowerdown_to_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>deep_pwrdwn_reg@0XF80060AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fe</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Deep powerdown register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_wrlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_rdlvl_max_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>fff000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_twrlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_trdlvl_max_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_wr_level_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_rd_data_eye_train</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2c@0XF80060B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1cffffff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_2d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_2t_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_skip_ocd</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_pre_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_2d@0XF80060B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Misc Debug register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>dfi_timing</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_rddata_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_min</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fe0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dfi_t_ctrlup_max</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>dfi_timing@0XF80060B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>200066</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DFI timing register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_CONTROL_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Uncorrectable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Clear_Correctable_DRAM_ECC_error</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error clear register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_CORRECTED_BIT_NUM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error correction register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060DC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNCORR_ECC_LOG_VALID</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC unrecoverable error status register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHE_ECC_STATS_REG_OFFSET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_CORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STAT_NUM_UNCORR_ERR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC error count register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ECC_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80060F4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_ecc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_scrub</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ECC_scrub@0XF80060F4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>ECC mode/scrub register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rcvr_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006114</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_on</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dif_off</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rcvr_enable@0XF8006114</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Phy receiver enable register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006118</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006118</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800611C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF800611C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006120</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006120</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PHY_Config</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006124</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_data_slice_in_use</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rdlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_inc_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>RESERVED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_tx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_board_lpbk_rx</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_shift_dq</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7fc0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_err_clr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dq_offset</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>PHY_Config@0XF8006124</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7fffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>40000001</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800612C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF800612C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006130</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006130</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>27000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006134</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>9b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006134</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>26c00</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006138</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wrlvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used by Write Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_gatelvl_init_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The user programmable init ratio used Gate Leveling FSM</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_init_ratio@0XF8006138</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>28800</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY init ratio register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006140</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006140</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006144</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006144</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006148</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF8006148</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_rd_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800614C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_rd_dqs_cfg@0XF800614C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>35</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY read DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006154</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006154</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006158</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006158</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7a</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800615C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF800615C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_wr_dqs_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006160</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>73</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>73</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_dqs_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_wr_dqs_cfg@0XF8006160</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>73</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write DQS configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006168</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006168</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800616C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF800616C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006170</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006170</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>phy_we_cfg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006174</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f7</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f7</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_fifo_we_in_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>phy_we_cfg@0XF8006174</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f7</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY fifo write enable configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800617C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF800617C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006180</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ba</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006184</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bc</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006184</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bc</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>wr_data_slv</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006188</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>b3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>b3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_data_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>wr_data_slv@0XF8006188</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>b3</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>PHY write data slave ratio configuration register for data slice 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_64</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006190</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_loopback</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Loopback testing. 1: enable, 0: disable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved for future Use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_at_spd_atpg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_force_err</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_bist_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_invert_clkout</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_all_dq_mpr_rd_resp</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_sel_logic</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_ratio</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffc00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_force</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>27:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe00000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rank0_delays</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>28:28</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_lpddr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_cmd_latency</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>30:30</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If set to 1, command comes to phy_ctrl through a flop.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_int_lpbk</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:31</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_64@0XF8006190</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>10040080</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control register (2)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_65</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006194</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_wr_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_rd_rl_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dll_lock_diff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3c00</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_wr_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_dqs_gate_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_use_rd_data_eye_level</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_dis_calib_rst</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_phy_ctrl_slave_delay</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>reg_65@0XF8006194</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1fc82</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Training control register (3)</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>page_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006204</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_page_addr_mask</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>page_mask@0XF8006204</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Page mask register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006208</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006208</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800620C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF800620C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006210</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006210</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_wr_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006214</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Write Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_wr_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_rmw_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_wr_port@0XF8006214</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>803ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for write port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006218</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006218</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800621C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF800621C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006220</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006220</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>axi_priority_rd_port</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006224</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_pri_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_aging_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable aging for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_disable_urgent_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable urgent for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_dis_page_match_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable the page match feature.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_arb_set_hpr_rd_portn</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable reads to be generated as HPR for this Read Port.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>axi_priority_rd_port@0XF8006224</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f03ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>3ff</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>AXI Priority control for read port 0.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_lpddr2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_per_bank_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_derate_enable</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_margin</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UNUSED</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl0@0XF80062A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 0 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_mr4_read_interval</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl1@0XF80062AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 1 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_min_stable_clock_x1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_idle_after_reset_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>120</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_t_mrw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>5</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl2@0XF80062B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>5125</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 2 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>lpddr_ctrl3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80062B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_max_auto_init_x1024</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>a8</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dev_zqinit_x32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3ff00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>lpddr_ctrl3@0XF80062B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>12a8</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>LPDDR2 Control 3 Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>POLL ON DCI STATUS</H1>
+<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_STATUS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B74</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DONE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI done signal</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>UNLOCK DDR</H1>
+<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_ctrl</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_soft_rstb</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_powerdown_en</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_data_bus_width</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_burst8_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_rdwr_idle_gap</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_rd_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_act_bypass</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:15</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reg_ddrc_dis_auto_refresh</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>ddrc_ctrl@0XF8006000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>81</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRC Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>CHECK DDR STATUS</H1>
+<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_sts_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8006054</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ddrc_reg_operating_mode</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_sts_reg@0XF8006054</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>tobe</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR0">
+DDRIOB_ADDR0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Address 0 Configuartion Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_ADDR1">
+DDRIOB_ADDR1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Address 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_CLOCK">
+DDRIOB_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential Clock Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_ADDR">
+DDRIOB_DRIVE_SLEW_ADDR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Address Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DATA">
+DDRIOB_DRIVE_SLEW_DATA
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Data Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_DIFF">
+DDRIOB_DRIVE_SLEW_DIFF
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Differential Strobe Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
+DDRIOB_DRIVE_SLEW_CLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Drive Slew Clcok Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DDR_CTRL">
+DDRIOB_DDR_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DDR Control Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DCI_CTRL">
+DDRIOB_DCI_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_00">
+MIO_PIN_00
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_01">
+MIO_PIN_01
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_02">
+MIO_PIN_02
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 2</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_03">
+MIO_PIN_03
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 3</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_04">
+MIO_PIN_04
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 4</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_05">
+MIO_PIN_05
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 5</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_06">
+MIO_PIN_06
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 6</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_07">
+MIO_PIN_07
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 7</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_08">
+MIO_PIN_08
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 8</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_09">
+MIO_PIN_09
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 9</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_10">
+MIO_PIN_10
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 10</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_11">
+MIO_PIN_11
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 11</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_12">
+MIO_PIN_12
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 12</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_13">
+MIO_PIN_13
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 13</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_14">
+MIO_PIN_14
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 14</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_15">
+MIO_PIN_15
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 15</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_16">
+MIO_PIN_16
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 16</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_17">
+MIO_PIN_17
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 17</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_18">
+MIO_PIN_18
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 18</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_19">
+MIO_PIN_19
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 19</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_20">
+MIO_PIN_20
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 20</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_21">
+MIO_PIN_21
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 21</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_22">
+MIO_PIN_22
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 22</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_23">
+MIO_PIN_23
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 23</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_24">
+MIO_PIN_24
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 24</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_25">
+MIO_PIN_25
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 25</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_26">
+MIO_PIN_26
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 26</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_27">
+MIO_PIN_27
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 27</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_28">
+MIO_PIN_28
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 28</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_29">
+MIO_PIN_29
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 29</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_30">
+MIO_PIN_30
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 30</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_31">
+MIO_PIN_31
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 31</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_32">
+MIO_PIN_32
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 32</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_33">
+MIO_PIN_33
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_34">
+MIO_PIN_34
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 34</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_35">
+MIO_PIN_35
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 35</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_36">
+MIO_PIN_36
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 36</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_37">
+MIO_PIN_37
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 37</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_38">
+MIO_PIN_38
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 38</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_39">
+MIO_PIN_39
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 39</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_40">
+MIO_PIN_40
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 40</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_41">
+MIO_PIN_41
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 41</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_42">
+MIO_PIN_42
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 42</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_43">
+MIO_PIN_43
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 43</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_44">
+MIO_PIN_44
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 44</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_45">
+MIO_PIN_45
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 45</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_46">
+MIO_PIN_46
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 46</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_47">
+MIO_PIN_47
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 47</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_48">
+MIO_PIN_48
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 48</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_49">
+MIO_PIN_49
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 49</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_50">
+MIO_PIN_50
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 50</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_51">
+MIO_PIN_51
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 51</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_52">
+MIO_PIN_52
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 52</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MIO_PIN_53">
+MIO_PIN_53
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>MIO Control for Pin 53</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SD0_WP_CD_SEL">
+SD0_WP_CD_SEL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO 0 WP CD select register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>OCM REMAPPING</H1>
+<H1>DDRIOB SETTINGS</H1>
+<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR0@0XF8000B40</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Address 0 Configuartion Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_ADDR1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B44</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_ADDR1@0XF8000B44</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Address 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>672</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>674</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B58</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_POWER</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INP_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCI_UPDATE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DCR_TYPE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OUTPUT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_CLOCK@0XF8000B58</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential Clock Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_ADDR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B5C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>180000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>18c068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Address Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DATA</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Data Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_DIFF</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B64</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Differential Strobe Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B68</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>68</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRIVE_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO drive strength for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_P</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>18000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the P devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLEW_N</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>f80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Programs the DDRIO slew rate for the N devices</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>GTL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RTERM</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:27</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f8000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Program the rterm</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f98068</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Drive Slew Clcok Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DDR_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B6C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_INT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF internal generator</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1e</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_EXT_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>60</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VREF_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>REFIO_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DRST_B_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CKE_PULLUP_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>14:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>73ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>260</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DDR Control Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DEASSERT RESET</H1>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>21</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DCI_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B70</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RESET</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>At least toggle once to initialise flops in DCI system</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>1 if any iob's use a terminate type, or if dci test block used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_TRI</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN tristate value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRP_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRP output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>VRN_OUT</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>VRN output value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NREF_OPT4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PREF_OPT2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UPDATE_CONTROL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DCI Update</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INIT_COMPLETE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>test Internal to IO bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_CLK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate DCI clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRN)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_HLP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate comparator output (VRP)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TST_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>25:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Emulate Reset</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>INT_DCI_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>26:26</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Need explanation here</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>7ffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>823</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB DCI configuration</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MIO PROGRAMMING</H1>
+<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_00</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000700</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_00@0XF8000700</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 0</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_01</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000704</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_01@0XF8000704</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_02</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000708</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_02@0XF8000708</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 2</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_03</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800070C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_03@0XF800070C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 3</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_04</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000710</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_04@0XF8000710</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 4</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_05</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000714</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_05@0XF8000714</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 5</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_06</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000718</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_06@0XF8000718</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 6</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_07</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800071C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_07@0XF800071C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 7</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_08</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000720</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_08@0XF8000720</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>602</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 8</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_09</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000724</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_09@0XF8000724</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 9</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_10</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000728</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_10@0XF8000728</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 10</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_11</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800072C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_11@0XF800072C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 11</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_12</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000730</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_12@0XF8000730</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 12</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_13</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000734</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_13@0XF8000734</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 13</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_14</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000738</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_14@0XF8000738</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 14</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_15</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800073C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>600</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_15@0XF800073C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1600</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 15</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_16</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000740</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_16@0XF8000740</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 16</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_17</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000744</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_17@0XF8000744</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 17</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_18</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000748</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_18@0XF8000748</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 18</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_19</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800074C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_19@0XF800074C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 19</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_20</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000750</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_20@0XF8000750</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 20</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_21</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000754</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_21@0XF8000754</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1302</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 21</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_22</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000758</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_22@0XF8000758</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 22</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_23</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800075C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_23@0XF800075C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 23</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_24</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000760</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_24@0XF8000760</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 24</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_25</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000764</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_25@0XF8000764</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 25</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_26</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000768</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_26@0XF8000768</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 26</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_27</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800076C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_27@0XF800076C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1303</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 27</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_28</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000770</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_28@0XF8000770</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 28</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_29</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000774</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_29@0XF8000774</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 29</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_30</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000778</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_30@0XF8000778</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 30</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_31</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800077C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_31@0XF800077C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 31</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_32</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000780</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_32@0XF8000780</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 32</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_33</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000784</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_33@0XF8000784</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 33</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_34</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000788</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_34@0XF8000788</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 34</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_35</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800078C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_35@0XF800078C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 35</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_36</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000790</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_36@0XF8000790</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1305</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 36</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000794</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_37@0XF8000794</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 37</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_38</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000798</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_38@0XF8000798</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 38</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_39</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF800079C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_39@0XF800079C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1304</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 39</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_40</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_40@0XF80007A0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 40</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_41</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_41@0XF80007A4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 41</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_42</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007A8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_42@0XF80007A8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 42</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_43</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007AC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_43@0XF80007AC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 43</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_44</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_44@0XF80007B0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 44</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_45</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_45@0XF80007B4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 45</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_46</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007B8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_46@0XF80007B8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 46</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_47</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007BC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_47@0XF80007BC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f01</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1201</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 47</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_48</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_48@0XF80007C0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 48</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_49</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_49@0XF80007C4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 49</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_50</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007C8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_50@0XF80007C8</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 50</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_51</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007CC</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_51@0XF80007CC</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1200</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 51</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_52</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_52@0XF80007D0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 52</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MIO_PIN_53</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF80007D4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TRI_ENABLE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Tri-state enable, active high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L0_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L1_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L2_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>L3_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Speed</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IO_Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>e00</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PULLUP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DisableRcvr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MIO_PIN_53@0XF80007D4</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>1280</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>MIO Control for Pin 53</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SD0_WP_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000830</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_WP_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>37</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>37</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SDIO0_CD_SEL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3f0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2f</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2f0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SD0_WP_CD_SEL@0XF8000830</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3f003f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>2f0037</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SDIO 0 WP CD select register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA0">
+DDRIOB_DATA0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DATA1">
+DDRIOB_DATA1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF0">
+DDRIOB_DIFF0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DDRIOB_DIFF1">
+DDRIOB_DIFF1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_divider_reg0">
+Baud_rate_divider_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Baud_rate_gen_reg0">
+Baud_rate_gen_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Control_reg0">
+Control_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Control register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#mode_reg0">
+mode_reg0
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>UART Mode register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#Config_reg">
+Config_reg
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#CTRL">
+CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#DIRM_1">
+DIRM_1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A244</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Direction mode configuration register: Configures bank 1 for direction mode, either input or output</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#OEN_1">
+OEN_1
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A248</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Output enable register: Configures the output enables of bank 1</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#MASK_DATA_1_LSW">
+MASK_DATA_1_LSW
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
+<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B48</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA0@0XF8000B48</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DATA1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B4C</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DATA1@0XF8000B4C</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Data 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B50</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF0@0XF8000B50</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 0 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DDRIOB_DIFF1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000B54</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IBUF_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TERM_DISABLE_MODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DDRIOB_DIFF1@0XF8000B54</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>180</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>DDRIOB Differential DQS 1 Configuration Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SRAM/NOR SET OPMODE</H1>
+<H1>UART REGISTERS</H1>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0001034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0001018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break. 1 = stop transmission of the break.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter 1 = receiver timeout counter is restarted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable. 1, the transmitter is disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable. 1= receiver is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0001000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0001004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IRMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UCLKEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0001004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_divider_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000034</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>BDIV</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_divider_reg0@0XE0000034</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>6</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Baud_rate_gen_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000018</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CD</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Baud_rate_gen_reg0@0XE0000018</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>7c</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Baud rate divider register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Control_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STPBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Stop transmitter break. 1 = stop transmission of the break.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>STTBRK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:7</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RSTTO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>6:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>40</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Restart receiver timeout counter 1 = receiver timeout counter is restarted</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:5</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit disable. 1, the transmitter is disabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXDIS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive disable. 1= receiver is enabled</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>TXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>RXRES</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Control_reg0@0XE0000000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>1ff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>17</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Control register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>mode_reg0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE0000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>IRMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UCLKEN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHMODE</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>300</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>NBSTOP</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>5:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>38</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CHRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>6</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CLKS</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>mode_reg0@0XE0000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>fff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>20</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>UART Mode register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>QSPI REGISTERS</H1>
+<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Config_reg</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000D000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>Holdb_dr</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:19</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>Config_reg@0XE000D000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>80000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SPI configuration register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>PL POWER ON RESET REGISTERS</H1>
+<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8007000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>PCFG_POR_CNT_4K</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>29:29</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>CTRL@0XF8007000</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>20000000</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
+<H1>NAND SET CYCLE</H1>
+<H1>OPMODE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>SRAM/NOR CS0 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS0 BASE ADDRESS</H1>
+<H1>SRAM/NOR CS1 SET CYCLE</H1>
+<H1>DIRECT COMMAND</H1>
+<H1>NOR CS1 BASE ADDRESS</H1>
+<H1>USB RESET</H1>
+<H1>USB0 RESET</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>DIR MODE BANK 1</H1>
+<H2><a name="DIRM_1">Register (<A href=#mod___slcr> slcr </A>)DIRM_1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIRM_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A244</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DIRECTION_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Direction mode for bank 1 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>DIRM_1@0XE000A244</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Direction mode configuration register: Configures bank 1 for direction mode, either input or output</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+<H1>OUTPUT ENABLE BANK 1</H1>
+<H2><a name="OEN_1">Register (<A href=#mod___slcr> slcr </A>)OEN_1</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OEN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A248</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>OP_ENABLE_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Output enables for bank 1 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>OEN_1@0XE000A248</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>3fffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Output enable register: Configures the output enables of bank 1</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
+<H1>ADD 1 MS DELAY</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
+<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
+<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XE000A008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>MASK_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>bfff</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>bfff0000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>DATA_1_LSW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>4000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>MASK_DATA_1_LSW@0XE000A008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>bfff4000</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
+<H1>ENET RESET</H1>
+<H1>I2C RESET</H1>
+<H1>NOR CHIP SELECT</H1>
+<H1>DIR MODE BANK 0</H1>
+<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
+<H1>OUTPUT ENABLE BANK 0</H1>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_UNLOCK">
+SLCR_UNLOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LVL_SHFTR_EN">
+LVL_SHFTR_EN
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#FPGA_RST_CTRL">
+FPGA_RST_CTRL
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>RW</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#SLCR_LOCK">
+SLCR_LOCK
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>SLCR SETTINGS</H1>
+<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_UNLOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000008</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>UNLOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_UNLOCK@0XF8000008</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>df0d</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Unlock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING LEVEL SHIFTER</H1>
+<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LVL_SHFTR_EN</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000900</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>USER_INP_ICT_EN_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LVL_SHFTR_EN@0XF8000900</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>f</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Level Shifters Enable</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>FPGA RESETS TO 0</H1>
+<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_RST_CTRL</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000240</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_3</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:25</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>fe000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_ACP_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>24:24</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>23:23</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>22:22</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>21:21</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_AXDS0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>20:20</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_2</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>19:18</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c0000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW1_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>17:17</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>20000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FSSW0_FPGA_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>16:16</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>10000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved_1</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:14</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>13:13</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_FMSW0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>12:12</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1000</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA3_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>11:11</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>800</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA2_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>10:10</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>400</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA1_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>9:9</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>200</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA_DMA0_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>8:8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>100</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>reserved</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>7:4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>f0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Reserved. Writes are ignored, read data is always zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA3_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>3:3</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>8</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA2_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>2:2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>4</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA1_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>1:1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>2</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>FPGA0_OUT_RST</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>1</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>FPGA_RST_CTRL@0XF8000240</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>0</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>FPGA Software Reset Control</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>AFI REGISTERS</H1>
+<H1>AFI0 REGISTERS</H1>
+<H1>AFI1 REGISTERS</H1>
+<H1>AFI2 REGISTERS</H1>
+<H1>AFI3 REGISTERS</H1>
+<H1>LOCK IT BACK</H1>
+<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>SLCR_LOCK</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8000004</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LOCK_KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>15:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>SLCR_LOCK@0XF8000004</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>767b</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>SLCR Write Protection Lock</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_1_0">ps7_debug_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<A href="#LAR">
+LAR
+</A>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>WO</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="ps7_debug_1_0">ps7_debug_1_0</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFC0FF>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFC0FF>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFC0FF>
+<B>Description</B>
+</TD>
+</TR>
+<H1>CROSS TRIGGER CONFIGURATIONS</H1>
+<H1>UNLOCKING CTI REGISTERS</H1>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8898FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8898FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8899FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8899FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Register Name</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Address</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Width</B>
+</TD>
+<TD width=10% BGCOLOR=#FFFF00>
+<B>Type</B>
+</TD>
+<TD width=15% BGCOLOR=#FFFF00>
+<B>Reset Value</B>
+</TD>
+<TD width=35% BGCOLOR=#FFFF00>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>LAR</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0XF8809FB0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>32</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>rw</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>0x00000000</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>--</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Field Name</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Bits</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Mask</B>
+</TD>
+<TD width=10% BGCOLOR=#C0FFC0>
+<B>Value</B>
+</TD>
+<TD width=15% BGCOLOR=#C0FFC0>
+<B>Shifted Value</B>
+</TD>
+<TD width=35% BGCOLOR=#C0FFC0>
+<B>Description</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>KEY</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=15% BGCOLOR=#FBF5EF>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#FBF5EF>
+<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
+</TD>
+</TR>
+<TR valign="top">
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>LAR@0XF8809FB0</B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>31:0</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B>ffffffff</B>
+</TD>
+<TD width=10% BGCOLOR=#C0C0C0>
+<B></B>
+</TD>
+<TD width=15% BGCOLOR=#C0C0C0>
+<B>c5acce55</B>
+</TD>
+<TD width=35% BGCOLOR=#C0C0C0>
+<B>Lock Access Register</B>
+</TD>
+</TR>
+</TABLE>
+<P>
+<H1>ENABLING CTI MODULES AND CHANNELS</H1>
+<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
+</TABLE>
+<P>
+</body>
+</head>
+</body>
+</html>
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.tcl b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..45487634dc7b4a8f2e5f69a4f38b69cc255c7428
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init.tcl
@@ -0,0 +1,844 @@
+proc ps7_pll_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000110 0x003FFFF0 0x000FA220
+ mask_write 0XF8000100 0x0007F000 0x00028000
+ mask_write 0XF8000100 0x00000010 0x00000010
+ mask_write 0XF8000100 0x00000001 0x00000001
+ mask_write 0XF8000100 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000001
+ mask_write 0XF8000100 0x00000010 0x00000000
+ mask_write 0XF8000120 0x1F003F30 0x1F000200
+ mask_write 0XF8000114 0x003FFFF0 0x0012C220
+ mask_write 0XF8000104 0x0007F000 0x00020000
+ mask_write 0XF8000104 0x00000010 0x00000010
+ mask_write 0XF8000104 0x00000001 0x00000001
+ mask_write 0XF8000104 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000002
+ mask_write 0XF8000104 0x00000010 0x00000000
+ mask_write 0XF8000124 0xFFF00003 0x0C200003
+ mask_write 0XF8000118 0x003FFFF0 0x001452C0
+ mask_write 0XF8000108 0x0007F000 0x0001E000
+ mask_write 0XF8000108 0x00000010 0x00000010
+ mask_write 0XF8000108 0x00000001 0x00000001
+ mask_write 0XF8000108 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000004
+ mask_write 0XF8000108 0x00000010 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000128 0x03F03F01 0x00700F01
+ mask_write 0XF8000138 0x00000011 0x00000001
+ mask_write 0XF8000140 0x03F03F71 0x00100801
+ mask_write 0XF800014C 0x00003F31 0x00000501
+ mask_write 0XF8000150 0x00003F33 0x00001401
+ mask_write 0XF8000154 0x00003F33 0x00000A03
+ mask_write 0XF8000168 0x00003F31 0x00000501
+ mask_write 0XF8000170 0x03F03F30 0x00200500
+ mask_write 0XF80001C4 0x00000001 0x00000001
+ mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+ mask_write 0XF8006000 0x0001FFFF 0x00000080
+ mask_write 0XF8006004 0x0007FFFF 0x00001082
+ mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+ mask_write 0XF800600C 0x03FFFFFF 0x02001001
+ mask_write 0XF8006010 0x03FFFFFF 0x00014001
+ mask_write 0XF8006014 0x001FFFFF 0x0004285B
+ mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+ mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+ mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+ mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+ mask_write 0XF8006028 0x00003FFF 0x00002007
+ mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+ mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+ mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+ mask_write 0XF8006038 0x00000003 0x00000000
+ mask_write 0XF800603C 0x000FFFFF 0x00000777
+ mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+ mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+ mask_write 0XF8006048 0x0003F03F 0x0003C008
+ mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+ mask_write 0XF8006058 0x00010000 0x00000000
+ mask_write 0XF800605C 0x0000FFFF 0x00005003
+ mask_write 0XF8006060 0x000017FF 0x0000003E
+ mask_write 0XF8006064 0x00021FE0 0x00020000
+ mask_write 0XF8006068 0x03FFFFFF 0x00284141
+ mask_write 0XF800606C 0x0000FFFF 0x00001610
+ mask_write 0XF8006078 0x03FFFFFF 0x00466111
+ mask_write 0XF800607C 0x000FFFFF 0x00032222
+ mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+ mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+ mask_write 0XF80060AC 0x000001FF 0x000001FE
+ mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+ mask_write 0XF80060B4 0x00000200 0x00000200
+ mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+ mask_write 0XF80060C4 0x00000003 0x00000000
+ mask_write 0XF80060C8 0x000000FF 0x00000000
+ mask_write 0XF80060DC 0x00000001 0x00000000
+ mask_write 0XF80060F0 0x0000FFFF 0x00000000
+ mask_write 0XF80060F4 0x0000000F 0x00000008
+ mask_write 0XF8006114 0x000000FF 0x00000000
+ mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+ mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+ mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+ mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+ mask_write 0XF800612C 0x000FFFFF 0x00027000
+ mask_write 0XF8006130 0x000FFFFF 0x00027000
+ mask_write 0XF8006134 0x000FFFFF 0x00026C00
+ mask_write 0XF8006138 0x000FFFFF 0x00028800
+ mask_write 0XF8006140 0x000FFFFF 0x00000035
+ mask_write 0XF8006144 0x000FFFFF 0x00000035
+ mask_write 0XF8006148 0x000FFFFF 0x00000035
+ mask_write 0XF800614C 0x000FFFFF 0x00000035
+ mask_write 0XF8006154 0x000FFFFF 0x0000007A
+ mask_write 0XF8006158 0x000FFFFF 0x0000007A
+ mask_write 0XF800615C 0x000FFFFF 0x0000007C
+ mask_write 0XF8006160 0x000FFFFF 0x00000073
+ mask_write 0XF8006168 0x001FFFFF 0x000000F1
+ mask_write 0XF800616C 0x001FFFFF 0x000000F1
+ mask_write 0XF8006170 0x001FFFFF 0x000000F0
+ mask_write 0XF8006174 0x001FFFFF 0x000000F7
+ mask_write 0XF800617C 0x000FFFFF 0x000000BA
+ mask_write 0XF8006180 0x000FFFFF 0x000000BA
+ mask_write 0XF8006184 0x000FFFFF 0x000000BC
+ mask_write 0XF8006188 0x000FFFFF 0x000000B3
+ mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+ mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+ mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+ mask_write 0XF8006208 0x000703FF 0x000003FF
+ mask_write 0XF800620C 0x000703FF 0x000003FF
+ mask_write 0XF8006210 0x000703FF 0x000003FF
+ mask_write 0XF8006214 0x000703FF 0x000003FF
+ mask_write 0XF8006218 0x000F03FF 0x000003FF
+ mask_write 0XF800621C 0x000F03FF 0x000003FF
+ mask_write 0XF8006220 0x000F03FF 0x000003FF
+ mask_write 0XF8006224 0x000F03FF 0x000003FF
+ mask_write 0XF80062A8 0x00000FF5 0x00000000
+ mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+ mask_write 0XF80062B0 0x003FFFFF 0x00005125
+ mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+ mask_poll 0XF8000B74 0x00002000
+ mask_write 0XF8006000 0x0001FFFF 0x00000081
+ mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B40 0x00000FFF 0x00000600
+ mask_write 0XF8000B44 0x00000FFF 0x00000600
+ mask_write 0XF8000B48 0x00000FFF 0x00000672
+ mask_write 0XF8000B4C 0x00000FFF 0x00000672
+ mask_write 0XF8000B50 0x00000FFF 0x00000674
+ mask_write 0XF8000B54 0x00000FFF 0x00000674
+ mask_write 0XF8000B58 0x00000FFF 0x00000600
+ mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
+ mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B6C 0x00007FFF 0x00000260
+ mask_write 0XF8000B70 0x00000001 0x00000001
+ mask_write 0XF8000B70 0x00000021 0x00000020
+ mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+ mask_write 0XF8000700 0x00003FFF 0x00001600
+ mask_write 0XF8000704 0x00003FFF 0x00001602
+ mask_write 0XF8000708 0x00003FFF 0x00000602
+ mask_write 0XF800070C 0x00003FFF 0x00000602
+ mask_write 0XF8000710 0x00003FFF 0x00000602
+ mask_write 0XF8000714 0x00003FFF 0x00000602
+ mask_write 0XF8000718 0x00003FFF 0x00000602
+ mask_write 0XF800071C 0x00003FFF 0x00000600
+ mask_write 0XF8000720 0x00003FFF 0x00000602
+ mask_write 0XF8000724 0x00003FFF 0x00001600
+ mask_write 0XF8000728 0x00003FFF 0x00001600
+ mask_write 0XF800072C 0x00003FFF 0x00001600
+ mask_write 0XF8000730 0x00003FFF 0x00001600
+ mask_write 0XF8000734 0x00003FFF 0x00001600
+ mask_write 0XF8000738 0x00003FFF 0x00001600
+ mask_write 0XF800073C 0x00003FFF 0x00001600
+ mask_write 0XF8000740 0x00003FFF 0x00001302
+ mask_write 0XF8000744 0x00003FFF 0x00001302
+ mask_write 0XF8000748 0x00003FFF 0x00001302
+ mask_write 0XF800074C 0x00003FFF 0x00001302
+ mask_write 0XF8000750 0x00003FFF 0x00001302
+ mask_write 0XF8000754 0x00003FFF 0x00001302
+ mask_write 0XF8000758 0x00003FFF 0x00001303
+ mask_write 0XF800075C 0x00003FFF 0x00001303
+ mask_write 0XF8000760 0x00003FFF 0x00001303
+ mask_write 0XF8000764 0x00003FFF 0x00001303
+ mask_write 0XF8000768 0x00003FFF 0x00001303
+ mask_write 0XF800076C 0x00003FFF 0x00001303
+ mask_write 0XF8000770 0x00003FFF 0x00001304
+ mask_write 0XF8000774 0x00003FFF 0x00001305
+ mask_write 0XF8000778 0x00003FFF 0x00001304
+ mask_write 0XF800077C 0x00003FFF 0x00001305
+ mask_write 0XF8000780 0x00003FFF 0x00001304
+ mask_write 0XF8000784 0x00003FFF 0x00001304
+ mask_write 0XF8000788 0x00003FFF 0x00001304
+ mask_write 0XF800078C 0x00003FFF 0x00001304
+ mask_write 0XF8000790 0x00003FFF 0x00001305
+ mask_write 0XF8000794 0x00003FFF 0x00001304
+ mask_write 0XF8000798 0x00003FFF 0x00001304
+ mask_write 0XF800079C 0x00003FFF 0x00001304
+ mask_write 0XF80007A0 0x00003FFF 0x00001280
+ mask_write 0XF80007A4 0x00003FFF 0x00001280
+ mask_write 0XF80007A8 0x00003FFF 0x00001280
+ mask_write 0XF80007AC 0x00003FFF 0x00001280
+ mask_write 0XF80007B0 0x00003FFF 0x00001280
+ mask_write 0XF80007B4 0x00003FFF 0x00001280
+ mask_write 0XF80007B8 0x00003FFF 0x00001200
+ mask_write 0XF80007BC 0x00003F01 0x00001201
+ mask_write 0XF80007C0 0x00003FFF 0x00001200
+ mask_write 0XF80007C4 0x00003FFF 0x00001200
+ mask_write 0XF80007C8 0x00003FFF 0x00001200
+ mask_write 0XF80007CC 0x00003FFF 0x00001200
+ mask_write 0XF80007D0 0x00003FFF 0x00001280
+ mask_write 0XF80007D4 0x00003FFF 0x00001280
+ mask_write 0XF8000830 0x003F003F 0x002F0037
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B48 0x00000180 0x00000180
+ mask_write 0XF8000B4C 0x00000180 0x00000180
+ mask_write 0XF8000B50 0x00000180 0x00000180
+ mask_write 0XF8000B54 0x00000180 0x00000180
+ mwr -force 0XF8000004 0x0000767B
+ mask_write 0XE0001034 0x000000FF 0x00000006
+ mask_write 0XE0001018 0x0000FFFF 0x0000007C
+ mask_write 0XE0001000 0x000001FF 0x00000017
+ mask_write 0XE0001004 0x000003FF 0x00000020
+ mask_write 0XE0000034 0x000000FF 0x00000006
+ mask_write 0XE0000018 0x0000FFFF 0x0000007C
+ mask_write 0XE0000000 0x000001FF 0x00000017
+ mask_write 0XE0000004 0x000003FF 0x00000020
+ mask_write 0XE000D000 0x00080000 0x00080000
+ mask_write 0XF8007000 0x20000000 0x00000000
+ mask_write 0XE000A244 0x003FFFFF 0x00004000
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+ mask_write 0XE000A248 0x003FFFFF 0x00004000
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+ mask_delay 0XF8F00200 1
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_3_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000900 0x0000000F 0x0000000F
+ mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+ mwr -force 0XF8898FB0 0xC5ACCE55
+ mwr -force 0XF8899FB0 0xC5ACCE55
+ mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000110 0x003FFFF0 0x000FA220
+ mask_write 0XF8000100 0x0007F000 0x00028000
+ mask_write 0XF8000100 0x00000010 0x00000010
+ mask_write 0XF8000100 0x00000001 0x00000001
+ mask_write 0XF8000100 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000001
+ mask_write 0XF8000100 0x00000010 0x00000000
+ mask_write 0XF8000120 0x1F003F30 0x1F000200
+ mask_write 0XF8000114 0x003FFFF0 0x0012C220
+ mask_write 0XF8000104 0x0007F000 0x00020000
+ mask_write 0XF8000104 0x00000010 0x00000010
+ mask_write 0XF8000104 0x00000001 0x00000001
+ mask_write 0XF8000104 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000002
+ mask_write 0XF8000104 0x00000010 0x00000000
+ mask_write 0XF8000124 0xFFF00003 0x0C200003
+ mask_write 0XF8000118 0x003FFFF0 0x001452C0
+ mask_write 0XF8000108 0x0007F000 0x0001E000
+ mask_write 0XF8000108 0x00000010 0x00000010
+ mask_write 0XF8000108 0x00000001 0x00000001
+ mask_write 0XF8000108 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000004
+ mask_write 0XF8000108 0x00000010 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000128 0x03F03F01 0x00700F01
+ mask_write 0XF8000138 0x00000011 0x00000001
+ mask_write 0XF8000140 0x03F03F71 0x00100801
+ mask_write 0XF800014C 0x00003F31 0x00000501
+ mask_write 0XF8000150 0x00003F33 0x00001401
+ mask_write 0XF8000154 0x00003F33 0x00000A03
+ mask_write 0XF8000168 0x00003F31 0x00000501
+ mask_write 0XF8000170 0x03F03F30 0x00200500
+ mask_write 0XF80001C4 0x00000001 0x00000001
+ mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+ mask_write 0XF8006000 0x0001FFFF 0x00000080
+ mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+ mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+ mask_write 0XF800600C 0x03FFFFFF 0x02001001
+ mask_write 0XF8006010 0x03FFFFFF 0x00014001
+ mask_write 0XF8006014 0x001FFFFF 0x0004285B
+ mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+ mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+ mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+ mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+ mask_write 0XF8006028 0x00003FFF 0x00002007
+ mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+ mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+ mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+ mask_write 0XF8006038 0x00001FC3 0x00000000
+ mask_write 0XF800603C 0x000FFFFF 0x00000777
+ mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+ mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+ mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+ mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+ mask_write 0XF8006058 0x0001FFFF 0x00000101
+ mask_write 0XF800605C 0x0000FFFF 0x00005003
+ mask_write 0XF8006060 0x000017FF 0x0000003E
+ mask_write 0XF8006064 0x00021FE0 0x00020000
+ mask_write 0XF8006068 0x03FFFFFF 0x00284141
+ mask_write 0XF800606C 0x0000FFFF 0x00001610
+ mask_write 0XF8006078 0x03FFFFFF 0x00466111
+ mask_write 0XF800607C 0x000FFFFF 0x00032222
+ mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+ mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+ mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+ mask_write 0XF80060AC 0x000001FF 0x000001FE
+ mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+ mask_write 0XF80060B4 0x000007FF 0x00000200
+ mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+ mask_write 0XF80060C4 0x00000003 0x00000000
+ mask_write 0XF80060C8 0x000000FF 0x00000000
+ mask_write 0XF80060DC 0x00000001 0x00000000
+ mask_write 0XF80060F0 0x0000FFFF 0x00000000
+ mask_write 0XF80060F4 0x0000000F 0x00000008
+ mask_write 0XF8006114 0x000000FF 0x00000000
+ mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+ mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+ mask_write 0XF800612C 0x000FFFFF 0x00027000
+ mask_write 0XF8006130 0x000FFFFF 0x00027000
+ mask_write 0XF8006134 0x000FFFFF 0x00026C00
+ mask_write 0XF8006138 0x000FFFFF 0x00028800
+ mask_write 0XF8006140 0x000FFFFF 0x00000035
+ mask_write 0XF8006144 0x000FFFFF 0x00000035
+ mask_write 0XF8006148 0x000FFFFF 0x00000035
+ mask_write 0XF800614C 0x000FFFFF 0x00000035
+ mask_write 0XF8006154 0x000FFFFF 0x0000007A
+ mask_write 0XF8006158 0x000FFFFF 0x0000007A
+ mask_write 0XF800615C 0x000FFFFF 0x0000007C
+ mask_write 0XF8006160 0x000FFFFF 0x00000073
+ mask_write 0XF8006168 0x001FFFFF 0x000000F1
+ mask_write 0XF800616C 0x001FFFFF 0x000000F1
+ mask_write 0XF8006170 0x001FFFFF 0x000000F0
+ mask_write 0XF8006174 0x001FFFFF 0x000000F7
+ mask_write 0XF800617C 0x000FFFFF 0x000000BA
+ mask_write 0XF8006180 0x000FFFFF 0x000000BA
+ mask_write 0XF8006184 0x000FFFFF 0x000000BC
+ mask_write 0XF8006188 0x000FFFFF 0x000000B3
+ mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+ mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+ mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+ mask_write 0XF8006208 0x000F03FF 0x000803FF
+ mask_write 0XF800620C 0x000F03FF 0x000803FF
+ mask_write 0XF8006210 0x000F03FF 0x000803FF
+ mask_write 0XF8006214 0x000F03FF 0x000803FF
+ mask_write 0XF8006218 0x000F03FF 0x000003FF
+ mask_write 0XF800621C 0x000F03FF 0x000003FF
+ mask_write 0XF8006220 0x000F03FF 0x000003FF
+ mask_write 0XF8006224 0x000F03FF 0x000003FF
+ mask_write 0XF80062A8 0x00000FF7 0x00000000
+ mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+ mask_write 0XF80062B0 0x003FFFFF 0x00005125
+ mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+ mask_poll 0XF8000B74 0x00002000
+ mask_write 0XF8006000 0x0001FFFF 0x00000081
+ mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B40 0x00000FFF 0x00000600
+ mask_write 0XF8000B44 0x00000FFF 0x00000600
+ mask_write 0XF8000B48 0x00000FFF 0x00000672
+ mask_write 0XF8000B4C 0x00000FFF 0x00000672
+ mask_write 0XF8000B50 0x00000FFF 0x00000674
+ mask_write 0XF8000B54 0x00000FFF 0x00000674
+ mask_write 0XF8000B58 0x00000FFF 0x00000600
+ mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
+ mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B6C 0x00007FFF 0x00000260
+ mask_write 0XF8000B70 0x00000021 0x00000021
+ mask_write 0XF8000B70 0x00000021 0x00000020
+ mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+ mask_write 0XF8000700 0x00003FFF 0x00001600
+ mask_write 0XF8000704 0x00003FFF 0x00001602
+ mask_write 0XF8000708 0x00003FFF 0x00000602
+ mask_write 0XF800070C 0x00003FFF 0x00000602
+ mask_write 0XF8000710 0x00003FFF 0x00000602
+ mask_write 0XF8000714 0x00003FFF 0x00000602
+ mask_write 0XF8000718 0x00003FFF 0x00000602
+ mask_write 0XF800071C 0x00003FFF 0x00000600
+ mask_write 0XF8000720 0x00003FFF 0x00000602
+ mask_write 0XF8000724 0x00003FFF 0x00001600
+ mask_write 0XF8000728 0x00003FFF 0x00001600
+ mask_write 0XF800072C 0x00003FFF 0x00001600
+ mask_write 0XF8000730 0x00003FFF 0x00001600
+ mask_write 0XF8000734 0x00003FFF 0x00001600
+ mask_write 0XF8000738 0x00003FFF 0x00001600
+ mask_write 0XF800073C 0x00003FFF 0x00001600
+ mask_write 0XF8000740 0x00003FFF 0x00001302
+ mask_write 0XF8000744 0x00003FFF 0x00001302
+ mask_write 0XF8000748 0x00003FFF 0x00001302
+ mask_write 0XF800074C 0x00003FFF 0x00001302
+ mask_write 0XF8000750 0x00003FFF 0x00001302
+ mask_write 0XF8000754 0x00003FFF 0x00001302
+ mask_write 0XF8000758 0x00003FFF 0x00001303
+ mask_write 0XF800075C 0x00003FFF 0x00001303
+ mask_write 0XF8000760 0x00003FFF 0x00001303
+ mask_write 0XF8000764 0x00003FFF 0x00001303
+ mask_write 0XF8000768 0x00003FFF 0x00001303
+ mask_write 0XF800076C 0x00003FFF 0x00001303
+ mask_write 0XF8000770 0x00003FFF 0x00001304
+ mask_write 0XF8000774 0x00003FFF 0x00001305
+ mask_write 0XF8000778 0x00003FFF 0x00001304
+ mask_write 0XF800077C 0x00003FFF 0x00001305
+ mask_write 0XF8000780 0x00003FFF 0x00001304
+ mask_write 0XF8000784 0x00003FFF 0x00001304
+ mask_write 0XF8000788 0x00003FFF 0x00001304
+ mask_write 0XF800078C 0x00003FFF 0x00001304
+ mask_write 0XF8000790 0x00003FFF 0x00001305
+ mask_write 0XF8000794 0x00003FFF 0x00001304
+ mask_write 0XF8000798 0x00003FFF 0x00001304
+ mask_write 0XF800079C 0x00003FFF 0x00001304
+ mask_write 0XF80007A0 0x00003FFF 0x00001280
+ mask_write 0XF80007A4 0x00003FFF 0x00001280
+ mask_write 0XF80007A8 0x00003FFF 0x00001280
+ mask_write 0XF80007AC 0x00003FFF 0x00001280
+ mask_write 0XF80007B0 0x00003FFF 0x00001280
+ mask_write 0XF80007B4 0x00003FFF 0x00001280
+ mask_write 0XF80007B8 0x00003FFF 0x00001200
+ mask_write 0XF80007BC 0x00003F01 0x00001201
+ mask_write 0XF80007C0 0x00003FFF 0x00001200
+ mask_write 0XF80007C4 0x00003FFF 0x00001200
+ mask_write 0XF80007C8 0x00003FFF 0x00001200
+ mask_write 0XF80007CC 0x00003FFF 0x00001200
+ mask_write 0XF80007D0 0x00003FFF 0x00001280
+ mask_write 0XF80007D4 0x00003FFF 0x00001280
+ mask_write 0XF8000830 0x003F003F 0x002F0037
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B48 0x00000180 0x00000180
+ mask_write 0XF8000B4C 0x00000180 0x00000180
+ mask_write 0XF8000B50 0x00000180 0x00000180
+ mask_write 0XF8000B54 0x00000180 0x00000180
+ mwr -force 0XF8000004 0x0000767B
+ mask_write 0XE0001034 0x000000FF 0x00000006
+ mask_write 0XE0001018 0x0000FFFF 0x0000007C
+ mask_write 0XE0001000 0x000001FF 0x00000017
+ mask_write 0XE0001004 0x00000FFF 0x00000020
+ mask_write 0XE0000034 0x000000FF 0x00000006
+ mask_write 0XE0000018 0x0000FFFF 0x0000007C
+ mask_write 0XE0000000 0x000001FF 0x00000017
+ mask_write 0XE0000004 0x00000FFF 0x00000020
+ mask_write 0XE000D000 0x00080000 0x00080000
+ mask_write 0XF8007000 0x20000000 0x00000000
+ mask_write 0XE000A244 0x003FFFFF 0x00004000
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+ mask_write 0XE000A248 0x003FFFFF 0x00004000
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+ mask_delay 0XF8F00200 1
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_2_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000900 0x0000000F 0x0000000F
+ mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+ mwr -force 0XF8898FB0 0xC5ACCE55
+ mwr -force 0XF8899FB0 0xC5ACCE55
+ mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000110 0x003FFFF0 0x000FA220
+ mask_write 0XF8000100 0x0007F000 0x00028000
+ mask_write 0XF8000100 0x00000010 0x00000010
+ mask_write 0XF8000100 0x00000001 0x00000001
+ mask_write 0XF8000100 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000001
+ mask_write 0XF8000100 0x00000010 0x00000000
+ mask_write 0XF8000120 0x1F003F30 0x1F000200
+ mask_write 0XF8000114 0x003FFFF0 0x0012C220
+ mask_write 0XF8000104 0x0007F000 0x00020000
+ mask_write 0XF8000104 0x00000010 0x00000010
+ mask_write 0XF8000104 0x00000001 0x00000001
+ mask_write 0XF8000104 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000002
+ mask_write 0XF8000104 0x00000010 0x00000000
+ mask_write 0XF8000124 0xFFF00003 0x0C200003
+ mask_write 0XF8000118 0x003FFFF0 0x001452C0
+ mask_write 0XF8000108 0x0007F000 0x0001E000
+ mask_write 0XF8000108 0x00000010 0x00000010
+ mask_write 0XF8000108 0x00000001 0x00000001
+ mask_write 0XF8000108 0x00000001 0x00000000
+ mask_poll 0XF800010C 0x00000004
+ mask_write 0XF8000108 0x00000010 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000128 0x03F03F01 0x00700F01
+ mask_write 0XF8000138 0x00000011 0x00000001
+ mask_write 0XF8000140 0x03F03F71 0x00100801
+ mask_write 0XF800014C 0x00003F31 0x00000501
+ mask_write 0XF8000150 0x00003F33 0x00001401
+ mask_write 0XF8000154 0x00003F33 0x00000A03
+ mask_write 0XF8000168 0x00003F31 0x00000501
+ mask_write 0XF8000170 0x03F03F30 0x00200500
+ mask_write 0XF80001C4 0x00000001 0x00000001
+ mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+ mask_write 0XF8006000 0x0001FFFF 0x00000080
+ mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+ mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+ mask_write 0XF800600C 0x03FFFFFF 0x02001001
+ mask_write 0XF8006010 0x03FFFFFF 0x00014001
+ mask_write 0XF8006014 0x001FFFFF 0x0004285B
+ mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+ mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+ mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+ mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+ mask_write 0XF8006028 0x00003FFF 0x00002007
+ mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+ mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+ mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+ mask_write 0XF8006038 0x00001FC3 0x00000000
+ mask_write 0XF800603C 0x000FFFFF 0x00000777
+ mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+ mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+ mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+ mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+ mask_write 0XF8006058 0x0001FFFF 0x00000101
+ mask_write 0XF800605C 0x0000FFFF 0x00005003
+ mask_write 0XF8006060 0x000017FF 0x0000003E
+ mask_write 0XF8006064 0x00021FE0 0x00020000
+ mask_write 0XF8006068 0x03FFFFFF 0x00284141
+ mask_write 0XF800606C 0x0000FFFF 0x00001610
+ mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+ mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+ mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+ mask_write 0XF80060AC 0x000001FF 0x000001FE
+ mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+ mask_write 0XF80060B4 0x000007FF 0x00000200
+ mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+ mask_write 0XF80060C4 0x00000003 0x00000000
+ mask_write 0XF80060C8 0x000000FF 0x00000000
+ mask_write 0XF80060DC 0x00000001 0x00000000
+ mask_write 0XF80060F0 0x0000FFFF 0x00000000
+ mask_write 0XF80060F4 0x0000000F 0x00000008
+ mask_write 0XF8006114 0x000000FF 0x00000000
+ mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+ mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+ mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+ mask_write 0XF800612C 0x000FFFFF 0x00027000
+ mask_write 0XF8006130 0x000FFFFF 0x00027000
+ mask_write 0XF8006134 0x000FFFFF 0x00026C00
+ mask_write 0XF8006138 0x000FFFFF 0x00028800
+ mask_write 0XF8006140 0x000FFFFF 0x00000035
+ mask_write 0XF8006144 0x000FFFFF 0x00000035
+ mask_write 0XF8006148 0x000FFFFF 0x00000035
+ mask_write 0XF800614C 0x000FFFFF 0x00000035
+ mask_write 0XF8006154 0x000FFFFF 0x0000007A
+ mask_write 0XF8006158 0x000FFFFF 0x0000007A
+ mask_write 0XF800615C 0x000FFFFF 0x0000007C
+ mask_write 0XF8006160 0x000FFFFF 0x00000073
+ mask_write 0XF8006168 0x001FFFFF 0x000000F1
+ mask_write 0XF800616C 0x001FFFFF 0x000000F1
+ mask_write 0XF8006170 0x001FFFFF 0x000000F0
+ mask_write 0XF8006174 0x001FFFFF 0x000000F7
+ mask_write 0XF800617C 0x000FFFFF 0x000000BA
+ mask_write 0XF8006180 0x000FFFFF 0x000000BA
+ mask_write 0XF8006184 0x000FFFFF 0x000000BC
+ mask_write 0XF8006188 0x000FFFFF 0x000000B3
+ mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+ mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+ mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+ mask_write 0XF8006208 0x000F03FF 0x000803FF
+ mask_write 0XF800620C 0x000F03FF 0x000803FF
+ mask_write 0XF8006210 0x000F03FF 0x000803FF
+ mask_write 0XF8006214 0x000F03FF 0x000803FF
+ mask_write 0XF8006218 0x000F03FF 0x000003FF
+ mask_write 0XF800621C 0x000F03FF 0x000003FF
+ mask_write 0XF8006220 0x000F03FF 0x000003FF
+ mask_write 0XF8006224 0x000F03FF 0x000003FF
+ mask_write 0XF80062A8 0x00000FF7 0x00000000
+ mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+ mask_write 0XF80062B0 0x003FFFFF 0x00005125
+ mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+ mask_poll 0XF8000B74 0x00002000
+ mask_write 0XF8006000 0x0001FFFF 0x00000081
+ mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B40 0x00000FFF 0x00000600
+ mask_write 0XF8000B44 0x00000FFF 0x00000600
+ mask_write 0XF8000B48 0x00000FFF 0x00000672
+ mask_write 0XF8000B4C 0x00000FFF 0x00000672
+ mask_write 0XF8000B50 0x00000FFF 0x00000674
+ mask_write 0XF8000B54 0x00000FFF 0x00000674
+ mask_write 0XF8000B58 0x00000FFF 0x00000600
+ mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
+ mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
+ mask_write 0XF8000B6C 0x000073FF 0x00000260
+ mask_write 0XF8000B70 0x00000021 0x00000021
+ mask_write 0XF8000B70 0x00000021 0x00000020
+ mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+ mask_write 0XF8000700 0x00003FFF 0x00001600
+ mask_write 0XF8000704 0x00003FFF 0x00001602
+ mask_write 0XF8000708 0x00003FFF 0x00000602
+ mask_write 0XF800070C 0x00003FFF 0x00000602
+ mask_write 0XF8000710 0x00003FFF 0x00000602
+ mask_write 0XF8000714 0x00003FFF 0x00000602
+ mask_write 0XF8000718 0x00003FFF 0x00000602
+ mask_write 0XF800071C 0x00003FFF 0x00000600
+ mask_write 0XF8000720 0x00003FFF 0x00000602
+ mask_write 0XF8000724 0x00003FFF 0x00001600
+ mask_write 0XF8000728 0x00003FFF 0x00001600
+ mask_write 0XF800072C 0x00003FFF 0x00001600
+ mask_write 0XF8000730 0x00003FFF 0x00001600
+ mask_write 0XF8000734 0x00003FFF 0x00001600
+ mask_write 0XF8000738 0x00003FFF 0x00001600
+ mask_write 0XF800073C 0x00003FFF 0x00001600
+ mask_write 0XF8000740 0x00003FFF 0x00001302
+ mask_write 0XF8000744 0x00003FFF 0x00001302
+ mask_write 0XF8000748 0x00003FFF 0x00001302
+ mask_write 0XF800074C 0x00003FFF 0x00001302
+ mask_write 0XF8000750 0x00003FFF 0x00001302
+ mask_write 0XF8000754 0x00003FFF 0x00001302
+ mask_write 0XF8000758 0x00003FFF 0x00001303
+ mask_write 0XF800075C 0x00003FFF 0x00001303
+ mask_write 0XF8000760 0x00003FFF 0x00001303
+ mask_write 0XF8000764 0x00003FFF 0x00001303
+ mask_write 0XF8000768 0x00003FFF 0x00001303
+ mask_write 0XF800076C 0x00003FFF 0x00001303
+ mask_write 0XF8000770 0x00003FFF 0x00001304
+ mask_write 0XF8000774 0x00003FFF 0x00001305
+ mask_write 0XF8000778 0x00003FFF 0x00001304
+ mask_write 0XF800077C 0x00003FFF 0x00001305
+ mask_write 0XF8000780 0x00003FFF 0x00001304
+ mask_write 0XF8000784 0x00003FFF 0x00001304
+ mask_write 0XF8000788 0x00003FFF 0x00001304
+ mask_write 0XF800078C 0x00003FFF 0x00001304
+ mask_write 0XF8000790 0x00003FFF 0x00001305
+ mask_write 0XF8000794 0x00003FFF 0x00001304
+ mask_write 0XF8000798 0x00003FFF 0x00001304
+ mask_write 0XF800079C 0x00003FFF 0x00001304
+ mask_write 0XF80007A0 0x00003FFF 0x00001280
+ mask_write 0XF80007A4 0x00003FFF 0x00001280
+ mask_write 0XF80007A8 0x00003FFF 0x00001280
+ mask_write 0XF80007AC 0x00003FFF 0x00001280
+ mask_write 0XF80007B0 0x00003FFF 0x00001280
+ mask_write 0XF80007B4 0x00003FFF 0x00001280
+ mask_write 0XF80007B8 0x00003FFF 0x00001200
+ mask_write 0XF80007BC 0x00003F01 0x00001201
+ mask_write 0XF80007C0 0x00003FFF 0x00001200
+ mask_write 0XF80007C4 0x00003FFF 0x00001200
+ mask_write 0XF80007C8 0x00003FFF 0x00001200
+ mask_write 0XF80007CC 0x00003FFF 0x00001200
+ mask_write 0XF80007D0 0x00003FFF 0x00001280
+ mask_write 0XF80007D4 0x00003FFF 0x00001280
+ mask_write 0XF8000830 0x003F003F 0x002F0037
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000B48 0x00000180 0x00000180
+ mask_write 0XF8000B4C 0x00000180 0x00000180
+ mask_write 0XF8000B50 0x00000180 0x00000180
+ mask_write 0XF8000B54 0x00000180 0x00000180
+ mwr -force 0XF8000004 0x0000767B
+ mask_write 0XE0001034 0x000000FF 0x00000006
+ mask_write 0XE0001018 0x0000FFFF 0x0000007C
+ mask_write 0XE0001000 0x000001FF 0x00000017
+ mask_write 0XE0001004 0x00000FFF 0x00000020
+ mask_write 0XE0000034 0x000000FF 0x00000006
+ mask_write 0XE0000018 0x0000FFFF 0x0000007C
+ mask_write 0XE0000000 0x000001FF 0x00000017
+ mask_write 0XE0000004 0x00000FFF 0x00000020
+ mask_write 0XE000D000 0x00080000 0x00080000
+ mask_write 0XF8007000 0x20000000 0x00000000
+ mask_write 0XE000A244 0x003FFFFF 0x00004000
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+ mask_write 0XE000A248 0x003FFFFF 0x00004000
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+ mask_delay 0XF8F00200 1
+ mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_1_0 {} {
+ mwr -force 0XF8000008 0x0000DF0D
+ mask_write 0XF8000900 0x0000000F 0x0000000F
+ mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+ mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+ mwr -force 0XF8898FB0 0xC5ACCE55
+ mwr -force 0XF8899FB0 0xC5ACCE55
+ mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ 667000000
+
+
+
+proc mask_poll { addr mask } {
+ set count 1
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval & $mask}]
+ while { $maskedval == 0 } {
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval & $mask}]
+ set count [ expr { $count + 1 } ]
+ if { $count == 100000000 } {
+ puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+ break
+ }
+ }
+}
+
+
+
+proc mask_delay { addr val } {
+ set delay [ get_number_of_cycles_for_delay $val ]
+ perf_reset_and_start_timer
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval < $delay}]
+ while { $maskedval == 1 } {
+ set curval "0x[string range [mrd $addr] end-8 end]"
+ set maskedval [expr {$curval < $delay}]
+ }
+ perf_reset_clock
+}
+
+proc ps_version { } {
+ set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+ set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+ return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ variable PCW_SILICON_VER_1_0
+ variable PCW_SILICON_VER_2_0
+ variable PCW_SILICON_VER_3_0
+ set sil_ver [ps_version]
+
+ if { $sil_ver == $PCW_SILICON_VER_1_0} {
+ ps7_post_config_1_0
+ } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+ ps7_post_config_2_0
+ } else {
+ ps7_post_config_3_0
+ }
+ configparams force-mem-accesses $saved_mode
+}
+
+proc ps7_debug {} {
+ variable PCW_SILICON_VER_1_0
+ variable PCW_SILICON_VER_2_0
+ variable PCW_SILICON_VER_3_0
+ set sil_ver [ps_version]
+
+ if { $sil_ver == $PCW_SILICON_VER_1_0} {
+ ps7_debug_1_0
+ } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+ ps7_debug_2_0
+ } else {
+ ps7_debug_3_0
+ }
+}
+proc ps7_init {} {
+ variable PCW_SILICON_VER_1_0
+ variable PCW_SILICON_VER_2_0
+ variable PCW_SILICON_VER_3_0
+ set sil_ver [ps_version]
+ if { $sil_ver == $PCW_SILICON_VER_1_0} {
+ ps7_mio_init_data_1_0
+ ps7_pll_init_data_1_0
+ ps7_clock_init_data_1_0
+ ps7_ddr_init_data_1_0
+ ps7_peripherals_init_data_1_0
+ #puts "PCW Silicon Version : 1.0"
+ } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+ ps7_mio_init_data_2_0
+ ps7_pll_init_data_2_0
+ ps7_clock_init_data_2_0
+ ps7_ddr_init_data_2_0
+ ps7_peripherals_init_data_2_0
+ #puts "PCW Silicon Version : 2.0"
+ } else {
+ ps7_mio_init_data_3_0
+ ps7_pll_init_data_3_0
+ ps7_clock_init_data_3_0
+ ps7_ddr_init_data_3_0
+ ps7_peripherals_init_data_3_0
+ #puts "PCW Silicon Version : 3.0"
+ }
+}
+
+
+# For delay calculation using global timer
+
+# start timer
+ proc perf_start_clock { } {
+
+ #writing SCU_GLOBAL_TIMER_CONTROL register
+
+ mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs
+ proc perf_reset_clock { } {
+ perf_disable_clock
+ mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+ mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+ # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ variable APU_FREQ
+ return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer
+proc perf_disable_clock {} {
+ mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
+}
+
+proc perf_reset_and_start_timer {} {
+ perf_reset_clock
+ perf_start_clock
+}
+
+
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init_gpl.c b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init_gpl.c
new file mode 100644
index 0000000000000000000000000000000000000000..7a8375cbeeedc630e98500e66d7a443556eff46a
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init_gpl.c
@@ -0,0 +1,12510 @@
+/******************************************************************************
+* (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000154[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF8000154[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF800612C[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF8006130[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9b
+ // .. .. ==> 0XF8006134[19:10] = 0x0000009BU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa2
+ // .. .. ==> 0XF8006138[19:10] = 0x000000A2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x73
+ // .. .. ==> 0XF8006160[9:0] = 0x00000073U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf0
+ // .. .. ==> 0XF8006170[10:0] = 0x000000F0U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf7
+ // .. .. ==> 0XF8006174[10:0] = 0x000000F7U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B5C[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B5C[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B60[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B60[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B64[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B64[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
+ // .. reserved_DRIVE_P = 0x68
+ // .. ==> 0XF8000B68[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. reserved_DRIVE_N = 0x0
+ // .. ==> 0XF8000B68[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000740[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000740[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000744[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000744[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000748[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000748[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800074C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800074C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000750[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000750[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000754[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000754[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000758[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000758[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800075C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800075C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000760[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000760[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000764[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000764[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000768[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000768[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800076C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800076C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000770[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000770[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000774[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000774[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000778[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000778[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800077C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800077C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000780[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000780[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000784[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000784[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000788[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000788[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800078C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800078C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000790[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000790[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000794[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000794[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000798[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000798[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800079C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800079C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007AC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007BC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+ // .. SDIO0_WP_SEL = 55
+ // .. ==> 0XF8000830[5:0] = 0x00000037U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
+ // .. SDIO0_CD_SEL = 47
+ // .. ==> 0XF8000830[21:16] = 0x0000002FU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x7c
+ // .. ==> 0XE0001018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. BDIV = 0x6
+ // .. ==> 0XE0000034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x7c
+ // .. ==> 0XE0000018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
+ // ..
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0000000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0000000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0000000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0000000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0000000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0000000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0000000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0000000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0000000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0000004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0000004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0000004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0000004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0000004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. .. START: AFI2 SECURE REGISTER
+ // .. .. FINISH: AFI2 SECURE REGISTER
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000154[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF8000154[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF800612C[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF8006130[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9b
+ // .. .. ==> 0XF8006134[19:10] = 0x0000009BU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa2
+ // .. .. ==> 0XF8006138[19:10] = 0x000000A2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x73
+ // .. .. ==> 0XF8006160[9:0] = 0x00000073U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf0
+ // .. .. ==> 0XF8006170[10:0] = 0x000000F0U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf7
+ // .. .. ==> 0XF8006174[10:0] = 0x000000F7U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B5C[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B5C[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B60[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B60[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B64[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B64[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B68[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B68[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000740[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000740[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000744[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000744[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000748[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000748[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800074C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800074C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000750[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000750[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000754[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000754[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000758[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000758[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800075C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800075C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000760[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000760[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000764[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000764[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000768[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000768[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800076C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800076C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000770[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000770[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000774[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000774[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000778[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000778[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800077C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800077C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000780[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000780[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000784[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000784[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000788[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000788[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800078C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800078C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000790[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000790[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000794[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000794[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000798[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000798[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800079C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800079C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007AC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007BC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+ // .. SDIO0_WP_SEL = 55
+ // .. ==> 0XF8000830[5:0] = 0x00000037U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
+ // .. SDIO0_CD_SEL = 47
+ // .. ==> 0XF8000830[21:16] = 0x0000002FU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x7c
+ // .. ==> 0XE0001018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. BDIV = 0x6
+ // .. ==> 0XE0000034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x7c
+ // .. ==> 0XE0000018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
+ // ..
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0000000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0000000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0000000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0000000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0000000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0000000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0000000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0000000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0000000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0000004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0000004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0000004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0000004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0000004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0000004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0000004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0xf
+ // .. ==> 0XF8000128[13:8] = 0x0000000FU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U
+ // .. DIVISOR1 = 0x7
+ // .. ==> 0XF8000128[25:20] = 0x00000007U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00700000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000154[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF8000154[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0x5
+ // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x5
+ // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // .. .. DIVISOR1 = 0x2
+ // .. .. ==> 0XF8000170[25:20] = 0x00000002U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. .. SDI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
+ // .. .. ==> 0XF8006004[11:0] = 0x00000082U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0xa1
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A1U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU),
+ // .. .. reg_ddrc_wr2pre = 0x13
+ // .. .. ==> 0XF8006018[4:0] = 0x00000013U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xf
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U
+ // .. .. reg_ddrc_t_xp = 0x5
+ // .. .. ==> 0XF800601C[19:15] = 0x00000005U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x5
+ // .. .. ==> 0XF800601C[27:23] = 0x00000005U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0xb30
+ // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+ // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF800612C[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9c
+ // .. .. ==> 0XF8006130[19:10] = 0x0000009CU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x9b
+ // .. .. ==> 0XF8006134[19:10] = 0x0000009BU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa2
+ // .. .. ==> 0XF8006138[19:10] = 0x000000A2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x73
+ // .. .. ==> 0XF8006160[9:0] = 0x00000073U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf1
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F1U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf0
+ // .. .. ==> 0XF8006170[10:0] = 0x000000F0U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf7
+ // .. .. ==> 0XF8006174[10:0] = 0x000000F7U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xba
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B5C[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B5C[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B60[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B60[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B64[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B64[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
+ // .. DRIVE_P = 0x68
+ // .. ==> 0XF8000B68[6:0] = 0x00000068U
+ // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
+ // .. DRIVE_N = 0x0
+ // .. ==> 0XF8000B68[13:7] = 0x00000000U
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
+ // .. VREF_INT_EN = 0x0
+ // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
+ // .. VREF_EXT_EN = 0x3
+ // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000740[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000740[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000744[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000744[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000748[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000748[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800074C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800074C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000750[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000750[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000754[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000754[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000758[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000758[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800075C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800075C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000760[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000760[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000764[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000764[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000768[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000768[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800076C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800076C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000770[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000770[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000774[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000774[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000778[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000778[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800077C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800077C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000780[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000780[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000784[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000784[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000788[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000788[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800078C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800078C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000790[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000790[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000794[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000794[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000798[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000798[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800079C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800079C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007A8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007AC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007BC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D0[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007D4[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+ // .. SDIO0_WP_SEL = 55
+ // .. ==> 0XF8000830[5:0] = 0x00000037U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
+ // .. SDIO0_CD_SEL = 47
+ // .. ==> 0XF8000830[21:16] = 0x0000002FU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x7c
+ // .. ==> 0XE0001018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. BDIV = 0x6
+ // .. ==> 0XE0000034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x7c
+ // .. ==> 0XE0000018[15:0] = 0x0000007CU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
+ // ..
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0000000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0000000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0000000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0000000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0000000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0000000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0000000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0000000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0000000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0000004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0000004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0000004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0000004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0000004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0000004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0000004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+
+
+
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init_gpl.h b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init_gpl.h
new file mode 100644
index 0000000000000000000000000000000000000000..e7708e0bf3a766d5738c7a406432b8ad17131cd2
--- /dev/null
+++ b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/ps7_init_gpl.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158730
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 100000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 10000000
+#define FPGA2_FREQ 10000000
+#define FPGA3_FREQ 10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/system.hdf b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/system.hdf
new file mode 100644
index 0000000000000000000000000000000000000000..45c8988c37a8163f438ae440a25556a03b75d41a
Binary files /dev/null and b/quad/xsdk_workspace/design_1_wrapper_hw_platform_0/system.hdf differ
diff --git a/quad/xsdk_workspace/real_quad/.cproject b/quad/xsdk_workspace/real_quad/.cproject
index 57f76856b0208ef5824dd1bc3f413b84b8f3c3cf..dca3e694a17589aa8b722b172effeb033bac8395 100644
--- a/quad/xsdk_workspace/real_quad/.cproject
+++ b/quad/xsdk_workspace/real_quad/.cproject
@@ -1,170 +1,155 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="xilinx.gnu.arm.exe.debug.980189137">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.980189137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <cconfiguration id="xilinx.gnu.armv7.exe.debug.1772200488">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.1772200488" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.980189137" name="Debug" parent="xilinx.gnu.arm.exe.debug">
- <folderInfo id="xilinx.gnu.arm.exe.debug.980189137." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.arm.exe.debug.toolchain.1195127676" name="Xilinx ARM GNU Toolchain" resourceTypeBasedDiscovery="true" superClass="xilinx.gnu.arm.exe.debug.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.2072264921" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
- <builder buildPath="${workspace_loc:/modular_quad_pid}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.debug.2124876787" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.toolchain.builder.debug"/>
- <tool id="xilinx.gnu.arm.c.toolchain.assembler.debug.192056667" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.debug">
- <inputType id="xilinx.gnu.assembler.input.532832448" superClass="xilinx.gnu.assembler.input"/>
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.debug.1772200488" name="Debug" parent="xilinx.gnu.armv7.exe.debug" prebuildStep="a9-linaro-pre-build-step">
+ <folderInfo id="xilinx.gnu.armv7.exe.debug.1772200488." name="/" resourcePath="">
+ <toolChain id="xilinx.gnu.armv7.exe.debug.toolchain.579163359" name="Xilinx ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.debug.toolchain">
+ <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.debug.93655910" isAbstract="false" name="Debug Platform" superClass="xilinx.armv7.target.gnu.base.debug"/>
+ <builder buildPath="${workspace_loc:/real_quad}/Debug" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.debug.321024823" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.armv7.toolchain.builder.debug"/>
+ <tool id="xilinx.gnu.armv7.c.toolchain.assembler.debug.924143018" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.debug">
+ <inputType id="xilinx.gnu.assembler.input.510877078" superClass="xilinx.gnu.assembler.input"/>
</tool>
- <tool id="xilinx.gnu.arm.c.toolchain.compiler.debug.177835003" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1900496019" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" value="gnu.c.optimization.level.none" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.1207856754" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.2123463819" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
+ <tool id="xilinx.gnu.armv7.c.toolchain.compiler.debug.2077189270" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.debug">
+ <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1004479508" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.option.debugging.level.4220453" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1415626566" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
</option>
- <option id="xilinx.gnu.compiler.symbols.defined.1696008720" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined"/>
- <option id="xilinx.gnu.compiler.dircategory.includes.1211006365" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/commands}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/computation_graph}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/graph_blocks}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/quad_app}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/queue}""/>
+ <option id="xilinx.gnu.compiler.misc.other.1076369915" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
+ <option id="xilinx.gnu.compiler.dircategory.includes.1497517650" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/commands}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/quad_app}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/computation_graph}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/graph_blocks}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/queue}""/>
</option>
- <inputType id="xilinx.gnu.arm.c.compiler.input.909725989" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
+ <inputType id="xilinx.gnu.armv7.c.compiler.input.782488544" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.debug.1470236349" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.9972228" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.595503730" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.53367111" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
+ <tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.debug.2034581493" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.debug">
+ <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1337168309" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.option.debugging.level.1948866134" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1933897978" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
</option>
</tool>
- <tool id="xilinx.gnu.arm.toolchain.archiver.585254344" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
- <tool id="xilinx.gnu.arm.c.toolchain.linker.debug.360488201" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.47881921" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.armv7.toolchain.archiver.986856462" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
+ <tool id="xilinx.gnu.armv7.c.toolchain.linker.debug.1890272868" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.debug">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.438175492" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.349145084" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.425180926" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.972374298" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.1025826490" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
+ <option id="xilinx.gnu.c.linker.option.lscript.672115765" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.link.option.ldflags.1808887684" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
+ <option id="xilinx.gnu.c.link.option.libs.1475984760" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
<listOptionValue builtIn="false" value="m"/>
</option>
- <option id="xilinx.gnu.c.link.option.paths.1462160427" name="Library search path (-L)" superClass="xilinx.gnu.c.link.option.paths"/>
- <inputType id="xilinx.gnu.linker.input.777404607" superClass="xilinx.gnu.linker.input">
+ <inputType id="xilinx.gnu.linker.input.1557255427" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.634888687" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
+ <inputType id="xilinx.gnu.linker.input.lscript.194604372" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.linker.debug.1921379343" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1819794269" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.armv7.cxx.toolchain.linker.debug.1326301381" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.debug">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.2009285661" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1650054208" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1470803686" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.1506564015" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.linker.option.lscript.1123126820" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
- <tool id="xilinx.gnu.arm.size.debug.923967150" name="ARM Print Size" superClass="xilinx.gnu.arm.size.debug"/>
+ <tool id="xilinx.gnu.armv7.size.debug.765770363" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.debug"/>
</toolChain>
</folderInfo>
<sourceEntries>
- <entry excluding="gen_diagram|test" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+ <entry excluding="ext/gen_diagram|ext/computation_graph/test|ext/quad_app/test|ext/queue/test|ext/test|ext/virt_quad" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
- <cconfiguration id="xilinx.gnu.arm.exe.release.255973624">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.release.255973624" moduleId="org.eclipse.cdt.core.settings" name="Release">
+ <cconfiguration id="xilinx.gnu.armv7.exe.release.1403478894">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.release.1403478894" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.release.255973624" name="Release" parent="xilinx.gnu.arm.exe.release">
- <folderInfo id="xilinx.gnu.arm.exe.release.255973624." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.arm.exe.release.toolchain.1375808537" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.release.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.release.230721338" isAbstract="false" name="Release Platform" superClass="xilinx.arm.target.gnu.base.release"/>
- <builder buildPath="${workspace_loc:/modular_quad_pid}/Release" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.release.122813927" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.toolchain.builder.release"/>
- <tool id="xilinx.gnu.arm.c.toolchain.assembler.release.1899854338" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.release">
- <inputType id="xilinx.gnu.assembler.input.756511915" superClass="xilinx.gnu.assembler.input"/>
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.release.1403478894" name="Release" parent="xilinx.gnu.armv7.exe.release" prebuildStep="a9-linaro-pre-build-step">
+ <folderInfo id="xilinx.gnu.armv7.exe.release.1403478894." name="/" resourcePath="">
+ <toolChain id="xilinx.gnu.armv7.exe.release.toolchain.1000121308" name="Xilinx ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.release.toolchain">
+ <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.release.192990091" isAbstract="false" name="Release Platform" superClass="xilinx.armv7.target.gnu.base.release"/>
+ <builder buildPath="${workspace_loc:/real_quad}/Release" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.release.179925932" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.armv7.toolchain.builder.release"/>
+ <tool id="xilinx.gnu.armv7.c.toolchain.assembler.release.27160032" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.release">
+ <inputType id="xilinx.gnu.assembler.input.73289996" superClass="xilinx.gnu.assembler.input"/>
</tool>
- <tool id="xilinx.gnu.arm.c.toolchain.compiler.release.85270120" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.release">
- <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.515686013" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.1121150517" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.687694973" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- </option>
- <option id="xilinx.gnu.compiler.symbols.defined.1562495938" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined" valueType="definedSymbols">
- <listOptionValue builtIn="false" value="NDEBUG=1"/>
- </option>
- <option id="xilinx.gnu.compiler.dircategory.includes.1873624761" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
+ <tool id="xilinx.gnu.armv7.c.toolchain.compiler.release.220030068" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.release">
+ <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1347510809" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.option.debugging.level.691696253" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1764413319" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/computation_graph}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/quad_app}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/queue}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/commands}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/real_quad/ext/graph_blocks}""/>
</option>
- <inputType id="xilinx.gnu.arm.c.compiler.input.846429887" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
+ <option id="xilinx.gnu.compiler.misc.other.1618899128" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
+ <inputType id="xilinx.gnu.armv7.c.compiler.input.1475444118" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.release.1846278293" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.release">
- <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1613253262" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.1485305325" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.2144106422" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
+ <tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.release.1387654150" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.release">
+ <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.338353934" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.option.debugging.level.1267507029" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.inferred.swplatform.includes.2012495119" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
</option>
</tool>
- <tool id="xilinx.gnu.arm.toolchain.archiver.86822110" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
- <tool id="xilinx.gnu.arm.c.toolchain.linker.release.264708896" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.444912795" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.armv7.toolchain.archiver.1600317418" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
+ <tool id="xilinx.gnu.armv7.c.toolchain.linker.release.1289301806" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.release">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1086929331" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1169214283" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1585611310" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.1266246445" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.962400757" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
- <listOptionValue builtIn="false" value="m"/>
- </option>
- <inputType id="xilinx.gnu.linker.input.1933167678" superClass="xilinx.gnu.linker.input">
+ <option id="xilinx.gnu.c.linker.option.lscript.27294522" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.link.option.ldflags.411346456" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
+ <inputType id="xilinx.gnu.linker.input.628141883" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.574206172" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
+ <inputType id="xilinx.gnu.linker.input.lscript.1819729905" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.linker.release.1512126497" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1491656562" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.armv7.cxx.toolchain.linker.release.510017234" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.release">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.269044543" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1353247076" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1110012772" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.486002186" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.linker.option.lscript.376019244" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
- <tool id="xilinx.gnu.arm.size.release.362029751" name="ARM Print Size" superClass="xilinx.gnu.arm.size.release"/>
+ <tool id="xilinx.gnu.armv7.size.release.929708576" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.release"/>
</toolChain>
</folderInfo>
<sourceEntries>
- <entry excluding="gen_diagram|test" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+ <entry excluding="ext/gen_diagram|ext/computation_graph/test|ext/quad_app/test|ext/queue/test|ext/test|ext/virt_quad" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
@@ -173,33 +158,22 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="modular_quad_pid.xilinx.gnu.arm.exe.832182557" name="Xilinx ARM Executable" projectType="xilinx.gnu.arm.exe"/>
+ <project id="real_quad.xilinx.gnu.armv7.exe.161152732" name="Xilinx ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
</storageModule>
- <storageModule moduleId="refreshScope" versionNumber="2">
- <configuration configurationName="Release">
- <resource resourceType="PROJECT" workspacePath="/modular_quad_pid"/>
- </configuration>
- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/modular_quad_pid"/>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.980189137;xilinx.gnu.arm.exe.debug.980189137.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.255973624;xilinx.gnu.arm.exe.release.255973624.;xilinx.gnu.arm.c.toolchain.compiler.release.85270120;xilinx.gnu.arm.c.compiler.input.846429887">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1772200488;xilinx.gnu.armv7.exe.debug.1772200488.">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.980189137">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1772200488;xilinx.gnu.armv7.exe.debug.1772200488.;xilinx.gnu.armv7.c.toolchain.compiler.debug.2077189270;xilinx.gnu.armv7.c.compiler.input.782488544">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.255973624;xilinx.gnu.arm.exe.release.255973624.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1403478894;xilinx.gnu.armv7.exe.release.1403478894.;xilinx.gnu.armv7.c.toolchain.compiler.release.220030068;xilinx.gnu.armv7.c.compiler.input.1475444118">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.980189137;xilinx.gnu.arm.exe.debug.980189137.;xilinx.gnu.arm.c.toolchain.compiler.debug.177835003;xilinx.gnu.arm.c.compiler.input.909725989">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1403478894;xilinx.gnu.armv7.exe.release.1403478894.">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
+ <storageModule moduleId="refreshScope"/>
</cproject>
diff --git a/quad/xsdk_workspace/real_quad/.gitignore b/quad/xsdk_workspace/real_quad/.gitignore
deleted file mode 100644
index 8274dfc9f03b3d46129a53606ca8ddd09c715e2f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/real_quad/.gitignore
+++ /dev/null
@@ -1,7 +0,0 @@
-*.o
-*.d
-*.elf
-*.size
-bootimage/
-Debug/
-Release/
\ No newline at end of file
diff --git a/quad/xsdk_workspace/real_quad/.project b/quad/xsdk_workspace/real_quad/.project
index 131ce10c1d2d7578c4e9a5753019bd1f0e84592e..8c5fc55b0fa08f8d3511bd1e9800388c318f828e 100644
--- a/quad/xsdk_workspace/real_quad/.project
+++ b/quad/xsdk_workspace/real_quad/.project
@@ -1,10 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>real_quad</name>
- <comment></comment>
+ <comment>Created by SDK v2018.3. system_bsp - ps7_cortexa9_0</comment>
<projects>
<project>system_bsp</project>
- <project>system_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
@@ -26,127 +25,9 @@
</natures>
<linkedResources>
<link>
- <name>ext/commands</name>
+ <name>ext</name>
<type>2</type>
- <location>/local/ucart/MicroCART/quad/src/commands</location>
- </link>
- <link>
- <name>ext/computation_graph</name>
- <type>2</type>
- <locationURI>QUAD_LOC/src/computation_graph</locationURI>
- </link>
- <link>
- <name>ext/graph_blocks</name>
- <type>2</type>
- <location>/local/ucart/MicroCART/quad/src/graph_blocks</location>
- </link>
- <link>
- <name>ext/quad_app</name>
- <type>2</type>
- <locationURI>QUAD_LOC/src/quad_app</locationURI>
- </link>
- <link>
- <name>ext/queue</name>
- <type>2</type>
- <locationURI>QUAD_LOC/src/queue</locationURI>
+ <location>/local/ucart/MicroCART/quad/src</location>
</link>
</linkedResources>
- <filteredResources>
- <filter>
- <id>1490997289335</id>
- <name></name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-obj</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/computation_graph</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/computation_graph</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/computation_graph</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/quad_app</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/quad_app</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/quad_app</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/queue</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/queue</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>0</id>
- <name>ext/queue</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- </filteredResources>
- <variableList>
- <variable>
- <name>QUAD_LOC</name>
- <value>$%7BPARENT-1-WORKSPACE_LOC%7D</value>
- </variable>
- </variableList>
</projectDescription>
diff --git a/quad/xsdk_workspace/real_quad/.settings/org.eclipse.cdt.codan.core.prefs b/quad/xsdk_workspace/real_quad/.settings/org.eclipse.cdt.codan.core.prefs
deleted file mode 100644
index 8e0550446a2bb045d01a9f8b73d47305f777665c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/real_quad/.settings/org.eclipse.cdt.codan.core.prefs
+++ /dev/null
@@ -1,34 +0,0 @@
-eclipse.preferences.version=1
-org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
-org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
-org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false}
-org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true}
-org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
-org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
-org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
-org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
diff --git a/quad/xsdk_workspace/real_quad/README.md b/quad/xsdk_workspace/real_quad/README.md
deleted file mode 100644
index 88089fe73a20d66069f58a28385db78db8ebed51..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/real_quad/README.md
+++ /dev/null
@@ -1,10 +0,0 @@
-# The Real Quad
-_It is real, because it flies._
-
-Welcome to the most lame README in MicroCART. Everything we are about to say
-has already been said elsewhere, including [Our quad folder README][1], [xsdk_workspace README][2], and [HOW_TO_USE_XSDK markdown][3].
-So we aren't saying it here. Hence, this README is pretty empty. Hence... lame.
-
-[1]: ../README.md
-[2]: ../../README.md
-[3]: ../../doc/how_to_use_XSDK.md
diff --git a/quad/xsdk_workspace/real_quad/ext/__CAUTION__.md b/quad/xsdk_workspace/real_quad/ext/__CAUTION__.md
deleted file mode 100644
index 6f7e2a00feb6d7083997b71389dcad6b36a0d616..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/real_quad/ext/__CAUTION__.md
+++ /dev/null
@@ -1,12 +0,0 @@
-****************************************
- Do not edit files in this directory!
-****************************************
-
-The fine print
-----
-
-Files in this directory are simlinked to external libraries. They exist here
-purely to help fascilitate the build process and permit debugging of those
-libraries within XSDK. Editing them here might build within XSDK, but it might
-break in its original context. Hence, don't edit these files within XSDK. Edit
-them within a workflow that uses the Makefile in the top-level quad folder.
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/Xilinx.spec b/quad/xsdk_workspace/real_quad/src/Xilinx.spec
similarity index 100%
rename from quad/xsdk_workspace_vivado/real_quad/src/Xilinx.spec
rename to quad/xsdk_workspace/real_quad/src/Xilinx.spec
diff --git a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo.h b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo.h
index 8f439cdf1872f1da5bcd0638d76a152f58c27f8f..5555a4adf8d527bd30b1d2837b3884e929f001d9 100644
--- a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo.h
+++ b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo.h
@@ -26,6 +26,59 @@
#define MAX_UART_BUFFER_SIZE 2048
+#define QUAD_NUM 1
+
+#if QUAD_NUM==0
+#define IMU_ACCX_SIGN -1
+#define IMU_ACCY_SIGN 1
+#define IMU_ACCZ_SIGN 1
+
+#define IMU_GYRX_SIGN -1
+#define IMU_GYRY_SIGN 1
+#define IMU_GYRZ_SIGN 1
+
+
+#define MOTOR_FRONTLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR
+#define MOTOR_FRONTRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR
+#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
+#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
+
+#define ACCEL_X_BIAS 0.08f
+#define ACCEL_Y_BIAS -0.057f
+#define ACCEL_Z_BIAS 0.0f
+
+#define GYRO_X_BIAS -0.006f
+#define GYRO_Y_BIAS 0.0545f
+#define GYRO_Z_BIAS 0.005//0.0541f
+
+#endif
+
+#if QUAD_NUM==1
+
+#define IMU_ACCX_SIGN 1
+#define IMU_ACCY_SIGN 1
+#define IMU_ACCZ_SIGN 1
+
+#define IMU_GYRX_SIGN 1
+#define IMU_GYRY_SIGN 1
+#define IMU_GYRZ_SIGN 1
+
+
+#define MOTOR_FRONTLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR
+#define MOTOR_FRONTRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR
+#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
+#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
+
+#define ACCEL_X_BIAS -0.01f
+#define ACCEL_Y_BIAS 0.041f
+#define ACCEL_Z_BIAS 0.0f
+
+#define GYRO_X_BIAS -0.024f
+#define GYRO_Y_BIAS -0.013f
+#define GYRO_Z_BIAS 0.02//0.0541f
+
+#endif
+
struct ZyboI2CState {
XIicPs *inst;
int busId;
diff --git a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_imu.c b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_imu.c
index 31b68f49d66c93896cb02f9f17afa4fe37f4cb34..5cf36172d7440dd44057acf6ad1c62026d0e56a8 100644
--- a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_imu.c
+++ b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_imu.c
@@ -44,14 +44,6 @@
// Sensitivity gain is based off MPU9150 datasheet (pg. 11)
#define GYRO_SENS 16.4
-#define GYRO_X_BIAS 0.005f
-#define GYRO_Y_BIAS -0.014f
-#define GYRO_Z_BIAS 0.0534//0.0541f
-
-#define ACCEL_X_BIAS 0.023f
-#define ACCEL_Y_BIAS 0.009f
-#define ACCEL_Z_BIAS 0.0686f
-
int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
@@ -106,8 +98,8 @@ int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
u8 buf[3];
u8 ASAX, ASAY, ASAZ;
- // Quickly read from the factory ROM to get correction coefficents
- int status = mpu9150_write(self->i2c, 0x0A, 0x0F);
+ // Quickly read from the factory ROM to get correction coefficients
+ int status = mpu9150_write(self->i2c, 0x0A, 0x1F);
if(status != 0) {
return status;
}
@@ -134,7 +126,9 @@ int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
struct I2CDriver *i2c = self->i2c;
i16 raw_accel_x, raw_accel_y, raw_accel_z;
+ i16 sensor_raw_accel_x, sensor_raw_accel_y, sensor_raw_accel_z;
i16 gyro_x, gyro_y, gyro_z;
+ i16 sensor_gyro_x, sensor_gyro_y, sensor_gyro_z;
u8 sensor_data[ACCEL_GYRO_READ_SIZE] = {};
@@ -142,25 +136,41 @@ int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
if (error) return error;
//Calculate accelerometer data
- raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
- raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
- raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
+ sensor_raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
+ sensor_raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
+ sensor_raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
+
+ // TODO: Update Matlab model with correct directions.
+ raw_accel_x = sensor_raw_accel_y;
+ raw_accel_y = -sensor_raw_accel_x;
+ raw_accel_z = sensor_raw_accel_z;
+// raw_accel_x = sensor_raw_accel_y;
+// raw_accel_y = sensor_raw_accel_x;
+// raw_accel_z = sensor_raw_accel_z;
// put in G's
- gam->accel_x = (raw_accel_x / 4096.0) + ACCEL_X_BIAS; // 4,096 is the gain per LSB of the measurement reading based on a configuration range of +-8g
- gam->accel_y = (raw_accel_y / 4096.0) + ACCEL_Y_BIAS;
- gam->accel_z = (raw_accel_z / 4096.0) + ACCEL_Z_BIAS;
+ gam->accel_x = IMU_ACCX_SIGN * (raw_accel_x / 4096.0) + ACCEL_X_BIAS; // 4,096 is the gain per LSB of the measurement reading based on a configuration range of +-8g
+ gam->accel_y = IMU_ACCY_SIGN * (raw_accel_y / 4096.0) + ACCEL_Y_BIAS;
+ gam->accel_z = IMU_ACCZ_SIGN * (raw_accel_z / 4096.0) + ACCEL_Z_BIAS;
//Convert gyro data to rate (we're only using the most 12 significant bits)
- gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
- gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
- gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
+ sensor_gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
+ sensor_gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
+ sensor_gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
+
+ //remap
+ gyro_x = sensor_gyro_y;
+ gyro_y = -sensor_gyro_x;
+ gyro_z = sensor_gyro_z;
+// gyro_x = sensor_gyro_y;
+// gyro_y = sensor_gyro_x;
+// gyro_z = sensor_gyro_z;
//Get the number of degrees
//javey: converted to radians to following SI units
- gam->gyro_xVel_p = ((gyro_x / GYRO_SENS) * DEG_TO_RAD) + GYRO_X_BIAS;
- gam->gyro_yVel_q = ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
- gam->gyro_zVel_r = ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
+ gam->gyro_xVel_p = IMU_GYRX_SIGN * ((gyro_x / GYRO_SENS) * DEG_TO_RAD) + GYRO_X_BIAS;
+ gam->gyro_yVel_q = IMU_GYRY_SIGN * ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
+ gam->gyro_zVel_r = IMU_GYRZ_SIGN * ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
// Magnometer
mpu9150_read_mag(self, gam);
@@ -214,6 +224,7 @@ int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
u8 mag_data[6];
u8 mag_status;
i16 raw_magX, raw_magY, raw_magZ;
+ i16 sensor_raw_magX, sensor_raw_magY, sensor_raw_magZ;
int trigger = 0;
@@ -234,9 +245,14 @@ int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
return status;
}
- raw_magX = (mag_data[1] << 8) | mag_data[0];
- raw_magY = (mag_data[3] << 8) | mag_data[2];
- raw_magZ = (mag_data[5] << 8) | mag_data[4];
+ sensor_raw_magX = (mag_data[1] << 8) | mag_data[0];
+ sensor_raw_magY = (mag_data[3] << 8) | mag_data[2];
+ sensor_raw_magZ = (mag_data[5] << 8) | mag_data[4];
+
+ //remap
+ raw_magX = -sensor_raw_magY;
+ raw_magY = sensor_raw_magX;
+ raw_magZ = sensor_raw_magZ;
// Set magnetometer data to output
gam->mag_x = raw_magX * gam->magX_correction;
diff --git a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_lidar.c b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_lidar.c
index 32d0fad0cd243c3e871c58eaaa10ead16c3d246b..62caca7532156520b9cd8a05df605de7bd18d123 100644
--- a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_lidar.c
+++ b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_lidar.c
@@ -16,7 +16,9 @@ int zybo_lidar_reset(struct LidarDriver *self, lidar_t *lidar) {
struct I2CDriver *i2c = self->i2c;
int error = 0;
-
+ //Device wakeup if asleep.
+ lidarlite_write(i2c, 0x00, 0x00);
+ usleep(15000);
// Device Reset & Wake up with default settings
error = lidarlite_write(i2c, 0x00, 0x00);
if (error) return error;
diff --git a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_motor.c b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_motor.c
index 576c1ecaf353bf3caf7f0f63999ac500b8353a84..869bb7973be25a2cc2e004c02a900b339949a46a 100644
--- a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_motor.c
+++ b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_motor.c
@@ -20,10 +20,10 @@ int zybo_motor_reset(struct MotorDriver *self) {
}
struct MotorDriverState *state = self->state;
- state->outputs[0] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_0_BASEADDR;
- state->outputs[1] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_1_BASEADDR;
- state->outputs[2] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_2_BASEADDR;
- state->outputs[3] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_3_BASEADDR;
+ state->outputs[0] = (int *) MOTOR_BACKRIGHT_BASEADDR;
+ state->outputs[1] = (int *) MOTOR_FRONTRIGHT_BASEADDR;
+ state->outputs[2] = (int *) MOTOR_BACKLEFT_BASEADDR;
+ state->outputs[3] = (int *) MOTOR_FRONTLEFT_BASEADDR;
// Set period width of PWM pulse
*(state->outputs[0]) = PERIOD_WIDTH;
diff --git a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_rc_receiver.c b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_rc_receiver.c
index 63d6ab525b330789670b251008bbcbc7d863b0ad..391333b0a65cc7d60213930ae36a37f0e7fef786 100644
--- a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_rc_receiver.c
+++ b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_rc_receiver.c
@@ -21,12 +21,12 @@ int zybo_rc_receiver_reset(struct RCReceiverDriver *self) {
// Save the addresses of the input PWM recorders
struct RCReceiverDriverState *state = self->state;
- state->channels[0] = (int *) XPAR_PWM_RECORDER_0_BASEADDR;
- state->channels[1] = (int *) XPAR_PWM_RECORDER_1_BASEADDR;
- state->channels[2] = (int *) XPAR_PWM_RECORDER_2_BASEADDR;
- state->channels[3] = (int *) XPAR_PWM_RECORDER_3_BASEADDR;
- state->channels[4] = (int *) XPAR_PWM_RECORDER_4_BASEADDR;
- state->channels[5] = (int *) XPAR_PWM_RECORDER_5_BASEADDR;
+ state->channels[0] = (int *) XPAR_PWM_RECORDER_0_S_AXI_BASEADDR;
+ state->channels[1] = (int *) XPAR_PWM_RECORDER_1_S_AXI_BASEADDR;
+ state->channels[2] = (int *) XPAR_PWM_RECORDER_2_S_AXI_BASEADDR;
+ state->channels[3] = (int *) XPAR_PWM_RECORDER_3_S_AXI_BASEADDR;
+ state->channels[4] = (int *) XPAR_PWM_RECORDER_4_S_AXI_BASEADDR;
+ state->channels[5] = (int *) XPAR_PWM_RECORDER_5_S_AXI_BASEADDR;
return 0;
}
diff --git a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_tests.c
index a38e87306620ba54d308d61cd450cf7e817614cc..ddc7971a52b063309245f92af66665241a228953 100644
--- a/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_tests.c
+++ b/quad/xsdk_workspace/real_quad/src/hw_impl_zybo_tests.c
@@ -50,7 +50,7 @@ int test_zybo_mio7_led_and_system() {
* distance of the LIDAR sensor.
*/
int test_zybo_i2c() {
- struct I2CDriver i2c = create_zybo_i2c(0);
+ struct I2CDriver i2c = create_zybo_i2c(1);
struct LidarDriver ld = create_zybo_lidar(&i2c);
i2c.reset(&i2c);
@@ -65,7 +65,7 @@ int test_zybo_i2c() {
int test_zybo_i2c_imu() {
struct I2CDriver i2c = create_zybo_i2c(0);
struct IMUDriver imu = create_zybo_imu(&i2c);
-
+ char buf[100];
gam_t gam;
if (i2c.reset(&i2c)) return 0;
if (imu.reset(&imu, &gam)) return 0;
@@ -73,6 +73,7 @@ int test_zybo_i2c_imu() {
int status = 0;
while (!status) {
status = imu.read(&imu, &gam);
+ usleep(5000);
}
return 0;
}
@@ -306,6 +307,7 @@ int test_zybo_uart_comm() {
unsigned char c;
while (1) {
if (comm.uart->read(comm.uart, &c)) {
+ uart.write(&uart, 0x55);
// read failed
led.turn_off(&led);
} else {
@@ -319,3 +321,48 @@ int test_zybo_uart_comm() {
}
+int test_zybo_pcb() {
+ struct UARTDriver uart = create_zybo_uart(0);
+ struct LEDDriver led = create_zybo_mio7_led();
+ struct RCReceiverDriver rc = create_zybo_rc_receiver();
+ struct MotorDriver motors = create_zybo_motors();
+ uart.reset(&uart);
+ led.reset(&led);
+ rc.reset(&rc);
+ motors.reset(&motors);
+
+ char stateMsg[100];
+ unsigned char c;
+ unsigned char led_state = 0;
+ float channels[6];
+ float pwm[4];
+ int i;
+ while (1) {
+ if(uart.read(&uart, &c) >= 0) {
+ if(led_state) {
+ led.turn_off(&led);
+ led_state = 0;
+ } else {
+ led.turn_on(&led);
+ led_state = 1;
+ }
+ }
+ for (i = 0; i < 6; i++) {
+ rc.read(&rc, i, &channels[i]);
+ }
+ pwm[0] = channels[0]+channels[1]+channels[3];
+ pwm[1] = channels[0]+channels[1]-channels[3];
+ pwm[2] = channels[0]-channels[1]+channels[3];
+ pwm[3] = channels[0]-channels[1]-channels[3];
+ sprintf(stateMsg, "%5.2f %5.2f %5.2f %5.2f %5.2f %5.2f -> %5.2f %5.2f %5.2f %5.2f\r\n", channels[0], channels[1], channels[2], channels[3], channels[4], channels[5], pwm[0], pwm[1], pwm[2], pwm[2]);
+ char* it;
+ for (it = stateMsg; *it; it++) {
+ uart.write(&uart, *it);
+ }
+ for (i = 0; i < 4; i++) {
+ motors.write(&motors, i, pwm[i]);
+ }
+ }
+
+ return 0;
+}
diff --git a/quad/xsdk_workspace/real_quad/src/lscript.ld b/quad/xsdk_workspace/real_quad/src/lscript.ld
index a9e7524bb4b15ca61a3d8c76f6a001e3b4c86e9f..4917c522732365b48f2a9d1ce3746be8fd89e037 100644
--- a/quad/xsdk_workspace/real_quad/src/lscript.ld
+++ b/quad/xsdk_workspace/real_quad/src/lscript.ld
@@ -2,19 +2,20 @@
/* */
/* This file is automatically generated by linker script generator.*/
/* */
-/* Version: Xilinx EDK 14.7 EDK_P.20131013 */
+/* Version: 2018.3 */
/* */
-/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
+/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
-/* Description : Cortex-A9 Linker Script */
+/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x100000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x6400000;
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x200000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
@@ -22,9 +23,10 @@ _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
MEMORY
{
- ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
- ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
- ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
+ ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
+ ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
+ ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+ ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
}
/* Specify the default entry point to the program */
@@ -36,7 +38,7 @@ ENTRY(_vector_table)
SECTIONS
{
.text : {
- *(.vectors)
+ KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
@@ -49,15 +51,15 @@ SECTIONS
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.init : {
KEEP (*(.init))
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.fini : {
KEEP (*(.fini))
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.rodata : {
__rodata_start = .;
@@ -65,14 +67,14 @@ SECTIONS
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.sdata2 : {
__sdata2_start = .;
@@ -80,7 +82,7 @@ SECTIONS
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.sbss2 : {
__sbss2_start = .;
@@ -88,7 +90,7 @@ SECTIONS
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.data : {
__data_start = .;
@@ -99,18 +101,18 @@ SECTIONS
*(.got)
*(.got.plt)
__data_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.got : {
*(.got)
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.ctors : {
__CTOR_LIST__ = .;
@@ -121,7 +123,7 @@ SECTIONS
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.dtors : {
__DTOR_LIST__ = .;
@@ -132,67 +134,67 @@ SECTIONS
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.eh_frame : {
*(.eh_frame)
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.gcc_except_table : {
*(.gcc_except_table)
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.sdata : {
__sdata_start = .;
@@ -200,7 +202,7 @@ SECTIONS
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.sbss (NOLOAD) : {
__sbss_start = .;
@@ -208,7 +210,7 @@ SECTIONS
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.tdata : {
__tdata_start = .;
@@ -216,7 +218,7 @@ SECTIONS
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.tbss : {
__tbss_start = .;
@@ -224,7 +226,7 @@ SECTIONS
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.bss (NOLOAD) : {
__bss_start = .;
@@ -233,7 +235,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
@@ -249,17 +251,19 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
+ . = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
- . += _STACK_SIZE;
+ . += _IRQ_STACK_SIZE;
+ . = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
@@ -277,7 +281,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
+} > ps7_ddr_0
_end = .;
}
diff --git a/quad/xsdk_workspace/system_bsp/.cproject b/quad/xsdk_workspace/system_bsp/.cproject
index d95314090b5587f6375b20955412f1ac382bb324..31dc597f64cc8e64b5a4e222c03e156d81c8a895 100644
--- a/quad/xsdk_workspace/system_bsp/.cproject
+++ b/quad/xsdk_workspace/system_bsp/.cproject
@@ -1,10 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.154473096">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.154473096" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+ <cconfiguration id="org.eclipse.cdt.core.default.config.1650379314">
+ <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1650379314" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
diff --git a/quad/xsdk_workspace/system_bsp/.project b/quad/xsdk_workspace/system_bsp/.project
index 73357d93db11bb1010e44ea8f0724960190d68a1..6a1248ca7803db1279d96e610c4ce22550440024 100644
--- a/quad/xsdk_workspace/system_bsp/.project
+++ b/quad/xsdk_workspace/system_bsp/.project
@@ -1,9 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>system_bsp</name>
- <comment></comment>
+ <comment>Created by SDK v2018.3</comment>
<projects>
- <project>sytem_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
@@ -11,7 +10,7 @@
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
- <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
+ <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
diff --git a/quad/xsdk_workspace/system_bsp/.sdkproject b/quad/xsdk_workspace/system_bsp/.sdkproject
index 3135ec9f796f86108f3510421221835514fcc15f..dd82e57dd062516fb69638e72b1609d20aa13292 100644
--- a/quad/xsdk_workspace/system_bsp/.sdkproject
+++ b/quad/xsdk_workspace/system_bsp/.sdkproject
@@ -1,3 +1,4 @@
THIRPARTY=false
+HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_0
PROCESSOR=ps7_cortexa9_0
MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace/system_bsp/Makefile b/quad/xsdk_workspace/system_bsp/Makefile
index fe2a0efc7cc39ff9edfdbb9064b229a72106cb58..1e68922caaf26866fdd396178d91b437eadf7fb2 100644
--- a/quad/xsdk_workspace/system_bsp/Makefile
+++ b/quad/xsdk_workspace/system_bsp/Makefile
@@ -1,21 +1,35 @@
-# Makefile generated by Xilinx SDK.
-
--include libgen.options
+# Makefile generated by Xilinx.
+PROCESSOR = ps7_cortexa9_0
LIBRARIES = ${PROCESSOR}/lib/libxil.a
-MSS = system.mss
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
all: libs
@echo 'Finished building libraries'
-libs: $(LIBRARIES)
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+libs: $(addsuffix /make.libs,$(SUBDIRS))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+ cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+ @echo "Running Make include in $(subst /make.include,,$@)"
+ $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
-$(LIBRARIES): $(MSS)
- libgen -hw ${HWSPEC}\
- ${REPOSITORIES}\
- -pe ${PROCESSOR} \
- -log libgen.log \
- $(MSS)
+%/make.libs: include
+ @echo "Running Make libs in $(subst /make.libs,,$@)"
+ $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
+%/make.clean:
+ $(MAKE) -C $(subst /make.clean,,$@) -s clean
clean:
- rm -rf ${PROCESSOR}
+ rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/quad/xsdk_workspace/system_bsp/libgen.options b/quad/xsdk_workspace/system_bsp/libgen.options
deleted file mode 100644
index c7623d91f4a1e0004da3838082aea20358655cc9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/system_bsp/libgen.options
+++ /dev/null
@@ -1,3 +0,0 @@
-PROCESSOR=ps7_cortexa9_0
-REPOSITORIES=
-HWSPEC=../sytem_hw_platform/system.xml
diff --git a/quad/xsdk_workspace/system_bsp/system.mss b/quad/xsdk_workspace/system_bsp/system.mss
index c68ab7b92b15f34acd7f5630013691eb388335e3..8baba1055579168560802baae23f5d08d2419994 100644
--- a/quad/xsdk_workspace/system_bsp/system.mss
+++ b/quad/xsdk_workspace/system_bsp/system.mss
@@ -4,295 +4,324 @@
BEGIN OS
PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 3.11.a
+ PARAMETER OS_VER = 6.8
PARAMETER PROC_INSTANCE = ps7_cortexa9_0
- PARAMETER STDIN = ps7_uart_1
- PARAMETER STDOUT = ps7_uart_1
+ PARAMETER stdin = ps7_uart_0
+ PARAMETER stdout = ps7_uart_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa9
- PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER DRIVER_VER = 2.7
PARAMETER HW_INSTANCE = ps7_cortexa9_0
- PARAMETER EXTRA_COMPILER_FLAGS = -O0 -g
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = tmrctr
- PARAMETER DRIVER_VER = 2.05.a
- PARAMETER HW_INSTANCE = axi_timer_0
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_btns
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 3.01.a
- PARAMETER HW_INSTANCE = btns_4bits_tri_io
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_leds
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_sws
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = tmrctr
+ PARAMETER DRIVER_VER = 4.5
+ PARAMETER HW_INSTANCE = axi_timer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_3
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.4
PARAMETER HW_INSTANCE = ps7_coresight_comp_0
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = ddrps
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = ps7_ddr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ddrc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = devcfg
- PARAMETER DRIVER_VER = 2.04.a
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = ps7_dev_cfg_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 1.06.a
+ PARAMETER DRIVER_VER = 2.4
PARAMETER HW_INSTANCE = ps7_dma_ns
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 1.06.a
+ PARAMETER DRIVER_VER = 2.4
PARAMETER HW_INSTANCE = ps7_dma_s
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 1.05.a
+ PARAMETER DRIVER_VER = 3.8
PARAMETER HW_INSTANCE = ps7_ethernet_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_globaltimer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpiops
- PARAMETER DRIVER_VER = 1.02.a
+ PARAMETER DRIVER_VER = 3.4
PARAMETER HW_INSTANCE = ps7_gpio_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_gpv_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 1.04.a
+ PARAMETER DRIVER_VER = 3.8
PARAMETER HW_INSTANCE = ps7_i2c_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 1.04.a
+ PARAMETER DRIVER_VER = 3.8
PARAMETER HW_INSTANCE = ps7_i2c_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_intc_dist_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_l2cachec_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ocmc_0
END
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pl310_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pmu_0
+END
+
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspips
- PARAMETER DRIVER_VER = 2.03.a
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = ps7_qspi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_qspi_linear_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ram_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ram_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_scuc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 1.05.a
+ PARAMETER DRIVER_VER = 3.10
PARAMETER HW_INSTANCE = ps7_scugic_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scutimer
- PARAMETER DRIVER_VER = 1.02.a
+ PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = ps7_scutimer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scuwdt
- PARAMETER DRIVER_VER = 1.02.a
+ PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = ps7_scuwdt_0
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 3.6
PARAMETER HW_INSTANCE = ps7_sd_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_slcr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 1.05.a
+ PARAMETER DRIVER_VER = 3.7
PARAMETER HW_INSTANCE = ps7_uart_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 1.05.a
+ PARAMETER DRIVER_VER = 3.7
PARAMETER HW_INSTANCE = ps7_uart_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = usbps
- PARAMETER DRIVER_VER = 1.05.a
+ PARAMETER DRIVER_VER = 2.4
PARAMETER HW_INSTANCE = ps7_usb_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = xadcps
- PARAMETER DRIVER_VER = 1.02.a
+ PARAMETER DRIVER_VER = 2.3
PARAMETER HW_INSTANCE = ps7_xadc_0
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = pwm_recorder_0
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = pwm_recorder_1
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = pwm_recorder_2
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = pwm_recorder_3
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = pwm_recorder_4
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = pwm_recorder_5
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_0
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_0
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_1
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_1
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_2
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_2
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_3
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_3
END
diff --git a/quad/xsdk_workspace/zybo_fsbl/.cproject b/quad/xsdk_workspace/zybo_fsbl/.cproject
deleted file mode 100644
index 1434e38d4d1165e75cdc6c29b1a70a808484531f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/.cproject
+++ /dev/null
@@ -1,172 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="xilinx.gnu.arm.exe.debug.631125449">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.631125449" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.631125449" name="Debug" parent="xilinx.gnu.arm.exe.debug">
- <folderInfo id="xilinx.gnu.arm.exe.debug.631125449." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.arm.exe.debug.toolchain.598522392" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.debug.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.1372637876" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
- <builder buildPath="${workspace_loc:/zybo_fsbl}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.debug.2066333847" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.arm.toolchain.builder.debug"/>
- <tool id="xilinx.gnu.arm.c.toolchain.assembler.debug.792124132" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.debug">
- <inputType id="xilinx.gnu.assembler.input.1066651972" superClass="xilinx.gnu.assembler.input"/>
- </tool>
- <tool id="xilinx.gnu.arm.c.toolchain.compiler.debug.371418732" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1709273506" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.1095090898" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.2076701770" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/include"/>
- </option>
- <inputType id="xilinx.gnu.arm.c.compiler.input.670667181" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
- </tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.debug.153994272" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.273904714" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.100308615" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1777219656" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/include"/>
- </option>
- </tool>
- <tool id="xilinx.gnu.arm.toolchain.archiver.15429244" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
- <tool id="xilinx.gnu.arm.c.toolchain.linker.debug.1131508766" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1222044113" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.13428014" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.1931360495" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.1547145650" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
- <listOptionValue builtIn="false" value="rsa"/>
- </option>
- <option id="xilinx.gnu.c.link.option.paths.999363621" superClass="xilinx.gnu.c.link.option.paths" valueType="libPaths">
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
- </option>
- <inputType id="xilinx.gnu.linker.input.1436307817" superClass="xilinx.gnu.linker.input">
- <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
- <additionalInput kind="additionalinput" paths="$(LIBS)"/>
- </inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.1950636018" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
- </tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.linker.debug.703659759" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.800774044" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.437956417" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.118016047" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- </tool>
- <tool id="xilinx.gnu.arm.size.debug.569464936" name="ARM Print Size" superClass="xilinx.gnu.arm.size.debug"/>
- </toolChain>
- </folderInfo>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- <cconfiguration id="xilinx.gnu.arm.exe.release.594409871">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.release.594409871" moduleId="org.eclipse.cdt.core.settings" name="Release">
- <externalSettings/>
- <extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.release.594409871" name="Release" parent="xilinx.gnu.arm.exe.release">
- <folderInfo id="xilinx.gnu.arm.exe.release.594409871." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.arm.exe.release.toolchain.507750734" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.release.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.release.1628399965" isAbstract="false" name="Release Platform" superClass="xilinx.arm.target.gnu.base.release"/>
- <builder buildPath="${workspace_loc:/zybo_fsbl}/Release" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.release.1422012668" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.arm.toolchain.builder.release"/>
- <tool id="xilinx.gnu.arm.c.toolchain.assembler.release.865141912" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.release">
- <inputType id="xilinx.gnu.assembler.input.1671779125" superClass="xilinx.gnu.assembler.input"/>
- </tool>
- <tool id="xilinx.gnu.arm.c.toolchain.compiler.release.2101352431" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.release">
- <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1644059076" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.1522632993" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1242558173" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/include"/>
- </option>
- <inputType id="xilinx.gnu.arm.c.compiler.input.729397047" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
- </tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.release.825857438" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.release">
- <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1953632681" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.2062160021" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.978611856" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/include"/>
- </option>
- </tool>
- <tool id="xilinx.gnu.arm.toolchain.archiver.297211059" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
- <tool id="xilinx.gnu.arm.c.toolchain.linker.release.1225963780" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1662060075" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1712694149" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.907765905" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.2026302928" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
- <listOptionValue builtIn="false" value="rsa"/>
- </option>
- <option id="xilinx.gnu.c.link.option.paths.1361224741" superClass="xilinx.gnu.c.link.option.paths" valueType="libPaths">
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
- </option>
- <inputType id="xilinx.gnu.linker.input.749170694" superClass="xilinx.gnu.linker.input">
- <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
- <additionalInput kind="additionalinput" paths="$(LIBS)"/>
- </inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.503889234" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
- </tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.linker.release.659189711" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1372604190" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1310678011" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.1404470723" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- </tool>
- <tool id="xilinx.gnu.arm.size.release.108428989" name="ARM Print Size" superClass="xilinx.gnu.arm.size.release"/>
- </toolChain>
- </folderInfo>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="zybo_fsbl.xilinx.gnu.arm.exe.117806380" name="Xilinx ARM Executable" projectType="xilinx.gnu.arm.exe"/>
- </storageModule>
- <storageModule moduleId="scannerConfiguration">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.594409871;xilinx.gnu.arm.exe.release.594409871.;xilinx.gnu.arm.c.toolchain.compiler.release.2101352431;xilinx.gnu.arm.c.compiler.input.729397047">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.631125449;xilinx.gnu.arm.exe.debug.631125449.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.594409871;xilinx.gnu.arm.exe.release.594409871.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.631125449;xilinx.gnu.arm.exe.debug.631125449.;xilinx.gnu.arm.c.toolchain.compiler.debug.371418732;xilinx.gnu.arm.c.compiler.input.670667181">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- </storageModule>
-</cproject>
diff --git a/quad/xsdk_workspace/zybo_fsbl/.project b/quad/xsdk_workspace/zybo_fsbl/.project
deleted file mode 100644
index bc2d382197a84b9721fcff26d44f304f29f1d097..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/.project
+++ /dev/null
@@ -1,26 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>zybo_fsbl</name>
- <comment>zybo_fsbl_bsp - ps7_cortexa9_0</comment>
- <projects>
- <project>zybo_fsbl_bsp</project>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace/zybo_fsbl/Debug/makefile b/quad/xsdk_workspace/zybo_fsbl/Debug/makefile
deleted file mode 100644
index e219253b8e3159f858ab3acaa338fcdf48a3096c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/Debug/makefile
+++ /dev/null
@@ -1,58 +0,0 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
--include ../makefile.init
-
-RM := rm -rf
-
-# All of the sources participating in the build are defined here
--include sources.mk
--include src/subdir.mk
--include subdir.mk
--include objects.mk
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-ifneq ($(strip $(S_UPPER_DEPS)),)
--include $(S_UPPER_DEPS)
-endif
-endif
-
--include ../makefile.defs
-
-# Add inputs and outputs from these tool invocations to the build variables
-ELFSIZE += \
-zybo_fsbl.elf.size \
-
-
-# All Target
-all: zybo_fsbl.elf secondary-outputs
-
-# Tool invocations
-zybo_fsbl.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
- @echo 'Building target: $@'
- @echo 'Invoking: ARM gcc linker'
- arm-xilinx-eabi-gcc -L"/local/ucart/MicroCART/quad/xsdk_workspace/zybo_fsbl/src" -Wl,-T -Wl,../src/lscript.ld -L../../zybo_fsbl_bsp/ps7_cortexa9_0/lib -o "zybo_fsbl.elf" $(OBJS) $(USER_OBJS) $(LIBS)
- @echo 'Finished building target: $@'
- @echo ' '
-
-zybo_fsbl.elf.size: zybo_fsbl.elf
- @echo 'Invoking: ARM Print Size'
- arm-xilinx-eabi-size zybo_fsbl.elf |tee "zybo_fsbl.elf.size"
- @echo 'Finished building: $@'
- @echo ' '
-
-# Other Targets
-clean:
- -$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES)$(ELFSIZE)$(S_UPPER_DEPS) zybo_fsbl.elf
- -@echo ' '
-
-secondary-outputs: $(ELFSIZE)
-
-.PHONY: all clean dependents
-.SECONDARY:
-
--include ../makefile.targets
diff --git a/quad/xsdk_workspace/zybo_fsbl/Debug/objects.mk b/quad/xsdk_workspace/zybo_fsbl/Debug/objects.mk
deleted file mode 100644
index 88ab2f86c60bc732322248eb99b64703856ff9af..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/Debug/objects.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-USER_OBJS :=
-
-LIBS := -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/Debug/sources.mk b/quad/xsdk_workspace/zybo_fsbl/Debug/sources.mk
deleted file mode 100644
index a7c54c38a1e61325feea8965fd7f659ed223d79b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/Debug/sources.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-O_SRCS :=
-C_SRCS :=
-LD_SRCS :=
-S_UPPER_SRCS :=
-S_SRCS :=
-OBJ_SRCS :=
-OBJS :=
-C_DEPS :=
-EXECUTABLES :=
-ELFSIZE :=
-S_UPPER_DEPS :=
-
-# Every subdirectory with source files must be described here
-SUBDIRS := \
-src \
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/Debug/src/subdir.mk b/quad/xsdk_workspace/zybo_fsbl/Debug/src/subdir.mk
deleted file mode 100644
index d3c44151fc0926a6bfab9a6c5516b0d6a7b96239..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/Debug/src/subdir.mk
+++ /dev/null
@@ -1,80 +0,0 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../src/ddr_init.c \
-../src/ff.c \
-../src/fsbl_hooks.c \
-../src/image_mover.c \
-../src/main.c \
-../src/md5.c \
-../src/mmc.c \
-../src/nand.c \
-../src/nor.c \
-../src/pcap.c \
-../src/ps7_init.c \
-../src/qspi.c \
-../src/rsa.c \
-../src/sd.c
-
-LD_SRCS += \
-../src/lscript.ld
-
-S_UPPER_SRCS += \
-../src/fsbl_handoff.S
-
-OBJS += \
-./src/ddr_init.o \
-./src/ff.o \
-./src/fsbl_handoff.o \
-./src/fsbl_hooks.o \
-./src/image_mover.o \
-./src/main.o \
-./src/md5.o \
-./src/mmc.o \
-./src/nand.o \
-./src/nor.o \
-./src/pcap.o \
-./src/ps7_init.o \
-./src/qspi.o \
-./src/rsa.o \
-./src/sd.o
-
-C_DEPS += \
-./src/ddr_init.d \
-./src/ff.d \
-./src/fsbl_hooks.d \
-./src/image_mover.d \
-./src/main.d \
-./src/md5.d \
-./src/mmc.d \
-./src/nand.d \
-./src/nor.d \
-./src/pcap.d \
-./src/ps7_init.d \
-./src/qspi.d \
-./src/rsa.d \
-./src/sd.d
-
-S_UPPER_DEPS += \
-./src/fsbl_handoff.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-src/%.o: ../src/%.c
- @echo 'Building file: $<'
- @echo 'Invoking: ARM gcc compiler'
- arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../zybo_fsbl_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
- @echo 'Finished building: $<'
- @echo ' '
-
-src/%.o: ../src/%.S
- @echo 'Building file: $<'
- @echo 'Invoking: ARM gcc compiler'
- arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../zybo_fsbl_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
- @echo 'Finished building: $<'
- @echo ' '
-
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ddr_init.c b/quad/xsdk_workspace/zybo_fsbl/src/ddr_init.c
deleted file mode 100644
index bf9a059a68a3d536e76e5c8f98e7e6c2219b7a0b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/ddr_init.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file ddr_init.c
-*
-* Initialize the DDR controller. When PCW is functioning, this would be gone.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 06/19/09 First release
-* 2.00a jz 05/11/11 Changed register to #defines, updated to peep11
-* 3.00a mb 30/05/12 included fsbl.h
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define DDR_CONFIG_BASE (XPS_DDR_CTRL_BASEADDR + 0x000)
-
-#define DDR_MSTR_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x000)
-
-#define DDR_TWORANKPHY_REG (XPS_DDR_CTRL_BASEADDR + 0x004)
-
-#define DDR_HPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x008)
-#define DDR_LPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x00C)
-#define DDR_W_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x010)
-#define DDR_DRAM_PARAMS_1_REG (XPS_DDR_CTRL_BASEADDR + 0x014)
-#define DDR_DRAM_PARAMS_2_REG (XPS_DDR_CTRL_BASEADDR + 0x018)
-#define DDR_DRAM_PARAMS_3_REG (XPS_DDR_CTRL_BASEADDR + 0x01C)
-#define DDR_DRAM_PARAMS_4_REG (XPS_DDR_CTRL_BASEADDR + 0x020)
-#define DDR_DRAM_PARAMS_5_REG (XPS_DDR_CTRL_BASEADDR + 0x024)
-#define DDR_DRAM_INIT_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x028)
-
-#define DDR_DRAM_MODE_1_REG (XPS_DDR_CTRL_BASEADDR + 0x02C)
-#define DDR_DRAM_MODE_2_REG (XPS_DDR_CTRL_BASEADDR + 0x030)
-#define DDR_DRAM_BURST8_REG (XPS_DDR_CTRL_BASEADDR + 0x034)
-
-#define DDR_DEBUG_REG (XPS_DDR_CTRL_BASEADDR + 0x038)
-
-#define DDR_ADDR_MAP_1_REG (XPS_DDR_CTRL_BASEADDR + 0x03C)
-#define DDR_ADDR_MAP_2_REG (XPS_DDR_CTRL_BASEADDR + 0x040)
-#define DDR_ADDR_MAP_3_REG (XPS_DDR_CTRL_BASEADDR + 0x044)
-
-#define DDR_ODT_RD_WR_REG (XPS_DDR_CTRL_BASEADDR + 0x048)
-#define DDR_PHY_RDC_FIFO_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x04C)
-#define DDR_REG_PHY_RDC_FIFO_CTRL (XPS_DDR_CTRL_BASEADDR + 0x050)
-#define DDR_STATUS_REG (XPS_DDR_CTRL_BASEADDR + 0x054)
-
-#define DDR_DLL_CALIB_REG (XPS_DDR_CTRL_BASEADDR + 0x058)
-#define DDR_ODT_REG (XPS_DDR_CTRL_BASEADDR + 0x05C)
-#define DDR_MISC_1_REG (XPS_DDR_CTRL_BASEADDR + 0x060)
-#define DDR_MISC_2_REG (XPS_DDR_CTRL_BASEADDR + 0x064)
-
-#define DDR_WR_DLL_FORCE (XPS_DDR_CTRL_BASEADDR + 0x068)
-#define DDR_RD_DLL_FORCE0_REG (XPS_DDR_CTRL_BASEADDR + 0x06C)
-#define DDR_RD_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x070)
-
-#define DDR_WR_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x074)
-#define DDR_RD_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x078)
-
-#define DDR_MSTR_DLL_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x07C)
-#define DDR_RD_SLAVE_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x080)
-#define DDR_RD_SLAVE_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x084)
-
-#define DDR_OF_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x088)
-#define DDR_OF_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x08C)
-#define DDR_OF_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x090)
-#define DDR_OF_STATUS3_REG (XPS_DDR_CTRL_BASEADDR + 0x094)
-
-#define DDR_MSTR_DLL_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x098)
-
-#define DDR_Wr_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x09C)
-#define DDR_REFRESH_TIMER01_REG (XPS_DDR_CTRL_BASEADDR + 0x0A0)
-#define DDR_T_ZQ_REG (XPS_DDR_CTRL_BASEADDR + 0x0A4)
-#define DDR_T_ZQ_SHORT_INTERVAL_REG (XPS_DDR_CTRL_BASEADDR + 0x0A8)
-
-#define DDR_STATUS_DATA_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0AC)
-#define DDR_STATUS_DATA_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B0)
-#define DDR_STATUS_DQS_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0B4)
-#define DDR_STATUS_DQS_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B8)
-
-#define DDR_WR_DATA_SLV0_REG (XPS_DDR_CTRL_BASEADDR + 0x17c)
-#define DDR_WR_DATA_SLV1_REG (XPS_DDR_CTRL_BASEADDR + 0x180)
-#define DDR_WR_DATA_SLV2_REG (XPS_DDR_CTRL_BASEADDR + 0x184)
-#define DDR_WR_DATA_SLV3_REG (XPS_DDR_CTRL_BASEADDR + 0x188)
-
-#define DDR_ID_REG (XPS_DDR_CTRL_BASEADDR + 0x200)
-#define DDR_DDR_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x204)
-
-#define DDR_PRIO_WR_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x208)
-#define DDR_PRIO_WR_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x20C)
-#define DDR_PRIO_WR_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x210)
-#define DDR_PRIO_WR_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x214)
-#define DDR_PRIO_RD_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x218)
-#define DDR_PRIO_RD_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x21C)
-#define DDR_PRIO_RD_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x220)
-#define DDR_PRIO_RD_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x224)
-
-#define DDR_PERF_MON_1_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x228)
-#define DDR_PERF_MON_1_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x22C)
-#define DDR_PERF_MON_1_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x230)
-#define DDR_PERF_MON_1_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x234)
-#define DDR_PERF_MON_2_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x238)
-#define DDR_PERF_MON_2_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x23C)
-#define DDR_PERF_MON_2_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x240)
-#define DDR_PERF_MON_2_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x244)
-#define DDR_PERF_MON_3_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x248)
-#define DDR_PERF_MON_3_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x24C)
-#define DDR_PERF_MON_3_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x250)
-#define DDR_PERF_MON_3_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x254)
-#define DDR_TRUSTED_MEM_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x258)
-
-#define DDR_EXCLACC_CFG_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x25C)
-#define DDR_EXCLACC_CFG_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x260)
-#define DDR_EXCLACC_CFG_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x264)
-#define DDR_EXCLACC_CFG_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x268)
-
-/* Trust zone configuration register */
-#define SLCR_LOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x4)
-#define SLCR_UNLOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x8)
-#define TZ_DDR_RAM_REG (XPS_SYS_CTRL_BASEADDR + 0x430)
-
-
-/* Mask defines */
-#define DDR_OUT_RESET_MASK 0x1
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define DDRIn32 Xil_In32
-#define DDROut32 Xil_Out32
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void init_ddr(void);
-
-#define DDRIn32 Xil_In32
-#define DDROut32 Xil_Out32
-
-static int verify = 0;
-
-static void NewDDROut32(u32 Address, u32 Value)
-{
- u32 Data;
-
- if (verify) {
- Data = DDRIn32(Address);
- if (Data != Value) fsbl_printf(DEBUG_INFO,"Verify failed, Address = %08X, \
- Data = %08X, Expected = %08X\n\r", Address, Data, Value);
- } else
- DDROut32(Address, Value);
-}
-
-#undef DDROut32
-#define DDROut32 NewDDROut32
-
-void init_ddr(void)
-{
- u32 RegValue;
-
- RegValue = DDRIn32(DDR_MSTR_CTRL_REG);
-
- /* If DDR is being taking out of reset, then it has been configured
- */
- if (RegValue & DDR_OUT_RESET_MASK)
- verify = 1;
-
- /* Configure DDR */
- DDROut32(DDR_MSTR_CTRL_REG, 0x00000200);
-
- /* direct rip of the DDR init tcl for the PEEP startup */
- DDROut32(DDR_TWORANKPHY_REG, 0x000C1061); /* # 0 */
-
- DDROut32(DDR_LPR_PARAMS_REG, 0x03001001); //;#3
- DDROut32(DDR_W_PARAMS_REG, 0x00014001); //;#4
-
- DDROut32(DDR_DRAM_PARAMS_1_REG, 0x0004e020); //; #5
-
-#ifdef PEEP_CODE
- DDROut32(DDR_DRAM_PARAMS_2_REG, 0x36264ccf); //; #6
-#else
- DDROut32(DDR_DRAM_PARAMS_2_REG, 0x349B48CD); //; #6
-#endif
- DDROut32(DDR_DRAM_PARAMS_3_REG, 0x820158a4); //; #7
-
- DDROut32(DDR_DRAM_PARAMS_4_REG, 0x250882c4); //; #8
-
- DDROut32(DDR_DRAM_INIT_PARAMS_REG, 0x00809004); //; #10
-
- DDROut32(DDR_DRAM_MODE_1_REG, 0x0); //; #11
-
- DDROut32(DDR_DRAM_MODE_2_REG, 0x00040952); //; #12
-
- DDROut32(DDR_DRAM_BURST8_REG, 0x00020022); //; #13
-
-#ifdef PEEP_CODE
- DDROut32(DDR_ADDR_MAP_1_REG, 0xF88); //; #15
-#endif
-
-#ifdef PALLADIUM
- DDROut32(DDR_ADDR_MAP_1_REG, 0x777); //; #15
-#endif
-
- DDROut32(DDR_ADDR_MAP_2_REG, 0xFF000000); //; #16
-
- DDROut32(DDR_ADDR_MAP_3_REG, 0x0FF66666); //; #17
-
- DDROut32(DDR_REG_PHY_RDC_FIFO_CTRL, 0x256); //; #20
-
- DDROut32(DDR_ODT_REG, 0x2223); //; #23
-
- DDROut32(DDR_MISC_2_REG, 0x00020FE0); //; #25
-
- DDROut32(DDR_T_ZQ_REG, 0x10200800); //; #41
-
- DDROut32(DDR_STATUS_DQS_SL_DLL_23_REG, 0x200065); //; #46
-
- DDROut32(DDR_WR_DATA_SLV0_REG, 0x50); //; #95
-
- DDROut32(DDR_WR_DATA_SLV1_REG, 0x50); //; #96
-
- DDROut32(DDR_WR_DATA_SLV2_REG, 0x50); //; #97
-
- DDROut32(DDR_WR_DATA_SLV3_REG, 0x50); //; #98
-
- DDROut32(DDR_ID_REG, 0x0); //; #128
-
- /* Enable ddr controller by taking the controller out of reset */
- DDROut32(DDR_MSTR_CTRL_REG,
- DDRIn32(DDR_MSTR_CTRL_REG) | DDR_OUT_RESET_MASK);
-
-#ifdef PALLADIUM
-
- /* Workaround for early palladium, to be removed for 4.61 */
- DDROut32(SLCR_UNLOCK_REG, 0xDF0D);
-
- DDROut32(TZ_DDR_RAM_REG, 0xffffffff);
-
- DDROut32(SLCR_LOCK_REG, 0x767B);
-
-#endif /* PALLADIUM*/
-}
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/diskio.h b/quad/xsdk_workspace/zybo_fsbl/src/diskio.h
deleted file mode 100644
index 5244efd77904e1023716a9990361208340a461e2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/diskio.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*-----------------------------------------------------------------------
-/ Low level disk interface modlue include file (C)ChaN, 2009
-/-----------------------------------------------------------------------*/
-
-#ifndef _DISKIO
-#define _DISKIO
-
-#include "integer.h"
-
-
-/* Status of Disk Functions */
-typedef BYTE DSTATUS;
-
-/* Results of Disk Functions */
-typedef enum {
- RES_OK = 0, /* 0: Successful */
- RES_ERROR, /* 1: R/W Error */
- RES_WRPRT, /* 2: Write Protected */
- RES_NOTRDY, /* 3: Not Ready */
- RES_PARERR /* 4: Invalid Parameter */
-} DRESULT;
-
-
-/*---------------------------------------*/
-/* Prototypes for disk control functions */
-
-int assign_drives (int, int);
-DSTATUS disk_initialize (BYTE);
-DSTATUS disk_status (BYTE);
-DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
-DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
-DRESULT disk_ioctl (BYTE, BYTE, void*);
-
-
-
-/* Disk Status Bits (DSTATUS) */
-
-#define STA_NOINIT 0x01 /* Drive not initialized */
-#define STA_NODISK 0x02 /* No medium in the drive */
-#define STA_PROTECT 0x04 /* Write protected */
-
-
-/* Command code for disk_ioctrl fucntion */
-
-/* Generic command (mandatory for FatFs) */
-#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
-#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
-#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
-#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
-
-#endif
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ff.c b/quad/xsdk_workspace/zybo_fsbl/src/ff.c
deleted file mode 100644
index 35bfa7e50afb44e44833ae218af15355a7210ea7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/ff.c
+++ /dev/null
@@ -1,3756 +0,0 @@
-/*----------------------------------------------------------------------------/
-/ FatFs - FAT file system module R0.08a (C)ChaN, 2010
-/-----------------------------------------------------------------------------/
-/ FatFs module is a generic FAT file system module for small embedded systems.
-/ This is a free software that opened for education, research and commercial
-/ developments under license policy of following terms.
-/
-/ Copyright (C) 2010, ChaN, all right reserved.
-/
-/ * The FatFs module is a free software and there is NO WARRANTY.
-/ * No restriction on use. You can use, modify and redistribute it for
-/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
-/ * Redistributions of source code must retain the above copyright notice.
-/
-/-----------------------------------------------------------------------------/
-/ Feb 26,'06 R0.00 Prototype.
-/
-/ Apr 29,'06 R0.01 First stable version.
-/
-/ Jun 01,'06 R0.02 Added FAT12 support.
-/ Removed unbuffered mode.
-/ Fixed a problem on small (<32M) partition.
-/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
-/
-/ Sep 22,'06 R0.03 Added f_rename().
-/ Changed option _FS_MINIMUM to _FS_MINIMIZE.
-/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
-/ Fixed f_mkdir() creates incorrect directory on FAT32.
-/
-/ Feb 04,'07 R0.04 Supported multiple drive system.
-/ Changed some interfaces for multiple drive system.
-/ Changed f_mountdrv() to f_mount().
-/ Added f_mkfs().
-/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
-/ Added a capability of extending file size to f_lseek().
-/ Added minimization level 3.
-/ Fixed an endian sensitive code in f_mkfs().
-/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
-/ Added FSInfo support.
-/ Fixed DBCS name can result FR_INVALID_NAME.
-/ Fixed short seek (<= csize) collapses the file object.
-/
-/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs().
-/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
-/ Fixed f_mkdir() on FAT32 creates incorrect directory.
-/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
-/ Fixed off by one error at FAT sub-type determination.
-/ Fixed btr in f_read() can be mistruncated.
-/ Fixed cached sector is not flushed when create and close without write.
-/
-/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets().
-/ Improved performance of f_lseek() on moving to the same or following cluster.
-/
-/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. (_FS_TINY)
-/ Added long file name support.
-/ Added multiple code page support.
-/ Added re-entrancy for multitask operation.
-/ Added auto cluster size selection to f_mkfs().
-/ Added rewind option to f_readdir().
-/ Changed result code of critical errors.
-/ Renamed string functions to avoid name collision.
-/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
-/ Added multiple sector size support.
-/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
-/ Fixed wrong cache control in f_lseek().
-/ Added relative path feature.
-/ Added f_chdir() and f_chdrive().
-/ Added proper case conversion to extended char.
-/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
-/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
-/ Fixed name matching error on the 13 char boundary.
-/ Added a configuration option, _LFN_UNICODE.
-/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
-/
-/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3)
-/ Added file lock feature. (_FS_SHARE)
-/ Added fast seek feature. (_USE_FASTSEEK)
-/ Changed some types on the API, XCHAR->TCHAR.
-/ Changed fname member in the FILINFO structure on Unicode cfg.
-/ String functions support UTF-8 encoding files on Unicode cfg.
-/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
-/ Added sector erase feature. (_USE_ERASE)
-/ Moved file lock semaphore table from fs object to the bss.
-/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
-/ Fixed f_mkfs() creates wrong FAT32 volume.
-/---------------------------------------------------------------------------*/
-#include "xparameters.h"
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-#include "ff.h" /* FatFs configurations and declarations */
-#include "diskio.h" /* Declarations of low level disk I/O functions */
-
-/*--------------------------------------------------------------------------
-
- Module Private Definitions
-
----------------------------------------------------------------------------*/
-
-#if _FATFS != 8255
-#error Wrong include file (ff.h).
-#endif
-
-
-/* Definitions on sector size */
-#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
-#error Wrong sector size.
-#endif
-#if _MAX_SS != 512
-#define SS(fs) ((fs)->ssize) /* Multiple sector size */
-#else
-#define SS(fs) 512U /* Fixed sector size */
-#endif
-
-
-/* Reentrancy related */
-#if _FS_REENTRANT
-#if _USE_LFN == 1
-#error Static LFN work area must not be used in re-entrant configuration.
-#endif
-#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; }
-#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
-#else
-#define ENTER_FF(fs)
-#define LEAVE_FF(fs, res) return res
-#endif
-
-#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
-
-
-/* File shareing feature */
-#if _FS_SHARE
-#if _FS_READONLY
-#error _FS_SHARE must be 0 on read-only cfg.
-#endif
-typedef struct {
- FATFS *fs; /* File ID 1, volume (NULL:blank entry) */
- DWORD clu; /* File ID 2, directory */
- WORD idx; /* File ID 3, directory index */
- WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
-} FILESEM;
-#endif
-
-
-/* Misc definitions */
-#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
-#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);}
-
-
-/* Character code support macros */
-#define IsUpper(c) (((c)>='A')&&((c)<='Z'))
-#define IsLower(c) (((c)>='a')&&((c)<='z'))
-#define IsDigit(c) (((c)>='0')&&((c)<='9'))
-
-#if _DF1S /* Code page is DBCS */
-
-#ifdef _DF2S /* Two 1st byte areas */
-#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
-#else /* One 1st byte area */
-#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
-#endif
-
-#ifdef _DS3S /* Three 2nd byte areas */
-#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
-#else /* Two 2nd byte areas */
-#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
-#endif
-
-#else /* Code page is SBCS */
-
-#define IsDBCS1(c) 0
-#define IsDBCS2(c) 0
-
-#endif /* _DF1S */
-
-
-/* Name status flags */
-#define NS 11 /* Offset of name status byte */
-#define NS_LOSS 0x01 /* Out of 8.3 format */
-#define NS_LFN 0x02 /* Force to create LFN entry */
-#define NS_LAST 0x04 /* Last segment */
-#define NS_BODY 0x08 /* Lower case flag (body) */
-#define NS_EXT 0x10 /* Lower case flag (ext) */
-#define NS_DOT 0x20 /* Dot entry */
-
-
-/* FAT sub-type boundaries */
-/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
-#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */
-#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */
-
-
-/* FatFs refers the members in the FAT structures as byte array instead of
-/ structure member because there are incompatibility of the packing option
-/ between compilers. */
-
-#define BS_jmpBoot 0
-#define BS_OEMName 3
-#define BPB_BytsPerSec 11
-#define BPB_SecPerClus 13
-#define BPB_RsvdSecCnt 14
-#define BPB_NumFATs 16
-#define BPB_RootEntCnt 17
-#define BPB_TotSec16 19
-#define BPB_Media 21
-#define BPB_FATSz16 22
-#define BPB_SecPerTrk 24
-#define BPB_NumHeads 26
-#define BPB_HiddSec 28
-#define BPB_TotSec32 32
-#define BS_DrvNum 36
-#define BS_BootSig 38
-#define BS_VolID 39
-#define BS_VolLab 43
-#define BS_FilSysType 54
-#define BPB_FATSz32 36
-#define BPB_ExtFlags 40
-#define BPB_FSVer 42
-#define BPB_RootClus 44
-#define BPB_FSInfo 48
-#define BPB_BkBootSec 50
-#define BS_DrvNum32 64
-#define BS_BootSig32 66
-#define BS_VolID32 67
-#define BS_VolLab32 71
-#define BS_FilSysType32 82
-#define FSI_LeadSig 0
-#define FSI_StrucSig 484
-#define FSI_Free_Count 488
-#define FSI_Nxt_Free 492
-#define MBR_Table 446
-#define BS_55AA 510
-
-#define DIR_Name 0
-#define DIR_Attr 11
-#define DIR_NTres 12
-#define DIR_CrtTime 14
-#define DIR_CrtDate 16
-#define DIR_FstClusHI 20
-#define DIR_WrtTime 22
-#define DIR_WrtDate 24
-#define DIR_FstClusLO 26
-#define DIR_FileSize 28
-#define LDIR_Ord 0
-#define LDIR_Attr 11
-#define LDIR_Type 12
-#define LDIR_Chksum 13
-#define LDIR_FstClusLO 26
-
-
-
-/*------------------------------------------------------------*/
-/* Work area */
-
-#if _VOLUMES
-static
-FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
-#else
-#error Number of drives must not be 0.
-#endif
-
-static
-WORD Fsid; /* File system mount ID */
-
-#if _FS_RPATH
-static
-BYTE CurrVol; /* Current drive */
-#endif
-
-#if _FS_SHARE
-static
-FILESEM Files[_FS_SHARE]; /* File lock semaphores */
-#endif
-
-#if _USE_LFN == 0 /* No LFN */
-#define DEF_NAMEBUF BYTE sfn[12]
-#define INIT_BUF(dobj) (dobj).fn = sfn
-#define FREE_BUF()
-
-#elif _USE_LFN == 1 /* LFN with static LFN working buffer */
-static WCHAR LfnBuf[_MAX_LFN+1];
-#define DEF_NAMEBUF BYTE sfn[12]
-#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
-#define FREE_BUF()
-
-#elif _USE_LFN == 2 /* LFN with dynamic LFN working buffer on the stack */
-#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
-#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; }
-#define FREE_BUF()
-
-#elif _USE_LFN == 3 /* LFN with dynamic LFN working buffer on the heap */
-#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn
-#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
- if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
- (dobj).lfn = lfn; (dobj).fn = sfn; }
-#define FREE_BUF() ff_memfree(lfn)
-
-#else
-#error Wrong LFN configuration.
-#endif
-
-
-
-
-/*--------------------------------------------------------------------------
-
- Module Private Functions
-
----------------------------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------------------*/
-/* String functions */
-/*-----------------------------------------------------------------------*/
-
-/* Copy memory to memory */
-static
-void mem_cpy (void* dst, const void* src, UINT cnt) {
- BYTE *d = (BYTE*)dst;
- const BYTE *s = (const BYTE*)src;
-
-#if _WORD_ACCESS == 1
- while (cnt >= sizeof(int)) {
- *(int*)d = *(int*)s;
- d += sizeof(int); s += sizeof(int);
- cnt -= sizeof(int);
- }
-#endif
- while (cnt--)
- *d++ = *s++;
-}
-
-/* Fill memory */
-static
-void mem_set (void* dst, int val, UINT cnt) {
- BYTE *d = (BYTE*)dst;
-
- while (cnt--)
- *d++ = (BYTE)val;
-}
-
-/* Compare memory to memory */
-static
-int mem_cmp (const void* dst, const void* src, UINT cnt) {
- const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
- int r = 0;
-
- while (cnt-- && (r = *d++ - *s++) == 0) ;
- return r;
-}
-
-/* Check if chr is contained in the string */
-static
-int chk_chr (const char* str, int chr) {
- while (*str && *str != chr) str++;
- return *str;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Request/Release grant to access the volume */
-/*-----------------------------------------------------------------------*/
-#if _FS_REENTRANT
-
-static
-int lock_fs (
- FATFS *fs /* File system object */
-)
-{
- return ff_req_grant(fs->sobj);
-}
-
-
-static
-void unlock_fs (
- FATFS *fs, /* File system object */
- FRESULT res /* Result code to be returned */
-)
-{
- if (res != FR_NOT_ENABLED &&
- res != FR_INVALID_DRIVE &&
- res != FR_INVALID_OBJECT &&
- res != FR_TIMEOUT) {
- ff_rel_grant(fs->sobj);
- }
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* File shareing control functions */
-/*-----------------------------------------------------------------------*/
-#if _FS_SHARE
-
-static
-FRESULT chk_lock ( /* Check if the file can be accessed */
- DIR* dj, /* Directory object pointing the file to be checked */
- int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
-)
-{
- UINT i, be;
-
- /* Search file semaphore table */
- for (i = be = 0; i < _FS_SHARE; i++) {
- if (Files[i].fs) { /* Existing entry */
- if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */
- Files[i].clu == dj->sclust &&
- Files[i].idx == dj->index) break;
- } else { /* Blank entry */
- be++;
- }
- }
- if (i == _FS_SHARE) /* The file is not opened */
- return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */
-
- /* The file has been opened. Reject any open against writing file and all write mode open */
- return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
-}
-
-
-static
-int enq_lock ( /* Check if an entry is available for a new file */
- FATFS* fs /* File system object */
-)
-{
- UINT i;
-
- for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ;
- return (i == _FS_SHARE) ? 0 : 1;
-}
-
-
-static
-UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */
- DIR* dj, /* Directory object pointing the file to register or increment */
- int acc /* Desired access mode (0:Read, !0:Write) */
-)
-{
- UINT i;
-
-
- for (i = 0; i < _FS_SHARE; i++) { /* Find the file */
- if (Files[i].fs == dj->fs &&
- Files[i].clu == dj->sclust &&
- Files[i].idx == dj->index) break;
- }
-
- if (i == _FS_SHARE) { /* Not opened. Register it as new. */
- for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ;
- if (i == _FS_SHARE) return 0; /* No space to register (int err) */
- Files[i].fs = dj->fs;
- Files[i].clu = dj->sclust;
- Files[i].idx = dj->index;
- Files[i].ctr = 0;
- }
-
- if (acc && Files[i].ctr) return 0; /* Access violation (int err) */
-
- Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
-
- return i + 1;
-}
-
-
-static
-FRESULT dec_lock ( /* Decrement file open counter */
- UINT i /* Semaphore index */
-)
-{
- WORD n;
- FRESULT res;
-
-
- if (--i < _FS_SHARE) {
- n = Files[i].ctr;
- if (n == 0x100) n = 0;
- if (n) n--;
- Files[i].ctr = n;
- if (!n) Files[i].fs = 0;
- res = FR_OK;
- } else {
- res = FR_INT_ERR;
- }
- return res;
-}
-
-
-static
-void clear_lock ( /* Clear lock entries of the volume */
- FATFS *fs
-)
-{
- UINT i;
-
- for (i = 0; i < _FS_SHARE; i++) {
- if (Files[i].fs == fs) Files[i].fs = 0;
- }
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change window offset */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT move_window (
- FATFS *fs, /* File system object */
- DWORD sector /* Sector number to make appearance in the fs->win[] */
-) /* Move to zero only writes back dirty window */
-{
- DWORD wsect;
-
- wsect = fs->winsect;
- if (wsect != sector) { /* Changed current window */
-#if !_FS_READONLY
- if (fs->wflag) { /* Write back dirty window if needed */
- if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
- return FR_DISK_ERR;
- fs->wflag = 0;
- if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */
- BYTE nf;
- for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */
- wsect += fs->fsize;
- disk_write(fs->drv, fs->win, wsect, 1);
- }
- }
- }
-#endif
- if (sector) {
- if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
- return FR_DISK_ERR;
- fs->winsect = sector;
- }
- }
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Clean-up cached data */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */
- FATFS *fs /* File system object */
-)
-{
- FRESULT res;
-
-
- res = move_window(fs, 0);
- if (res == FR_OK) {
- /* Update FSInfo sector if needed */
- if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
- fs->winsect = 0;
- mem_set(fs->win, 0, 512);
- ST_WORD(fs->win+BS_55AA, 0xAA55);
- ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
- ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
- ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
- ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
- disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
- fs->fsi_flag = 0;
- }
- /* Make sure that no pending write process in the physical drive */
- if (disk_ioctl(fs->drv, CTRL_SYNC, (void*)0) != RES_OK)
- res = FR_DISK_ERR;
- }
-
- return res;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get sector# from cluster# */
-/*-----------------------------------------------------------------------*/
-
-
-DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to be converted */
-)
-{
- clst -= 2;
- if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */
- return clst * fs->csize + fs->database;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Read value of a FAT entry */
-/*-----------------------------------------------------------------------*/
-
-
-DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to get the link information */
-)
-{
- UINT wc, bc;
- BYTE *p;
-
-
- if (clst < 2 || clst >= fs->n_fatent) /* Chack range */
- return 1;
-
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = (UINT)clst; bc += bc / 2;
- if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
- wc = fs->win[bc % SS(fs)]; bc++;
- if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
- wc |= fs->win[bc % SS(fs)] << 8;
- return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
-
- case FS_FAT16 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
- p = &fs->win[clst * 2 % SS(fs)];
- return LD_WORD(p);
-
- case FS_FAT32 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
- p = &fs->win[clst * 4 % SS(fs)];
- return LD_DWORD(p) & 0x0FFFFFFF;
- }
-
- return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Change value of a FAT entry */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-
-FRESULT put_fat (
- FATFS *fs, /* File system object */
- DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
- DWORD val /* New value to mark the cluster */
-)
-{
- UINT bc;
- BYTE *p;
- FRESULT res;
-
-
- if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
- res = FR_INT_ERR;
-
- } else {
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = clst; bc += bc / 2;
- res = move_window(fs, fs->fatbase + (bc / SS(fs)));
- if (res != FR_OK) break;
- p = &fs->win[bc % SS(fs)];
- *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
- bc++;
- fs->wflag = 1;
- res = move_window(fs, fs->fatbase + (bc / SS(fs)));
- if (res != FR_OK) break;
- p = &fs->win[bc % SS(fs)];
- *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
- break;
-
- case FS_FAT16 :
- res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
- if (res != FR_OK) break;
- p = &fs->win[clst * 2 % SS(fs)];
- ST_WORD(p, (WORD)val);
- break;
-
- case FS_FAT32 :
- res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
- if (res != FR_OK) break;
- p = &fs->win[clst * 4 % SS(fs)];
- val |= LD_DWORD(p) & 0xF0000000;
- ST_DWORD(p, val);
- break;
-
- default :
- res = FR_INT_ERR;
- }
- fs->wflag = 1;
- }
-
- return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Remove a cluster chain */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT remove_chain (
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to remove a chain from */
-)
-{
- FRESULT res;
- DWORD nxt;
-#if _USE_ERASE
- DWORD scl = clst, ecl = clst, resion[2];
-#endif
-
- if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
- res = FR_INT_ERR;
-
- } else {
- res = FR_OK;
- while (clst < fs->n_fatent) { /* Not a last link? */
- nxt = get_fat(fs, clst); /* Get cluster status */
- if (nxt == 0) break; /* Empty cluster? */
- if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */
- if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */
- res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */
- if (res != FR_OK) break;
- if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */
- fs->free_clust++;
- fs->fsi_flag = 1;
- }
-#if _USE_ERASE
- if (ecl + 1 == nxt) { /* Next cluster is contiguous */
- ecl = nxt;
- } else { /* End of contiguous clusters */
- resion[0] = clust2sect(fs, scl); /* Start sector */
- resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
- disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */
- scl = ecl = nxt;
- }
-#endif
- clst = nxt; /* Next cluster */
- }
- }
-
- return res;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Stretch or Create a cluster chain */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to stretch. 0 means create a new chain. */
-)
-{
- DWORD cs, ncl, scl;
- FRESULT res;
-
-
- if (clst == 0) { /* Create a new chain */
- scl = fs->last_clust; /* Get suggested start point */
- if (!scl || scl >= fs->n_fatent) scl = 1;
- }
- else { /* Stretch the current chain */
- cs = get_fat(fs, clst); /* Check the cluster status */
- if (cs < 2) return 1; /* It is an invalid cluster */
- if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
- scl = clst;
- }
-
- ncl = scl; /* Start cluster */
- for (;;) {
- ncl++; /* Next cluster */
- if (ncl >= fs->n_fatent) { /* Wrap around */
- ncl = 2;
- if (ncl > scl) return 0; /* No free cluster */
- }
- cs = get_fat(fs, ncl); /* Get the cluster status */
- if (cs == 0) break; /* Found a free cluster */
- if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
- return cs;
- if (ncl == scl) return 0; /* No free cluster */
- }
-
- res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */
- if (res == FR_OK && clst != 0) {
- res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */
- }
- if (res == FR_OK) {
- fs->last_clust = ncl; /* Update FSINFO */
- if (fs->free_clust != 0xFFFFFFFF) {
- fs->free_clust--;
- fs->fsi_flag = 1;
- }
- } else {
- ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
- }
-
- return ncl; /* Return new cluster number or error code */
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Set directory index */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_sdi (
- DIR *dj, /* Pointer to directory object */
- WORD idx /* Directory index number */
-)
-{
- DWORD clst;
- WORD ic;
-
-
- dj->index = idx;
- clst = dj->sclust;
- if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */
- return FR_INT_ERR;
- if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */
- clst = dj->fs->dirbase;
-
- if (clst == 0) { /* Static table (root-dir in FAT12/16) */
- dj->clust = clst;
- if (idx >= dj->fs->n_rootdir) /* Index is out of range */
- return FR_INT_ERR;
- dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */
- }
- else { /* Dynamic table (sub-dirs or root-dir in FAT32) */
- ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */
- while (idx >= ic) { /* Follow cluster chain */
- clst = get_fat(dj->fs, clst); /* Get next cluster */
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
- if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */
- return FR_INT_ERR;
- idx -= ic;
- }
- dj->clust = clst;
- dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */
- }
-
- dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */
-
- return FR_OK; /* Seek succeeded */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Move directory index next */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */
- DIR *dj, /* Pointer to directory object */
- int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
-)
-{
- DWORD clst;
- WORD i;
-
-
- i = dj->index + 1;
- if (!i || !dj->sect) /* Report EOT when index has reached 65535 */
- return FR_NO_FILE;
-
- if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */
- dj->sect++; /* Next sector */
-
- if (dj->clust == 0) { /* Static table */
- if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */
- return FR_NO_FILE;
- }
- else { /* Dynamic table */
- if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */
- clst = get_fat(dj->fs, dj->clust); /* Get next cluster */
- if (clst <= 1) return FR_INT_ERR;
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
- if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */
-#if !_FS_READONLY
- BYTE c;
- if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */
- clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */
- if (clst == 0) return FR_DENIED; /* No free cluster */
- if (clst == 1) return FR_INT_ERR;
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
- /* Clean-up stretched table */
- if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */
- mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */
- dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */
- for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */
- dj->fs->wflag = 1;
- if (move_window(dj->fs, 0)) return FR_DISK_ERR;
- dj->fs->winsect++;
- }
- dj->fs->winsect -= c; /* Rewind window address */
-#else
- return FR_NO_FILE; /* Report EOT */
-#endif
- }
- dj->clust = clst; /* Initialize data for new cluster */
- dj->sect = clust2sect(dj->fs, clst);
- }
- }
- }
-
- dj->index = i;
- dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32;
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-static
-const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */
-
-
-static
-int cmp_lfn ( /* 1:Matched, 0:Not matched */
- WCHAR *lfnbuf, /* Pointer to the LFN to be compared */
- BYTE *dir /* Pointer to the directory entry containing a part of LFN */
-)
-{
- UINT i, s;
- WCHAR wc, uc;
-
-
- i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */
- s = 0; wc = 1;
- do {
- uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
- if (wc) { /* Last char has not been processed */
- wc = ff_wtoupper(uc); /* Convert it to upper case */
- if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */
- return 0; /* Not matched */
- } else {
- if (uc != 0xFFFF) return 0; /* Check filler */
- }
- } while (++s < 13); /* Repeat until all chars in the entry are checked */
-
- if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */
- return 0;
-
- return 1; /* The part of LFN matched */
-}
-
-
-
-static
-int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */
- WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */
- BYTE *dir /* Pointer to the directory entry */
-)
-{
- UINT i, s;
- WCHAR wc, uc;
-
-
- i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
-
- s = 0; wc = 1;
- do {
- uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
- if (wc) { /* Last char has not been processed */
- if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
- lfnbuf[i++] = wc = uc; /* Store it */
- } else {
- if (uc != 0xFFFF) return 0; /* Check filler */
- }
- } while (++s < 13); /* Read all character in the entry */
-
- if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */
- if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
- lfnbuf[i] = 0;
- }
-
- return 1;
-}
-
-
-#if !_FS_READONLY
-static
-void fit_lfn (
- const WCHAR *lfnbuf, /* Pointer to the LFN buffer */
- BYTE *dir, /* Pointer to the directory entry */
- BYTE ord, /* LFN order (1-20) */
- BYTE sum /* SFN sum */
-)
-{
- UINT i, s;
- WCHAR wc;
-
-
- dir[LDIR_Chksum] = sum; /* Set check sum */
- dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
- dir[LDIR_Type] = 0;
- ST_WORD(dir+LDIR_FstClusLO, 0);
-
- i = (ord - 1) * 13; /* Get offset in the LFN buffer */
- s = wc = 0;
- do {
- if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */
- ST_WORD(dir+LfnOfs[s], wc); /* Put it */
- if (!wc) wc = 0xFFFF; /* Padding chars following last char */
- } while (++s < 13);
- if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */
- dir[LDIR_Ord] = ord; /* Set the LFN order */
-}
-
-#endif
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create numbered name */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-void gen_numname (
- BYTE *dst, /* Pointer to generated SFN */
- const BYTE *src, /* Pointer to source SFN to be modified */
- const WCHAR *lfn, /* Pointer to LFN */
- WORD seq /* Sequence number */
-)
-{
- BYTE ns[8], c;
- UINT i, j;
-
-
- mem_cpy(dst, src, 11);
-
- if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */
- do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn);
- }
-
- /* itoa */
- i = 7;
- do {
- c = (seq % 16) + '0';
- if (c > '9') c += 7;
- ns[i--] = c;
- seq /= 16;
- } while (seq);
- ns[i] = '~';
-
- /* Append the number */
- for (j = 0; j < i && dst[j] != ' '; j++) {
- if (IsDBCS1(dst[j])) {
- if (j == i - 1) break;
- j++;
- }
- }
- do {
- dst[j++] = (i < 8) ? ns[i++] : ' ';
- } while (j < 8);
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Calculate sum of an SFN */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-static
-BYTE sum_sfn (
- const BYTE *dir /* Ptr to directory entry */
-)
-{
- BYTE sum = 0;
- UINT n = 11;
-
- do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
- return sum;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Find an object in the directory */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_find (
- DIR *dj /* Pointer to the directory object linked to the file name */
-)
-{
- FRESULT res;
- BYTE c, *dir;
-#if _USE_LFN
- BYTE a, ord, sum;
-#endif
-
- res = dir_sdi(dj, 0); /* Rewind directory object */
- if (res != FR_OK) return res;
-
-#if _USE_LFN
- ord = sum = 0xFF;
-#endif
- do {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- dir = dj->dir; /* Ptr to the directory entry of current index */
- c = dir[DIR_Name];
- if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
-#if _USE_LFN /* LFN configuration */
- a = dir[DIR_Attr] & AM_MASK;
- if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
- ord = 0xFF;
- } else {
- if (a == AM_LFN) { /* An LFN entry is found */
- if (dj->lfn) {
- if (c & 0x40) { /* Is it start of LFN sequence? */
- sum = dir[LDIR_Chksum];
- c &= 0xBF; ord = c; /* LFN start order */
- dj->lfn_idx = dj->index;
- }
- /* Check validity of the LFN entry and compare it with given name */
- ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
- }
- } else { /* An SFN entry is found */
- if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
- ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */
- if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */
- }
- }
-#else /* Non LFN configuration */
- if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
- break;
-#endif
- res = dir_next(dj, 0); /* Next entry */
- } while (res == FR_OK);
-
- return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read an object from the directory */
-/*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1
-static
-FRESULT dir_read (
- DIR *dj /* Pointer to the directory object that pointing the entry to be read */
-)
-{
- FRESULT res;
- BYTE c, *dir;
-#if _USE_LFN
- BYTE a, ord = 0xFF, sum = 0xFF;
-#endif
-
- res = FR_NO_FILE;
- while (dj->sect) {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- dir = dj->dir; /* Ptr to the directory entry of current index */
- c = dir[DIR_Name];
- if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
-#if _USE_LFN /* LFN configuration */
- a = dir[DIR_Attr] & AM_MASK;
- if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
- ord = 0xFF;
- } else {
- if (a == AM_LFN) { /* An LFN entry is found */
- if (c & 0x40) { /* Is it start of LFN sequence? */
- sum = dir[LDIR_Chksum];
- c &= 0xBF; ord = c;
- dj->lfn_idx = dj->index;
- }
- /* Check LFN validity and capture it */
- ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
- } else { /* An SFN entry is found */
- if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */
- dj->lfn_idx = 0xFFFF; /* It has no LFN. */
- break;
- }
- }
-#else /* Non LFN configuration */
- if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */
- break;
-#endif
- res = dir_next(dj, 0); /* Next entry */
- if (res != FR_OK) break;
- }
-
- if (res != FR_OK) dj->sect = 0;
-
- return res;
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Register an object to the directory */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
- DIR *dj /* Target directory with object name to be created */
-)
-{
- FRESULT res;
- BYTE c, *dir;
-#if _USE_LFN /* LFN configuration */
- WORD n, ne, is;
- BYTE sn[12], *fn, sum;
- WCHAR *lfn;
-
-
- fn = dj->fn; lfn = dj->lfn;
- mem_cpy(sn, fn, 12);
-
- if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */
- return FR_INVALID_NAME;
-
- if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
- fn[NS] = 0; dj->lfn = 0; /* Find only SFN */
- for (n = 1; n < 100; n++) {
- gen_numname(fn, sn, lfn, n); /* Generate a numbered name */
- res = dir_find(dj); /* Check if the name collides with existing SFN */
- if (res != FR_OK) break;
- }
- if (n == 100) return FR_DENIED; /* Abort if too many collisions */
- if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
- fn[NS] = sn[NS]; dj->lfn = lfn;
- }
-
- if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */
- for (ne = 0; lfn[ne]; ne++) ;
- ne = (ne + 25) / 13;
- } else { /* Otherwise reserve only an SFN entry. */
- ne = 1;
- }
-
- /* Reserve contiguous entries */
- res = dir_sdi(dj, 0);
- if (res != FR_OK) return res;
- n = is = 0;
- do {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- c = *dj->dir; /* Check the entry status */
- if (c == 0xE5 || c == 0) { /* Is it a blank entry? */
- if (n == 0) is = dj->index; /* First index of the contiguous entry */
- if (++n == ne) break; /* A contiguous entry that required count is found */
- } else {
- n = 0; /* Not a blank entry. Restart to search */
- }
- res = dir_next(dj, 1); /* Next entry with table stretch */
- } while (res == FR_OK);
-
- if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */
- res = dir_sdi(dj, is);
- if (res == FR_OK) {
- sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */
- ne--;
- do { /* Store LFN entries in bottom first */
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
- dj->fs->wflag = 1;
- res = dir_next(dj, 0); /* Next entry */
- } while (res == FR_OK && --ne);
- }
- }
-
-#else /* Non LFN configuration */
- res = dir_sdi(dj, 0);
- if (res == FR_OK) {
- do { /* Find a blank entry for the SFN */
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- c = *dj->dir;
- if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */
- res = dir_next(dj, 1); /* Next entry with table stretch */
- } while (res == FR_OK);
- }
-#endif
-
- if (res == FR_OK) { /* Initialize the SFN entry */
- res = move_window(dj->fs, dj->sect);
- if (res == FR_OK) {
- dir = dj->dir;
- mem_set(dir, 0, 32); /* Clean the entry */
- mem_cpy(dir, dj->fn, 11); /* Put SFN */
-#if _USE_LFN
- dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */
-#endif
- dj->fs->wflag = 1;
- }
- }
-
- return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Remove an object from the directory */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY && !_FS_MINIMIZE
-static
-FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */
- DIR *dj /* Directory object pointing the entry to be removed */
-)
-{
- FRESULT res;
-#if _USE_LFN /* LFN configuration */
- WORD i;
-
- i = dj->index; /* SFN index */
- res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */
- if (res == FR_OK) {
- do {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- *dj->dir = 0xE5; /* Mark the entry "deleted" */
- dj->fs->wflag = 1;
- if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */
- res = dir_next(dj, 0); /* Next entry */
- } while (res == FR_OK);
- if (res == FR_NO_FILE) res = FR_INT_ERR;
- }
-
-#else /* Non LFN configuration */
- res = dir_sdi(dj, dj->index);
- if (res == FR_OK) {
- res = move_window(dj->fs, dj->sect);
- if (res == FR_OK) {
- *dj->dir = 0xE5; /* Mark the entry "deleted" */
- dj->fs->wflag = 1;
- }
- }
-#endif
-
- return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Pick a segment and create the object name in directory form */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT create_name (
- DIR *dj, /* Pointer to the directory object */
- const TCHAR **path /* Pointer to pointer to the segment in the path string */
-)
-{
-#ifdef _EXCVT
- static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */
-#endif
-
-#if _USE_LFN /* LFN configuration */
- BYTE b, cf;
- WCHAR w, *lfn;
- UINT i, ni, si, di;
- const TCHAR *p;
-
- /* Create LFN in Unicode */
- si = di = 0;
- p = *path;
- lfn = dj->lfn;
- for (;;) {
- w = p[si++]; /* Get a character */
- if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */
- if (di >= _MAX_LFN) /* Reject too long name */
- return FR_INVALID_NAME;
-#if !_LFN_UNICODE
- w &= 0xFF;
- if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
- b = (BYTE)p[si++]; /* Get 2nd byte */
- if (!IsDBCS2(b))
- return FR_INVALID_NAME; /* Reject invalid sequence */
- w = (w << 8) + b; /* Create a DBC */
- }
- w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */
- if (!w) return FR_INVALID_NAME; /* Reject invalid code */
-#endif
- if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
- return FR_INVALID_NAME;
- lfn[di++] = w; /* Store the Unicode char */
- }
- *path = &p[si]; /* Return pointer to the next segment */
- cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
-#if _FS_RPATH
- if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
- (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
- lfn[di] = 0;
- for (i = 0; i < 11; i++)
- dj->fn[i] = (i < di) ? '.' : ' ';
- dj->fn[i] = cf | NS_DOT; /* This is a dot entry */
- return FR_OK;
- }
-#endif
- while (di) { /* Strip trailing spaces and dots */
- w = lfn[di-1];
- if (w != ' ' && w != '.') break;
- di--;
- }
- if (!di) return FR_INVALID_NAME; /* Reject nul string */
-
- lfn[di] = 0; /* LFN is created */
-
- /* Create SFN in directory form */
- mem_set(dj->fn, ' ', 11);
- for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */
- if (si) cf |= NS_LOSS | NS_LFN;
- while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */
-
- b = i = 0; ni = 8;
- for (;;) {
- w = lfn[si++]; /* Get an LFN char */
- if (!w) break; /* Break on end of the LFN */
- if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */
- cf |= NS_LOSS | NS_LFN; continue;
- }
-
- if (i >= ni || si == di) { /* Extension or end of SFN */
- if (ni == 11) { /* Long extension */
- cf |= NS_LOSS | NS_LFN; break;
- }
- if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */
- if (si > di) break; /* No extension */
- si = di; i = 8; ni = 11; /* Enter extension section */
- b <<= 2; continue;
- }
-
- if (w >= 0x80) { /* Non ASCII char */
-#ifdef _EXCVT
- w = ff_convert(w, 0); /* Unicode -> OEM code */
- if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */
-#else
- w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */
-#endif
- cf |= NS_LFN; /* Force create LFN entry */
- }
-
- if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */
- if (i >= ni - 1) {
- cf |= NS_LOSS | NS_LFN; i = ni; continue;
- }
- dj->fn[i++] = (BYTE)(w >> 8);
- } else { /* Single byte char */
- if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */
- w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
- } else {
- if (IsUpper(w)) { /* ASCII large capital */
- b |= 2;
- } else {
- if (IsLower(w)) { /* ASCII small capital */
- b |= 1; w -= 0x20;
- }
- }
- }
- }
- dj->fn[i++] = (BYTE)w;
- }
-
- if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */
-
- if (ni == 8) b <<= 2;
- if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */
- cf |= NS_LFN;
- if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */
- if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */
- if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
- }
-
- dj->fn[NS] = cf; /* SFN is created */
-
- return FR_OK;
-
-
-#else /* Non-LFN configuration */
- BYTE b, c, d, *sfn;
- UINT ni, si, i;
- const char *p;
-
- /* Create file name in directory form */
- sfn = dj->fn;
- mem_set(sfn, ' ', 11);
- si = i = b = 0; ni = 8;
- p = *path;
-#if _FS_RPATH
- if (p[si] == '.') { /* Is this a dot entry? */
- for (;;) {
- c = (BYTE)p[si++];
- if (c != '.' || si >= 3) break;
- sfn[i++] = c;
- }
- if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
- *path = &p[si]; /* Return pointer to the next segment */
- sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
- return FR_OK;
- }
-#endif
- for (;;) {
- c = (BYTE)p[si++];
- if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */
- if (c == '.' || i >= ni) {
- if (ni != 8 || c != '.') return FR_INVALID_NAME;
- i = 8; ni = 11;
- b <<= 2; continue;
- }
- if (c >= 0x80) { /* Extended char? */
- b |= 3; /* Eliminate NT flag */
-#ifdef _EXCVT
- c = excvt[c-0x80]; /* Upper conversion (SBCS) */
-#else
-#if !_DF1S /* ASCII only cfg */
- return FR_INVALID_NAME;
-#endif
-#endif
- }
- if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
- d = (BYTE)p[si++]; /* Get 2nd byte */
- if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */
- return FR_INVALID_NAME;
- sfn[i++] = c;
- sfn[i++] = d;
- } else { /* Single byte code */
- if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */
- return FR_INVALID_NAME;
- if (IsUpper(c)) { /* ASCII large capital? */
- b |= 2;
- } else {
- if (IsLower(c)) { /* ASCII small capital? */
- b |= 1; c -= 0x20;
- }
- }
- sfn[i++] = c;
- }
- }
- *path = &p[si]; /* Return pointer to the next segment */
- c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
-
- if (!i) return FR_INVALID_NAME; /* Reject nul string */
- if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */
-
- if (ni == 8) b <<= 2;
- if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */
- if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */
-
- sfn[NS] = c; /* Store NT flag, File name is created */
-
- return FR_OK;
-#endif
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get file information from directory entry */
-/*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1
-static
-void get_fileinfo ( /* No return code */
- DIR *dj, /* Pointer to the directory object */
- FILINFO *fno /* Pointer to the file information to be filled */
-)
-{
- UINT i;
- BYTE nt, *dir;
- TCHAR *p, c;
-
-
- p = fno->fname;
- if (dj->sect) {
- dir = dj->dir;
- nt = dir[DIR_NTres]; /* NT flag */
- for (i = 0; i < 8; i++) { /* Copy name body */
- c = dir[i];
- if (c == ' ') break;
- if (c == 0x05) c = (TCHAR)0xE5;
- if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
-#if _LFN_UNICODE
- if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
- c = (c << 8) | dir[++i];
- c = ff_convert(c, 1);
- if (!c) c = '?';
-#endif
- *p++ = c;
- }
- if (dir[8] != ' ') { /* Copy name extension */
- *p++ = '.';
- for (i = 8; i < 11; i++) {
- c = dir[i];
- if (c == ' ') break;
- if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
-#if _LFN_UNICODE
- if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
- c = (c << 8) | dir[++i];
- c = ff_convert(c, 1);
- if (!c) c = '?';
-#endif
- *p++ = c;
- }
- }
- fno->fattrib = dir[DIR_Attr]; /* Attribute */
- fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */
- fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */
- fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */
- }
- *p = 0; /* Terminate SFN str by a \0 */
-
-#if _USE_LFN
- if (fno->lfname && fno->lfsize) {
- TCHAR *tp = fno->lfname;
- WCHAR w, *lfn;
-
- i = 0;
- if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
- lfn = dj->lfn;
- while ((w = *lfn++) != 0) { /* Get an LFN char */
-#if !_LFN_UNICODE
- w = ff_convert(w, 0); /* Unicode -> OEM conversion */
- if (!w) { i = 0; break; } /* Could not convert, no LFN */
- if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */
- tp[i++] = (TCHAR)(w >> 8);
-#endif
- if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */
- tp[i++] = (TCHAR)w;
- }
- }
- tp[i] = 0; /* Terminate the LFN str by a \0 */
- }
-#endif
-}
-#endif /* _FS_MINIMIZE <= 1 */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Follow a file path */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
- DIR *dj, /* Directory object to return last directory and found object */
- const TCHAR *path /* Full-path string to find a file or directory */
-)
-{
- FRESULT res;
- BYTE *dir, ns;
-
-
-#if _FS_RPATH
- if (*path == '/' || *path == '\\') { /* There is a heading separator */
- path++; dj->sclust = 0; /* Strip it and start from the root dir */
- } else { /* No heading separator */
- dj->sclust = dj->fs->cdir; /* Start from the current dir */
- }
-#else
- if (*path == '/' || *path == '\\') /* Strip heading separator if exist */
- path++;
- dj->sclust = 0; /* Start from the root dir */
-#endif
-
- if ((UINT)*path < ' ') { /* Nul path means the start directory itself */
- res = dir_sdi(dj, 0);
- dj->dir = 0;
-
- } else { /* Follow path */
- for (;;) {
- res = create_name(dj, &path); /* Get a segment */
- if (res != FR_OK) break;
- res = dir_find(dj); /* Find it */
- ns = *(dj->fn+NS);
- if (res != FR_OK) { /* Failed to find the object */
- if (res != FR_NO_FILE) break; /* Abort if any hard error occured */
- /* Object not found */
- if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */
- dj->sclust = 0; dj->dir = 0; /* It is the root dir */
- res = FR_OK;
- if (!(ns & NS_LAST)) continue;
- } else { /* Could not find the object */
- if (!(ns & NS_LAST)) res = FR_NO_PATH;
- }
- break;
- }
- if (ns & NS_LAST) break; /* Last segment match. Function completed. */
- dir = dj->dir; /* There is next segment. Follow the sub directory */
- if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
- res = FR_NO_PATH; break;
- }
- dj->sclust = LD_CLUST(dir);
- }
- }
-
- return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Load boot record and check if it is an FAT boot record */
-/*-----------------------------------------------------------------------*/
-
-static
-BYTE check_fs ( /* 0:The FAT BR, 1:Valid BR but not an FAT, 2:Not a BR, 3:Disk error */
- FATFS *fs, /* File system object */
- DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */
-)
-{
- if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) { /* Load boot record */
- return 3;
- }
-
- if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) { /* Check record signature (always placed at offset 510 even if the sector size is >512) */
- return 2;
- }
-
- if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */
- return 0;
- if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
- return 0;
-
- return 1;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file system object is valid or not */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */
- const TCHAR **path, /* Pointer to pointer to the path name (drive number) */
- FATFS **rfs, /* Pointer to pointer to the found file system object */
- BYTE chk_wp /* !=0: Check media write protection for write access */
-)
-{
- BYTE fmt, b, *tbl;
- UINT vol;
- DSTATUS stat;
- DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
- WORD nrsv;
- const TCHAR *p = *path;
- FATFS *fs;
-
- /* Get logical drive number from the path name */
- vol = p[0] - '0'; /* Is there a drive number? */
- if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */
- p += 2; *path = p; /* Return pointer to the path name */
- } else { /* No drive number is given */
-#if _FS_RPATH
- vol = CurrVol; /* Use current drive */
-#else
- vol = 0; /* Use drive 0 */
-#endif
- }
-
- /* Check if the logical drive is valid or not */
- if (vol >= _VOLUMES) /* Is the drive number valid? */
- return FR_INVALID_DRIVE;
- *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */
- if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */
-
- ENTER_FF(fs); /* Lock file system */
-
- if (fs->fs_type) { /* If the logical drive has been mounted */
- stat = disk_status(fs->drv);
- if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */
-#if !_FS_READONLY
- if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */
- return FR_WRITE_PROTECTED;
-#endif
- return FR_OK; /* The file system object is valid */
- }
- }
-
- /* The logical drive must be mounted. */
- /* Following code attempts to mount a volume. (analyze BPB and initialize the fs object) */
-
- fs->fs_type = 0; /* Clear the file system object */
- fs->drv = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */
- stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */
- if (stat & STA_NOINIT) /* Check if the initialization succeeded */
- return FR_NOT_READY; /* Failed to initialize due to no media or hard error */
-#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */
- if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
- return FR_DISK_ERR;
-#endif
-#if !_FS_READONLY
- if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */
- return FR_WRITE_PROTECTED;
-#endif
- /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */
- fmt = check_fs(fs, bsect = 0); /* Check sector 0 if it is a VBR */
- if (fmt == 1) { /* Not an FAT-VBR, the disk may be partitioned */
- /* Check the partition listed in top of the partition table */
- tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */
- if (tbl[4]) { /* Is the partition existing? */
- bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */
- fmt = check_fs(fs, bsect); /* Check the partition */
- }
- }
- if (fmt == 3) return FR_DISK_ERR;
- if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */
-
- /* Following code initializes the file system object */
-
- if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) { /* (BPB_BytsPerSec must be equal to the physical sector size) */
-
- return FR_NO_FILESYSTEM;
- }
-
- fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */
- if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
- fs->fsize = fasize;
-
- fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */
- if (b != 1 && b != 2) {
- return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
- }
- fasize *= b; /* Number of sectors for FAT area */
-
- fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */
- if (!b || (b & (b - 1))) {
- return FR_NO_FILESYSTEM; /* (Must be power of 2) */
- }
-
- fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */
- if (fs->n_rootdir % (SS(fs) / 32)) {
- return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */
- }
-
- tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */
- if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
-
- nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */
- if (!nrsv) {
- return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */
- }
-
- /* Determine the FAT sub type */
- sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / 32); /* RSV+FAT+DIR */
- if (tsect < sysect) {
- return FR_NO_FILESYSTEM; /* (Invalid volume size) */
- }
- nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
- if (!nclst) {
- return FR_NO_FILESYSTEM; /* (Invalid volume size) */
- }
- fmt = FS_FAT12;
- if (nclst >= MIN_FAT16) fmt = FS_FAT16;
- if (nclst >= MIN_FAT32) fmt = FS_FAT32;
-
- /* Boundaries and Limits */
- fs->n_fatent = nclst + 2; /* Number of FAT entries */
- fs->database = bsect + sysect; /* Data start sector */
- fs->fatbase = bsect + nrsv; /* FAT start sector */
- if (fmt == FS_FAT32) {
- if (fs->n_rootdir) {
- return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
- }
- fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */
- szbfat = fs->n_fatent * 4; /* (Required FAT size) */
- } else {
- if (!fs->n_rootdir) {
- return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
- }
- fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
- szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */
- fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
- }
- if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) { /* (FAT size must not be less than FAT sectors */
- return FR_NO_FILESYSTEM;
- }
-
-#if !_FS_READONLY
- /* Initialize cluster allocation information */
- fs->free_clust = 0xFFFFFFFF;
- fs->last_clust = 0;
-
- /* Get fsinfo if available */
- if (fmt == FS_FAT32) {
- fs->fsi_flag = 0;
- fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
- if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
- LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
- LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
- LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
- fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
- fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
- }
- }
-#endif
- fs->fs_type = fmt; /* FAT sub-type */
- fs->id = ++Fsid; /* File system mount ID */
- fs->winsect = 0; /* Invalidate sector cache */
- fs->wflag = 0;
-#if _FS_RPATH
- fs->cdir = 0; /* Current directory (root dir) */
-#endif
-#if _FS_SHARE /* Clear file lock semaphores */
- clear_lock(fs);
-#endif
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file/dir object is valid or not */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */
- FATFS *fs, /* Pointer to the file system object */
- WORD id /* Member id of the target object to be checked */
-)
-{
- if (!fs || !fs->fs_type || fs->id != id)
- return FR_INVALID_OBJECT;
-
- ENTER_FF(fs); /* Lock file system */
-
- if (disk_status(fs->drv) & STA_NOINIT)
- return FR_NOT_READY;
-
- return FR_OK;
-}
-
-
-
-
-/*--------------------------------------------------------------------------
-
- Public Functions
-
---------------------------------------------------------------------------*/
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Mount/Unmount a Logical Drive */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mount (
- BYTE vol, /* Logical drive number to be mounted/unmounted */
- FATFS *fs /* Pointer to new file system object (NULL for unmount)*/
-)
-{
- FATFS *rfs;
-
-
- if (vol >= _VOLUMES) /* Check if the drive number is valid */
- return FR_INVALID_DRIVE;
- rfs = FatFs[vol]; /* Get current fs object */
-
- if (rfs) {
-#if _FS_SHARE
- clear_lock(rfs);
-#endif
-#if _FS_REENTRANT /* Discard sync object of the current volume */
- if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
-#endif
- rfs->fs_type = 0; /* Clear old fs object */
- }
-
- if (fs) {
- fs->fs_type = 0; /* Clear new fs object */
-#if _FS_REENTRANT /* Create sync object for the new volume */
- if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
-#endif
- }
- FatFs[vol] = fs; /* Register new fs object */
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Open or Create a File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_open (
- FIL *fp, /* Pointer to the blank file object */
- const TCHAR *path, /* Pointer to the file name */
- BYTE mode /* Access mode and file open mode flags */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- fp->fs = 0; /* Clear file object */
-
-#if !_FS_READONLY
- mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
- res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
-#else
- mode &= FA_READ;
- res = chk_mounted(&path, &dj.fs, 0);
-#endif
- INIT_BUF(dj);
- if (res == FR_OK)
- res = follow_path(&dj, path); /* Follow the file path */
- dir = dj.dir;
-
-#if !_FS_READONLY /* R/W configuration */
- if (res == FR_OK) {
- if (!dir) /* Current dir itself */
- res = FR_INVALID_NAME;
-#if _FS_SHARE
- else
- res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
-#endif
- }
- /* Create or Open a file */
- if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
- DWORD dw, cl;
-
- if (res != FR_OK) { /* No file, create new */
- if (res == FR_NO_FILE) /* There is no file to open, create a new entry */
-#if _FS_SHARE
- res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
-#else
- res = dir_register(&dj);
-#endif
- mode |= FA_CREATE_ALWAYS; /* File is created */
- dir = dj.dir; /* New entry */
- }
- else { /* Any object is already existing */
- if (mode & FA_CREATE_NEW) { /* Cannot create new */
- res = FR_EXIST;
- } else {
- if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) /* Cannot overwrite it (R/O or DIR) */
- res = FR_DENIED;
- }
- }
- if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
- dw = get_fattime(); /* Created time */
- ST_DWORD(dir+DIR_CrtTime, dw);
- dir[DIR_Attr] = 0; /* Reset attribute */
- ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */
- cl = LD_CLUST(dir); /* Get start cluster */
- ST_CLUST(dir, 0); /* cluster = 0 */
- dj.fs->wflag = 1;
- if (cl) { /* Remove the cluster chain if exist */
- dw = dj.fs->winsect;
- res = remove_chain(dj.fs, cl);
- if (res == FR_OK) {
- dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */
- res = move_window(dj.fs, dw);
- }
- }
- }
- }
- else { /* Open an existing file */
- if (res == FR_OK) { /* Follow succeeded */
- if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */
- res = FR_NO_FILE;
- } else {
- if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
- res = FR_DENIED;
- }
- }
- }
- if (res == FR_OK) {
- if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */
- mode |= FA__WRITTEN;
- fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */
- fp->dir_ptr = dir;
-#if _FS_SHARE
- fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
- if (!fp->lockid) res = FR_INT_ERR;
-#endif
- }
-
-#else /* R/O configuration */
- if (res == FR_OK) { /* Follow succeeded */
- if (!dir) { /* Current dir itself */
- res = FR_INVALID_NAME;
- } else {
- if (dir[DIR_Attr] & AM_DIR) /* It is a directory */
- res = FR_NO_FILE;
- }
- }
-#endif
- FREE_BUF();
-
- if (res == FR_OK) {
- fp->flag = mode; /* File access mode */
- fp->org_clust = LD_CLUST(dir); /* File start cluster */
- fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */
- fp->fptr = 0; /* File pointer */
- fp->dsect = 0;
-#if _USE_FASTSEEK
- fp->cltbl = 0; /* No cluster link map table */
-#endif
- fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_read (
- FIL *fp, /* Pointer to the file object */
- void *buff, /* Pointer to data buffer */
- UINT btr, /* Number of bytes to read */
- UINT *br /* Pointer to number of bytes read */
-)
-{
- FRESULT res;
- DWORD clst, sect, remain;
- UINT rcnt, cc;
- BYTE csect, *rbuff = (BYTE *)buff;
-
- *br = 0; /* Initialize byte counter */
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check abort flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
- if (!(fp->flag & FA_READ)) /* Check access mode */
- LEAVE_FF(fp->fs, FR_DENIED);
- remain = fp->fsize - fp->fptr;
- if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
-
- for ( ; btr; /* Repeat until all data transferred */
- rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
- if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
- csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
- if (!csect) { /* On the cluster boundary? */
- clst = (fp->fptr == 0) ? /* On the top of the file? */
- fp->org_clust : get_fat(fp->fs, fp->curr_clust);
- if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->curr_clust = clst; /* Update current cluster */
- }
- sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */
- if (!sect) ABORT(fp->fs, FR_INT_ERR);
- sect += csect;
- cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */
- if (cc) { /* Read maximum contiguous sectors directly */
- if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
- cc = fp->fs->csize - csect;
- if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
-#if _FS_TINY
- if (fp->fs->wflag && fp->fs->winsect - sect < cc)
- mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
-#else
- if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
- mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
-#endif
-#endif
- rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
- continue;
- }
-#if !_FS_TINY
-#if !_FS_READONLY
- if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- if (fp->dsect != sect) { /* Fill sector buffer with file data */
- if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- }
-#endif
- fp->dsect = sect;
- }
- rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */
- if (rcnt > btr) rcnt = btr;
-#if _FS_TINY
- if (move_window(fp->fs, fp->dsect)) /* Move sector window */
- ABORT(fp->fs, FR_DISK_ERR);
- mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
-#else
- mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
-#endif
- }
-
- LEAVE_FF(fp->fs, FR_OK);
-}
-
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Write File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_write (
- FIL *fp, /* Pointer to the file object */
- const void *buff, /* Pointer to the data to be written */
- UINT btw, /* Number of bytes to write */
- UINT *bw /* Pointer to number of bytes written */
-)
-{
- FRESULT res;
- DWORD clst, sect;
- UINT wcnt, cc;
- const BYTE *wbuff = buff;
- BYTE csect;
-
-
- *bw = 0; /* Initialize byte counter */
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check abort flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
- if (!(fp->flag & FA_WRITE)) /* Check access mode */
- LEAVE_FF(fp->fs, FR_DENIED);
- if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */
-
- for ( ; btw; /* Repeat until all data transferred */
- wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
- if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
- csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
- if (!csect) { /* On the cluster boundary? */
- if (fp->fptr == 0) { /* On the top of the file? */
- clst = fp->org_clust; /* Follow from the origin */
- if (clst == 0) /* When there is no cluster chain, */
- fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */
- } else { /* Middle or end of the file */
- clst = create_chain(fp->fs, fp->curr_clust); /* Follow or stretch cluster chain */
- }
- if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
- if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->curr_clust = clst; /* Update current cluster */
- }
-#if _FS_TINY
- if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */
- ABORT(fp->fs, FR_DISK_ERR);
-#else
- if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */
- if (!sect) ABORT(fp->fs, FR_INT_ERR);
- sect += csect;
- cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */
- if (cc) { /* Write maximum contiguous sectors directly */
- if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
- cc = fp->fs->csize - csect;
- if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#if _FS_TINY
- if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */
- mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
- fp->fs->wflag = 0;
- }
-#else
- if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */
- mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
- continue;
- }
-#if _FS_TINY
- if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */
- if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR);
- fp->fs->winsect = sect;
- }
-#else
- if (fp->dsect != sect) { /* Fill sector buffer with file data */
- if (fp->fptr < fp->fsize &&
- disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- }
-#endif
- fp->dsect = sect;
- }
- wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
- if (wcnt > btw) wcnt = btw;
-#if _FS_TINY
- if (move_window(fp->fs, fp->dsect)) /* Move sector window */
- ABORT(fp->fs, FR_DISK_ERR);
- mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
- fp->fs->wflag = 1;
-#else
- mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
- fp->flag |= FA__DIRTY;
-#endif
- }
-
- if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */
- fp->flag |= FA__WRITTEN; /* Set file change flag */
-
- LEAVE_FF(fp->fs, FR_OK);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Synchronize the File Object */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_sync (
- FIL *fp /* Pointer to the file object */
-)
-{
- FRESULT res;
- DWORD tim;
- BYTE *dir;
-
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res == FR_OK) {
- if (fp->flag & FA__WRITTEN) { /* Has the file been written? */
-#if !_FS_TINY /* Write-back dirty buffer */
- if (fp->flag & FA__DIRTY) {
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- LEAVE_FF(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- /* Update the directory entry */
- res = move_window(fp->fs, fp->dir_sect);
- if (res == FR_OK) {
- dir = fp->dir_ptr;
- dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
- ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */
- ST_CLUST(dir, fp->org_clust); /* Update start cluster */
- tim = get_fattime(); /* Update updated time */
- ST_DWORD(dir+DIR_WrtTime, tim);
- fp->flag &= ~FA__WRITTEN;
- fp->fs->wflag = 1;
- res = sync(fp->fs);
- }
- }
- }
-
- LEAVE_FF(fp->fs, res);
-}
-
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Close File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_close (
- FIL *fp /* Pointer to the file object to be closed */
-)
-{
- FRESULT res;
-
-#if _FS_READONLY
- FATFS *fs = fp->fs;
- res = validate(fs, fp->id);
- if (res == FR_OK) fp->fs = 0; /* Discard file object */
- LEAVE_FF(fs, res);
-
-#else
- res = f_sync(fp); /* Flush cached data */
-#if _FS_SHARE
- if (res == FR_OK) { /* Decrement open counter */
-#if _FS_REENTRANT
- res = validate(fp->fs, fp->id);
- if (res == FR_OK) {
- res = dec_lock(fp->lockid);
- unlock_fs(fp->fs, FR_OK);
- }
-#else
- res = dec_lock(fp->lockid);
-#endif
- }
-#endif
- if (res == FR_OK) fp->fs = 0; /* Discard file object */
- return res;
-#endif
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Current Drive/Directory Handlings */
-/*-----------------------------------------------------------------------*/
-
-#if _FS_RPATH >= 1
-
-FRESULT f_chdrive (
- BYTE drv /* Drive number */
-)
-{
- if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
-
- CurrVol = drv;
-
- return FR_OK;
-}
-
-
-
-FRESULT f_chdir (
- const TCHAR *path /* Pointer to the directory path */
-)
-{
- FRESULT res;
- DIR dj;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 0);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the path */
- FREE_BUF();
- if (res == FR_OK) { /* Follow completed */
- if (!dj.dir) {
- dj.fs->cdir = dj.sclust; /* Start directory itself */
- } else {
- if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */
- dj.fs->cdir = LD_CLUST(dj.dir);
- else
- res = FR_NO_PATH; /* Reached but a file */
- }
- }
- if (res == FR_NO_FILE) res = FR_NO_PATH;
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-#if _FS_RPATH >= 2
-FRESULT f_getcwd (
- TCHAR *path, /* Pointer to the directory path */
- UINT sz_path /* Size of path */
-)
-{
- FRESULT res;
- DIR dj;
- UINT i, n;
- DWORD ccl;
- TCHAR *tp;
- FILINFO fno;
- DEF_NAMEBUF;
-
-
- *path = 0;
- res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */
- if (res == FR_OK) {
- INIT_BUF(dj);
- i = sz_path; /* Bottom of buffer (dir stack base) */
- dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */
- while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */
- res = dir_sdi(&dj, 1); /* Get parent dir */
- if (res != FR_OK) break;
- res = dir_read(&dj);
- if (res != FR_OK) break;
- dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */
- res = dir_sdi(&dj, 0);
- if (res != FR_OK) break;
- do { /* Find the entry links to the child dir */
- res = dir_read(&dj);
- if (res != FR_OK) break;
- if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */
- res = dir_next(&dj, 0);
- } while (res == FR_OK);
- if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
- if (res != FR_OK) break;
-#if _USE_LFN
- fno.lfname = path;
- fno.lfsize = i;
-#endif
- get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */
- tp = fno.fname;
- if (_USE_LFN && *path) tp = path;
- for (n = 0; tp[n]; n++) ;
- if (i < n + 3) {
- res = FR_NOT_ENOUGH_CORE; break;
- }
- while (n) path[--i] = tp[--n];
- path[--i] = '/';
- }
- tp = path;
- if (res == FR_OK) {
- *tp++ = '0' + CurrVol; /* Put drive number */
- *tp++ = ':';
- if (i == sz_path) { /* Root-dir */
- *tp++ = '/';
- } else { /* Sub-dir */
- do /* Add stacked path str */
- *tp++ = path[i++];
- while (i < sz_path);
- }
- }
- *tp = 0;
- FREE_BUF();
- }
-
- LEAVE_FF(dj.fs, res);
-}
-#endif /* _FS_RPATH >= 2 */
-#endif /* _FS_RPATH >= 1 */
-
-
-
-#if _FS_MINIMIZE <= 2
-/*-----------------------------------------------------------------------*/
-/* Seek File R/W Pointer */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_lseek (
- FIL *fp, /* Pointer to the file object */
- DWORD ofs /* File pointer from top of file */
-)
-{
- FRESULT res;
-
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check abort flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
-
-#if _USE_FASTSEEK
- if (fp->cltbl) { /* Fast seek */
- DWORD cl, pcl, ncl, tcl, dsc, tlen, *tbl = fp->cltbl;
- BYTE csc;
-
- tlen = *tbl++;
- if (ofs == CREATE_LINKMAP) { /* Create link map table */
- cl = fp->org_clust;
- if (cl) {
- do {
- if (tlen < 4) { /* Not enough table items */
- res = FR_NOT_ENOUGH_CORE; break;
- }
- tcl = cl; ncl = 0;
- do { /* Get a fragment and store the top and length */
- pcl = cl; ncl++;
- cl = get_fat(fp->fs, cl);
- if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
- if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- } while (cl == pcl + 1);
- *tbl++ = ncl; *tbl++ = tcl;
- tlen -= 2;
- } while (cl < fp->fs->n_fatent);
- }
- *tbl = 0; /* Terminate table */
-
- } else { /* Fast seek */
- if (ofs > fp->fsize) /* Clip offset at the file size */
- ofs = fp->fsize;
- fp->fptr = ofs; /* Set file pointer */
- if (ofs) {
- dsc = (ofs - 1) / SS(fp->fs);
- cl = dsc / fp->fs->csize;
- for (;;) {
- ncl = *tbl++;
- if (!ncl) ABORT(fp->fs, FR_INT_ERR);
- if (cl < ncl) break;
- cl -= ncl; tbl++;
- }
- fp->curr_clust = cl + *tbl;
- csc = (BYTE)(dsc & (fp->fs->csize - 1));
- dsc = clust2sect(fp->fs, fp->curr_clust);
- if (!dsc) ABORT(fp->fs, FR_INT_ERR);
- dsc += csc;
- if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {
-#if !_FS_TINY
-#if !_FS_READONLY
- if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#endif
- fp->dsect = dsc;
- }
- }
- }
- } else
-#endif
-
- /* Normal Seek */
- {
- DWORD clst, bcs, nsect, ifptr;
-
- if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */
-#if !_FS_READONLY
- && !(fp->flag & FA_WRITE)
-#endif
- ) ofs = fp->fsize;
-
- ifptr = fp->fptr;
- fp->fptr = nsect = 0;
- if (ofs) {
- bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */
- if (ifptr > 0 &&
- (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
- fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */
- ofs -= fp->fptr;
- clst = fp->curr_clust;
- } else { /* When seek to back cluster, */
- clst = fp->org_clust; /* start from the first cluster */
-#if !_FS_READONLY
- if (clst == 0) { /* If no cluster chain, create a new chain */
- clst = create_chain(fp->fs, 0);
- if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->org_clust = clst;
- }
-#endif
- fp->curr_clust = clst;
- }
- if (clst != 0) {
- while (ofs > bcs) { /* Cluster following loop */
-#if !_FS_READONLY
- if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
- clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */
- if (clst == 0) { /* When disk gets full, clip file size */
- ofs = bcs; break;
- }
- } else
-#endif
- clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
- fp->curr_clust = clst;
- fp->fptr += bcs;
- ofs -= bcs;
- }
- fp->fptr += ofs;
- if (ofs % SS(fp->fs)) {
- nsect = clust2sect(fp->fs, clst); /* Current sector */
- if (!nsect) ABORT(fp->fs, FR_INT_ERR);
- nsect += ofs / SS(fp->fs);
- }
- }
- }
- if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {
-#if !_FS_TINY
-#if !_FS_READONLY
- if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#endif
- fp->dsect = nsect;
- }
-#if !_FS_READONLY
- if (fp->fptr > fp->fsize) { /* Set change flag if the file size is extended */
- fp->fsize = fp->fptr;
- fp->flag |= FA__WRITTEN;
- }
-#endif
- }
-
- LEAVE_FF(fp->fs, res);
-}
-
-
-
-#if _FS_MINIMIZE <= 1
-/*-----------------------------------------------------------------------*/
-/* Create a Directroy Object */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_opendir (
- DIR *dj, /* Pointer to directory object to create */
- const TCHAR *path /* Pointer to the directory path */
-)
-{
- FRESULT res;
- DEF_NAMEBUF;
-
- res = chk_mounted(&path, &dj->fs, 0);
- if (res == FR_OK) {
- INIT_BUF(*dj);
- res = follow_path(dj, path); /* Follow the path to the directory */
- FREE_BUF();
- if (res == FR_OK) { /* Follow completed */
- if (dj->dir) { /* It is not the root dir */
- if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */
- dj->sclust = LD_CLUST(dj->dir);
- } else { /* The object is not a directory */
- res = FR_NO_PATH;
- }
- }
- if (res == FR_OK) {
- dj->id = dj->fs->id;
- res = dir_sdi(dj, 0); /* Rewind dir */
- }
- }
- if (res == FR_NO_FILE) res = FR_NO_PATH;
- }
-
- LEAVE_FF(dj->fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Directory Entry in Sequense */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_readdir (
- DIR *dj, /* Pointer to the open directory object */
- FILINFO *fno /* Pointer to file information to return */
-)
-{
- FRESULT res;
- DEF_NAMEBUF;
-
-
- res = validate(dj->fs, dj->id); /* Check validity of the object */
- if (res == FR_OK) {
- if (!fno) {
- res = dir_sdi(dj, 0); /* Rewind the directory object */
- } else {
- INIT_BUF(*dj);
- res = dir_read(dj); /* Read an directory item */
- if (res == FR_NO_FILE) { /* Reached end of dir */
- dj->sect = 0;
- res = FR_OK;
- }
- if (res == FR_OK) { /* A valid entry is found */
- get_fileinfo(dj, fno); /* Get the object information */
- res = dir_next(dj, 0); /* Increment index for next */
- if (res == FR_NO_FILE) {
- dj->sect = 0;
- res = FR_OK;
- }
- }
- FREE_BUF();
- }
- }
-
- LEAVE_FF(dj->fs, res);
-}
-
-
-
-#if _FS_MINIMIZE == 0
-/*-----------------------------------------------------------------------*/
-/* Get File Status */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_stat (
- const TCHAR *path, /* Pointer to the file path */
- FILINFO *fno /* Pointer to file information to return */
-)
-{
- FRESULT res;
- DIR dj;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 0);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK) { /* Follow completed */
- if (dj.dir) /* Found an object */
- get_fileinfo(&dj, fno);
- else /* It is root dir */
- res = FR_INVALID_NAME;
- }
- FREE_BUF();
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Get Number of Free Clusters */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_getfree (
- const TCHAR *path, /* Pointer to the logical drive number (root dir) */
- DWORD *nclst, /* Pointer to the variable to return number of free clusters */
- FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */
-)
-{
- FRESULT res;
- DWORD n, clst, sect, stat;
- UINT i;
- BYTE fat, *p;
-
-
- /* Get drive number */
- res = chk_mounted(&path, fatfs, 0);
- if (res == FR_OK) {
- /* If free_clust is valid, return it without full cluster scan */
- if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) {
- *nclst = (*fatfs)->free_clust;
- } else {
- /* Get number of free clusters */
- fat = (*fatfs)->fs_type;
- n = 0;
- if (fat == FS_FAT12) {
- clst = 2;
- do {
- stat = get_fat(*fatfs, clst);
- if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
- if (stat == 1) { res = FR_INT_ERR; break; }
- if (stat == 0) n++;
- } while (++clst < (*fatfs)->n_fatent);
- } else {
- clst = (*fatfs)->n_fatent;
- sect = (*fatfs)->fatbase;
- i = 0; p = 0;
- do {
- if (!i) {
- res = move_window(*fatfs, sect++);
- if (res != FR_OK) break;
- p = (*fatfs)->win;
- i = SS(*fatfs);
- }
- if (fat == FS_FAT16) {
- if (LD_WORD(p) == 0) n++;
- p += 2; i -= 2;
- } else {
- if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
- p += 4; i -= 4;
- }
- } while (--clst);
- }
- (*fatfs)->free_clust = n;
- if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1;
- *nclst = n;
- }
- }
- LEAVE_FF(*fatfs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Truncate File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_truncate (
- FIL *fp /* Pointer to the file object */
-)
-{
- FRESULT res;
- DWORD ncl;
-
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res == FR_OK) {
- if (fp->flag & FA__ERROR) { /* Check abort flag */
- res = FR_INT_ERR;
- } else {
- if (!(fp->flag & FA_WRITE)) /* Check access mode */
- res = FR_DENIED;
- }
- }
- if (res == FR_OK) {
- if (fp->fsize > fp->fptr) {
- fp->fsize = fp->fptr; /* Set file size to current R/W point */
- fp->flag |= FA__WRITTEN;
- if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
- res = remove_chain(fp->fs, fp->org_clust);
- fp->org_clust = 0;
- } else { /* When truncate a part of the file, remove remaining clusters */
- ncl = get_fat(fp->fs, fp->curr_clust);
- res = FR_OK;
- if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
- if (ncl == 1) res = FR_INT_ERR;
- if (res == FR_OK && ncl < fp->fs->n_fatent) {
- res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF);
- if (res == FR_OK) res = remove_chain(fp->fs, ncl);
- }
- }
- }
- if (res != FR_OK) fp->flag |= FA__ERROR;
- }
-
- LEAVE_FF(fp->fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Delete a File or Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_unlink (
- const TCHAR *path /* Pointer to the file or directory path */
-)
-{
- FRESULT res;
- DIR dj, sdj;
- BYTE *dir;
- DWORD dclst;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME; /* Cannot remove dot entry */
-#if _FS_SHARE
- if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */
-#endif
- if (res == FR_OK) { /* The object is accessible */
- dir = dj.dir;
- if (!dir) {
- res = FR_INVALID_NAME; /* Cannot remove the start directory */
- } else {
- if (dir[DIR_Attr] & AM_RDO)
- res = FR_DENIED; /* Cannot remove R/O object */
- }
- dclst = LD_CLUST(dir);
- if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
- if (dclst < 2) {
- res = FR_INT_ERR;
- } else {
- mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */
- sdj.sclust = dclst;
- res = dir_sdi(&sdj, 2); /* Exclude dot entries */
- if (res == FR_OK) {
- res = dir_read(&sdj);
- if (res == FR_OK /* Not empty dir */
-#if _FS_RPATH
- || dclst == sdj.fs->cdir /* Current dir */
-#endif
- ) res = FR_DENIED;
- if (res == FR_NO_FILE) res = FR_OK; /* Empty */
- }
- }
- }
- if (res == FR_OK) {
- res = dir_remove(&dj); /* Remove the directory entry */
- if (res == FR_OK) {
- if (dclst) /* Remove the cluster chain if exist */
- res = remove_chain(dj.fs, dclst);
- if (res == FR_OK) res = sync(dj.fs);
- }
- }
- }
- FREE_BUF();
- }
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create a Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mkdir (
- const TCHAR *path /* Pointer to the directory path */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir, n;
- DWORD dsc, dcl, pcl, tim = get_fattime();
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
- if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_NO_FILE) { /* Can create a new directory */
- dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */
- res = FR_OK;
- if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
- if (dcl == 1) res = FR_INT_ERR;
- if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
- if (res == FR_OK) /* Flush FAT */
- res = move_window(dj.fs, 0);
- if (res == FR_OK) { /* Initialize the new directory table */
- dsc = clust2sect(dj.fs, dcl);
- dir = dj.fs->win;
- mem_set(dir, 0, SS(dj.fs));
- mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */
- dir[DIR_Name] = '.';
- dir[DIR_Attr] = AM_DIR;
- ST_DWORD(dir+DIR_WrtTime, tim);
- ST_CLUST(dir, dcl);
- mem_cpy(dir+32, dir, 32); /* Create ".." entry */
- dir[33] = '.'; pcl = dj.sclust;
- if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
- pcl = 0;
- ST_CLUST(dir+32, pcl);
- for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */
- dj.fs->winsect = dsc++;
- dj.fs->wflag = 1;
- res = move_window(dj.fs, 0);
- if (res != FR_OK) break;
- mem_set(dir, 0, SS(dj.fs));
- }
- }
- if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */
- if (res != FR_OK) {
- remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */
- } else {
- dir = dj.dir;
- dir[DIR_Attr] = AM_DIR; /* Attribute */
- ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */
- ST_CLUST(dir, dcl); /* Table start cluster */
- dj.fs->wflag = 1;
- res = sync(dj.fs);
- }
- }
- FREE_BUF();
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Attribute */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_chmod (
- const TCHAR *path, /* Pointer to the file path */
- BYTE value, /* Attribute bits */
- BYTE mask /* Attribute mask to change */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- FREE_BUF();
- if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_OK) {
- dir = dj.dir;
- if (!dir) { /* Is it a root directory? */
- res = FR_INVALID_NAME;
- } else { /* File or sub directory */
- mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
- dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
- dj.fs->wflag = 1;
- res = sync(dj.fs);
- }
- }
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Timestamp */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_utime (
- const TCHAR *path, /* Pointer to the file/directory name */
- const FILINFO *fno /* Pointer to the time stamp to be set */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- FREE_BUF();
- if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_OK) {
- dir = dj.dir;
- if (!dir) { /* Root directory */
- res = FR_INVALID_NAME;
- } else { /* File or sub-directory */
- ST_WORD(dir+DIR_WrtTime, fno->ftime);
- ST_WORD(dir+DIR_WrtDate, fno->fdate);
- dj.fs->wflag = 1;
- res = sync(dj.fs);
- }
- }
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Rename File/Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_rename (
- const TCHAR *path_old, /* Pointer to the old name */
- const TCHAR *path_new /* Pointer to the new name */
-)
-{
- FRESULT res;
- DIR djo, djn;
- BYTE buf[21], *dir;
- DWORD dw;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path_old, &djo.fs, 1);
- if (res == FR_OK) {
- djn.fs = djo.fs;
- INIT_BUF(djo);
- res = follow_path(&djo, path_old); /* Check old object */
- if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
-#if _FS_SHARE
- if (res == FR_OK) res = chk_lock(&djo, 2);
-#endif
- if (res == FR_OK) { /* Old object is found */
- if (!djo.dir) { /* Is root dir? */
- res = FR_NO_FILE;
- } else {
- mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */
- mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */
- res = follow_path(&djn, path_new);
- if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */
- if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */
-/* Start critical section that any interruption or error can cause cross-link */
- res = dir_register(&djn); /* Register the new entry */
- if (res == FR_OK) {
- dir = djn.dir; /* Copy object information except for name */
- mem_cpy(dir+13, buf+2, 19);
- dir[DIR_Attr] = buf[0] | AM_ARC;
- djo.fs->wflag = 1;
- if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */
- dw = clust2sect(djn.fs, LD_CLUST(dir));
- if (!dw) {
- res = FR_INT_ERR;
- } else {
- res = move_window(djn.fs, dw);
- dir = djn.fs->win+32; /* .. entry */
- if (res == FR_OK && dir[1] == '.') {
- dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust;
- ST_CLUST(dir, dw);
- djn.fs->wflag = 1;
- }
- }
- }
- if (res == FR_OK) {
- res = dir_remove(&djo); /* Remove old entry */
- if (res == FR_OK)
- res = sync(djo.fs);
- }
- }
-/* End critical section */
- }
- }
- }
- FREE_BUF();
- }
- LEAVE_FF(djo.fs, res);
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _FS_MINIMIZE == 0 */
-#endif /* _FS_MINIMIZE <= 1 */
-#endif /* _FS_MINIMIZE <= 2 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Forward data to the stream directly (available on only tiny cfg) */
-/*-----------------------------------------------------------------------*/
-#if _USE_FORWARD && _FS_TINY
-
-FRESULT f_forward (
- FIL *fp, /* Pointer to the file object */
- UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
- UINT btr, /* Number of bytes to forward */
- UINT *bf /* Pointer to number of bytes forwarded */
-)
-{
- FRESULT res;
- DWORD remain, clst, sect;
- UINT rcnt;
- BYTE csect;
-
-
- *bf = 0; /* Initialize byte counter */
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check error flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
- if (!(fp->flag & FA_READ)) /* Check access mode */
- LEAVE_FF(fp->fs, FR_DENIED);
-
- remain = fp->fsize - fp->fptr;
- if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
-
- for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */
- fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) {
- csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
- if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
- if (!csect) { /* On the cluster boundary? */
- clst = (fp->fptr == 0) ? /* On the top of the file? */
- fp->org_clust : get_fat(fp->fs, fp->curr_clust);
- if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->curr_clust = clst; /* Update current cluster */
- }
- }
- sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */
- if (!sect) ABORT(fp->fs, FR_INT_ERR);
- sect += csect;
- if (move_window(fp->fs, sect)) /* Move sector window */
- ABORT(fp->fs, FR_DISK_ERR);
- fp->dsect = sect;
- rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */
- if (rcnt > btr) rcnt = btr;
- rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
- if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
- }
-
- LEAVE_FF(fp->fs, FR_OK);
-}
-#endif /* _USE_FORWARD */
-
-
-
-#if _USE_MKFS && !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Create File System on the Drive */
-/*-----------------------------------------------------------------------*/
-#define N_ROOTDIR 512 /* Multiple of 32 */
-#define N_FATS 1 /* 1 or 2 */
-
-
-FRESULT f_mkfs (
- BYTE drv, /* Logical drive number */
- BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */
- UINT au /* Allocation unit size [bytes] */
-)
-{
- static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0};
- static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
- BYTE fmt, md, *tbl;
- DWORD n_clst, vs, n, wsect;
- UINT i;
- DWORD b_vol, b_fat, b_dir, b_data; /* Offset (LBA) */
- DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */
- FATFS *fs;
- DSTATUS stat;
-
- /* Check mounted drive and clear work area */
- if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
- fs = FatFs[drv];
- if (!fs) return FR_NOT_ENABLED;
- fs->fs_type = 0;
- drv = LD2PD(drv);
-
- /* Get disk statics */
- stat = disk_initialize(drv);
- if (stat & STA_NOINIT) return FR_NOT_READY;
- if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
-#if _MAX_SS != 512 /* Get disk sector size */
- if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK)
- return FR_DISK_ERR;
-#endif
- if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
- return FR_DISK_ERR;
- b_vol = (sfd) ? 0 : 63; /* Volume start sector */
- n_vol -= b_vol;
- if (au & (au - 1)) au = 0; /* Check validity of the allocation unit size */
- if (!au) { /* AU auto selection */
- vs = n_vol / (2000 / (SS(fs) / 512));
- for (i = 0; vs < vst[i]; i++) ;
- au = cst[i];
- }
- au /= SS(fs); /* Number of sectors per cluster */
- if (au == 0) au = 1;
- if (au > 128) au = 128;
-
- /* Pre-compute number of clusters and FAT syb-type */
- n_clst = n_vol / au;
- fmt = FS_FAT12;
- if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
- if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
-
- /* Determine offset and size of FAT structure */
- if (fmt == FS_FAT32) {
- n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
- n_rsv = 32;
- n_dir = 0;
- } else {
- n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
- n_fat = (n_fat + SS(fs) - 1) / SS(fs);
- n_rsv = 1;
- n_dir = N_ROOTDIR * 32UL / SS(fs);
- }
- b_fat = b_vol + n_rsv; /* FAT area start sector */
- b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */
- b_data = b_dir + n_dir; /* Data area start sector */
- if (n_vol < b_data + au) return FR_MKFS_ABORTED; /* Too small volume */
-
- /* Align data start sector to erase block boundary (for flash memory media) */
- if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
- n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */
- n = (n - b_data) / N_FATS;
- if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */
- n_rsv += n;
- b_fat += n;
- } else { /* FAT12/16: Expand FAT size */
- n_fat += n;
- }
-
- /* Determine number of cluster and final check of validity of the FAT sub-type */
- n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
- if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16)
- || (fmt == FS_FAT32 && n_clst < MIN_FAT32))
- return FR_MKFS_ABORTED;
-
- /* Create partition table if required */
- if (sfd) {
- md = 0xF0;
- } else {
- DWORD n_disk = b_vol + n_vol;
-
- mem_set(fs->win, 0, SS(fs));
- tbl = fs->win+MBR_Table;
- ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */
- if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */
- n_disk = n_disk / 63 / 255;
- tbl[7] = (BYTE)n_disk;
- tbl[6] = (BYTE)((n_disk >> 2) | 63);
- } else {
- ST_WORD(&tbl[6], 0xFFFF);
- }
- tbl[5] = 254;
- if (fmt != FS_FAT32) /* System ID */
- tbl[4] = (n_vol < 0x10000) ? 0x04 : 0x06;
- else
- tbl[4] = 0x0c;
- ST_DWORD(tbl+8, 63); /* Partition start in LBA */
- ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */
- ST_WORD(tbl+64, 0xAA55); /* Signature */
- if (disk_write(drv, fs->win, 0, 1) != RES_OK)
- return FR_DISK_ERR;
- md = 0xF8;
- }
-
- /* Create volume boot record */
- tbl = fs->win; /* Clear sector */
- mem_set(tbl, 0, SS(fs));
- mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot code, OEM name */
- i = SS(fs); /* Sector size */
- ST_WORD(tbl+BPB_BytsPerSec, i);
- tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */
- ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */
- tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */
- i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */
- ST_WORD(tbl+BPB_RootEntCnt, i);
- if (n_vol < 0x10000) { /* Number of total sectors */
- ST_WORD(tbl+BPB_TotSec16, n_vol);
- } else {
- ST_DWORD(tbl+BPB_TotSec32, n_vol);
- }
- tbl[BPB_Media] = md; /* Media descriptor */
- ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */
- ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */
- ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */
- n = get_fattime(); /* Use current time as VSN */
- if (fmt == FS_FAT32) {
- ST_DWORD(tbl+BS_VolID32, n); /* VSN */
- ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */
- ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */
- ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */
- ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */
- tbl[BS_DrvNum32] = 0x80; /* Drive number */
- tbl[BS_BootSig32] = 0x29; /* Extended boot signature */
- mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
- } else {
- ST_DWORD(tbl+BS_VolID, n); /* VSN */
- ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */
- tbl[BS_DrvNum] = 0x80; /* Drive number */
- tbl[BS_BootSig] = 0x29; /* Extended boot signature */
- mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
- }
- ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */
- if (disk_write(drv, tbl, b_vol, 1) != RES_OK)/* Write original (VBR) */
- return FR_DISK_ERR;
- if (fmt == FS_FAT32) /* Write backup (VBR+6) */
- disk_write(drv, tbl, b_vol + 6, 1);
-
- /* Initialize FAT area */
- wsect = b_fat;
- for (i = 0; i < N_FATS; i++) {
- mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */
- n = md; /* Media descriptor byte */
- if (fmt != FS_FAT32) {
- n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
- ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */
- } else {
- n |= 0xFFFFFF00;
- ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */
- ST_DWORD(tbl+4, 0xFFFFFFFF);
- ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */
- }
- if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
- return FR_DISK_ERR;
- mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */
- for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector write */
- if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
- return FR_DISK_ERR;
- }
- }
-
- /* Initialize root directory */
- i = (fmt == FS_FAT32) ? au : n_dir;
- do {
- if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
- return FR_DISK_ERR;
- } while (--i);
-
-#if _USE_ERASE /* Erase data area if needed */
- {
- DWORD eb[2];
-
- eb[0] = wsect; eb[1] = wsect + n_clst * au - 1;
- disk_ioctl(drv, CTRL_ERASE_SECTOR, eb);
- }
-#endif
-
- /* Create FSInfo if needed */
- if (fmt == FS_FAT32) {
- ST_WORD(tbl+BS_55AA, 0xAA55);
- ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
- ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
- ST_DWORD(tbl+FSI_Free_Count, n_clst - 1);
- ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF);
- disk_write(drv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */
- disk_write(drv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */
- }
-
- return (disk_ioctl(drv, CTRL_SYNC, (void*)0) == RES_OK) ? FR_OK : FR_DISK_ERR;
-}
-
-#endif /* _USE_MKFS && !_FS_READONLY */
-
-
-
-
-#if _USE_STRFUNC
-/*-----------------------------------------------------------------------*/
-/* Get a string from the file */
-/*-----------------------------------------------------------------------*/
-TCHAR* f_gets (
- TCHAR* buff, /* Pointer to the string buffer to read */
- int len, /* Size of string buffer (characters) */
- FIL* fil /* Pointer to the file object */
-)
-{
- int n = 0;
- TCHAR c, *p = buff;
- BYTE s[2];
- UINT rc;
-
-
- while (n < len - 1) { /* Read bytes until buffer gets filled */
- f_read(fil, s, 1, &rc);
- if (rc != 1) break; /* Break on EOF or error */
- c = s[0];
-#if _LFN_UNICODE /* Read a character in UTF-8 encoding */
- if (c >= 0x80) {
- if (c < 0xC0) continue; /* Skip stray trailer */
- if (c < 0xE0) { /* Two-byte sequense */
- f_read(fil, s, 1, &rc);
- if (rc != 1) break;
- c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
- if (c < 0x80) c = '?';
- } else {
- if (c < 0xF0) { /* Three-byte sequense */
- f_read(fil, s, 2, &rc);
- if (rc != 2) break;
- c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
- if (c < 0x800) c = '?';
- } else { /* Reject four-byte sequense */
- c = '?';
- }
- }
- }
-#endif
-#if _USE_STRFUNC >= 2
- if (c == '\r') continue; /* Strip '\r' */
-#endif
- *p++ = c;
- n++;
- if (c == '\n') break; /* Break on EOL */
- }
- *p = 0;
- return n ? buff : 0; /* When no data read (eof or error), return with error. */
-}
-
-
-
-#if !_FS_READONLY
-#include <stdarg.h>
-/*-----------------------------------------------------------------------*/
-/* Put a character to the file */
-/*-----------------------------------------------------------------------*/
-int f_putc (
- TCHAR c, /* A character to be output */
- FIL* fil /* Pointer to the file object */
-)
-{
- UINT bw, btw;
- BYTE s[3];
-
-
-#if _USE_STRFUNC >= 2
- if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */
-#endif
-
-#if _LFN_UNICODE /* Write the character in UTF-8 encoding */
- if (c < 0x80) { /* 7-bit */
- s[0] = (BYTE)c;
- btw = 1;
- } else {
- if (c < 0x800) { /* 11-bit */
- s[0] = (BYTE)(0xC0 | (c >> 6));
- s[1] = (BYTE)(0x80 | (c & 0x3F));
- btw = 2;
- } else { /* 16-bit */
- s[0] = (BYTE)(0xE0 | (c >> 12));
- s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
- s[2] = (BYTE)(0x80 | (c & 0x3F));
- btw = 3;
- }
- }
-#else /* Write the character without conversion */
- s[0] = (BYTE)c;
- btw = 1;
-#endif
- f_write(fil, s, btw, &bw); /* Write the char to the file */
- return (bw == btw) ? 1 : EOF; /* Return the result */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a string to the file */
-/*-----------------------------------------------------------------------*/
-int f_puts (
- const TCHAR* str, /* Pointer to the string to be output */
- FIL* fil /* Pointer to the file object */
-)
-{
- int n;
-
-
- for (n = 0; *str; str++, n++) {
- if (f_putc(*str, fil) == EOF) return EOF;
- }
- return n;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a formatted string to the file */
-/*-----------------------------------------------------------------------*/
-int f_printf (
- FIL* fil, /* Pointer to the file object */
- const TCHAR* str, /* Pointer to the format string */
- ... /* Optional arguments... */
-)
-{
- va_list arp;
- BYTE f, r;
- UINT i, w;
- ULONG val;
- TCHAR c, d, s[16];
- int res, cc;
-
-
- va_start(arp, str);
-
- for (cc = res = 0; cc != EOF; res += cc) {
- c = *str++;
- if (c == 0) break; /* End of string */
- if (c != '%') { /* Non escape character */
- cc = f_putc(c, fil);
- if (cc != EOF) cc = 1;
- continue;
- }
- w = f = 0;
- c = *str++;
- if (c == '0') { /* Flag: '0' padding */
- f = 1; c = *str++;
- }
- while (IsDigit(c)) { /* Precision */
- w = w * 10 + c - '0';
- c = *str++;
- }
- if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
- f |= 2; c = *str++;
- }
- if (!c) break;
- d = c;
- if (IsLower(d)) d -= 0x20;
- switch (d) { /* Type is... */
- case 'S' : /* String */
- cc = f_puts(va_arg(arp, TCHAR*), fil); continue;
- case 'C' : /* Character */
- cc = f_putc((TCHAR)va_arg(arp, int), fil); continue;
- case 'B' : /* Binary */
- r = 2; break;
- case 'O' : /* Octal */
- r = 8; break;
- case 'D' : /* Signed decimal */
- case 'U' : /* Unsigned decimal */
- r = 10; break;
- case 'X' : /* Hexdecimal */
- r = 16; break;
- default: /* Unknown */
- cc = f_putc(c, fil); continue;
- }
-
- /* Get an argument */
- val = (f & 2) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : va_arg(arp, unsigned int));
- if (d == 'D' && (val & 0x80000000)) {
- val = 0 - val;
- f |= 4;
- }
- /* Put it in numeral string */
- i = 0;
- do {
- d = (TCHAR)(val % r); val /= r;
- if (d > 9) {
- d += 7;
- if (c == 'x') d += 0x20;
- }
- s[i++] = d + '0';
- } while (val && i < sizeof(s) / sizeof(s[0]));
- if (f & 4) s[i++] = '-';
- cc = 0;
- while (i < w-- && cc != EOF) {
- cc = f_putc((TCHAR)((f & 1) ? '0' : ' '), fil);
- res++;
- }
- do {
- cc = f_putc(s[--i], fil);
- res++;
- } while (i && cc != EOF);
- if (cc != EOF) cc = 0;
- }
-
- va_end(arp);
- return (cc == EOF) ? cc : res;
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _USE_STRFUNC */
-
-#endif /* XPAR_PS7_SD_0_S_AXI_BASEADDR */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ff.h b/quad/xsdk_workspace/zybo_fsbl/src/ff.h
deleted file mode 100644
index a2cf4907a0c1fb7e207492ca4c8b68fb14e5b821..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/ff.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/*---------------------------------------------------------------------------/
-/ FatFs - FAT file system module include file R0.08a (C)ChaN, 2010
-/----------------------------------------------------------------------------/
-/ FatFs module is a generic FAT file system module for small embedded systems.
-/ This is a free software that opened for education, research and commercial
-/ developments under license policy of following trems.
-/
-/ Copyright (C) 2010, ChaN, all right reserved.
-/
-/ * The FatFs module is a free software and there is NO WARRANTY.
-/ * No restriction on use. You can use, modify and redistribute it for
-/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
-/ * Redistributions of source code must retain the above copyright notice.
-/
-/----------------------------------------------------------------------------*/
-
-#ifndef _FATFS
-#define _FATFS 8255 /* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h" /* Basic integer types */
-#include "ffconf.h" /* FatFs configuration options */
-
-#if _FATFS != _FFCONF
-#error Wrong configuration file (ffconf.h).
-#endif
-
-
-/* DBCS code ranges and SBCS extend char conversion table */
-
-#if _CODE_PAGE == 932 /* Japanese Shift-JIS */
-#define _DF1S 0x81 /* DBC 1st byte range 1 start */
-#define _DF1E 0x9F /* DBC 1st byte range 1 end */
-#define _DF2S 0xE0 /* DBC 1st byte range 2 start */
-#define _DF2E 0xFC /* DBC 1st byte range 2 end */
-#define _DS1S 0x40 /* DBC 2nd byte range 1 start */
-#define _DS1E 0x7E /* DBC 2nd byte range 1 end */
-#define _DS2S 0x80 /* DBC 2nd byte range 2 start */
-#define _DS2E 0xFC /* DBC 2nd byte range 2 end */
-
-#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
-#define _DF1S 0x81
-#define _DF1E 0xFE
-#define _DS1S 0x40
-#define _DS1E 0x7E
-#define _DS2S 0x80
-#define _DS2E 0xFE
-
-#elif _CODE_PAGE == 949 /* Korean */
-#define _DF1S 0x81
-#define _DF1E 0xFE
-#define _DS1S 0x41
-#define _DS1E 0x5A
-#define _DS2S 0x61
-#define _DS2E 0x7A
-#define _DS3S 0x81
-#define _DS3E 0xFE
-
-#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
-#define _DF1S 0x81
-#define _DF1E 0xFE
-#define _DS1S 0x40
-#define _DS1E 0x7E
-#define _DS2S 0xA1
-#define _DS2E 0xFE
-
-#elif _CODE_PAGE == 437 /* U.S. (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 720 /* Arabic (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 737 /* Greek (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
- 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 775 /* Baltic (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
- 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
-
-#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
- 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
- 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 857 /* Turkish (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 866 /* Russian (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
-
-#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
- 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
-
-#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
-
-#elif _CODE_PAGE == 1253 /* Greek (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
- 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
-
-#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
-
-#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
-
-#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
-
-#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */
-#define _DF1S 0
-
-#else
-#error Unknown code page
-
-#endif
-
-
-
-/* Definitions of volume management */
-
-#if _MULTI_PARTITION /* Multiple partition configuration */
-#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive# */
-#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition# */
-typedef struct {
- BYTE pd; /* Physical drive# */
- BYTE pt; /* Partition # (0-3) */
-} PARTITION;
-extern const PARTITION VolToPart[]; /* Volume - Physical location resolution table */
-
-#else /* Single partition configuration */
-#define LD2PD(vol) (vol) /* Logical drive# is bound to the same physical drive# */
-#define LD2PT(vol) 0 /* Always mounts the 1st partition */
-
-#endif
-
-
-
-/* Type of path name strings on FatFs API */
-
-#if _LFN_UNICODE /* Unicode string */
-#if !_USE_LFN
-#error _LFN_UNICODE must be 0 in non-LFN cfg.
-#endif
-#ifndef _INC_TCHAR
-typedef WCHAR TCHAR;
-#define _T(x) L ## x
-#define _TEXT(x) L ## x
-#endif
-
-#else /* ANSI/OEM string */
-#ifndef _INC_TCHAR
-typedef char TCHAR;
-#define _T(x) x
-#define _TEXT(x) x
-#endif
-
-#endif
-
-
-
-/* File system object structure (FATFS) */
-
-typedef struct {
- BYTE fs_type; /* FAT sub-type (0:Not mounted) */
- BYTE drv; /* Physical drive number */
- BYTE csize; /* Sectors per cluster (1,2,4...128) */
- BYTE n_fats; /* Number of FAT copies (1,2) */
- BYTE wflag; /* win[] dirty flag (1:must be written back) */
- BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */
- WORD id; /* File system mount ID */
- WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
-#if _MAX_SS != 512
- WORD ssize; /* Bytes per sector (512,1024,2048,4096) */
-#endif
-#if _FS_REENTRANT
- _SYNC_t sobj; /* Identifier of sync object */
-#endif
-#if !_FS_READONLY
- DWORD last_clust; /* Last allocated cluster */
- DWORD free_clust; /* Number of free clusters */
- DWORD fsi_sector; /* fsinfo sector (FAT32) */
-#endif
-#if _FS_RPATH
- DWORD cdir; /* Current directory start cluster (0:root) */
-#endif
- DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
- DWORD fsize; /* Sectors per FAT */
- DWORD fatbase; /* FAT start sector */
- DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
- DWORD database; /* Data start sector */
- DWORD winsect; /* Current sector appearing in the win[] */
- BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
-} FATFS;
-
-
-
-/* File object structure (FIL) */
-
-typedef struct {
- FATFS* fs; /* Pointer to the owner file system object */
- WORD id; /* Owner file system mount ID */
- BYTE flag; /* File status flags */
- BYTE pad1;
- DWORD fptr; /* File read/write pointer (0 on file open) */
- DWORD fsize; /* File size */
- DWORD org_clust; /* File start cluster (0 when fsize==0) */
- DWORD curr_clust; /* Current cluster */
- DWORD dsect; /* Current data sector */
-#if !_FS_READONLY
- DWORD dir_sect; /* Sector containing the directory entry */
- BYTE* dir_ptr; /* Ponter to the directory entry in the window */
-#endif
-#if _USE_FASTSEEK
- DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */
-#endif
-#if _FS_SHARE
- UINT lockid; /* File lock ID (index of file semaphore table) */
-#endif
-#if !_FS_TINY
- BYTE buf[_MAX_SS]; /* File data read/write buffer */
-#endif
-} FIL;
-
-
-
-/* Directory object structure (DIR) */
-
-typedef struct {
- FATFS* fs; /* Pointer to the owner file system object */
- WORD id; /* Owner file system mount ID */
- WORD index; /* Current read/write index number */
- DWORD sclust; /* Table start cluster (0:Root dir) */
- DWORD clust; /* Current cluster */
- DWORD sect; /* Current sector */
- BYTE* dir; /* Pointer to the current SFN entry in the win[] */
- BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
-#if _USE_LFN
- WCHAR* lfn; /* Pointer to the LFN working buffer */
- WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
-#endif
-} DIR;
-
-
-
-/* File status structure (FILINFO) */
-
-typedef struct {
- DWORD fsize; /* File size */
- WORD fdate; /* Last modified date */
- WORD ftime; /* Last modified time */
- BYTE fattrib; /* Attribute */
- TCHAR fname[13]; /* Short file name (8.3 format) */
-#if _USE_LFN
- TCHAR* lfname; /* Pointer to the LFN buffer */
- UINT lfsize; /* Size of LFN buffer in TCHAR */
-#endif
-} FILINFO;
-
-
-
-/* File function return code (FRESULT) */
-
-typedef enum {
- FR_OK = 0, /* (0) Succeeded */
- FR_DISK_ERR, /* (1) A hard error occured in the low level disk I/O layer */
- FR_INT_ERR, /* (2) Assertion failed */
- FR_NOT_READY, /* (3) The physical drive cannot work */
- FR_NO_FILE, /* (4) Could not find the file */
- FR_NO_PATH, /* (5) Could not find the path */
- FR_INVALID_NAME, /* (6) The path name format is invalid */
- FR_DENIED, /* (7) Acces denied due to prohibited access or directory full */
- FR_EXIST, /* (8) Acces denied due to prohibited access */
- FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
- FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
- FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
- FR_NOT_ENABLED, /* (12) The volume has no work area */
- FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume on the physical drive */
- FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
- FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
- FR_LOCKED, /* (16) The operation is rejected according to the file shareing policy */
- FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
- FR_TOO_MANY_OPEN_FILES /* (18) Number of open files > _FS_SHARE */
-} FRESULT;
-
-
-
-/*--------------------------------------------------------------*/
-/* FatFs module application interface */
-
-FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */
-FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */
-FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */
-FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */
-FRESULT f_close (FIL*); /* Close an open file object */
-FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */
-FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */
-FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
-
-#if !_FS_READONLY
-FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */
-FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */
-FRESULT f_truncate (FIL*); /* Truncate file */
-FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
-FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
-FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
-FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */
-FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */
-FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
-#endif
-
-#if _USE_FORWARD
-FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */
-#endif
-
-#if _USE_MKFS
-FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */
-#endif
-
-#if _FS_RPATH
-FRESULT f_chdrive (BYTE); /* Change current drive */
-FRESULT f_chdir (const TCHAR*); /* Change current directory */
-FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */
-#endif
-
-#if _USE_STRFUNC
-int f_putc (TCHAR, FIL*); /* Put a character to the file */
-int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
-int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
-TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
-#ifndef EOF
-#define EOF (-1)
-#endif
-#endif
-
-#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
-#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
-#define f_tell(fp) ((fp)->fptr)
-#define f_size(fp) ((fp)->fsize)
-
-
-
-/*--------------------------------------------------------------*/
-/* Additional user defined functions */
-
-/* RTC function */
-#if !_FS_READONLY
-DWORD get_fattime (void);
-#endif
-
-/* Unicode support functions */
-#if _USE_LFN /* Unicode - OEM code conversion */
-WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */
-WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */
-#if _USE_LFN == 3 /* Memory functions */
-void* ff_memalloc (UINT); /* Allocate memory block */
-void ff_memfree (void*); /* Free memory block */
-#endif
-#endif
-
-/* Sync functions */
-#if _FS_REENTRANT
-int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
-int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
-int ff_req_grant (_SYNC_t); /* Lock sync object */
-void ff_rel_grant (_SYNC_t); /* Unlock sync object */
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Flags and offset address */
-
-
-/* File access control and file status flags (FIL.flag) */
-
-#define FA_READ 0x01
-#define FA_OPEN_EXISTING 0x00
-#define FA__ERROR 0x80
-
-#if !_FS_READONLY
-#define FA_WRITE 0x02
-#define FA_CREATE_NEW 0x04
-#define FA_CREATE_ALWAYS 0x08
-#define FA_OPEN_ALWAYS 0x10
-#define FA__WRITTEN 0x20
-#define FA__DIRTY 0x40
-#endif
-
-
-/* FAT sub type (FATFS.fs_type) */
-
-#define FS_FAT12 1
-#define FS_FAT16 2
-#define FS_FAT32 3
-
-
-/* File attribute bits for directory entry */
-
-#define AM_RDO 0x01 /* Read only */
-#define AM_HID 0x02 /* Hidden */
-#define AM_SYS 0x04 /* System */
-#define AM_VOL 0x08 /* Volume label */
-#define AM_LFN 0x0F /* LFN entry */
-#define AM_DIR 0x10 /* Directory */
-#define AM_ARC 0x20 /* Archive */
-#define AM_MASK 0x3F /* Mask of defined bits */
-
-
-/* Fast seek function */
-#define CREATE_LINKMAP 0xFFFFFFFF
-
-
-/*--------------------------------*/
-/* Multi-byte word access macros */
-
-#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
- #define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
- #define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
- #define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
- #define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
-#else /* Use byte-by-byte access to the FAT structure */
- #define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
- #define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr))
- #define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8)
- #define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FATFS */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ffconf.h b/quad/xsdk_workspace/zybo_fsbl/src/ffconf.h
deleted file mode 100644
index 1b57f9705773169512413e4f60ba658703f12fd9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/ffconf.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*---------------------------------------------------------------------------/
-/ FatFs - FAT file system module configuration file R0.08a (C)ChaN, 2010
-/----------------------------------------------------------------------------/
-/
-/ CAUTION! Do not forget to make clean the project after any changes to
-/ the configuration options.
-/
-/----------------------------------------------------------------------------*/
-#ifndef _FFCONF
-#define _FFCONF 8255 /* Revision ID */
-
-
-/*---------------------------------------------------------------------------/
-/ Function and Buffer Configurations
-/----------------------------------------------------------------------------*/
-
-#define _FS_TINY 1 /* 0:Normal or 1:Tiny */
-/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
-/ object instead of the sector buffer in the individual file object for file
-/ data transfer. This reduces memory consumption 512 bytes each file object. */
-
-
-#define _FS_READONLY 1 /* 0:Read/Write or 1:Read only */
-/* Setting _FS_READONLY to 1 defines read only configuration. This removes
-/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
-/ f_truncate and useless f_getfree. */
-
-
-#define _FS_MINIMIZE 1 /* 0 to 3 */
-/* The _FS_MINIMIZE option defines minimization level to remove some functions.
-/
-/ 0: Full function.
-/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
-/ are removed.
-/ 2: f_opendir and f_readdir are removed in addition to 1.
-/ 3: f_lseek is removed in addition to 2. */
-
-
-#define _USE_STRFUNC 0 /* 0:Disable or 1/2:Enable */
-/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
-
-
-#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
-/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
-
-
-#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
-/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
-
-
-#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
-/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ Locale and Namespace Configurations
-/----------------------------------------------------------------------------*/
-
-#define _CODE_PAGE 437
-/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
-/ Incorrect setting of the code page can cause a file open failure.
-/
-/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
-/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
-/ 949 - Korean (DBCS, OEM, Windows)
-/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
-/ 1250 - Central Europe (Windows)
-/ 1251 - Cyrillic (Windows)
-/ 1252 - Latin 1 (Windows)
-/ 1253 - Greek (Windows)
-/ 1254 - Turkish (Windows)
-/ 1255 - Hebrew (Windows)
-/ 1256 - Arabic (Windows)
-/ 1257 - Baltic (Windows)
-/ 1258 - Vietnam (OEM, Windows)
-/ 437 - U.S. (OEM)
-/ 720 - Arabic (OEM)
-/ 737 - Greek (OEM)
-/ 775 - Baltic (OEM)
-/ 850 - Multilingual Latin 1 (OEM)
-/ 858 - Multilingual Latin 1 + Euro (OEM)
-/ 852 - Latin 2 (OEM)
-/ 855 - Cyrillic (OEM)
-/ 866 - Russian (OEM)
-/ 857 - Turkish (OEM)
-/ 862 - Hebrew (OEM)
-/ 874 - Thai (OEM, Windows)
-/ 1 - ASCII only (Valid for non LFN cfg.)
-*/
-
-
-#define _USE_LFN 0 /* 0 to 3 */
-#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
-/* The _USE_LFN option switches the LFN support.
-/
-/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
-/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
-/ 2: Enable LFN with dynamic working buffer on the STACK.
-/ 3: Enable LFN with dynamic working buffer on the HEAP.
-/
-/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
-/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
-/ to the project. When enable to use heap, memory control functions
-/ ff_memalloc() and ff_memfree() must be added to the project. */
-
-
-#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
-/* To switch the character code set on FatFs API to Unicode,
-/ enable LFN feature and set _LFN_UNICODE to 1. */
-
-
-#define _FS_RPATH 0 /* 0 to 2 */
-/* The _FS_RPATH option configures relative path feature.
-/
-/ 0: Disable relative path feature and remove related functions.
-/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
-/ 2: f_getcwd() is available in addition to 1.
-/
-/ Note that output of the f_readdir fnction is affected by this option. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ Physical Drive Configurations
-/----------------------------------------------------------------------------*/
-
-#define _VOLUMES 1
-/* Number of volumes (logical drives) to be used. */
-
-
-#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
-/* Maximum sector size to be handled.
-/ Always set 512 for memory card and hard disk but a larger value may be
-/ required for floppy disk (512/1024) and optical disk (512/2048).
-/ When _MAX_SS is larger than 512, GET_SECTOR_SIZE command must be implememted
-/ to the disk_ioctl function. */
-
-
-#define _MULTI_PARTITION 0 /* 0:Single partition or 1:Multiple partition */
-/* When set to 0, each volume is bound to the same physical drive number and
-/ it can mount only first primaly partition. When it is set to 1, each volume
-/ is tied to the partitions listed in VolToPart[]. */
-
-
-#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
-/* To enable sector erase feature, set _USE_ERASE to 1. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ System Configurations
-/----------------------------------------------------------------------------*/
-
-#define _WORD_ACCESS 0 /* 0 or 1 */
-/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
-/ option defines which access method is used to the word data on the FAT volume.
-/
-/ 0: Byte-by-byte access.
-/ 1: Word access. Do not choose this unless following condition is met.
-/
-/ When the byte order on the memory is big-endian or address miss-aligned word
-/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
-/ If it is not the case, the value can also be set to 1 to improve the
-/ performance and code size. */
-
-
-/* Include a header file here to define sync object types on the O/S */
-/* #include <windows.h>, <ucos_ii.h.h>, <semphr.h> or ohters. */
-
-#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
-#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
-#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
-
-/* The _FS_REENTRANT option switches the reentrancy of the FatFs module.
-/
-/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
-/ 1: Enable reentrancy. Also user provided synchronization handlers,
-/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
-/ function must be added to the project. */
-
-
-#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */
-/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value
- defines how many files can be opened simultaneously. */
-
-
-#endif /* _FFCONFIG */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/fsbl.h b/quad/xsdk_workspace/zybo_fsbl/src/fsbl.h
deleted file mode 100644
index edb0e039e48855ad119c479d2a66d84465a5f979..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/fsbl.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file fsbl.h
-*
-* Contains the function prototypes, defines and macros for the
-* First Stage Boot Loader (FSBL) functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 03/04/11 Initial release
-* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
-* xparameters.h file
-* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
-* Added the debug levels
-* 4.00a sgd 02/28/13 Removed DDR initialization check
-* Removed DDR ECC initialization code
-* Modified hand off address check to 1MB
-* Added RSA authentication support
-* Removed LPBK_DLY_ADJ register setting code as we use
-* divisor 8
-* Removed check for Fabric is already initialized
-*
-* CR's fixed and description
-* 689026: FSBL doesn't hold PL resets active during
-* bit download
-* Resolution: PL resets are released just before
-* handoff
-*
-* 689077: FSBL hangs at Handoff clearing the
-* TX UART buffer
-* Resolution: STDOUT_BASEADDRESS macro value changes
-* based UART select, hence used STDOUT_BASEADDRESS
-* as UART base address
-*
-* 695578: FSBL failed to load standalone application
-* in secure bootmode
-* Resolution: Application will be placed at load address
-* instead of DDR temporary address
-*
-* 699475: FSBL functionality is broken and its
-* not able to boot in QSPI/NAND bootmode
-* Resolution: New flags are added DevCfg driver
-* for handling loopback
-* XDCFG_CONCURRENT_NONSEC_READ_WRITE
-* XDCFG_CONCURRENT_SECURE_READ_WRITE
-*
-* 683145: Define stack area for FIQ, UNDEF modes
-* in linker file
-* Resolution: FSBL linker modified to create stack area
-* for FIQ, UNDEF
-*
-* 705664: FSBL fails to decrypt the bitstream when
-* the image is AES encrypted using non-zero key value
-* Resolution: Fabric cleaning will not be done
-* for AES-E-Fuse encryption
-*
-* Watchdog disabled for AES E-Fuse encryption
-*
-* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
-* Added QSPI Flash Size > 128Mbit support
-* QSPI Dual Stack support
-* Added Md5 checksum support
-*
-* CR's fixed and description
-* 692045 FSBL: Linker script of FSBL has PHDR workaround,
-* this needs to be fixed
-* Resolution: Removed PHDR from Linker file
-*
-* 704287 FSBL: fsbl.h file has a few error codes that
-* are not used by FSBL, that needs to be removed
-* Resolution: Removed unused error codes
-*
-* 704379 FSBL: Check if DDR is in proper state before
-* handoff
-* Resolution: Added DDR initialization check
-*
-* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
-* the debug level is FSBL_DEBUG only.
-*
-* 710128 FSBL: Linux boot failing without load attribute
-* set for Linux partitions in BIF
-* Resolution: FSBL will load partitions with valid load
-* address and stop loading if any invalid load address
-*
-* 708728 Issues seen while making HP interconnect
-* 32 bit wide
-* Resolution: ps7_post_config function generated by PCW
-* will be called after Bit stream download
-* Added MMC support
-* 6.00a kc 07/31/2013 CR's fixed and description
-* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
-* for authenticating the Partition images
-* Resolution: FSBL now uses the PPK left by Boot ROM in
-* OCM for authencating the SPK
-*
-* 724165 Partition Header used by FSBL is not
-* authenticated
-* Resolution: FSBL now authenticates the partition header
-*
-* 691150 ps7_init does not check for peripheral
-* initialization failures or timeout on polls
-* Resolution: Return value of ps7_init() is now checked
-* by FSBL and prints the error string
-*
-* 708316 PS7_init.tcl file should have Error mechanism
-* for all mask_poll
-* Resolution: Return value of ps7_init() is now checked
-* by FSBL and prints the error string
-*
-* 732062 FSBL fails to build if UART not available
-* Resolution: Added define to call xil_printf only
-* if uart is defined
-*
-* 722979 Provide customer-friendly changelogs in FSBL
-* Resolution: Added CR description for all the files
-*
-* 732865 Backward compatibility for ps7_init function
-* Resolution: Added a new define for ps7_init success
-* and value is defined based on ps7_init define
-*
-* Fix for CR#739711 - FSBL not able to read Large
-* QSPI (512M) in IO Mode
-* Resolution: Modified the address calculation
-* algorithm in dual parallel mode for QSPI
-*
-* </pre>
-*
-* </pre>
-*
-* @note
-*
-* Flags in FSBL
-*
-* FSBL_PERF
-*
-* This Flag can be set at compilation time. This flag is set for
-* measuring the performance of FSBL.That is the time taken to execute is
-* measured.when this flag is set.Execution time with reference to
-* global timer is taken here
-*
-* Total Execution time is the time taken for executing FSBL till handoff
-* to any application .
-* If there is a bitstream in the partition header then the
-* execution time includes the copying of the bitstream to DDR
-* (in case of SD/NAND bootmode)
-* and programming the devcfg dma is accounted.
-*
-* FSBL provides two debug levels
-* DEBUG GENERAL - fsbl_printf under this category will appear only when the
-* FSBL_DEBUG flag is set during compilation
-* DEBUG_INFO - fsbl_printf under this category will appear when the
-* FSBL_DEBUG_INFO flag is set during compilation
-* For a more detailed output log can be used.
-* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
-* RSA functions
-* These macros are input to the fsbl_printf function
-*
-* DEBUG LEVELS
-* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
-* that are with the DEBUG_GENERAL argument are shown
-* FSBL_DEBUG_INFO is level 2, when this flag is set during the
-* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
-*
-* DEFAULT LEVEL
-* By default no print messages will appear.
-*
-* NON_PS_INSTANTIATED_BITSTREAM
-*
-* FSBL will not enable the level shifters for a NON PS instantiated
-* Bitstream.This flag can be set during compilation for a NON PS instantiated
-* bitstream
-*
-* ECC_ENABLE
-* This flag will be defined in the ps7_init.h file when ECC is enabled
-* in the DDR configuration (XPS GUI)
-*
-* RSA_SUPPORT
-* This flag is used to enable authentication feature
-* Default this macro disabled, reason to avoid increase in code size
-*
-* MMC_SUPPORT
-* This flag is used to enable MMC support feature
-*
-*******************************************************************************/
-#ifndef XIL_FSBL_H
-#define XIL_FSBL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "xparameters.h"
-#include "xpseudo_asm.h"
-#include "xil_printf.h"
-#include "pcap.h"
-#include "fsbl_debug.h"
-#include "ps7_init.h"
-#ifdef FSBL_PERF
-#include "xtime_l.h"
-#include <stdio.h>
-#endif
-
-
-/************************** Constant Definitions *****************************/
-/*
- * SDK release version
- */
-#define SDK_RELEASE_VER 14
-#define SDK_SUB_VER 7
-#define SDK_RELEASE_YEAR 2013
-#define SDK_RELEASE_QUARTER 3
-
-#define WORD_LENGTH_SHIFT 2
-
-/*
- * On a Successful handoff to an application FSBL sets this SUCCESS code
- */
-#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
-
-/*
- * Backward compatibility for ps7_init
- */
-#ifdef NEW_PS7_ERR_CODE
-#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
-#else
-#define FSBL_PS7_INIT_SUCCESS (1)
-#endif
-
-/*
- * ERROR CODES
- * The following are the Error codes that FSBL uses
- * If the Debug prints are enabled only then the error codes will be
- * seen on the com port.Without the debug prints enabled no error codes will
- * be visible.There are not saved in any register
- * Boot Mode States used for error and status output
- * Error codes are defined below
- */
-#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
-#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
-#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
-#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
-#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
-#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
-#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
-#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
-#define NO_DDR 0xA008 /**< DDR missing */
-#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
-#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
-#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
-#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
-#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
-#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
-#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
-#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
-#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
-#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
-/*
- * FSBL Exception error codes
- */
-#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
-#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
-#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
-#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
-#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
-#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
-
-/*
- * FSBL hook routine failures
- */
-#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
-#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
- download hook failed */
-#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
- download hook failed */
-
-/*
- * Watchdog related Error codes
- */
-#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
-#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
-
-/*
- * SLCR Registers
- */
-#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
-#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
-#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
-#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
-#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
-#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
-#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
-
-/*
- * Efuse Status Register
- */
-#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
-#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
-
-/*
- * PS reset control register define
- */
-#define PS_RST_MASK 0x1 /**< PS software reset */
-
-/*
- * SLCR BOOT Mode Register defines
- */
-#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
-
-/*
- * Boot Modes
- */
-#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
-#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
-#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
-#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
-#define SD_MODE 0x00000005 /**< SD Boot Mode */
-#define MMC_MODE 0x00000006 /**< MMC Boot Device */
-
-#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
-#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
-
-/*
- * Golden image offset
- */
-#define GOLDEN_IMAGE_OFFSET 0x8000
-
-/*
- * Silicon Version
- */
-#define SILICON_VERSION_1 0
-#define SILICON_VERSION_2 1
-#define SILICON_VERSION_3 2
-#define SILICON_VERSION_3_1 3
-
-/*
- * DDR start address for storing the data temporarily(1M)
- * Need to finalize correct logic
- */
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
-#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
-#else
-/*
- * In case of PL DDR, this macros defined based PL DDR address
- */
-#define DDR_START_ADDR 0x00
-#define DDR_END_ADDR 0x00
-#endif
-
-#define DDR_TEMP_START_ADDR DDR_START_ADDR
-/*
- * DDR test pattern
- */
-#define DDR_TEST_PATTERN 0xAA55AA55
-#define DDR_TEST_OFFSET 0x100000
-/*
- *
- */
-#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
-#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
-#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
-#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
-#define LQSPI_CFG_OFFSET 0xA0
-#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
-
-/*
- * These are the SLCR lock and unlock macros
- */
-#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
-#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
-
-#define IMAGE_HEADER_CHECKSUM_COUNT 10
-
-/* Boot ROM Image defines */
-#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
-#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
-#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
-#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
-#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
-#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
-#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
-#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
-#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
-#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
-#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
-#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
-
-/* Reboot status register defines:
- * 0xF0000000 for FSBL fallback mask to notify Boot Rom
- * 0x60000000 for FSBL to mark that FSBL has not handoff yet
- * 0x00FFFFFF for user application to use across soft reset
- */
-#define FSBL_FAIL_MASK 0xF0000000
-#define FSBL_IN_MASK 0x60000000
-
-/* The address that holds the base address for the image Boot ROM found */
-#define BASEADDR_HOLDER 0xFFFFFFF8
-
-/**************************** Type Definitions *******************************/
-
-/************************** Function Prototypes ******************************/
-
-void OutputStatus(u32 State);
-void FsblFallback(void);
-
-int FsblSetNextPartition(int Num);
-void *(memcpy_rom)(void * s1, const void * s2, u32 n);
-char *strcpy_rom(char *Dest, const char *Src);
-
-void ClearFSBLIn(void);
-void MarkFSBLIn(void);
-void FsblHandoff(u32 FsblStartAddr);
-u32 GetResetReason(void);
-
-#ifdef FSBL_PERF
-void FsblGetGlobalTime (XTime tCur);
-void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
-#endif
-void GetSiliconVersion(void);
-void FsblHandoffExit(u32 FsblStartAddr);
-void FsblHandoffJtagExit();
-/************************** Variable Definitions *****************************/
-extern int SkipPartition;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_debug.h b/quad/xsdk_workspace/zybo_fsbl/src/fsbl_debug.h
deleted file mode 100644
index a03cf621695cd4a7fed8a90bc3f66ecb1f8d81e9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_debug.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**************************************************************
- * (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
- *
- * This file contains confidential and proprietary information
- * of Xilinx, Inc. and is protected under U.S. and
- * international copyright and other intellectual property
- * laws.
- *
- * DISCLAIMER
- * This disclaimer is not a license and does not grant any
- * rights to the materials distributed herewith. Except as
- * otherwise provided in a valid license issued to you by
- * Xilinx, and to the maximum extent permitted by applicable
- * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- * (2) Xilinx shall not be liable (whether in contract or tort,
- * including negligence, or under any other theory of
- * liability) for any loss or damage of any kind or nature
- * related to, arising under or in connection with these
- * materials, including for any direct, or any indirect,
- * special, incidental, or consequential loss or damage
- * (including loss of data, profits, goodwill, or any type of
- * loss or damage suffered as a result of any action brought
- * by a third party) even if such damage or loss was
- * reasonably foreseeable or Xilinx had been advised of the
- * possibility of the same.
- *
- * CRITICAL APPLICATIONS
- * Xilinx products are not designed or intended to be fail-
- * safe, or for use in any application requiring fail-safe
- * performance, such as life-support or safety devices or
- * systems, Class III medical devices, nuclear facilities,
- * applications related to the deployment of airbags, or any
- * other applications that could lead to death, personal
- * injury, or severe property or environmental damage
- * (individually and collectively, "Critical
- * Applications"). Customer assumes the sole risk and
- * liability of any use of Xilinx products in Critical
- * Applications, subject only to applicable laws and
- * regulations governing limitations on product liability.
- *
- * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- * PART OF THIS FILE AT ALL TIMES.
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file fsbl_debug.h
-*
-* This file contains the debug verbose information for FSBL print functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a mb 01/09/12 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef _FSBL_DEBUG_H
-#define _FSBL_DEBUG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#define DEBUG_GENERAL 0x00000001 /* general debug messages */
-#define DEBUG_INFO 0x00000002 /* More debug information */
-
-#if defined (FSBL_DEBUG_INFO)
-#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
-#elif defined (FSBL_DEBUG)
-#define fsbl_dbg_current_types (DEBUG_GENERAL)
-#else
-#define fsbl_dbg_current_types 0
-#endif
-
-#ifdef STDOUT_BASEADDRESS
-#define fsbl_printf(type,...) \
- if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
-#else
-#define fsbl_printf(type, ...)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FSBL_DEBUG_H */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_handoff.S b/quad/xsdk_workspace/zybo_fsbl/src/fsbl_handoff.S
deleted file mode 100644
index 8aa30897745719594c39cea15aebee2e160cceb5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_handoff.S
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file handoff.S
-*
-* Contains the code that does the handoff to the loaded application. This
-* code lives high in the ROM.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date.word Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 03/01/10 Initial release
-*
-* </pre>
-*
-* @note
-* Assumes that the starting address of the FSBL is provided by the calling routine
-* in R0.
-*
-******************************************************************************/
-
-.globl FsblHandoffJtagExit
-
-.globl FsblHandoffExit
-
-.section .handoff,"axS"
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-FsblHandoffJtagExit:
- mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
- mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
-
- dsb
- isb /* make sure it completes */
-
- ldr r4, =0
- mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
-
- isb /* make sure it completes */
-Loop:
- wfe
- b Loop
-
-FsblHandoffExit:
- mov lr, r0 /* move the destination address into link register */
-
- mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
- mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
-
- dsb
- isb /* make sure it completes */
-
- ldr r4, =0
- mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
-
- isb /* make sure it completes */
-
-
- bx lr /* force the switch, destination should have been in r0 */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-.end
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_hooks.c b/quad/xsdk_workspace/zybo_fsbl/src/fsbl_hooks.c
deleted file mode 100644
index 7b27a25e79d5c78438b8d5b4e1b09fcbc8eb2a99..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_hooks.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-
-/*****************************************************************************
-*
-* @file fsbl_hooks.c
-*
-* This file provides functions that serve as user hooks. The user can add the
-* additional functionality required into these routines. This would help retain
-* the normal FSBL flow unchanged.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a np 08/03/12 Initial release
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-
-#include "fsbl.h"
-#include "xstatus.h"
-#include "fsbl_hooks.h"
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/******************************************************************************
-* This function is the hook which will be called before the bitstream download.
-* The user can add all the customized code required to be executed before the
-* bitstream download to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookBeforeBitstreamDload(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here. Errors to be stored in the status variable
- * and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
-
- return (Status);
-}
-
-/******************************************************************************
-* This function is the hook which will be called after the bitstream download.
-* The user can add all the customized code required to be executed after the
-* bitstream download to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookAfterBitstreamDload(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
-
- return (Status);
-}
-
-/******************************************************************************
-* This function is the hook which will be called before the FSBL does a handoff
-* to the application. The user can add all the customized code required to be
-* executed before the handoff to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookBeforeHandoff(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
-
- return (Status);
-}
-
-
-/******************************************************************************
-* This function is the hook which will be called in case FSBL fall back
-*
-* @param None
-*
-* @return None
-*
-****************************************************************************/
-void FsblHookFallback(void)
-{
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
- while(1);
-}
-
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_hooks.h b/quad/xsdk_workspace/zybo_fsbl/src/fsbl_hooks.h
deleted file mode 100644
index 6ba5c039fb67ec6696820987f7ad7d87f558deae..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/fsbl_hooks.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file fsbl_hooks.h
-*
-* Contains the function prototypes, defines and macros required by fsbl_hooks.c
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a np/mb 10/08/12 Initial release
-* Corrected the prototype
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef FSBL_HOOKS_H_
-#define FSBL_HOOKS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-
-/************************** Function Prototypes ******************************/
-
-/* FSBL hook function which is called before bitstream download */
-u32 FsblHookBeforeBitstreamDload(void);
-
-/* FSBL hook function which is called after bitstream download */
-u32 FsblHookAfterBitstreamDload(void);
-
-/* FSBL hook function which is called before handoff to the application */
-u32 FsblHookBeforeHandoff(void);
-
-/* FSBL hook function which is called in FSBL fallback */
-void FsblHookFallback(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/image_mover.c b/quad/xsdk_workspace/zybo_fsbl/src/image_mover.c
deleted file mode 100644
index 81ab06a5135fffa9f2bcf9117b611c323326f447..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/image_mover.c
+++ /dev/null
@@ -1,1301 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file image_mover.c
-*
-* Move partitions to either DDR to execute or to program FPGA.
-* It performs partition walk.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 05/24/11 Initial release
-* 2.00a jz 06/30/11 Updated partition header defs for 64-byte
-* alignment change in data2mem tool
-* 2.00a mb 05/25/12 Updated for standalone based bsp FSBL
-* Nand/SD encryption and review comments
-* 3.00a np 08/30/12 Added FSBL user hook calls
-* (before and after bitstream download.)
-* 4.00a sgd 02/28/13 Fix for CR#691148
-* Fix for CR#695578
-*
-* 4.00a sgd 04/23/13 Fix for CR#710128
-* 5.00a kc 07/30/13 Fix for CR#724165
-* Fix for CR#724166
-* Fix for CR#732062
-*
-* </pre>
-*
-* @note
-* A partition is either an executable or a bitstream to program FPGA
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "image_mover.h"
-#include "xil_printf.h"
-#include "xreg_cortexa9.h"
-#include "pcap.h"
-#include "fsbl_hooks.h"
-#include "md5.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-#ifdef RSA_SUPPORT
-#include "rsa.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/* We are 32-bit machine */
-#define MAXIMUM_IMAGE_WORD_LEN 0x40000000
-#define MD5_CHECKSUM_SIZE 16
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset);
-u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum);
-u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum);
-
-/************************** Variable Definitions *****************************/
-/*
- * Partition information flags
- */
-u8 EncryptedPartitionFlag;
-u8 PLPartitionFlag;
-u8 PSPartitionFlag;
-u8 SignedPartitionFlag;
-u8 PartitionChecksumFlag;
-u8 BitstreamFlag;
-u8 ApplicationFlag;
-
-u32 ExecutionAddress;
-ImageMoverType MoveImage;
-
-/*
- * Header array
- */
-PartHeader PartitionHeader[MAX_PARTITION_NUMBER];
-u32 PartitionCount;
-u32 FsblLength;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-extern u32 Silicon_Version;
-extern u32 FlashReadBaseAddress;
-extern u8 LinearBootDeviceFlag;
-extern XDcfg *DcfgInstPtr;
-
-/*****************************************************************************/
-/**
-*
-* This function
-*
-* @param
-*
-* @return
-*
-*
-* @note None
-*
-****************************************************************************/
-u32 LoadBootImage(void)
-{
- u32 RebootStatusRegister = 0;
- u32 MultiBootReg = 0;
- u32 ImageStartAddress = 0;
- u32 PartitionNum;
- u32 PartitionDataLength;
- u32 PartitionImageLength;
- u32 PartitionTotalSize;
- u32 PartitionExecAddr;
- u32 PartitionAttr;
- u32 ExecAddress = 0;
- u32 PartitionLoadAddr;
- u32 PartitionStartAddr;
- u32 PartitionChecksumOffset;
- u8 ExecAddrFlag = 0 ;
- u32 Status;
- PartHeader *HeaderPtr;
- u32 EfuseStatusRegValue;
-#ifdef RSA_SUPPORT
- u32 HeaderSize;
-#endif
- /*
- * Resetting the Flags
- */
- BitstreamFlag = 0;
- ApplicationFlag = 0;
-
- RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
- fsbl_printf(DEBUG_INFO,
- "Reboot status register: 0x%08x\r\n",RebootStatusRegister);
-
- if (Silicon_Version == SILICON_VERSION_1) {
- /*
- * Clear out fallback mask from previous run
- * We start from the first partition again
- */
- if ((RebootStatusRegister & FSBL_FAIL_MASK) ==
- FSBL_FAIL_MASK) {
- fsbl_printf(DEBUG_INFO,
- "Reboot status shows previous run falls back\r\n");
- RebootStatusRegister &= ~(FSBL_FAIL_MASK);
- Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister);
- }
-
- /*
- * Read the image start address
- */
- ImageStartAddress = *(u32 *)BASEADDR_HOLDER;
- } else {
- /*
- * read the multiboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08x\r\n",MultiBootReg);
-
- /*
- * Compute the image start address
- */
- ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
- }
-
- fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08x\r\n",ImageStartAddress);
-
- /*
- * Get partitions header information
- */
- Status = GetPartitionHeaderInfo(ImageStartAddress);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
-
- /*
- * RSA is not implemented in 1.0 and 2.0
- * silicon
- */
- if ((Silicon_Version != SILICON_VERSION_1) &&
- (Silicon_Version != SILICON_VERSION_2)) {
- /*
- * Read Efuse Status Register
- */
- EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG);
- if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) {
- fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n");
-#ifdef RSA_SUPPORT
- /*
- * Set the Ppk
- */
- SetPpk();
-
- /*
- * Read partition header with signature
- */
- Status = GetImageHeaderAndSignature(ImageStartAddress,
- (u32 *)DDR_TEMP_START_ADDR);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,
- "Read Partition Header signature Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
- HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE;
-
- Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,
- "Partition Header signature Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
-#else
- /*
- * In case user not enabled RSA authentication feature
- */
- fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
- OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
- FsblFallback();
-#endif
- }
- }
-
-#ifdef MMC_SUPPORT
- /*
- * In case of MMC support
- * boot image preset in MMC will not have FSBL partition
- */
- PartitionNum = 0;
-#else
- /*
- * First partition header was ignored by FSBL
- * As it contain FSBL partition information
- */
- PartitionNum = 1;
-#endif
-
- while (PartitionNum < PartitionCount) {
-
- fsbl_printf(DEBUG_INFO, "Partition Number: %d\r\n", PartitionNum);
-
- HeaderPtr = &PartitionHeader[PartitionNum];
-
- /*
- * Print partition header information
- */
- HeaderDump(HeaderPtr);
-
- /*
- * Validate partition header
- */
- Status = ValidateHeader(HeaderPtr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n");
- OutputStatus(INVALID_HEADER_FAIL);
- FsblFallback();
- }
-
- /*
- * Load partition header information in to local variables
- */
- PartitionDataLength = HeaderPtr->DataWordLen;
- PartitionImageLength = HeaderPtr->ImageWordLen;
- PartitionExecAddr = HeaderPtr->ExecAddr;
- PartitionAttr = HeaderPtr->PartitionAttr;
- PartitionLoadAddr = HeaderPtr->LoadAddr;
- PartitionChecksumOffset = HeaderPtr->CheckSumOffset;
- PartitionStartAddr = HeaderPtr->PartitionStart;
- PartitionTotalSize = HeaderPtr->PartitionWordLen;
-
-
- if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) {
- fsbl_printf(DEBUG_INFO, "Bitstream\r\n");
- PLPartitionFlag = 1;
- PSPartitionFlag = 0;
- BitstreamFlag = 1;
- if (ApplicationFlag == 1) {
-#ifdef STDOUT_BASEADDRESS
- xil_printf("\r\nFSBL Warning !!!"
- "Bitstream not loaded into PL\r\n");
- xil_printf("Partition order invalid\r\n");
-#endif
- break;
- }
- }
-
- if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) {
- fsbl_printf(DEBUG_INFO, "Application\r\n");
- PSPartitionFlag = 1;
- PLPartitionFlag = 0;
- ApplicationFlag = 1;
- }
-
- /*
- * Encrypted partition will have different value
- * for Image length and data length
- */
- if (PartitionDataLength != PartitionImageLength) {
- fsbl_printf(DEBUG_INFO, "Encrypted\r\n");
- EncryptedPartitionFlag = 1;
- } else {
- EncryptedPartitionFlag = 0;
- }
-
- /*
- * Check for partition checksum check
- */
- if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) {
- PartitionChecksumFlag = 1;
- } else {
- PartitionChecksumFlag = 0;
- }
-
- /*
- * RSA signature check
- */
- if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) {
- fsbl_printf(DEBUG_INFO, "RSA Signed\r\n");
- SignedPartitionFlag = 1;
- } else {
- SignedPartitionFlag = 0;
- }
-
- /*
- * Load address check
- * Loop will break when PS load address zero and partition is
- * un-signed or un-encrypted
- */
- if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) {
- if ((PartitionLoadAddr == 0) &&
- (!((SignedPartitionFlag == 1) ||
- (EncryptedPartitionFlag == 1)))) {
- break;
- } else {
- fsbl_printf(DEBUG_GENERAL,
- "INVALID_LOAD_ADDRESS_FAIL\r\n");
- OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
- FsblFallback();
- }
- }
-
- if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) {
- fsbl_printf(DEBUG_GENERAL,
- "INVALID_LOAD_ADDRESS_FAIL\r\n");
- OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
- FsblFallback();
- }
-
- /*
- * Load execution address of first PS partition
- */
- if (PSPartitionFlag && (!ExecAddrFlag)) {
- ExecAddrFlag++;
- ExecAddress = PartitionExecAddr;
- }
-
- /*
- * FSBL user hook call before bitstream download
- */
- if (PLPartitionFlag) {
- Status = FsblHookBeforeBitstreamDload();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n");
- OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL);
- FsblFallback();
- }
- }
-
- /*
- * Move partitions from boot device
- */
- Status = PartitionMove(ImageStartAddress, HeaderPtr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n");
- OutputStatus(PARTITION_MOVE_FAIL);
- FsblFallback();
- }
-
- if ((SignedPartitionFlag) || (PartitionChecksumFlag)) {
- if(PLPartitionFlag) {
- /*
- * PL partition loaded in to DDR temporary address
- * for authentication and checksum verification
- */
- PartitionStartAddr = DDR_TEMP_START_ADDR;
- } else {
- PartitionStartAddr = PartitionLoadAddr;
- }
-
- if (PartitionChecksumFlag) {
- /*
- * Validate the partition data with checksum
- */
- Status = ValidateParition(PartitionStartAddr,
- (PartitionTotalSize << WORD_LENGTH_SHIFT),
- (PartitionChecksumOffset << WORD_LENGTH_SHIFT));
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n");
- OutputStatus(PARTITION_CHECKSUM_FAIL);
- FsblFallback();
- }
-
- fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n");
- }
-
- /*
- * Authentication Partition
- */
- if (SignedPartitionFlag == 1 ) {
-#ifdef RSA_SUPPORT
- Status = AuthenticatePartition((u8*)PartitionStartAddr,
- (PartitionTotalSize << WORD_LENGTH_SHIFT));
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n");
- OutputStatus(AUTHENTICATION_FAIL);
- FsblFallback();
- }
- fsbl_printf(DEBUG_INFO,"Authentication Done\r\n");
-#else
- /*
- * In case user not enabled RSA authentication feature
- */
- fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
- OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
- FsblFallback();
-#endif
- }
-
- /*
- * Decrypt PS partition
- */
- if (EncryptedPartitionFlag && PSPartitionFlag) {
- Status = DecryptPartition(PartitionStartAddr,
- PartitionDataLength,
- PartitionImageLength);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n");
- OutputStatus(DECRYPTION_FAIL);
- FsblFallback();
- }
- }
-
- /*
- * Load Signed PL partition in Fabric
- */
- if (PLPartitionFlag) {
- Status = PcapLoadPartition((u32*)PartitionStartAddr,
- (u32*)PartitionLoadAddr,
- PartitionImageLength,
- PartitionDataLength,
- EncryptedPartitionFlag);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n");
- OutputStatus(BITSTREAM_DOWNLOAD_FAIL);
- FsblFallback();
- }
- }
- }
-
-
- /*
- * FSBL user hook call after bitstream download
- */
- if (PLPartitionFlag) {
- Status = FsblHookAfterBitstreamDload();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n");
- OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL);
- FsblFallback();
- }
- }
- /*
- * Increment partition number
- */
- PartitionNum++;
- }
-
- return ExecAddress;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function loads all partition header information in global array
-*
-* @param ImageAddress is the start address of the image
-*
-* @return - XST_SUCCESS if Get partition Header information successful
-* - XST_FAILURE if Get Partition Header information failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
-{
- u32 PartitionHeaderOffset;
- u32 Status;
-
-
- /*
- * Get the length of the FSBL from BootHeader
- */
- Status = GetFsblLength(ImageBaseAddress, &FsblLength);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Get the start address of the partition header table
- */
- Status = GetPartitionHeaderStartAddr(ImageBaseAddress,
- &PartitionHeaderOffset);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Header offset on flash
- */
- PartitionHeaderOffset += ImageBaseAddress;
-
- fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08x\r\n",
- PartitionHeaderOffset);
-
- /*
- * Load all partitions header data in to global variable
- */
- Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset,
- &PartitionHeader[0]);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Get partitions count from partitions header information
- */
- PartitionCount = GetPartitionCount(&PartitionHeader[0]);
-
- fsbl_printf(DEBUG_INFO, "Partition Count: %d\r\n", PartitionCount);
-
- /*
- * Partition Count check
- */
- if (PartitionCount >= MAX_PARTITION_NUMBER) {
- fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n");
- return XST_FAILURE;
-
- } else if (PartitionCount <= 1) {
- fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function goes to the partition header of the specified partition
-*
-* @param ImageAddress is the start address of the image
-*
-* @return Offset Partition header address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function goes to the partition header of the specified partition
-*
-* @param ImageAddress is the start address of the image
-*
-* @return Offset to Image header table address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-/*****************************************************************************/
-/**
-*
-* This function gets the length of the FSBL
-*
-* @param ImageAddress is the start address of the image
-*
-* @return FsblLength is the length of the fsbl
-*
-* @return - XST_SUCCESS if fsbl length reading is successful
-* - XST_FAILURE if fsbl length reading failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET,
- (u32)FsblLength, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-#ifdef RSA_SUPPORT
-/*****************************************************************************/
-/**
-*
-* This function goes to read the image headers and its signature. Image
-* header consists of image header table, image headers, partition
-* headers
-*
-* @param ImageBaseAddress is the start address of the image header
-*
-* @return Offset Partition header address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset)
-{
- u32 Status;
- u32 ImageHeaderOffset;
-
- /*
- * Get the start address of the partition header table
- */
- Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset,
- TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
-/*****************************************************************************/
-/**
-*
-* This function get the header information of the all the partitions and load into
-* global array
-*
-* @param PartHeaderOffset Offset address where the header information present
-*
-* @param Header Partition header pointer
-*
-* @return - XST_SUCCESS if Load Partitions Header information successful
-* - XST_FAILURE if Load Partitions Header information failed
-*
-* @note None
-*
-****************************************************************************/
-u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header)
-{
- u32 Status;
-
- Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function dumps the partition header.
-*
-* @param Header Partition header pointer
-*
-* @return None
-*
-* @note None
-*
-******************************************************************************/
-void HeaderDump(PartHeader *Header)
-{
- fsbl_printf(DEBUG_INFO, "Header Dump\r\n");
- fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08x\r\n",
- Header->ImageWordLen);
- fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08x\r\n",
- Header->DataWordLen);
- fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08x\r\n",
- Header->PartitionWordLen);
- fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08x\r\n",
- Header->LoadAddr);
- fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08x\r\n",
- Header->ExecAddr);
- fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08x\r\n",
- Header->PartitionStart);
- fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08x\r\n",
- Header->PartitionAttr);
- fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08x\r\n",
- Header->CheckSumOffset);
- fsbl_printf(DEBUG_INFO, "Section Count: 0x%08x\r\n",
- Header->SectionCount);
- fsbl_printf(DEBUG_INFO, "Checksum: 0x%08x\r\n",
- Header->CheckSum);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function calculates the partitions count from header information
-*
-* @param Header Partition header pointer
-*
-* @return Count Partition count
-*
-* @note None
-*
-*******************************************************************************/
-u32 GetPartitionCount(PartHeader *Header)
-{
- u32 Count=0;
- struct HeaderArray *Hap;
-
- for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) {
- Hap = (struct HeaderArray *)&Header[Count];
- if(IsLastPartition(Hap)!=XST_FAILURE)
- break;
- }
-
- return Count;
-}
-
-/******************************************************************************/
-/**
-* This function check whether the current partition is the end of partitions
-*
-* The partition is the end of the partitions if it looks like this:
-* 0x00000000
-* 0x00000000
-* ....
-* 0x00000000
-* 0x00000000
-* 0xFFFFFFFF
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS if it is the last partition
-* - XST_FAILURE if it is not last partition
-*
-****************************************************************************/
-u32 IsLastPartition(struct HeaderArray *H)
-{
- int Index;
-
- if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) {
- return XST_FAILURE;
- }
-
- for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) {
-
- if (H->Fields[Index] != 0x0) {
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function validates the partition header.
-*
-* @param Header Partition header pointer
-*
-* @return
-* - XST_FAILURE if bad header.
-* - XST_SUCCESS if successful.
-*
-* @note None
-*
-*******************************************************************************/
-u32 ValidateHeader(PartHeader *Header)
-{
- struct HeaderArray *Hap;
-
- Hap = (struct HeaderArray *)Header;
-
- /*
- * If there are no partitions to load, fail
- */
- if (IsEmptyHeader(Hap) == XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Validate partition header checksum
- */
- if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Validate partition data size
- */
- if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) {
- fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-* This function check whether the current partition header is empty.
-* A partition header is considered empty if image word length is 0 and the
-* last word is 0.
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS , If the partition header is empty
-* - XST_FAILURE , If the partition header is NOT empty
-*
-* @note Caller is responsible to make sure the address is valid.
-*
-*
-****************************************************************************/
-u32 IsEmptyHeader(struct HeaderArray *H)
-{
- int Index;
-
- for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) {
- if (H->Fields[Index] != 0x0) {
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function checks the header checksum If the header checksum is not valid
-* XST_FAILURE is returned.
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS is header checksum is ok
-* - XST_FAILURE if the header checksum is not correct
-*
-* @note None.
-*
-****************************************************************************/
-u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H)
-{
- u32 Checksum;
- u32 Count;
-
- Checksum = 0;
-
- for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) {
- /*
- * Read the word from the header
- */
- Checksum += H->Fields[Count];
- }
-
- /*
- * Invert checksum, last bit of error checking
- */
- Checksum ^= 0xFFFFFFFF;
-
- /*
- * Validate the checksum
- */
- if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) {
- fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8x != 0x%8.8x\r\n",
- Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function load the partition from boot device
-*
-* @param ImageBaseAddress Base address on flash
-* @param Header Partition header pointer
-*
-* @return
-* - XST_SUCCESS if partition move successful
-* - XST_FAILURE if check failed move failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header)
-{
- u32 SourceAddr;
- u32 Status;
- u8 SecureTransferFlag = 0;
- u32 LoadAddr;
- u32 ImageWordLen;
- u32 DataWordLen;
-
- SourceAddr = ImageBaseAddress;
- SourceAddr += Header->PartitionStart<<WORD_LENGTH_SHIFT;
- LoadAddr = Header->LoadAddr;
- ImageWordLen = Header->ImageWordLen;
- DataWordLen = Header->DataWordLen;
-
- /*
- * Add flash base address for linear boot devices
- */
- if (LinearBootDeviceFlag) {
- SourceAddr += FlashReadBaseAddress;
- }
-
- /*
- * Partition encrypted
- */
- if(EncryptedPartitionFlag) {
- SecureTransferFlag = 1;
- }
-
- /*
- * For Signed partition, Total partition image need to copied to DDR
- */
- if (SignedPartitionFlag) {
- ImageWordLen = Header->PartitionWordLen;
- DataWordLen = Header->PartitionWordLen;
- }
-
- /*
- * Encrypted and Signed PS partition need to be loaded on to DDR
- * without decryption
- */
- if (PSPartitionFlag &&
- (SignedPartitionFlag || PartitionChecksumFlag) &&
- EncryptedPartitionFlag) {
- SecureTransferFlag = 0;
- }
-
- /*
- * CPU is used for data transfer in case of non-linear
- * boot device
- */
- if (!LinearBootDeviceFlag) {
- /*
- * PL partition copied to DDR temporary location
- */
- if (PLPartitionFlag) {
- LoadAddr = DDR_TEMP_START_ADDR;
- }
-
- Status = MoveImage(SourceAddr,
- LoadAddr,
- (ImageWordLen << WORD_LENGTH_SHIFT));
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * As image present at load address
- */
- SourceAddr = LoadAddr;
- }
-
- if ((LinearBootDeviceFlag && PLPartitionFlag &&
- (SignedPartitionFlag || PartitionChecksumFlag)) ||
- (LinearBootDeviceFlag && PSPartitionFlag) ||
- ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) {
- /*
- * PL signed partition copied to DDR temporary location
- * using non-secure PCAP for linear boot device
- */
- if(PLPartitionFlag){
- SecureTransferFlag = 0;
- LoadAddr = DDR_TEMP_START_ADDR;
- }
-
- /*
- * Data transfer using PCAP
- */
- Status = PcapDataTransfer((u32*)SourceAddr,
- (u32*)LoadAddr,
- ImageWordLen,
- DataWordLen,
- SecureTransferFlag);
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * As image present at load address
- */
- SourceAddr = LoadAddr;
- }
-
- /*
- * Load Bitstream partition in to fabric only
- * if checksum and authentication bits are not set
- */
- if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) {
- Status = PcapLoadPartition((u32*)SourceAddr,
- (u32*)Header->LoadAddr,
- Header->ImageWordLen,
- Header->DataWordLen,
- EncryptedPartitionFlag);
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n");
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function load the decrypts partition
-*
-* @param StartAddr Source start address
-* @param DataLength Data length in words
-* @param ImageLength Image length in words
-*
-* @return
-* - XST_SUCCESS if decryption successful
-* - XST_FAILURE if decryption failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength)
-{
- u32 Status;
- u8 SecureTransferFlag =1;
-
- /*
- * Data transfer using PCAP
- */
- Status = PcapDataTransfer((u32*)StartAddr,
- (u32*)StartAddr,
- ImageLength,
- DataLength,
- SecureTransferFlag);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Validate Partition Data by using checksum preset in image
-*
-* @param Partition header pointer
-* @param Partition check sum offset
-* @return
-* - XST_SUCCESS if partition data is ok
-* - XST_FAILURE if partition data is corrupted
-*
-* @note None
-*
-*******************************************************************************/
-u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset)
-{
- u8 Checksum[MD5_CHECKSUM_SIZE];
- u8 CalcChecksum[MD5_CHECKSUM_SIZE];
- u32 Status;
- u32 Index;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * Get checksum from flash
- */
- Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO, "Actual checksum\r\n");
-
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]);
- }
-
- fsbl_printf(DEBUG_INFO, "\r\n");
-
- /*
- * Calculate checksum for the partition
- */
- Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n");
-
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]);
- }
-
- fsbl_printf(DEBUG_INFO, "\r\n");
-
- /*
- * Compare actual checksum with the calculated checksum
- */
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- if(Checksum[Index] != CalcChecksum[Index]) {
- fsbl_printf(DEBUG_GENERAL, "Error: "
- "Partition DataChecksum 0x%0x!= 0x%0x\r\n",
- Checksum[Index], CalcChecksum[Index]);
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function gets partition checksum from flash
-*
-* @param Check sum offset
-* @param Checksum pointer
-* @return
-* - XST_SUCCESS if checksum read success
-* - XST_FAILURE if unable get checksum
-*
-* @note None
-*
-*******************************************************************************/
-u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum)
-{
- u32 Status;
-
- Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function calculates the checksum preset in image
-*
-* @param Start address
-* @param Length of the data
-* @param Checksum pointer
-*
-* @return
-* - XST_SUCCESS if Checksum calculate successful
-* - XST_FAILURE if Checksum calculate failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum)
-{
- /*
- * Calculate checksum using MD5 algorithm
- */
- md5((u8*)SourceAddr, DataLength, Checksum, 0 );
-
- return XST_SUCCESS;
-}
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/image_mover.h b/quad/xsdk_workspace/zybo_fsbl/src/image_mover.h
deleted file mode 100644
index e74d0bebc73914649fe4215781373086dfe4059c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/image_mover.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file image_mover.h
-*
-* This file contains the interface for moving the image from FLASH to OCM
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 03/04/11 Initial release
-* 2.00a jz 06/04/11 partition header expands to 12 words
-* 5.00a kc 07/30/13 Added defines for image header information
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___IMAGE_MOVER_H___
-#define ___IMAGE_MOVER_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define PARTITION_NUMBER_SHIFT 24
-#define MAX_PARTITION_NUMBER (0xE)
-
-/* Boot Image Header defines */
-#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
-#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
-#define IMAGE_HEADER_SIZE (64)
-#define IMAGE_HEADER_TABLE_SIZE (64)
-#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
-#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
-#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
- TOTAL_IMAGE_HEADER_SIZE + \
- TOTAL_PARTITION_HEADER_SIZE + 64)
-
-/* Partition Header defines */
-#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
-#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
-#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
-#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
-#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
-#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
-#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
-#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
-#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
-#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
-#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
-
-/* Attribute word defines */
-#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
-#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
-#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
-#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
-#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
-
-
-/**************************** Type Definitions *******************************/
-typedef u32 (*ImageMoverType)( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-typedef struct StructPartHeader {
- u32 ImageWordLen; /* 0x0 */
- u32 DataWordLen; /* 0x4 */
- u32 PartitionWordLen; /* 0x8 */
- u32 LoadAddr; /* 0xC */
- u32 ExecAddr; /* 0x10 */
- u32 PartitionStart; /* 0x14 */
- u32 PartitionAttr; /* 0x18 */
- u32 SectionCount; /* 0x1C */
- u32 CheckSumOffset; /* 0x20 */
- u32 Pads1[1];
- u32 ACOffset; /* 0x28 */
- u32 Pads2[4];
- u32 CheckSum; /* 0x3C */
-}PartHeader;
-
-struct HeaderArray {
- u32 Fields[16];
-};
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define MoverIn32 Xil_In32
-#define MoverOut32 Xil_Out32
-
-/************************** Function Prototypes ******************************/
-u32 LoadBootImage(void);
-u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
-u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
-u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
-u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
-u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset);
-u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
-u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
-u32 IsEmptyHeader(struct HeaderArray *H);
-u32 IsLastPartition(struct HeaderArray *H);
-void HeaderDump(PartHeader *Header);
-u32 GetPartitionCount(PartHeader *Header);
-u32 ValidateHeader(PartHeader *Header);
-u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___IMAGE_MOVER_H___ */
-
-
-
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/integer.h b/quad/xsdk_workspace/zybo_fsbl/src/integer.h
deleted file mode 100644
index 75f5709a3873ba02f6928f1fc612d2f62d7aa028..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/integer.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*-------------------------------------------*/
-/* Integer type definitions for FatFs module */
-/*-------------------------------------------*/
-
-#ifndef _INTEGER
-#define _INTEGER
-
-#ifdef _WIN32 /* FatFs development platform */
-
-#include <tchar.h>
-
-#else /* Embedded platform */
-
-/* These types must be 16-bit, 32-bit or larger integer */
-typedef int INT;
-typedef unsigned int UINT;
-
-/* These types must be 8-bit integer */
-typedef char CHAR;
-typedef unsigned char UCHAR;
-typedef unsigned char BYTE;
-
-/* These types must be 16-bit integer */
-typedef short SHORT;
-typedef unsigned short USHORT;
-typedef unsigned short WORD;
-typedef unsigned short WCHAR;
-
-/* These types must be 32-bit integer */
-typedef long LONG;
-typedef unsigned long ULONG;
-typedef unsigned long DWORD;
-
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/librsa.a b/quad/xsdk_workspace/zybo_fsbl/src/librsa.a
deleted file mode 100644
index cdf35a3f339c3d48fe2c67eea6e13806618178a2..0000000000000000000000000000000000000000
Binary files a/quad/xsdk_workspace/zybo_fsbl/src/librsa.a and /dev/null differ
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/lscript.ld b/quad/xsdk_workspace/zybo_fsbl/src/lscript.ld
deleted file mode 100644
index d86df11b1e9cc1e5f3a74586509fdd18dfbda07b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/lscript.ld
+++ /dev/null
@@ -1,287 +0,0 @@
-/*******************************************************************/
-/* */
-/* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved */
-/* */
-/* Description : FSBL Linker Script */
-/* */
-/*******************************************************************/
-
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
-
-_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
-
-_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
-_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
-_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
-_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
-
-/* Define Memories in the system */
-
-MEMORY
-{
- ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
- ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
-}
-
-/* Specify the default entry point to the program */
-
-ENTRY(_vector_table)
-
-
-SECTIONS
-{
-.text : {
- *(.vectors)
- *(.boot)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
- *(.plt)
- *(.gnu_warning)
- *(.gcc_execpt_table)
- *(.glue_7)
- *(.glue_7t)
- *(.vfp11_veneer)
- *(.ARM.extab)
- *(.gnu.linkonce.armextab.*)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.init : {
- KEEP (*(.init))
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.fini : {
- KEEP (*(.fini))
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rodata : {
- __rodata_start = .;
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- __rodata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rodata1 : {
- __rodata1_start = .;
- *(.rodata1)
- *(.rodata1.*)
- __rodata1_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sdata2 : {
- __sdata2_start = .;
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- __sdata2_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sbss2 : {
- __sbss2_start = .;
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- __sbss2_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.data : {
- __data_start = .;
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- *(.jcr)
- *(.got)
- *(.got.plt)
- __data_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.data1 : {
- __data1_start = .;
- *(.data1)
- *(.data1.*)
- __data1_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.got : {
- *(.got)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ctors : {
- __CTOR_LIST__ = .;
- ___CTORS_LIST___ = .;
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- ___CTORS_END___ = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.dtors : {
- __DTOR_LIST__ = .;
- ___DTORS_LIST___ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- ___DTORS_END___ = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.fixup : {
- __fixup_start = .;
- *(.fixup)
- __fixup_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.eh_frame : {
- *(.eh_frame)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.eh_framehdr : {
- __eh_framehdr_start = .;
- *(.eh_framehdr)
- __eh_framehdr_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.gcc_except_table : {
- *(.gcc_except_table)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.mmu_tbl ALIGN(0x4000): {
- __mmu_tbl_start = .;
- *(.mmu_tbl)
- __mmu_tbl_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ARM.exidx : {
- __exidx_start = .;
- *(.ARM.exidx*)
- *(.gnu.linkonce.armexidix.*.*)
- __exidx_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.preinit_array : {
- __preinit_array_start = .;
- KEEP (*(SORT(.preinit_array.*)))
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.init_array : {
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.fini_array : {
- __fini_array_start = .;
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array))
- __fini_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rsa_ac : {
- . = ALIGN(64);
- __rsa_ac_start = .;
- . += _RSA_AC_SIZE;
- __rsa_ac_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ARM.attributes : {
- __ARM.attributes_start = .;
- *(.ARM.attributes)
- __ARM.attributes_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sdata : {
- __sdata_start = .;
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- __sdata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sbss (NOLOAD) : {
- __sbss_start = .;
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- __sbss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.tdata : {
- __tdata_start = .;
- *(.tdata)
- *(.tdata.*)
- *(.gnu.linkonce.td.*)
- __tdata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.tbss : {
- __tbss_start = .;
- *(.tbss)
- *(.tbss.*)
- *(.gnu.linkonce.tb.*)
- __tbss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.bss (NOLOAD) : {
- __bss_start = .;
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- __bss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
-
-_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
-
-/* Generate Stack and Heap definitions */
-
-.heap (NOLOAD) : {
- . = ALIGN(16);
- _heap = .;
- HeapBase = .;
- _heap_start = .;
- . += _HEAP_SIZE;
- _heap_end = .;
- HeapLimit = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.stack (NOLOAD) : {
- . = ALIGN(16);
- _stack_end = .;
- . += _STACK_SIZE;
- _stack = .;
- __stack = _stack;
- . = ALIGN(16);
- _irq_stack_end = .;
- . += _STACK_SIZE;
- __irq_stack = .;
- _supervisor_stack_end = .;
- . += _SUPERVISOR_STACK_SIZE;
- . = ALIGN(16);
- __supervisor_stack = .;
- _abort_stack_end = .;
- . += _ABORT_STACK_SIZE;
- . = ALIGN(16);
- __abort_stack = .;
- _fiq_stack_end = .;
- . += _FIQ_STACK_SIZE;
- . = ALIGN(16);
- __fiq_stack = .;
- _undef_stack_end = .;
- . += _UNDEF_STACK_SIZE;
- . = ALIGN(16);
- __undef_stack = .;
-} > ps7_ram_1_S_AXI_BASEADDR
-
-_end = .;
-}
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/main.c b/quad/xsdk_workspace/zybo_fsbl/src/main.c
deleted file mode 100644
index aff88aebf52fe41d711a91aee3bf4785050bb1ba..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/main.c
+++ /dev/null
@@ -1,1516 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file main.c
-*
-* The main file for the First Stage Boot Loader (FSBL).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 06/04/11 Initial release
-* 2.00a mb 25/05/12 standalone based FSBL
-* 3.00a np/mb 08/03/12 Added call to FSBL user hook - before handoff.
-* DDR ECC initialization added
-* fsbl print with verbose added
-* Performance measurement added
-* Flushed the UART Tx buffer
-* Added the performance time for ECC DDR init
-* Added clearing of ECC Error Code
-* Added the watchdog timer value
-* 4.00a sgd 02/28/13 Code Cleanup
-* Fix for CR#681014 - ECC init in FSBL should not
-* call fabric_init()
-* Fix for CR#689077 - FSBL hangs at Handoff clearing the
-* TX UART buffer when using UART0
-* instead of UART1
-* Fix for CR#694038 - FSBL debug logs always prints 14.3
-* as the Revision number - this is
-* incorrect
-* Fix for CR#694039 - FSBL prints "unsupported silicon
-* version for v3.0" 3.0 Silicon
-* Fix for CR#699475 - FSBL functionality is broken and
-* its not able to boot in QSPI/NAND
-* bootmode
-* Removed DDR initialization check
-* Removed DDR ECC initialization code
-* Modified hand off address check to 1MB
-* Added RSA authentication support
-* Watchdog disabled for AES E-Fuse encryption
-* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
-* Fix for CR#708728 - Issues seen while making HP
-* interconnect 32 bit wide
-* 6.00a kc 07/30/13 Fix for CR#708316 - PS7_init.tcl file should have
-* Error mechanism for all mask_poll
-* Fix for CR#691150 - ps7_init does not check for
-* peripheral initialization failures
-* or timeout on polls
-* Fix for CR#724165 - Partition Header used by FSBL is
-* not authenticated
-* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
-* by Boot ROM for authenticating
-* the Partition images
-* Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* Fix for CR#732865 - Backward compatibility for ps7_init
-* function
-* </pre>
-*
-* @note
-* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy
-* the partitions from the flash device. If the partition is bitstream then
-* the bitstream is programmed in the Fabric and for an partition that is
-* an application , FSBL will copy the application into DDR and does a
-* handoff.The application should not be starting at the OCM address,
-* FSBL does not remap the DDR. Application should use DDR starting from 1MB
-*
-* FSBL can be stitched along with bitstream and application using bootgen
-*
-* Refer to fsbl.h file for details on the compilation flags supported in FSBL
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "fsbl.h"
-#include "qspi.h"
-#include "nand.h"
-#include "nor.h"
-#include "sd.h"
-#include "pcap.h"
-#include "image_mover.h"
-#include "xparameters.h"
-#include "xil_cache.h"
-#include "xil_exception.h"
-#include "xstatus.h"
-#include "fsbl_hooks.h"
-#include "xtime_l.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-#ifdef STDOUT_BASEADDRESS
-#include "xuartps_hw.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID
-#define WDT_EXPIRE_TIME 100
-#define WDT_CRV_SHIFT 12
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-/************************** Function Prototypes ******************************/
-extern int ps7_init();
-extern char* getPS7MessageInfo(unsigned key);
-#ifdef PS7_POST_CONFIG
-extern int ps7_post_config();
-#endif
-#ifdef PEEP_CODE
-extern void init_ddr(void);
-#endif
-
-static void Update_MultiBootRegister(void);
-/* Exception handlers */
-static void RegisterHandlers(void);
-static void Undef_Handler (void);
-static void SVC_Handler (void);
-static void PreFetch_Abort_Handler (void);
-static void Data_Abort_Handler (void);
-static void IRQ_Handler (void);
-static void FIQ_Handler (void);
-
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-int InitWatchDog(void);
-u32 ConvertTime_WdtCounter(u32 seconds);
-void CheckWDTReset(void);
-#endif
-
-u32 NextValidImageCheck(void);
-
-u32 DDRInitCheck(void);
-
-/************************** Variable Definitions *****************************/
-/*
- * Base Address for the Read Functionality for Image Processing
- */
-u32 FlashReadBaseAddress = 0;
-/*
- * Silicon Version
- */
-u32 Silicon_Version;
-
-/*
- * Boot Device flag
- */
-u8 LinearBootDeviceFlag;
-
-u32 PcapCtrlRegVal;
-
-u8 SystemInitFlag;
-
-extern ImageMoverType MoveImage;
-extern XDcfg *DcfgInstPtr;
-extern u8 BitstreamFlag;
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-extern u32 QspiFlashSize;
-#endif
-/*****************************************************************************/
-/**
-*
-* This is the main function for the FSBL ROM code.
-*
-*
-* @param None.
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-* @note
-*
-****************************************************************************/
-int main(void)
-{
- u32 BootModeRegister = 0;
- u32 HandoffAddress = 0;
- u32 Status = XST_SUCCESS;
-
-#ifdef PEEP_CODE
- /*
- * PEEP DDR initialization
- */
- init_ddr();
-#else
- /*
- * PCW initialization for MIO,PLL,CLK and DDR
- */
- Status = ps7_init();
- if (Status != FSBL_PS7_INIT_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n",
- getPS7MessageInfo(Status));
- OutputStatus(PS7_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-#endif
-
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-
- /* If Performance measurement is required
- * then read the Global Timer value , Please note that the
- * time taken for mio, clock and ddr initialisation
- * done in the ps7_init function is not accounted in the FSBL
- *
- */
-#ifdef FSBL_PERF
- XTime tCur = 0;
- FsblGetGlobalTime(tCur);
-#endif
-
- /*
- * Flush the Caches
- */
- Xil_DCacheFlush();
-
- /*
- * Disable Data Cache
- */
- Xil_DCacheDisable();
-
- /*
- * Register the Exception handlers
- */
- RegisterHandlers();
-
- /*
- * Print the FSBL Banner
- */
- fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r");
- fsbl_printf(DEBUG_GENERAL,"Release %d.%d/%d.%d %s-%s\r\n",
- SDK_RELEASE_VER, SDK_SUB_VER,
- SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER,
- __DATE__,__TIME__);
-
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-
- /*
- * DDR Read/write test
- */
- Status = DDRInitCheck();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n");
- /* Error Handling here */
- OutputStatus(DDR_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
-
- /*
- * PCAP initialization
- */
- Status = InitPcap();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r");
- OutputStatus(PCAP_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
- fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n");
-
- /*
- * Get the Silicon Version
- */
- GetSiliconVersion();
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Check if WDT Reset has occurred or not
- */
- CheckWDTReset();
-
- /*
- * Initialize the Watchdog Timer so that it is ready to use
- */
- Status = InitWatchDog();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r");
- OutputStatus(WDT_INIT_FAIL);
- FsblFallback();
- }
- fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n");
-#endif
-
- /*
- * Get PCAP controller settings
- */
- PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK) {
- /*
- * For E-Fuse AES encryption Watch dog Timer disabled and
- * User not allowed to do system reset
- */
-#ifdef XPAR_XWDTPS_0_BASEADDR
- fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n");
- XWdtPs_Stop(&Watchdog);
-#endif
- fsbl_printf(DEBUG_INFO,"User not allowed to do "
- "any system resets\r\n");
- }
-
- /*
- * Store FSBL run state in Reboot Status Register
- */
- MarkFSBLIn();
-
- /*
- * Read bootmode register
- */
- BootModeRegister = Xil_In32(BOOT_MODE_REG);
- BootModeRegister &= BOOT_MODES_MASK;
-
- /*
- * QSPI BOOT MODE
- */
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-
-#ifdef MMC_SUPPORT
- /*
- * To support MMC boot
- * QSPI boot mode detection ignored
- */
- if (BootModeRegister == QSPI_MODE) {
- BootModeRegister = MMC_MODE;
- }
-#endif
-
- if (BootModeRegister == QSPI_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r");
- InitQspi();
- MoveImage = QspiAccess;
- fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n");
- } else
-#endif
-
- /*
- * NAND BOOT MODE
- */
-#ifdef XPAR_PS7_NAND_0_BASEADDR
- if (BootModeRegister == NAND_FLASH_MODE) {
- /*
- * Boot ROM always initialize the nand at lower speed
- * This is the chance to put it to an optimum speed for your nand
- * device
- */
- fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n");
-
- Status = InitNand();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n");
- /*
- * Error Handling here
- */
- OutputStatus(NAND_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = NandAccess;
- fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n");
- } else
-#endif
-
- /*
- * NOR BOOT MODE
- */
- if (BootModeRegister == NOR_FLASH_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r");
- /*
- * Boot ROM always initialize the nor at lower speed
- * This is the chance to put it to an optimum speed for your nor
- * device
- */
- InitNor();
- fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n");
- MoveImage = NorAccess;
- } else
-
- /*
- * SD BOOT MODE
- */
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-
- if (BootModeRegister == SD_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n");
-
- /*
- * SD initialization returns file open error or success
- */
- Status = InitSD("BOOT.BIN");
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n");
- OutputStatus(SD_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = SDAccess;
- fsbl_printf(DEBUG_INFO,"SD Init Done \r\n");
- } else
-
- if (BootModeRegister == MMC_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n");
-
- /*
- * MMC initialization returns file open error or success
- */
- Status = InitSD("BOOT.BIN");
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n");
- OutputStatus(SD_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = SDAccess;
- fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n");
- } else
-
-#endif
-
- /*
- * JTAG BOOT MODE
- */
- if (BootModeRegister == JTAG_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n");
- /*
- * Stop the Watchdog before JTAG handoff
- */
-#ifdef XPAR_XWDTPS_0_BASEADDR
- XWdtPs_Stop(&Watchdog);
-#endif
- /*
- * Clear our mark in reboot status register
- */
- ClearFSBLIn();
-
- /*
- * SLCR lock
- */
- SlcrLock();
-
- FsblHandoffJtagExit();
- } else {
- fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n");
- OutputStatus(ILLEGAL_BOOT_MODE);
- /*
- * fallback starts, no return
- */
- FsblFallback();
- }
-
- fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08x\r\n", FlashReadBaseAddress);
-
- /*
- * Check for valid flash address
- */
- if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) &&
- (FlashReadBaseAddress != XPS_NAND_BASEADDR) &&
- (FlashReadBaseAddress != XPS_NOR_BASEADDR) &&
- (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) {
- fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n");
- OutputStatus(INVALID_FLASH_ADDRESS);
- FsblFallback();
- }
-
- /*
- * NOR and QSPI (parallel) are linear boot devices
- */
- if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) {
- fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n");
- LinearBootDeviceFlag = 1;
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * This used only in case of E-Fuse encryption
- * For image search
- */
- SystemInitFlag = 1;
-
- /*
- * Load boot image
- */
- HandoffAddress = LoadBootImage();
-
- fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08x\r\n",HandoffAddress);
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Total Execution time is ");
- FsblMeasurePerfTime(tCur,tEnd);
-#endif
-
- /*
- * FSBL handoff to valid handoff address or
- * exit in JTAG
- */
- FsblHandoff(HandoffAddress);
-
-#else
- OutputStatus(NO_DDR);
- FsblFallback();
-#endif
-
- return Status;
-}
-
-/******************************************************************************/
-/**
-*
-* This function reset the CPU and goes for Boot ROM fallback handling
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void FsblFallback(void)
-{
- u32 RebootStatusReg;
- u32 Status;
- u32 HandoffAddr;
- u32 BootModeRegister;
-
- /*
- * Read bootmode register
- */
- BootModeRegister = Xil_In32(BOOT_MODE_REG);
- BootModeRegister &= BOOT_MODES_MASK;
-
- /*
- * Fallback support check
- */
- if (!((BootModeRegister == QSPI_MODE) ||
- (BootModeRegister == NAND_FLASH_MODE) ||
- (BootModeRegister == NOR_FLASH_MODE))) {
- fsbl_printf(DEBUG_INFO,"\r\n"
- "This Boot Mode Doesn't Support Fallback\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
-
- /*
- * update the Multiboot Register for Golden search hunt
- */
- Update_MultiBootRegister();
-
- /*
- * Notify Boot ROM something is wrong
- */
- RebootStatusReg = Xil_In32(REBOOT_STATUS_REG);
-
- /*
- * Set the FSBL Fail mask
- */
- Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK);
-
- /*
- * Barrier for synchronization
- */
- asm(
- "dsb\n\t"
- "isb"
- );
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK) {
- /*
- * Next valid image search can happen only
- * when system initialization done
- */
- if (SystemInitFlag == 1) {
- /*
- * Clean the Fabric
- */
- FabricInit();
-
- /*
- * Search for next valid image
- */
- Status = NextValidImageCheck();
- if(Status != XST_SUCCESS){
- fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
-
- /*
- * Load next valid image
- */
- HandoffAddr = LoadBootImage();
-
- /*
- * Handoff to next image
- */
- FsblHandoff(HandoffAddr);
- } else {
- fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n");
- fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
- }
-
- /*
- * Reset PS, so Boot ROM will restart
- */
- Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function hands the A9/PS to the loaded user code.
-*
-* @param none
-*
-* @return none
-*
-* @note This function does not return.
-*
-****************************************************************************/
-void FsblHandoff(u32 FsblStartAddr)
-{
- u32 Status;
-
- /*
- * Enable level shifter
- */
- if(BitstreamFlag) {
- /*
- * FSBL will not enable the level shifters for a NON PS instantiated
- * Bitstream
- * CR# 671028
- * This flag can be set during compilation for a NON PS instantiated
- * bitstream
- */
-#ifndef NON_PS_INSTANTIATED_BITSTREAM
-#ifdef PS7_POST_CONFIG
- ps7_post_config();
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-#else
- /*
- * Set Level Shifters DT618760
- */
- Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS);
- fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS "
- "Address = 0x%x Value = 0x%x \n\r",
- PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN));
-
- /*
- * Enable AXI interface
- */
- Xil_Out32(FPGA_RESET_REG, 0);
- fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r");
- fsbl_printf(DEBUG_INFO, "FPGA Reset Register "
- "Address = 0x%x , Value = 0x%x \r\n",
- FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG));
-#endif
-#endif
- }
-
- /*
- * FSBL user hook call before handoff to the application
- */
- Status = FsblHookBeforeHandoff();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n");
- OutputStatus(FSBL_HANDOFF_HOOK_FAIL);
- FsblFallback();
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- XWdtPs_Stop(&Watchdog);
-#endif
-
- /*
- * Clear our mark in reboot status register
- */
- ClearFSBLIn();
-
- if(FsblStartAddr == 0) {
- /*
- * SLCR lock
- */
- SlcrLock();
-
- fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n");
- FsblHandoffJtagExit();
- } else {
- fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n");
- OutputStatus(SUCCESSFUL_HANDOFF);
- FsblHandoffExit(FsblStartAddr);
- }
-
- OutputStatus(ILLEGAL_RETURN);
-
- FsblFallback();
-}
-
-/******************************************************************************/
-/**
-*
-* This function outputs the status for the provided State in the boot process.
-*
-* @param State is where in the boot process the output is desired.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void OutputStatus(u32 State)
-{
-#ifdef STDOUT_BASEADDRESS
- u32 UartReg = 0;
-
- fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4x\r\n", State);
- /*
- * The TX buffer needs to be flushed out
- * If this is not done some of the prints will not appear on the
- * serial output
- */
- UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
- while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) {
- UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
- }
-#endif
-}
-
-/******************************************************************************/
-/**
-*
-* This function handles the error and lockdown processing and outputs the status
-* for the provided State in the boot process.
-*
-* This function is called upon exceptions.
-*
-* @param State - where in the boot process the error occured.
-*
-* @return None.
-*
-* @note This function does not return, the PS block is reset
-*
-****************************************************************************/
-void ErrorLockdown(u32 State)
-{
- /*
- * Store the error status
- */
- OutputStatus(State);
-
- /*
- * Fall back
- */
- FsblFallback();
-}
-
-/******************************************************************************/
-/**
-*
-* This function copies a memory region to another memory region
-*
-* @param s1 is starting address for destination
-* @param s2 is starting address for the source
-* @param n is the number of bytes to copy
-*
-* @return Starting address for destination
-*
-****************************************************************************/
-void *(memcpy_rom)(void * s1, const void * s2, u32 n)
-{
- char *dst = (char *)s1;
- const char *src = (char *)s2;
-
- /*
- * Loop and copy
- */
- while (n-- != 0)
- *dst++ = *src++;
- return s1;
-}
-/******************************************************************************/
-/**
-*
-* This function copies a string to another, the source string must be null-
-* terminated.
-*
-* @param Dest is starting address for the destination string
-* @param Src is starting address for the source string
-*
-* @return Starting address for the destination string
-*
-****************************************************************************/
-char *strcpy_rom(char *Dest, const char *Src)
-{
- unsigned i;
- for (i=0; Src[i] != '\0'; ++i)
- Dest[i] = Src[i];
- Dest[i] = '\0';
- return Dest;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function sets FSBL is running mask in reboot status register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void MarkFSBLIn(void)
-{
- Xil_Out32(REBOOT_STATUS_REG,
- Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function clears FSBL is running mask in reboot status register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void ClearFSBLIn(void)
-{
- Xil_Out32(REBOOT_STATUS_REG,
- (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK));
-}
-
-/******************************************************************************/
-/**
-*
-* This function Registers the Exception Handlers
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-static void RegisterHandlers(void)
-{
- Xil_ExceptionInit();
-
- /*
- * Initialize the vector table. Register the stub Handler for each
- * exception.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
- (Xil_ExceptionHandler)Undef_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT,
- (Xil_ExceptionHandler)SVC_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
- (Xil_ExceptionHandler)PreFetch_Abort_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
- (Xil_ExceptionHandler)Data_Abort_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
- (Xil_ExceptionHandler)IRQ_Handler,(void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
- (Xil_ExceptionHandler)FIQ_Handler,(void *) 0);
-
- Xil_ExceptionEnable();
-
-}
-
-static void Undef_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n");
- ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT);
-}
-
-static void SVC_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_SWI_INT);
-}
-
-static void PreFetch_Abort_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT);
-}
-
-static void Data_Abort_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT);
-}
-
-static void IRQ_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_IRQ_INT);
-}
-
-static void FIQ_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_FIQ_INT);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function Updates the Multi boot Register to enable golden image
-* search for boot rom
-*
-* @param None
-*
-* @return
-* return none
-*
-****************************************************************************/
-static void Update_MultiBootRegister(void)
-{
- u32 MultiBootReg = 0;
-
- if (Silicon_Version != SILICON_VERSION_1) {
- /*
- * Read the mulitboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- /*
- * Incrementing multiboot register by one
- */
- MultiBootReg++;
-
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET,
- MultiBootReg);
-
- fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08x\r\n",
- MultiBootReg);
- }
-}
-
-
-/******************************************************************************
-*
-* This function reset the CPU and goes for Boot ROM fallback handling
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-*******************************************************************************/
-
-u32 GetResetReason(void)
-{
- u32 Regval;
-
- /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */
- /* for storing the RESET_REASON register value*/
- Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF);
-
- return Regval;
-}
-
-
-/******************************************************************************
-*
-* This function Gets the ticks from the Global Timer
-*
-* @param Current time
-*
-* @return
-* None
-*
-* @note None
-*
-*******************************************************************************/
-#ifdef FSBL_PERF
-void FsblGetGlobalTime (XTime tCur)
-{
- XTime_GetTime(&tCur);
-}
-
-
-/******************************************************************************
-*
-* This function Measures the execution time
-*
-* @param Current time , End time
-*
-* @return
-* None
-*
-* @note None
-*
-*******************************************************************************/
-void FsblMeasurePerfTime (XTime tCur, XTime tEnd)
-{
- double tDiff = 0.0;
- double tPerfSeconds;
- XTime_GetTime(&tEnd);
- tDiff = (double)tEnd - (double)tCur;
-
- /*
- * Convert tPerf into Seconds
- */
- tPerfSeconds = tDiff/COUNTS_PER_SECOND;
-
- /*
- * Convert tPerf into Seconds
- */
- tPerfSeconds = tDiff/COUNTS_PER_SECOND;
-
-#if defined(FSBL_DEBUG) || defined(FSBL_DEBUG_INFO)
- printf("%f seconds \r\n",tPerfSeconds);
-#endif
-
-}
-#endif
-
-/******************************************************************************
-*
-* This function initializes the Watchdog driver and starts the timer
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the Watchdog driver is initialized
-* - XST_FAILURE if Watchdog driver initialization fails
-*
-* @note None
-*
-*******************************************************************************/
-#ifdef XPAR_XWDTPS_0_BASEADDR
-int InitWatchDog(void)
-{
- u32 Status = XST_SUCCESS;
- XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */
- u32 CounterValue = 1;
-
- ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID);
- Status = XWdtPs_CfgInitialize(&Watchdog,
- ConfigPtr,
- ConfigPtr->BaseAddress);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r");
- return XST_FAILURE;
- }
-
- /*
- * Setting the divider value
- */
- XWdtPs_SetControlValue(&Watchdog,
- XWDTPS_CLK_PRESCALE,
- XWDTPS_CCR_PSCALE_4096);
- /*
- * Convert time to Watchdog counter reset value
- */
- CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME);
-
- /*
- * Set the Watchdog counter reset value
- */
- XWdtPs_SetControlValue(&Watchdog,
- XWDTPS_COUNTER_RESET,
- CounterValue);
- /*
- * enable reset output, as we are only using this as a basic counter
- */
- XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL);
-
- /*
- * Start the Watchdog timer
- */
- XWdtPs_Start(&Watchdog);
-
- XWdtPs_RestartWdt(&Watchdog);
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function checks whether WDT reset has happened during FSBL run
-*
-* If WDT reset happened during FSBL run, then need to fallback
-*
-* @param None.
-*
-* @return
-* None
-*
-* @note None
-*
-****************************************************************************/
-void CheckWDTReset(void)
-{
- u32 ResetReason;
- u32 RebootStatusRegister;
-
- RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
-
- /*
- * For 1.0 Silicon the reason for Reset is in the ResetReason Register
- * Hence this register can be read to know the cause for previous reset
- * that happened.
- * Check if that reset is a Software WatchDog reset that happened
- */
- if (Silicon_Version == SILICON_VERSION_1) {
- ResetReason = Xil_In32(RESET_REASON_REG);
- } else {
- ResetReason = GetResetReason();
- }
- /*
- * If the FSBL_IN_MASK Has not been cleared, WDT happened
- * before FSBL exits
- */
- if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) {
- if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) {
- /*
- * Clear the SWDT Reset bit
- */
- ResetReason &= ~RESET_REASON_SWDT;
- if (Silicon_Version == SILICON_VERSION_1) {
- /*
- * for 1.0 Silicon we need to write
- * 1 to the RESET REASON Clear register
- */
- Xil_Out32(RESET_REASON_CLR, 1);
- } else {
- Xil_Out32(REBOOT_STATUS_REG, ResetReason);
- }
-
- fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r");
- }
- }
-}
-
-
-/******************************************************************************
-*
-* This function converts time into Watchdog counter value
-*
-* @param watchdog expire time in seconds
-*
-* @return
-* Counter value for Watchdog
-*
-* @note None
-*
-*******************************************************************************/
-u32 ConvertTime_WdtCounter(u32 seconds)
-{
- double time = 0.0;
- double CounterValue;
- u32 Crv = 0;
- u32 Prescaler,PrescalerValue;
-
- Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE);
-
- if (Prescaler == XWDTPS_CCR_PSCALE_0008)
- PrescalerValue = 8;
- if (Prescaler == XWDTPS_CCR_PSCALE_0064)
- PrescalerValue = 64;
- if (Prescaler == XWDTPS_CCR_PSCALE_4096)
- PrescalerValue = 4096;
-
- time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ;
-
- CounterValue = seconds / time;
-
- Crv = (u32)CounterValue;
- Crv >>= WDT_CRV_SHIFT;
-
- return Crv;
-}
-
-#endif
-
-
-/******************************************************************************
-*
-* This function Gets the Silicon Version stores in global variable
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-*******************************************************************************/
-void GetSiliconVersion(void)
-{
- /*
- * Get the silicon version
- */
- Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr);
- if(Silicon_Version == SILICON_VERSION_3_1) {
- fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n");
- } else {
- fsbl_printf(DEBUG_GENERAL,"Silicon Version %d.0\r\n",
- Silicon_Version + 1);
- }
-}
-
-
-/******************************************************************************
-*
-* This function HeaderChecksum will calculates the header checksum and
-* compares with checksum read from flash
-*
-* @param FlashOffsetAddress Flash offset address
-*
-* @return
-* - XST_SUCCESS if ID matches
-* - XST_FAILURE if ID mismatches
-*
-* @note None
-*
-*******************************************************************************/
-u32 HeaderChecksum(u32 FlashOffsetAddress){
- u32 Checksum = 0;
- u32 Count;
- u32 TempValue = 0;
-
- for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) {
- /*
- * Read the word from the header
- */
- MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4);
-
- /*
- * Update checksum
- */
- Checksum += TempValue;
- }
-
- /*
- * Invert checksum, last bit of error checking
- */
- Checksum ^= 0xFFFFFFFF;
- MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4);
-
- /*
- * Validate the checksum
- */
- if (TempValue != Checksum){
- fsbl_printf(DEBUG_INFO, "Checksum = %8.8x\r\n", Checksum);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function ImageCheckID will do check for XLNX pattern
-*
-* @param FlashOffsetAddress Flash offset address
-*
-* @return
-* - XST_SUCCESS if ID matches
-* - XST_FAILURE if ID mismatches
-*
-* @note None
-*
-*******************************************************************************/
-u32 ImageCheckID(u32 FlashOffsetAddress){
- u32 ID;
-
- /*
- * Read in the header info
- */
- MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4);
-
- /*
- * Check the ID, make sure image is XLNX format
- */
- if (ID != IMAGE_IDENT){
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function NextValidImageCheck search for valid boot image
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if valid image found
-* - XST_FAILURE if no image found
-*
-* @note None
-*
-*******************************************************************************/
-u32 NextValidImageCheck(void)
-{
- u32 ImageBaseAddr;
- u32 MultiBootReg;
- u32 BootDevMaxSize=0;
-
- fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image");
-
- /*
- * Setting variable with maximum flash size based on boot mode
- */
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
- if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) {
- BootDevMaxSize = QspiFlashSize;
- }
-#endif
-
- if (FlashReadBaseAddress == XPS_NAND_BASEADDR) {
- BootDevMaxSize = NAND_FLASH_SIZE;
- }
-
- if (FlashReadBaseAddress == XPS_NOR_BASEADDR) {
- BootDevMaxSize = NOR_FLASH_SIZE;
- }
-
- /*
- * Read the multiboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- /*
- * Compute the image start address
- */
- ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
-
- /*
- * Valid image search continue till end of the flash
- * With increment 32KB in each iteration
- */
- while (ImageBaseAddr < BootDevMaxSize) {
-
- fsbl_printf(DEBUG_INFO,".");
-
- /*
- * Valid image search using XLNX pattern at fixed offset
- * and header checksum
- */
- if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) &&
- (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) {
-
- fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8x\r\n",
- ImageBaseAddr);
- /*
- * Update multiboot register
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET,
- MultiBootReg);
-
- return XST_SUCCESS;
- }
-
- /*
- * Increment mulitboot count
- */
- MultiBootReg++;
-
- /*
- * Compute the image start address
- */
- ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
- }
-
- return XST_FAILURE;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Checks for the ddr initialization completion
-*
-* @param None.
-*
-* @return
-* - XST_SUCCESS if the initialization is successful
-* - XST_FAILURE if the initialization is NOT successful
-*
-* @note None.
-*
-****************************************************************************/
-u32 DDRInitCheck(void)
-{
- u32 ReadVal;
-
- /*
- * Write and Read from the DDR location for sanity checks
- */
- Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN);
- ReadVal = Xil_In32(DDR_START_ADDR);
- if (ReadVal != DDR_TEST_PATTERN) {
- return XST_FAILURE;
- }
-
- /*
- * Write and Read from the DDR location for sanity checks
- */
- Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN);
- ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET);
- if (ReadVal != DDR_TEST_PATTERN) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/md5.c b/quad/xsdk_workspace/zybo_fsbl/src/md5.c
deleted file mode 100644
index 1aa0819001d70a519d62e404ecdf96b66cce7a8f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/md5.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
- * All rights reserved.
- *
- * This package is an SSL implementation written
- * by Eric Young (eay@cryptsoft.com).
- * The implementation was written so as to conform with Netscapes SSL.
- *
- * This library is free for commercial and non-commercial use as long as
- * the following conditions are aheared to. The following conditions
- * apply to all code found in this distribution, be it the RC4, RSA,
- * lhash, DES, etc., code; not just the SSL code. The SSL documentation
- * included with this distribution is covered by the same copyright terms
- * except that the holder is Tim Hudson (tjh@cryptsoft.com).
- *
- * Copyright remains Eric Young's, and as such any Copyright notices in
- * the code are not to be removed.
- * If this package is used in a product, Eric Young should be given attribution
- * as the author of the parts of the library used.
- * This can be in the form of a textual message at program startup or
- * in documentation (online or textual) provided with the package.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * "This product includes cryptographic software written by
- * Eric Young (eay@cryptsoft.com)"
- * The word 'cryptographic' can be left out if the rouines from the library
- * being used are not cryptographic related :-).
- * 4. If you include any Windows specific code (or a derivative thereof) from
- * the apps directory (application code) you must include an acknowledgement:
- * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
- *
- * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * The licence and distribution terms for any publically available version or
- * derivative of this code cannot be changed. i.e. this code cannot simply be
- * copied and put under another distribution licence
- * [including the GNU Public Licence.]
- */
-/*****************************************************************************/
-/**
-*
-* @file md5.c
-*
-* Contains code to calculate checksum using md5 algorithm
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00a sgd 05/17/13 Initial release
-*
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-/****************************** Include Files *********************************/
-
-#include "md5.h"
-
-/******************************************************************************/
-/**
-*
-* This function sets the memory
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void * _memset( void *dest, int ch, u32 count )
-{
- register char *dst8 = (char*)dest;
-
- while( count-- )
- *dst8++ = ch;
-
- return dest;
-}
-
-/******************************************************************************/
-/**
-*
-* This function copy the memory
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void * _memcpy( void *dest, const void *src,
- u32 count, boolean doByteSwap )
-{
- register char * dst8 = (char*)dest;
- register char * src8 = (char*)src;
-
- if( doByteSwap == FALSE ) {
- while( count-- )
- *dst8++ = *src8++;
- } else {
- count /= sizeof( u32 );
-
- while( count-- ) {
- dst8[ 0 ] = src8[ 3 ];
- dst8[ 1 ] = src8[ 2 ];
- dst8[ 2 ] = src8[ 1 ];
- dst8[ 3 ] = src8[ 0 ];
-
- dst8 += 4;
- src8 += 4;
- }
- }
-
- return dest;
-}
-
-/******************************************************************************/
-/**
-*
-* This function is the core of the MD5 algorithm,
-* this alters an existing MD5 hash to
-* reflect the addition of 16 longwords of new data. MD5Update blocks
-* the data and converts bytes into longwords for this routine.
-*
-* Use binary integer part of the sine of integers (Radians) as constants.
-* Calculated as:
-*
-* for( i = 0; i < 63; i++ )
-* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
-*
-* Following number is the per-round shift amount.
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void MD5Transform( u32 *buffer, u32 *intermediate )
-{
- register u32 a, b, c, d;
-
- a = buffer[ 0 ];
- b = buffer[ 1 ];
- c = buffer[ 2 ];
- d = buffer[ 3 ];
-
- MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
-
- MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
-
- MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
-
- MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
-
- buffer[ 0 ] += a;
- buffer[ 1 ] += b;
- buffer[ 2 ] += c;
- buffer[ 3 ] += d;
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function Start MD5 accumulation
-* Set bit count to 0 and buffer to mysterious initialization constants
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Init( MD5Context *context )
-{
-
- context->buffer[ 0 ] = 0x67452301;
- context->buffer[ 1 ] = 0xefcdab89;
- context->buffer[ 2 ] = 0x98badcfe;
- context->buffer[ 3 ] = 0x10325476;
-
- context->bits[ 0 ] = 0;
- context->bits[ 1 ] = 0;
-
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function updates context to reflect the concatenation of another
-* buffer full of bytes
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Update( MD5Context *context, u8 *buffer,
- u32 len, boolean doByteSwap )
-{
- register u32 temp;
- register u8 * p;
-
- /*
- * Update bitcount
- */
-
- temp = context->bits[ 0 ];
-
- if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
- /*
- * Carry from low to high
- */
- context->bits[ 1 ]++;
- }
-
- context->bits[ 1 ] += len >> 29;
-
- /*
- * Bytes already in shsInfo->data
- */
-
- temp = ( temp >> 3 ) & 0x3f;
-
- /*
- * Handle any leading odd-sized chunks
- */
-
- if( temp ) {
- p = (u8 *)context->intermediate + temp;
-
- temp = MD5_SIGNATURE_BYTE_SIZE - temp;
-
- if( len < temp ) {
- _memcpy( p, buffer, len, doByteSwap );
- return;
- }
-
- _memcpy( p, buffer, temp, doByteSwap );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- buffer += temp;
- len -= temp;
-
- }
-
- /*
- * Process data in 64-byte, 512 bit, chunks
- */
-
- while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
- _memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
- doByteSwap );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- buffer += MD5_SIGNATURE_BYTE_SIZE;
- len -= MD5_SIGNATURE_BYTE_SIZE;
-
- }
-
- /*
- * Handle any remaining bytes of data
- */
- _memcpy( context->intermediate, buffer, len, doByteSwap );
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function final wrap-up - pad to 64-byte boundary with the bit pattern
-* 1 0* (64-bit count of bits processed, MSB-first
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Final( MD5Context *context, u8 *digest,
- boolean doByteSwap )
-{
- u32 count;
- u8 * p;
-
- /*
- * Compute number of bytes mod 64
- */
- count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
-
- /*
- * Set the first char of padding to 0x80. This is safe since there is
- * always at least one byte free
- */
- p = context->intermediate + count;
- *p++ = 0x80;
-
- /*
- * Bytes of padding needed to make 64 bytes
- */
- count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
-
- /*
- * Pad out to 56 mod 64
- */
- if( count < 8 ) {
- /*
- * Two lots of padding: Pad the first block to 64 bytes
- */
- _memset( p, 0, count );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- /*
- * Now fill the next block with 56 bytes
- */
- _memset( context->intermediate, 0, 56 );
- } else {
- /*
- * Pad block to 56 bytes
- */
- _memset( p, 0, count - 8 );
- }
-
- /*
- * Append length in bits and transform
- */
- ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
- ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- /*
- * Now return the digest
- */
- _memcpy( digest, context->buffer, 16, doByteSwap );
-}
-
-/******************************************************************************/
-/**
-*
-* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
-* 'input'. 'digest' must have enough space to hold 16 bytes
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
-{
- MD5Context context;
-
- MD5Init( &context );
-
- MD5Update( &context, input, len, doByteSwap );
-
- MD5Final( &context, digest, doByteSwap );
-}
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/md5.h b/quad/xsdk_workspace/zybo_fsbl/src/md5.h
deleted file mode 100644
index a00c17b1a1f3bba0a90b0105b93e2746aff3070c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/md5.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file md5.h
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00a sgd 05/17/13 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___MD5_H___
-#define ___MD5_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-#define MD5_SIGNATURE_BYTE_SIZE 64
-
-/**************************** Type Definitions *******************************/
-
-typedef u8 boolean;
-typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
-
-struct MD5Context
- {
- u32 buffer[ 4 ];
- u32 bits[ 2 ];
- signature intermediate;
- };
-typedef struct MD5Context MD5Context;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * The four core functions - F1 is optimized somewhat
- */
-#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
-#define F2( x, y, z ) F1( z, x, y )
-#define F3( x, y, z ) ( x ^ y ^ z )
-#define F4( x, y, z ) ( y ^ ( x | ~z ) )
-
-
-/*
- * This is the central step in the MD5 algorithm
- */
-#define MD5_STEP( f, w, x, y, z, data, s ) \
- ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
-
-
-/************************** Function Prototypes ******************************/
-
-void * _memset( void *dest, int ch, u32 count );
-
-void * _memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
-
-void MD5Transform( u32 *buffer, u32 *intermediate );
-
-void MD5Init( MD5Context *context );
-
-void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
-
-void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
-
-void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___MD5_H___ */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/mmc.c b/quad/xsdk_workspace/zybo_fsbl/src/mmc.c
deleted file mode 100644
index 8543b10c404dd636f1c595ba0842e5aee91748ed..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/mmc.c
+++ /dev/null
@@ -1,1181 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file mmc.c
-*
-* SD interface to FatFS
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a bh 05/28/11 Initial release
-* 1.00a nm 03/20/12 Changed the SD base clock divider from
- 0x40 to 0x04.
-* 3.00a mb 08/16/12 Added the flag XPAR_PS7_SD_0_S_AXI_BASEADDR
-* 3.00a sgd 08/16/12 SD Boot time improvement
-* Added SD high speed and 4bit support check
-* 4.00a sgd 02/28/13 Code cleanup
-* 5.00a sgd 05/17/13 Added MMC support
-* To support MMC, added two separate functions
-* sd_init for SD initialization
-* mmc_init for MMC initialization
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "fsbl.h"
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-
-#include "diskio.h" /* Common include file for FatFs and disk I/O layer */
-#include "ff.h"
-#include "xil_types.h"
-#include "sd_hardware.h"
-#include "sleep.h"
-#ifndef PEEP_CODE
-#include "ps7_init.h"
-#endif
-
-/*
- * Map logical volume to physical drive + partition.
- * Logical X [0-3] to Physical 0, partition X
- */
-#if _MULTI_PARTITION
-const PARTITION VolToPart[] = {
- {0, 0}, {0, 1}, {0, 2}, {0, 3} };
-#endif
-
-static DSTATUS Stat; /* Disk status */
-static BYTE CardType; /* b0:MMC, b1:SDv1, b2:SDv2, b3:Block addressing */
-
-/* Block Count variable */
-static u16 blkcnt;
-/* Block Size variable */
-static u16 blksize;
-
-/* ADMA2 descriptor table */
-static u32 desc_table[4];
-
-#define sd_out32(OutAddress, Value) Xil_Out32((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (OutAddress), (Value))
-#define sd_out16(OutAddress, Value) Xil_Out16((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (OutAddress), (Value))
-#define sd_out8(OutAddress, Value) Xil_Out8((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (OutAddress), (Value))
-
-#define sd_in32(InAddress) Xil_In32((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (InAddress))
-#define sd_in16(InAddress) Xil_In16((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (InAddress))
-#define sd_in8(InAddress) Xil_In8((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (InAddress))
-
-#ifdef MMC_SUPPORT
-
-#define MMC_CLK_52M 52000000
-#define MMC_CLK_26M 26000000
-#define MMC_HS_SUPPORT 0x1
-#define MMC_4BIT_SUPPORT 0x1
-#define EXT_CSD_BUS_WIDTH 183
-#define EXT_CSD_HS_TIMING 185
-#define MMC_SWITCH_MODE_WRITE_BYTE 0x03
-#define MMC_OCR_REG_VALUE ((0x1 << 30) | (0x1FF << 15))
-
-static DRESULT mmc_init(void);
-#else
-
-static DRESULT sd_init(void);
-
-#endif
-/******************************************************************************/
-/**
-*
-* This function Initializes the SD controller
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-static void init_port(void)
-{
- unsigned clk;
- unsigned clk_div;
-
- Stat = STA_NOINIT;
-
- /*
- * Power off the card
- */
- sd_out8(SD_PWR_CTRL_R, 0);
-
- /*
- * Disable interrupts
- */
- sd_out32(SD_SIG_ENA_R, 0);
-
- /*
- * Perform soft reset
- */
- sd_out8(SD_SOFT_RST_R, SD_RST_ALL);
-
- /*
- * Wait for reset to complete
- */
- while (sd_in8(SD_SOFT_RST_R)) {
- ;
- }
-
- /*
- * Power on the card
- */
- sd_out8(SD_PWR_CTRL_R, SD_POWER_33|SD_POWER_ON);
-
- /*
- * Enable ADMA2
- */
- sd_out8(SD_HOST_CTRL_R, SD_HOST_ADMA2);
-
- clk_div = (SDIO_FREQ/SD_CLK_400K);
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- clk = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, clk);
- do {
- clk = sd_in16(SD_CLK_CTL_R);
- } while (!(clk & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- clk |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, clk);
-
- sd_out32(SD_SIG_ENA_R, 0xFFFFFFFF);
- sd_out32(SD_INT_ENA_R, 0xFFFFFFFF);
-}
-
-
-/******************************************************************************/
-/**
-*
-* Module Private Functions
-*
-****************************************************************************/
-/*
- * MMC/SD commands
- */
-#define CMD0 (0) /* GO_IDLE_STATE */
-#define CMD1 (1) /* SEND_OP_COND */
-#define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */
-#define CMD2 (2) /* SEND_CID */
-#define CMD3 (3) /* RELATIVE_ADDR */
-#define CMD4 (4) /* SET_DSR */
-#define CMD5 (5) /* SLEEP_WAKE (SDC) */
-#define CMD6 (6) /* SWITCH_FUNC */
-#define ACMD6 (0x80+6) /* SET_BUS_WIDTH (SDC) */
-#define CMD7 (7) /* SELECT */
-#define CMD8 (8) /* SEND_IF_COND/SEND_EXT_CSD */
-#define CMD9 (9) /* SEND_CSD */
-#define CMD10 (10) /* SEND_CID */
-#define CMD12 (12) /* STOP_TRANSMISSION */
-#define ACMD13 (0x80+13) /* SD_STATUS (SDC) */
-#define CMD16 (16) /* SET_BLOCKLEN */
-#define CMD17 (17) /* READ_SINGLE_BLOCK */
-#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
-#define CMD23 (23) /* SET_BLOCK_COUNT */
-#define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */
-#define CMD24 (24) /* WRITE_BLOCK */
-#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
-#define CMD41 (41) /* SEND_OP_COND (ACMD) */
-#define ACMD42 (0x80+42) /* SET_CLR_CARD_DETECT (ACMD) */
-#define ACMD51 (0x80+51) /* SEND_SCR */
-#define CMD52 (52) /* */
-#define CMD55 (55) /* APP_CMD */
-#define CMD58 (58) /* READ_OCR */
-
-/*
- * Card type flags (CardType)
- */
-#define CT_MMC 0x01 /* MMC ver 3 */
-#define CT_SD1 0x02 /* SD ver 1 */
-#define CT_SD2 0x04 /* SD ver 2 */
-#define CT_SDC (CT_SD1|CT_SD2) /* SD */
-#define CT_BLOCK 0x08 /* Block addressing */
-
-
-/******************************************************************************/
-/**
-*
-* This function Determine the value of the controller transfer register
-* for the provided
-*
-* @param cmd command index
-*
-* @return cmd value
-*
-* @note None
-*
-****************************************************************************/
-static int make_command (unsigned cmd)
-{
- unsigned retval;
-
- retval = cmd << 8;
-
-#define RSP_NONE SD_CMD_RESP_NONE
-#define RSP_R1 (SD_CMD_INDEX|SD_CMD_RESP_48 |SD_CMD_CRC)
-#define RSP_R1b (SD_CMD_INDEX|SD_CMD_RESP_48_BUSY|SD_CMD_CRC)
-#define RSP_R2 (SD_CMD_CRC |SD_CMD_RESP_136)
-#define RSP_R3 (SD_CMD_RESP_48)
-#define RSP_R6 (SD_CMD_INDEX|SD_CMD_RESP_48_BUSY|SD_CMD_CRC)
-
- switch(cmd) {
- case CMD0:
- retval |= (SD_CMD_RESP_NONE);
- break;
- case CMD1:
- retval |= RSP_R3;
- break;
- case CMD2:
- retval |= RSP_R2;
- break;
- case CMD3:
- retval |= RSP_R6;
- break;
- case CMD4:
- retval |= (SD_CMD_RESP_NONE);
- break;
- case CMD5:
- retval |= RSP_R1b;
- break;
-#ifdef MMC_SUPPORT
- case CMD6:
- retval |= RSP_R1b;
- break;
-#else
- case CMD6:
- retval |= RSP_R1 | SD_CMD_DATA;
- break;
-#endif
- case ACMD6:
- retval |= RSP_R1;
- break;
- case CMD7:
- retval |= RSP_R1;
- break;
-#ifdef MMC_SUPPORT
- case CMD8:
- retval |= RSP_R1 | SD_CMD_DATA;
- break;
-#else
- case CMD8:
- retval |= RSP_R1;
- break;
-#endif
- case CMD9:
- retval |= RSP_R2;
- break;
- case CMD10:
- case CMD12:
- case ACMD13:
- case CMD16:
- retval |= RSP_R1;
- break;
- case CMD17:
- case CMD18:
- retval |= RSP_R1|SD_CMD_DATA;
- break;
- case CMD23:
- case ACMD23:
- case CMD24:
- case CMD25:
- case CMD41:
- retval |= RSP_R3;
- break;
- case ACMD42:
- retval |= RSP_R1;
- break;
- case ACMD51:
- retval |= RSP_R1|SD_CMD_DATA;
- break;
- case CMD52:
- case CMD55:
- retval |= RSP_R1;
- break;
- case CMD58:
- break;
- }
-
- return retval;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Determine the value of the controller transfer register
-* for the provided
-*
-* @param cmd Command byte
-*
-* @param arg Argument
-*
-* @param response Response from device
-*
-* @return 1 on success
-* 0 on timeout
-*
-* @note None
-*
-****************************************************************************/
-static BYTE send_cmd (BYTE cmd, DWORD arg, DWORD *response)
-{
- u32 status;
- u16 cmdreg;
-
- if (response) {
- *response = 0;
- }
-
- /*
- * Wait until the device is willing to accept commands
- */
- do {
- status = sd_in32(SD_PRES_STATE_R);
- } while (status & (SD_CMD_INHIBIT|SD_DATA_INHIBIT));
-
- /*
- * Clear all pending interrupt status
- */
- sd_out32(SD_INT_STAT_R, 0xFFFFFFFF);
-
- /*
- * 512 byte block size.
- * This is only relevant for data commands.
- */
- sd_out16(SD_BLOCK_SZ_R, blksize);
- sd_out16(SD_BLOCK_CNT_R, blkcnt);
-
- /*
- * Setting timeout to max value
- */
- sd_out8(SD_TIMEOUT_CTL_R, 0xE);
-
- sd_out32(SD_ARG_R, arg);
-
- if (cmd!=CMD18) {
- sd_out16(SD_TRNS_MODE_R, SD_TRNS_READ|SD_TRNS_DMA);
- } else {
- /*
- * Set the transfer mode to read, DMA, multiple block
- * (applicable only to data commands)
- * This is all that this software supports.
- */
- sd_out16(SD_TRNS_MODE_R, SD_TRNS_READ|SD_TRNS_MULTI|
- SD_TRNS_ACMD12|SD_TRNS_BLK_CNT_EN|SD_TRNS_DMA);
- }
-
- /*
- * Initiate the command
- */
- cmdreg = make_command(cmd);
- sd_out16(SD_CMD_R, cmdreg);
-
- /*
- * Poll until operation complete
- */
- while (1) {
- status = sd_in32(SD_INT_STAT_R);
- if (status & SD_INT_ERROR) {
- fsbl_printf(DEBUG_GENERAL,"send_cmd: Error: (0x%08x) cmd: %d arg: 0x%x\n",
- status, cmd, arg);
- sd_out8(SD_SOFT_RST_R, SD_RST_CMD|SD_RST_DATA);
-
- return 0;
- }
- /*
- * Check for Command complete
- */
- if (status & SD_INT_CMD_CMPL) {
- sd_out32(SD_INT_STAT_R, SD_INT_CMD_CMPL);
- break;
- }
- }
-
- status = sd_in32(SD_RSP_R);
- if (response) {
- *response = status;
- }
-
- return 1;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function Setup ADMA2 for data transfer
-*
-* @param buff_ptr
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void setup_adma2_trans(BYTE *buff_ptr)
-{
- /*
- * Set descriptor table
- */
- desc_table[0] = ((blkcnt*blksize) << DESC_ATBR_LEN_SHIFT)|
- DESC_ATBR_ACT_TRAN|DESC_ATBR_END|DESC_ATBR_VALID;
- desc_table[1] = (u32)buff_ptr;
-
- /*
- * Set ADMA system address register
- */
- sd_out32(SD_ADMA_ADDR_R, (u32)&desc_table[0]);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function is wait for DMA transfer complete
-*
-* @param None
-*
-* @return 0 for failure
-* 1 for success
-* @note None
-*
-****************************************************************************/
-static BYTE dma_trans_cmpl(void)
-{
- u32 status;
-
- /*
- * Poll until operation complete
- */
- while (1) {
- status = sd_in32(SD_INT_STAT_R);
- if (status & SD_INT_ERROR) {
- fsbl_printf(DEBUG_GENERAL,"dma_trans_cmpl: Error: (0x%08x)\r\n",
- status);
- return 0;
- }
-
- /*
- * Check for Transfer complete
- */
- if (status & SD_INT_TRNS_CMPL) {
- sd_out32(SD_INT_STAT_R, SD_INT_TRNS_CMPL);
- break;
- }
- }
- return 1;
-}
-
-/*--------------------------------------------------------------------------
-
- Public Functions
-
----------------------------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------------------*/
-/* Get Disk Status */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_status (
- BYTE drv /* Drive number (0) */
-)
-{
- DSTATUS s = Stat;
- unsigned statusreg;
-
- statusreg = sd_in32(SD_PRES_STATE_R);
- if (!(statusreg & SD_CARD_INS)) {
- s = STA_NODISK | STA_NOINIT;
- } else {
- s &= ~STA_NODISK;
- if (statusreg & SD_CARD_WP)
- s |= STA_PROTECT;
- else
- s &= ~STA_PROTECT;
- }
- Stat = s;
-
- return s;
-}
-
-/*-----------------------------------------------------------------------*/
-/* Initialize Disk Drive */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_initialize (
- BYTE drv /* Physical drive number (0) */
-)
-{
- DSTATUS s;
-
- /*
- * Check if card is in the socket
- */
- s = disk_status(drv);
- if (s & STA_NODISK) {
- fsbl_printf(DEBUG_GENERAL,"No SD card present.\n");
- return s;
- }
-
- /*
- * Initialize the host controller
- */
- init_port();
-
-#ifdef MMC_SUPPORT
- s = mmc_init();
- if(s != RES_OK) {
- fsbl_printf(DEBUG_GENERAL,"MMC Initialization Failed.\n");
- return s;
- }
-#else
- s = sd_init();
- if(s != RES_OK) {
- fsbl_printf(DEBUG_GENERAL,"SD Initialization Failed.\n");
- return s;
- }
-#endif
-
- if (CardType) /* Initialization succeeded */
- s &= ~STA_NOINIT;
- else /* Initialization failed */
- s |= STA_NOINIT;
- Stat = s;
-
- return s;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Sector(s) */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_read (
- BYTE drv, /* Physical drive number (0) */
- BYTE *buff, /* Pointer to the data buffer to store read data */
- DWORD sector, /* Start sector number (LBA) */
- BYTE count /* Sector count (1..128) */
-)
-{
- DSTATUS s;
-
- s = disk_status(drv);
- if (s & STA_NOINIT) return RES_NOTRDY;
- if (!count) return RES_PARERR;
- /* Convert LBA to byte address if needed */
- if (!(CardType & CT_BLOCK)) sector *= SD_BLOCK_SZ;
-
- blkcnt = count;
- blksize= SD_BLOCK_SZ;
-
- /* set adma2 for transfer */
- setup_adma2_trans(buff);
-
- /* Multiple block read */
- send_cmd(CMD18, sector, NULL);
-
- /* check for dma transfer complete */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- return RES_OK;
-}
-
-
-/*-----------------------------------------------------------------------*/
-/* Miscellaneous Functions */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_ioctl (
- BYTE drv, /* Physical drive number (0) */
- BYTE ctrl, /* Control code */
- void *buff /* Buffer to send/receive control data */
-)
-{
- DRESULT res;
-
- if (disk_status(drv) & STA_NOINIT) /* Check if card is in the socket */
- return RES_NOTRDY;
-
- res = RES_ERROR;
- switch (ctrl) {
- case CTRL_SYNC : /* Make sure that no pending write process */
- break;
-
- case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
- break;
-
- case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
- *(DWORD*)buff = 128;
- res = RES_OK;
- break;
-
- default:
- res = RES_PARERR;
- break;
- }
-
- return res;
-}
-
-/******************************************************************************/
-/**
-*
-* This function is User Provided Timer Function for FatFs module
-*
-* @param None
-*
-* @return DWORD
-*
-* @note None
-*
-****************************************************************************/
-DWORD get_fattime (void)
-{
- return ((DWORD)(2010 - 1980) << 25) /* Fixed to Jan. 1, 2010 */
- | ((DWORD)1 << 21)
- | ((DWORD)1 << 16)
- | ((DWORD)0 << 11)
- | ((DWORD)0 << 5)
- | ((DWORD)0 >> 1);
-}
-
-
-
-#ifdef MMC_SUPPORT
-/*
- * MMC initialization
- */
-static DRESULT mmc_init(void)
-{
- BYTE ty;
- DSTATUS s;
- DWORD response;
- unsigned rca;
- u16 regval;
- u16 clk_div;
- u32 argument;
- u8 status_data[512];
-
- ty= CT_MMC;
-
- /*
- * Enter Idle state
- */
- send_cmd(CMD0, 0, NULL);
-
- /*
- * Wait for leaving idle state (CMD1 with HCS bit)
- */
- while (1) {
-
- argument = MMC_OCR_REG_VALUE;
-
- s= send_cmd(CMD1, argument, &response);
- if (s == 0) {
- /*
- * command error; probably an SD card
- */
- ty = 0;
- goto fail;
- }
- if (response & 1<<31) {
- break;
- }
- }
-
- if (response & 1<<30) {
- /*
- * Card supports block addressing
- */
- ty |= CT_BLOCK;
- }
-
- /*
- * Get CID
- */
- send_cmd(CMD2, 0, &response);
-
- /*
- * Set RCA
- */
- rca = 0x1234;
- send_cmd(CMD3, rca << 16, &response);
-
- /*
- * Send CSD
- */
- send_cmd(CMD9,rca<<16,&response);
-
- /*
- * select card
- */
- send_cmd(CMD7, rca << 16, &response);
-
- /*
- * Switch the bus width to 4bit
- */
- argument = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
- (EXT_CSD_BUS_WIDTH << 16) |
- (1 << 8);
- send_cmd(CMD6, argument, &response);
-
- /*
- * Delay for device to setup
- */
- usleep(1000);
-
- /*
- * Enable 4bit mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_4BIT;
- sd_out16(SD_HOST_CTRL_R, regval);
-
- /*
- * Switch device to high speed
- */
- argument = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
- (EXT_CSD_HS_TIMING << 16) |
- (1 << 8);
- send_cmd(CMD6, argument, &response);
-
- /*
- * Delay for device to setup
- */
- usleep(1000);
-
- /*
- * Verify Bus width switch to high speed support
- */
- blkcnt = 1;
- blksize= 512;
-
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Check for high speed support switch
- */
- send_cmd(CMD8, 0x0, &response);
-
- /*
- * Check for dma transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * Check for 4bit support
- */
- if (status_data[EXT_CSD_BUS_WIDTH] == MMC_4BIT_SUPPORT) {
- fsbl_printf(DEBUG_INFO, "Bus Width 4Bit\r\n");
- }
-
-
- if (status_data[EXT_CSD_HS_TIMING] == MMC_HS_SUPPORT) {
- fsbl_printf(DEBUG_INFO, "High Speed Mode\r\n");
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- clk_div = (SDIO_FREQ / MMC_CLK_52M);
- if (!(SDIO_FREQ % MMC_CLK_52M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Enable high speed mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_HS;
- sd_out16(SD_HOST_CTRL_R, regval);
- } else {
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Calculating clock divisor
- */
- clk_div = (SDIO_FREQ / MMC_CLK_26M);
- if (!(SDIO_FREQ % MMC_CLK_26M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- }
-
- /*
- * Set R/W block length to 512
- */
- send_cmd(CMD16, SD_BLOCK_SZ, &response);
-
-fail:
- CardType = ty;
-
- return RES_OK;
-}
-
-#else
-/*
- * SD initialization
- */
-DRESULT sd_init(void)
-{
- BYTE ty;
- DSTATUS s;
- DWORD response;
- unsigned rca;
- u16 regval;
- u8 status_data[64];
- u8 sd_4bit_flag=0;
- u8 sd_hs_flag=0;
- u16 clk_div;
-
- /*
- * Enter Idle state
- */
- send_cmd(CMD0, 0, NULL);
-
- ty = CT_SD1;
- /*
- * SDv2?
- */
- if (send_cmd(CMD8, 0x1AA, &response) == 1) {
- /*
- * The card can work at vdd range of 2.7-3.6V
- */
- if (response == 0x1AA) {
- ty = CT_SD2;
- }
- }
-
- /*
- * Wait for leaving idle state (ACMD41 with HCS bit)
- */
- while (1) {
- /*
- * ACMD41, Set Operating Continuous
- */
- send_cmd(CMD55, 0, NULL);
- /* 0x00ff8000 */
- s = send_cmd(CMD41, 0x40300000, &response);
- if (s == 0) {
- /*
- * command error; probably an MMC card
- * presently unsupported; abort
- */
- ty = 0;
- goto fail;
- }
- if (response & 1<<31) {
- break;
- }
- }
- if (response & 1<<30) {
- /*
- * Card supports block addressing
- */
- ty |= CT_BLOCK;
- }
-
- /*
- * Get CID
- */
- send_cmd(CMD2, 0, &response);
-
- /*
- * Get RCA
- */
- rca = 0x1234;
- send_cmd(CMD3, rca << 16, &response);
- rca = response >> 16;
-
- /*
- * select card
- */
- send_cmd(CMD7, rca << 16, &response);
-
- /*
- * Getting 4bit support information
- */
- blkcnt = 1;
- blksize= 8;
-
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Application specific command
- */
- send_cmd(CMD55, rca << 16, &response);
-
- /*
- * Read SD Configuration Register
- */
- send_cmd(ACMD51, 0, &response);
-
- /*
- * Check for dma transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * SD 4-bit support check
- */
- if (status_data[1]&SD_4BIT_SUPPORT) {
- sd_4bit_flag=1;
- }
-
- /*
- * Getting high speed support support information
- */
- blkcnt = 1;
- blksize= 64;
-
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Check for high speed support switch
- */
- send_cmd(CMD6, 0x00FFFFF0, &response);
-
- /*
- * Check for dma transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * SD high speed support check
- */
- if (status_data[13]&SD_HS_SUPPORT) {
- sd_hs_flag=1;
- }
-
- /*
- * Application specific command
- */
- send_cmd(CMD55, rca << 16, &response);
-
- /*
- * Clear card detect pull-up
- */
- send_cmd(ACMD42, 0, &response);
-
- if (sd_4bit_flag) {
- /*
- * Application specific command
- */
- send_cmd(CMD55, rca << 16, &response);
-
- /*
- * Set data bus width to 4-bit
- */
- send_cmd(ACMD6, 2, &response);
-
- /*
- * Enable 4bit mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_4BIT;
- sd_out16(SD_HOST_CTRL_R, regval);
- }
-
- if (sd_hs_flag) {
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Switch device to high speed
- */
- send_cmd(CMD6, 0x80FFFFF1, &response);
-
- /*
- * Check for DMA transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- clk_div = (SDIO_FREQ/SD_CLK_50M);
- if (!(SDIO_FREQ%SD_CLK_50M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Enable high speed mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_HS;
- sd_out16(SD_HOST_CTRL_R, regval);
- } else {
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Calculating clock divisor
- */
- clk_div = (SDIO_FREQ/SD_CLK_25M);
- if (!(SDIO_FREQ%SD_CLK_25M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- }
-
- /*
- * Set R/W block length to 512
- */
- send_cmd(CMD16, SD_BLOCK_SZ, &response);
-
-fail:
- CardType = ty;
-
- return RES_OK;
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/nand.c b/quad/xsdk_workspace/zybo_fsbl/src/nand.c
deleted file mode 100644
index 7a50c35bea57061cd536ac5d94ce4aea39206095..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/nand.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nand.c
-*
-* Contains code for the NAND FLASH functionality. Bad Block management
-* is simple: skip the bad blocks and keep going.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
-* 3.00a sgd 30/01/13 Code cleanup
-* 5.00a sgd 17/05/13 Support for Multi Boot
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xparameters.h"
-#include "fsbl.h"
-#ifdef XPAR_PS7_NAND_0_BASEADDR
-#include "nand.h"
-#include "xnandps_bbm.h"
-
-
-/************************** Constant Definitions *****************************/
-
-#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
- u64 Offset,
- u32 Length);
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-extern u32 FlashOffsetAddress;
-
-XNandPs *NandInstPtr;
-XNandPs NandInstance; /* XNand Instance. */
-
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the NAND FLASH interface.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if the controller initializes correctly
-* - XST_FAILURE if the controller fails to initializes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 InitNand(void)
-{
-
- u32 Status;
- XNandPs_Config *ConfigPtr;
-
- /*
- * Set up pointers to instance and the config structure
- */
- NandInstPtr = &NandInstance;
-
- /*
- * Initialize the flash driver.
- */
- ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID);
-
- if (ConfigPtr == NULL) {
- fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
- return XST_FAILURE;
- }
-
- Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
- ConfigPtr->SmcBase,ConfigPtr->FlashBase);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"NAND intialization failed \n \r");
- return XST_FAILURE;
- }
-
- /*
- * Set up base address for access
- */
- FlashReadBaseAddress = XPS_NAND_BASEADDR;
-
- fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
- NandInstPtr->Geometry.FlashWidth);
-
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
- Status);
- return XST_FAILURE;
- }
-
- /*
- * set up the FLASH access pointers
- */
- fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the NAND FLASH interface for the Simplified header
-* functionality. This function handles bad blocks.
-*
-* The source address is the absolute good address, bad blocks are skipped
-* without incrementing the source address.
-*
-* @param SourceAddress is address in FLASH data space, absolute good address
-* @param DestinationAddress is address in OCM data space
-*
-* @return XST_SUCCESS if the transfer completes correctly
-* XST_FAILURE if the transfer fails to completes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u32 ActLen;
- u32 BlockOffset;
- u32 Block;
- u32 Status;
- u32 BytesLeft = LengthBytes;
- u32 BlockSize = NandInstPtr->Geometry.BlockSize;
- u8 *BufPtr = (u8 *)DestinationAddress;
- u32 ReadLen;
- u32 BlockReadLen;
- u32 Offset;
- u32 TmpAddress = 0 ;
- u32 BlockCount = 0;
- u32 BadBlocks = 0;
-
- /*
- * First get bad blocks before the source address
- */
- while (TmpAddress < SourceAddress) {
- while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
- XST_SUCCESS) {
- BlockCount ++;
- BadBlocks ++;
- }
-
- TmpAddress += BlockSize;
- BlockCount ++;
- }
-
- Offset = SourceAddress + BadBlocks * BlockSize;
-
- /*
- * Calculate the actual length including bad blocks
- */
- ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
-
- /*
- * Check if the actual length cross flash size
- */
- if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
- return XST_FAILURE;
- }
-
- while (BytesLeft > 0) {
- BlockOffset = Offset & (BlockSize - 1);
- Block = (Offset & ~(BlockSize - 1))/BlockSize;
- BlockReadLen = BlockSize - BlockOffset;
-
- Status = XNandPs_IsBlockBad(NandInstPtr, Block);
- if (Status == XST_SUCCESS) {
- /* Move to next block */
- Offset += BlockReadLen;
- continue;
- }
-
- /*
- * Check if we cross block boundary
- */
- if (BytesLeft < BlockReadLen) {
- ReadLen = BytesLeft;
- } else {
- ReadLen = BlockReadLen;
- }
-
- /*
- * Read from the NAND flash
- */
- Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
- if (Status != XST_SUCCESS) {
- return Status;
- }
- BytesLeft -= ReadLen;
- Offset += ReadLen;
- BufPtr += ReadLen;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the length including bad blocks from a given offset and
-* length.
-*
-* @param NandInstPtr is the pointer to the XNandPs instance.
-* @param Offset is the flash data address to read from.
-* @param Length is number of bytes to read.
-*
-* @return
-* - Return actual length including bad blocks.
-*
-* @note None.
-*
-******************************************************************************/
-static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
- u64 Offset,
- u32 Length)
-{
- u32 BlockSize = NandInstPtr->Geometry.BlockSize;
- u32 CurBlockLen;
- u32 CurBlock;
- u32 Status;
- u32 TempLen = 0;
- u32 ActLen = 0;
-
- while (TempLen < Length) {
- CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
- CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
-
- /*
- * Check if the block is bad
- */
- Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
- if (Status != XST_SUCCESS) {
- /* Good Block */
- TempLen += CurBlockLen;
- }
- ActLen += CurBlockLen;
- Offset += CurBlockLen;
- if (Offset >= NandInstPtr->Geometry.DeviceSize) {
- break;
- }
- }
-
- return ActLen;
-}
-
-#endif
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/nand.h b/quad/xsdk_workspace/zybo_fsbl/src/nand.h
deleted file mode 100644
index a7bdb08af8284ee66f8bf7b0c8130af0027d25bd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/nand.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nand.h
-*
-* This file contains the interface for the NAND FLASH functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___NAND_H___
-#define ___NAND_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-
-#include "smc.h"
-
-#ifdef XPAR_PS7_NAND_0_BASEADDR
-
-#include "xnandps.h"
-#include "xnandps_bbm.h"
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 InitNand(void);
-
-u32 NandAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthWords);
-#endif
-/************************** Variable Definitions *****************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___NAND_H___ */
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/nor.c b/quad/xsdk_workspace/zybo_fsbl/src/nor.c
deleted file mode 100644
index 0dc6c14ec5e17ebc15ca7f2a1b69b3a336da9f47..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/nor.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nor.c
-*
-* Contains code for the NOR FLASH functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 2.00a mb 25/05/12 mio init removed
-* 3.00a sgd 30/01/13 Code cleanup
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "nor.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-
-/******************************************************************************/
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the NOR FLASH interface.
-*
-* @param None
-*
-* @return None
-*
-* @note None.
-*
-****************************************************************************/
-void InitNor(void)
-{
-
- /*
- * Set up the base address for access
- */
- FlashReadBaseAddress = XPS_NOR_BASEADDR;
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the NOR FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in OCM data space
-* @param LengthBytes is the data length to transfer in bytes
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u32 Data;
- u32 Count;
- u32 *SourceAddr;
- u32 *DestAddr;
- u32 LengthWords;
-
- /*
- * check for non-word tail
- * add bytes to cover the end
- */
- if ((LengthBytes%4) != 0){
-
- LengthBytes += (4 - (LengthBytes & 0x00000003));
- }
-
- LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
-
- SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
- DestAddr = (u32 *)(DestinationAddress);
-
- /*
- * Word transfers, endianism isn't an issue
- */
- for (Count=0; Count < LengthWords; Count++){
-
- Data = Xil_In32((u32)(SourceAddr++));
- Xil_Out32((u32)(DestAddr++), Data);
- }
-
- return XST_SUCCESS;
-}
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/nor.h b/quad/xsdk_workspace/zybo_fsbl/src/nor.h
deleted file mode 100644
index 8e5fe0b6ab1f05225e0f9632b10f5c6419cc64c5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/nor.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nor.h
-*
-* This file contains the interface for the NOR FLASH functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___NOR_H___
-#define ___NOR_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-
-#include "smc.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-
-void InitNor(void);
-
-u32 NorAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___NOR_H___ */
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/pcap.c b/quad/xsdk_workspace/zybo_fsbl/src/pcap.c
deleted file mode 100644
index 50bebab3829103dfdc8ae08aa1284a5c00dcf4f3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/pcap.c
+++ /dev/null
@@ -1,655 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file pcap.c
-*
-* Contains code for enabling and accessing the PCAP
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 02/10/10 Initial release
-* 2.00a jz 05/28/11 Add SD support
-* 2.00a mb 25/05/12 using the EDK provided devcfg driver
-* Nand/SD encryption and review comments
-* 3.00a mb 16/08/12 Added the poll function
-* Removed the FPGA_RST_CTRL define
-* Added the flag for NON PS instantiated bitstream
-* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
-* fabric_init()
-* Fix for CR#689026 - FSBL doesn't hold PL resets active
-* during bit download
-* Fix for CR#699475 - FSBL functionality is broken and
-* its not able to boot in QSPI/NAND
-* bootmode
-* Fix for CR#705664 - FSBL fails to decrypt the
-* bitstream when the image is AES
-* encrypted using non-zero key value
-* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "pcap.h"
-#include "nand.h" /* For NAND geometry information */
-#include "fsbl.h"
-#include "image_mover.h" /* For MoveImage */
-#include "xparameters.h"
-#include "xil_exception.h"
-#include "xdevcfg.h"
-#include "sleep.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-/************************** Constant Definitions *****************************/
-/*
- * The following constants map to the XPAR parameters created in the
- * xparameters.h file. They are only defined here such that a user can easily
- * change all the needed parameters in one place.
- */
-
-#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
-
-/************************** Variable Definitions *****************************/
-/* Devcfg driver instance */
-static XDcfg DcfgInstance;
-XDcfg *DcfgInstPtr;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-/******************************************************************************/
-/**
-*
-* This function transfer data using PCAP
-*
-* @param SourceDataPtr is a pointer to where the data is read from
-* @param DestinationDataPtr is a pointer to where the data is written to
-* @param SourceLength is the length of the data to be moved in words
-* @param DestinationLength is the length of the data to be moved in words
-* @param SecureTransfer indicated the encryption key location, 0 for
-* non-encrypted
-*
-* @return
-* - XST_SUCCESS if the transfer is successful
-* - XST_FAILURE if the transfer fails
-*
-* @note None
-*
-****************************************************************************/
-u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
- u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
-{
- u32 Status;
- u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
-
- /*
- * Check for secure transfer
- */
- if (SecureTransfer) {
- PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
- }
-
-#ifdef FSBL_PERF
- XTime tXferCur = 0;
- FsblGetGlobalTime(tXferCur);
-#endif
-
- /*
- * Clear the PCAP status registers
- */
- Status = ClearPcapStatus();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
- return XST_FAILURE;
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * PCAP single DMA transfer setup
- */
- SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
- DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
-
- /*
- * Transfer using Device Configuration
- */
- Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
- SourceLength,
- (u8 *)DestinationDataPtr,
- DestinationLength, PcapTransferType);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
- return XST_FAILURE;
- }
-
- /*
- * Dump the PCAP registers
- */
- PcapDumpRegisters();
-
- /*
- * Poll for the DMA done
- */
- Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tXferEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Time taken is ");
- FsblMeasurePerfTime(tXferCur,tXferEnd);
-#endif
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function loads PL partition using PCAP
-*
-* @param SourceDataPtr is a pointer to where the data is read from
-* @param DestinationDataPtr is a pointer to where the data is written to
-* @param SourceLength is the length of the data to be moved in words
-* @param DestinationLength is the length of the data to be moved in words
-* @param SecureTransfer indicated the encryption key location, 0 for
-* non-encrypted
-*
-* @return
-* - XST_SUCCESS if the transfer is successful
-* - XST_FAILURE if the transfer fails
-*
-* @note None
-*
-****************************************************************************/
-u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
- u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
-{
- u32 Status;
- u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
-
- /*
- * Check for secure transfer
- */
- if (SecureTransfer) {
- PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
- }
-
-#ifdef FSBL_PERF
- XTime tXferCur = 0;
- FsblGetGlobalTime(tXferCur);
-#endif
-
- /*
- * Clear the PCAP status registers
- */
- Status = ClearPcapStatus();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
- return XST_FAILURE;
- }
-
- /*
- * For Bitstream case destination address will be 0xFFFFFFFF
- */
- DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
-
- /*
- * New Bitstream download initialization sequence
- */
- FabricInit();
-
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * PCAP single DMA transfer setup
- */
- SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
- DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
-
- /*
- * Transfer using Device Configuration
- */
- Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
- SourceLength,
- (u8 *)DestinationDataPtr,
- DestinationLength, PcapTransferType);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
- return XST_FAILURE;
- }
-
-
- /*
- * Dump the PCAP registers
- */
- PcapDumpRegisters();
-
-
- /*
- * Poll for the DMA done
- */
- Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
-
- /*
- * Poll for FPGA Done
- */
- Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tXferEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Time taken is ");
- FsblMeasurePerfTime(tXferCur,tXferEnd);
-#endif
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Initializes the PCAP driver.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if the pcap driver initialization is successful
-* - XST_FAILURE if the pcap driver initialization fails
-*
-* @note none
-*
-****************************************************************************/
-int InitPcap(void)
-{
- XDcfg_Config *ConfigPtr;
- int Status = XST_SUCCESS;
- DcfgInstPtr = &DcfgInstance;
-
- /*
- * Initialize the Device Configuration Interface driver.
- */
- ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
-
- Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
- ConfigPtr->BaseAddr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function programs the Fabric for use.
-*
-* @param None
-*
-* @return None
-* - XST_SUCCESS if the Fabric initialization is successful
-* - XST_FAILURE if the Fabric initialization fails
-* @note None
-*
-****************************************************************************/
-void FabricInit(void)
-{
- u32 PcapReg;
- u32 StatusReg;
-
- /*
- * Set Level Shifters DT618760 - PS to PL enabling
- */
- Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
- fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%x \r\n",
- Xil_In32(PS_LVL_SHFTR_EN));
-
- /*
- * Get DEVCFG controller settings
- */
- PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * 5msec delay
- */
- usleep(5000);
- /*
- * Setting PCFG_PROG_B signal to low
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * 5msec delay
- */
- usleep(5000);
- /*
- * Polling the PCAP_INIT status for Reset
- */
- while(XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK);
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Polling the PCAP_INIT status for Set
- */
- while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK));
-
- /*
- * Get Device configuration status
- */
- StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
- fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%x \r\n",StatusReg);
-
- fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
-}
-
-/******************************************************************************/
-/**
-*
-* This function Clears the PCAP status registers.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the pcap status registers are cleared
-* - XST_FAILURE if errors are there
-* - XST_DEVICE_BUSY if Pcap device is busy
-* @note None
-*
-****************************************************************************/
-u32 ClearPcapStatus(void)
-{
-
- u32 StatusReg;
- u32 IntStatusReg;
-
- /*
- * Clear it all, so if Boot ROM comes back, it can proceed
- */
- XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
-
- /*
- * Get PCAP Interrupt Status Register
- */
- IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
- IntStatusReg);
- return XST_FAILURE;
- }
-
- /*
- * Read the PCAP status register for DMA status
- */
- StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
-
- fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8x\r\n", StatusReg);
-
- /*
- * If the queue is full, return w/ XST_DEVICE_BUSY
- */
- if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
- XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
-
- fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
- return XST_DEVICE_BUSY;
- }
-
- fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
-
- /*
- * There are unacknowledged DMA commands outstanding
- */
- if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
- XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
-
- IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
-
- if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
- XDCFG_IXR_DMA_DONE_MASK){
- /*
- * Error state, transfer cannot occur
- */
- fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
- return XST_FAILURE;
- }
- else {
- /*
- * clear out the status
- */
- XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
- }
- }
-
- if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
- XDcfg_IntrClear(DcfgInstPtr, StatusReg &
- XDCFG_STATUS_DMA_DONE_CNT_MASK);
- }
-
- fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function prints PCAP register status.
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-****************************************************************************/
-void PcapDumpRegisters (void) {
-
- fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
-
- fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
-}
-
-/******************************************************************************/
-/**
-*
-* This function Polls for the DMA done or FPGA done.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if polling for DMA/FPGA done is successful
-* - XST_FAILURE if polling for DMA/FPGA done fails
-*
-* @note none
-*
-****************************************************************************/
-int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
-{
- int Count = MaxCount;
- u32 IntrStsReg = 0;
-
- /*
- * poll for the DMA done
- */
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- while ((IntrStsReg & MaskValue) !=
- MaskValue) {
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- Count -=1;
-
- if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
- IntrStsReg);
- PcapDumpRegisters();
- return XST_FAILURE;
- }
-
- if(!Count) {
- fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
- return XST_FAILURE;
- }
- if (Count > (MAX_COUNT-100)) {
- fsbl_printf(DEBUG_GENERAL,".");
- }
- }
-
- fsbl_printf(DEBUG_GENERAL,"\n\r");
-
- XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
-
- return XST_SUCCESS;
-}
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/pcap.h b/quad/xsdk_workspace/zybo_fsbl/src/pcap.h
deleted file mode 100644
index b0242d78fb5e2783921a263de06af9f71829985c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/pcap.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file pcap.h
-*
-* This file contains the interface for intiializing and accessing the PCAP
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 02/10/10 Initial release
-* 2.00a mb 16/08/12 Added the macros and function prototypes
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___PCAP_H___
-#define ___PCAP_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xdevcfg.h"
-
-/************************** Function Prototypes ******************************/
-
-
-/* Multiboot register offset mask */
-#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
-#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
-
-#define PCAP_LAST_TRANSFER 1
-#define MAX_COUNT 1000000000
-#define LVL_PL_PS 0x0000000F
-#define LVL_PS_PL 0x0000000A
-
-/* Fix for #672779 */
-#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-int InitPcap(void);
-void PcapDumpRegisters(void);
-u32 ClearPcapStatus(void);
-void FabricInit(void);
-int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
-u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
- u32 DestinationLength, u32 Flags);
-u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
- u32 DestinationLength, u32 Flags);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___PCAP_H___ */
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/qspi.c b/quad/xsdk_workspace/zybo_fsbl/src/qspi.c
deleted file mode 100644
index 6e1c15f713b79b95a46e533bfa4c05109415e5db..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/qspi.c
+++ /dev/null
@@ -1,724 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file qspi.c
-*
-* Contains code for the QSPI FLASH functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
-* are set
-* 4.00a sg 02/28/13 Cleanup
-* Removed LPBK_DLY_ADJ register setting code as we use
-* divisor 8
-* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
-* Dual Stack support
-* Fix for CR:721674 - FSBL- Failed to boot from Dual
-* stacked QSPI
-* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* Fix for CR#739711 - FSBL not able to read Large QSPI
-* (512M) in IO Mode
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "qspi.h"
-#include "image_mover.h"
-
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-#include "xqspips_hw.h"
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The following constants map to the XPAR parameters created in the
- * xparameters.h file. They are defined here such that a user can easily
- * change all the needed parameters in one place.
- */
-#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
-
-/*
- * The following constants define the commands which may be sent to the FLASH
- * device.
- */
-#define QUAD_READ_CMD 0x6B
-#define READ_ID_CMD 0x9F
-
-#define WRITE_ENABLE_CMD 0x06
-#define BANK_REG_RD 0x16
-#define BANK_REG_WR 0x17
-/* Bank register is called Extended Address Reg in Micron */
-#define EXTADD_REG_RD 0xC8
-#define EXTADD_REG_WR 0xC5
-
-#define COMMAND_OFFSET 0 /* FLASH instruction */
-#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
-#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
-#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
-#define DATA_OFFSET 4 /* Start of Data for Read/Write */
-#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
- reads */
-#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
- quad reads */
-#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
-#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
-#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
-/*
- * The following constants specify the extra bytes which are sent to the
- * FLASH on the QSPI interface, that are not data, but control information
- * which includes the command and address
- */
-#define OVERHEAD_SIZE 4
-
-/*
- * The following constants specify the max amount of data and the size of the
- * the buffer required to hold the data and overhead to transfer the data to
- * and from the FLASH.
- */
-#define DATA_SIZE 4096
-
-/*
- * The following defines are for dual flash interface.
- */
-#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
-#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
- address and return data */
-
-#define SINGLE_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_STACK_CONFIG_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-XQspiPs QspiInstance;
-XQspiPs *QspiInstancePtr;
-u32 QspiFlashSize;
-u32 QspiFlashMake;
-extern u32 FlashReadBaseAddress;
-extern u8 LinearBootDeviceFlag;
-
-/*
- * The following variables are used to read and write to the eeprom and they
- * are global to avoid having large buffers on the stack
- */
-u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
-u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
-
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the QSPI interface.
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-u32 InitQspi(void)
-{
- XQspiPs_Config *QspiConfig;
- int Status;
-
- QspiInstancePtr = &QspiInstance;
-
- /*
- * Set up the base address for access
- */
- FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
-
- /*
- * Initialize the QSPI driver so that it's ready to use
- */
- QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
- if (NULL == QspiConfig) {
- return XST_FAILURE;
- }
-
- Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
- QspiConfig->BaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Set Manual Chip select options and drive HOLD_B pin high.
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Set the prescaler for QSPI clock
- */
- XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
-
- /*
- * Read Flash ID and extract Manufacture and Size information
- */
- Status = FlashReadID();
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- if (XPAR_PS7_QSPI_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
- /*
- * For Flash size <128Mbit controller configured in linear mode
- */
- if (QspiFlashSize <= FLASH_SIZE_16MB) {
- LinearBootDeviceFlag = 1;
-
- /*
- * Enable linear mode
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Single linear read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, SINGLE_QSPI_CONFIG_QUAD_READ);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- }
- }
-
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
- /*
- * For Single Flash size <128Mbit controller configured in linear mode
- */
- if (QspiFlashSize <= FLASH_SIZE_16MB) {
- /*
- * Setting linear access flag
- */
- LinearBootDeviceFlag = 1;
-
- /*
- * Enable linear mode
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Dual linear read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_QUAD_READ);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- }
-
- /*
- * Total flash size is two time of single flash size
- */
- QspiFlashSize = 2 * QspiFlashSize;
- }
-
- /*
- * It is expected to same flash size for both chip selection
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
-
- QspiFlashSize = 2 * QspiFlashSize;
-
- /*
- * Enable two flash memories on separate buses
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_STACK_CONFIG_READ);
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* This function reads serial FLASH ID connected to the SPI interface.
-* It then deduces the make and size of the flash and obtains the
-* connection mode to point to corresponding parameters in the flash
-* configuration table. The flash driver will function based on this and
-* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
-* Winbond 128Mbit
-*
-* @param none
-*
-* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
-*
-* @note None.
-*
-******************************************************************************/
-u32 FlashReadID(void)
-{
- u32 Status;
-
- /*
- * Read ID in Auto mode.
- */
- WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
- WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
- WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
-
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- RD_ID_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
-
- fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
- ReadBuffer[2],
- ReadBuffer[3]);
-
- /*
- * Deduce flash make
- */
- if (ReadBuffer[1] == MICRON_ID) {
- QspiFlashMake = MICRON_ID;
- fsbl_printf(DEBUG_INFO, "MICRON ");
- } else if(ReadBuffer[1] == SPANSION_ID) {
- QspiFlashMake = SPANSION_ID;
- fsbl_printf(DEBUG_INFO, "SPANSION ");
- } else if(ReadBuffer[1] == WINBOND_ID) {
- QspiFlashMake = WINBOND_ID;
- fsbl_printf(DEBUG_INFO, "WINBOND ");
- }
-
- /*
- * Deduce flash Size
- */
- if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
- QspiFlashSize = FLASH_SIZE_128M;
- fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
- QspiFlashSize = FLASH_SIZE_256M;
- fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_512M) {
- QspiFlashSize = FLASH_SIZE_512M;
- fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_1G) {
- QspiFlashSize = FLASH_SIZE_1G;
- fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function reads from the serial FLASH connected to the
-* QSPI interface.
-*
-* @param Address contains the address to read data from in the FLASH.
-* @param ByteCount contains the number of bytes to read.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void FlashRead(u32 Address, u32 ByteCount)
-{
- /*
- * Setup the write command with the specified address and data for the
- * FLASH
- */
- WriteBuffer[COMMAND_OFFSET] = QUAD_READ_CMD;
- WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
- WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
- WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
-
- ByteCount += DUMMY_SIZE;
-
- /*
- * Send the read command to the FLASH to read the specified number
- * of bytes from the FLASH, send the read command and address and
- * receive the specified number of bytes of data in the data buffer
- */
- XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- ByteCount + OVERHEAD_SIZE);
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the QSPI FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in DDR data space
-* @param LengthBytes is the length of the data in Bytes
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u8 *BufferPtr;
- u32 Length = 0;
- u32 BankSel = 0;
- u32 LqspiCrReg;
- u32 Status;
- u8 BankSwitchFlag = 1;
-
- /*
- * Linear access check
- */
- if (LinearBootDeviceFlag == 1) {
- /*
- * Check for non-word tail, add bytes to cover the end
- */
- if ((LengthBytes%4) != 0){
- LengthBytes += (4 - (LengthBytes & 0x00000003));
- }
-
- memcpy((void*)DestinationAddress,
- (const void*)(SourceAddress + FlashReadBaseAddress),
- (size_t)LengthBytes);
- } else {
- /*
- * Non Linear access
- */
- BufferPtr = (u8*)DestinationAddress;
-
- /*
- * Dual parallel connection actual flash is half
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- SourceAddress = SourceAddress/2;
- }
-
- while(LengthBytes > 0) {
- /*
- * Local of DATA_SIZE size used for read/write buffer
- */
- if(LengthBytes > DATA_SIZE) {
- Length = DATA_SIZE;
- } else {
- Length = LengthBytes;
- }
-
- /*
- * Dual stack connection
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
- /*
- * Get the current LQSPI configuration value
- */
- LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
-
- /*
- * Select lower or upper Flash based on sector address
- */
- if (SourceAddress >= (QspiFlashSize/2)) {
- /*
- * Set selection to U_PAGE
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
- LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
-
- /*
- * Subtract first flash size when accessing second flash
- */
- SourceAddress = SourceAddress - (QspiFlashSize/2);
-
- fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
- }
- }
-
- /*
- * Select bank
- */
- if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
- BankSel = SourceAddress/FLASH_SIZE_16MB;
-
- fsbl_printf(DEBUG_INFO, "Bank Selection %d\n\r", BankSel);
-
- Status = SendBankSelect(BankSel);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
- return XST_FAILURE;
- }
-
- BankSwitchFlag = 0;
- }
-
- /*
- * If data to be read spans beyond the current bank, then
- * calculate length in current bank else no change in length
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- /*
- * In dual parallel mode, check should be for half
- * the length.
- */
- if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
- {
- Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
- /*
- * Above length calculated is for single flash
- * Length should be doubled since dual parallel
- */
- Length = Length * 2;
- BankSwitchFlag = 1;
- }
- } else {
- if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
- {
- Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
- BankSwitchFlag = 1;
- }
- }
-
- /*
- * Copying the image to local buffer
- */
- FlashRead(SourceAddress, Length);
-
- /*
- * Moving the data from local buffer to DDR destination address
- */
- memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
-
- /*
- * Updated the variables
- */
- LengthBytes -= Length;
-
- /*
- * For Dual parallel connection address increment should be half
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- SourceAddress += Length/2;
- } else {
- SourceAddress += Length;
- }
-
- BufferPtr = (u8*)((u32)BufferPtr + Length);
- }
-
- /*
- * Reset Bank selection to zero
- */
- Status = SendBankSelect(0);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
- return XST_FAILURE;
- }
-
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
-
- /*
- * Reset selection to L_PAGE
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
- LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
-
- fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-
-/******************************************************************************
-*
-* This functions selects the current bank
-*
-* @param BankSel is the bank to be selected in the flash device(s).
-*
-* @return XST_SUCCESS if bank selected
-* XST_FAILURE if selection failed
-* @note None.
-*
-******************************************************************************/
-u32 SendBankSelect(u8 BankSel)
-{
- u32 Status;
-
- /*
- * bank select commands for Micron and Spansion are different
- */
- if (QspiFlashMake == MICRON_ID) {
- /*
- * For micron command WREN should be sent first
- * except for some specific feature set
- */
- WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- WRITE_ENABLE_CMD_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
- WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (QspiFlashMake == SPANSION_ID) {
- WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
- WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- /*
- * For testing - Read bank to verify
- */
- if (QspiFlashMake == SPANSION_ID) {
- WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (QspiFlashMake == MICRON_ID) {
- WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (ReadBuffer[1] != BankSel) {
- fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
- ReadBuffer[1]);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/qspi.h b/quad/xsdk_workspace/zybo_fsbl/src/qspi.h
deleted file mode 100644
index 9bac79c382d68927fca61df4d27ae8c0219f0dac..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/qspi.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file qspi.h
-*
-* This file contains the interface for the QSPI FLASH functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
-* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
-* Dual Stack support
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___QSPI_H___
-#define ___QSPI_H___
-
-#include "fsbl.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define SINGLE_FLASH_CONNECTION 0
-#define DUAL_STACK_CONNECTION 1
-#define DUAL_PARALLEL_CONNECTION 2
-#define FLASH_SIZE_16MB 0x1000000
-
-/*
- * Bank mask
- */
-#define BANKMASK 0xF000000
-
-/*
- * Identification of Flash
- * Micron:
- * Byte 0 is Manufacturer ID;
- * Byte 1 is first byte of Device ID - 0xBB or 0xBA
- * Byte 2 is second byte of Device ID describes flash size:
- * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
- * Spansion:
- * Byte 0 is Manufacturer ID;
- * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
- * Byte 2 is second byte of Device ID describes flash size:
- * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
- */
-
-#define MICRON_ID 0x20
-#define SPANSION_ID 0x01
-#define WINBOND_ID 0xEF
-
-#define FLASH_SIZE_ID_128M 0x18
-#define FLASH_SIZE_ID_256M 0x19
-#define FLASH_SIZE_ID_512M 0x20
-#define FLASH_SIZE_ID_1G 0x21
-
-/*
- * Size in bytes
- */
-#define FLASH_SIZE_128M 0x1000000
-#define FLASH_SIZE_256M 0x2000000
-#define FLASH_SIZE_512M 0x4000000
-#define FLASH_SIZE_1G 0x8000000
-
-/************************** Function Prototypes ******************************/
-u32 InitQspi(void);
-
-u32 QspiAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-u32 FlashReadID(void);
-u32 SendBankSelect(u8 BankSel);
-/************************** Variable Definitions *****************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___QSPI_H___ */
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/rsa.c b/quad/xsdk_workspace/zybo_fsbl/src/rsa.c
deleted file mode 100644
index 1f43b605330bc6b1c4ef6a03be409cff4c5fb034..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/rsa.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file rsa.c
-*
-* Contains code for the RSA authentication
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.00a sgd 02/28/13 Initial release
-* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
-* Fix for CR#724165 - Partition Header used by FSBL is
-* not authenticated
-* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
-* by Boot ROM for authenticating
-* the Partition images
-* Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "rsa.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-
-/************************** Variable Definitions *****************************/
-
-#ifdef RSA_SUPPORT
-static u8 *PpkModular;
-static u8 *PpkModularEx;
-static u32 PpkExp;
-
-
-extern u32 FsblLength;
-
-void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
-{
-#ifdef FSBL_DEBUG_RSA
- int Index;
- fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
- for (Index=0;Index<Len;Index++)
- {
- fsbl_printf(DEBUG_INFO, "%02x",Buf[Index]);
- if ((Index+1)%16 == 0){
- fsbl_printf(DEBUG_INFO, "\r\n");
- }
- }
- fsbl_printf(DEBUG_INFO, "\r\n %s END\r\n",Str);
-#endif
- return;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function is used to set ppk pointer to ppk in OCM
-*
-* @param None
-*
-* @return
-*
-* @note None
-*
-******************************************************************************/
-
-void SetPpk(void )
-{
- u32 PadSize;
- u8 *PpkPtr;
-
- /*
- * Set PpkPtr to PPK in OCM
- */
-
- /*
- * Skip FSBL Length
- */
- PpkPtr = (u8 *)(FsblLength);
- /*
- * Skip to 64 byte Boundary
- */
- PadSize = ((u32)PpkPtr % 64);
- if(PadSize != 0)
- {
- PpkPtr += (64 - PadSize);
- }
-
- /*
- * Increment the pointer by authentication Header size
- */
- PpkPtr += RSA_HEADER_SIZE;
-
- /*
- * Increment the pointer by Magic word size
- */
- PpkPtr += RSA_MAGIC_WORD_SIZE;
-
- /*
- * Set pointer to PPK
- */
- PpkModular = (u8 *)PpkPtr;
- PpkPtr += RSA_PPK_MODULAR_SIZE;
- PpkModularEx = (u8 *)PpkPtr;
- PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
- PpkExp = *((u32 *)PpkPtr);
-
- return;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function Authenticate Partition Signature
-*
-* @param Partition header pointer
-*
-* @return
-* - XST_SUCCESS if Authentication passed
-* - XST_FAILURE if Authentication failed
-*
-* @note None
-*
-******************************************************************************/
-u32 AuthenticatePartition(u8 *Buffer, u32 Size)
-{
- u8 DecryptSignature[256];
- u8 HashSignature[32];
- u8 *SpkModular;
- u8 *SpkModularEx;
- u32 SpkExp;
- u8 *SignaturePtr;
- u32 Status;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * Point to Authentication Certificate
- */
- SignaturePtr = (u8 *)(Buffer + Size - RSA_SIGNATURE_SIZE);
-
- /*
- * Increment the pointer by authentication Header size
- */
- SignaturePtr += RSA_HEADER_SIZE;
-
- /*
- * Increment the pointer by Magic word size
- */
- SignaturePtr += RSA_MAGIC_WORD_SIZE;
-
- /*
- * Increment the pointer beyond the PPK
- */
- SignaturePtr += RSA_PPK_MODULAR_SIZE;
- SignaturePtr += RSA_PPK_MODULAR_EXT_SIZE;
- SignaturePtr += RSA_PPK_EXPO_SIZE;
-
- /*
- * Calculate Hash Signature
- */
- sha_256((u8 *)SignaturePtr, (RSA_SPK_MODULAR_EXT_SIZE +
- RSA_SPK_EXPO_SIZE + RSA_SPK_MODULAR_SIZE),
- HashSignature);
- FsblPrintArray(HashSignature, 32, "SPK Hash Calculated");
-
- /*
- * Extract SPK signature
- */
- SpkModular = (u8 *)SignaturePtr;
- SignaturePtr += RSA_SPK_MODULAR_SIZE;
- SpkModularEx = (u8 *)SignaturePtr;
- SignaturePtr += RSA_SPK_MODULAR_EXT_SIZE;
- SpkExp = *((u32 *)SignaturePtr);
- SignaturePtr += RSA_SPK_EXPO_SIZE;
-
- /*
- * Decrypt SPK Signature
- */
- rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
- (RSA_NUMBER)SignaturePtr,
- (u32)PpkExp,
- (RSA_NUMBER)PpkModular,
- (RSA_NUMBER)PpkModularEx);
- FsblPrintArray(DecryptSignature, RSA_SPK_SIGNATURE_SIZE,
- "SPK Decrypted Hash");
-
-
- Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Partition SPK Signature "
- "Authentication failed\r\n");
- return XST_FAILURE;
- }
- SignaturePtr += RSA_SPK_SIGNATURE_SIZE;
-
- /*
- * Decrypt Partition Signature
- */
- rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
- (RSA_NUMBER)SignaturePtr,
- (u32)SpkExp,
- (RSA_NUMBER)SpkModular,
- (RSA_NUMBER)SpkModularEx);
- FsblPrintArray(DecryptSignature, RSA_PARTITION_SIGNATURE_SIZE,
- "Partition Decrypted Hash");
-
- /*
- * Partition Authentication
- * Calculate Hash Signature
- */
- sha_256((u8 *)Buffer,
- (Size - RSA_PARTITION_SIGNATURE_SIZE),
- HashSignature);
- FsblPrintArray(HashSignature, 32,
- "Partition Hash Calculated");
-
- Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Partition Signature "
- "Authentication failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function recreates the and check signature
-*
-* @param Partition signature
-* @param Partition hash value which includes boot header, partition data
-* @return
-* - XST_SUCCESS if check passed
-* - XST_FAILURE if check failed
-*
-* @note None
-*
-******************************************************************************/
-u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash)
-{
- u8 T_padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
- 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
- u8 * pad_ptr = signature + 256;
- u32 pad = 256 - 3 - 19 - 32;
- u32 ii;
-
- /*
- * Re-Create PKCS#1v1.5 Padding
- * MSB ----------------------------------------------------LSB
- * 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
- */
- if (*--pad_ptr != 0x00 || *--pad_ptr != 0x01) {
- return XST_FAILURE;
- }
-
- for (ii = 0; ii < pad; ii++) {
- if (*--pad_ptr != 0xFF) {
- return XST_FAILURE;
- }
- }
-
- if (*--pad_ptr != 0x00) {
- return XST_FAILURE;
- }
-
- for (ii = 0; ii < sizeof(T_padding); ii++) {
- if (*--pad_ptr != T_padding[ii]) {
- return XST_FAILURE;
- }
- }
-
- for (ii = 0; ii < 32; ii++) {
- if (*--pad_ptr != hash[ii])
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/rsa.h b/quad/xsdk_workspace/zybo_fsbl/src/rsa.h
deleted file mode 100644
index bb1c5f37adeb8b5337cc9c268f06607d0e5463af..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/rsa.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file rsa.h
-*
-* This file contains the RSA algorithm functions
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.00a sg 02/28/13 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___RSA_H___
-#define ___RSA_H___
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************************** Include Files *********************************/
-
-/*
- * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
- * 32-bit digits are approximately 4 times faster
- */
-
-//#define RSA_DIGIT_16
-#define RSA_DIGIT_32
-
-/*
- * RSA loop unrolling selection
- * RSA main loop can be unrolled 2, 4 or 8 ways
- */
-#define RSA_UNROLL 1
-
-/*
- * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
- */
-//#define RSA_ARM_OPTIMIZED
-
-/*
- * Check the compatibility of the selection
- */
-#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
- #error Please select a digit size
-#endif
-#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
- #error Please select just one digit size
-#endif
-#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
- #error Assembly level code is only supported for the GCC/ARM combination
-#endif
-#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
- #error Only 1, 2, 4, and 8 unrolling are supported
-#endif
-
-#ifdef RSA_DIGIT_16
-#define RSA_DIGIT unsigned short
-#define RSA_SDIGIT short
-#define RSA_DDIGIT unsigned long
-#endif
-#ifdef RSA_DIGIT_32
-#define RSA_DIGIT unsigned long
-#define RSA_SDIGIT long
-#define RSA_DDIGIT unsigned long long
-#endif
-
-#define RSA_NUMBER RSA_DIGIT *
-#define RSA_NBITS 2048
-#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
-#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
-
-/*
- * Double-digit to single digit conversion
- */
-#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
-#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
-
-#define SHA_BLKSIZE 512
-#define SHA_BLKBYTES (SHA_BLKSIZE/8)
-#define SHA_BLKWORDS (SHA_BLKBYTES/4)
-
-#define SHA_VALSIZE 256
-#define SHA_VALBYTES (SHA_VALSIZE/8)
-#define SHA_VALWORDS (SHA_VALBYTES/4)
-
-#define RSA_PPK_MODULAR_SIZE 256
-#define RSA_PPK_MODULAR_EXT_SIZE 256
-#define RSA_PPK_EXPO_SIZE 64
-#define RSA_SPK_MODULAR_SIZE 256
-#define RSA_SPK_MODULAR_EXT_SIZE 256
-#define RSA_SPK_EXPO_SIZE 64
-#define RSA_SPK_SIGNATURE_SIZE 256
-#define RSA_PARTITION_SIGNATURE_SIZE 256
-#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
-#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
-#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
-
-/*
- * SHA-256 context structure
- * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
- * total byte length counter (used both to manage the buffer and for padding)
- */
-typedef struct
-{
- unsigned int state[8];
- unsigned char buffer[SHA_BLKBYTES];
- unsigned long long bytes;
-} sha2_context;
-
-/*
- * RSA-2048 user interfaces
- */
-void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
- const unsigned char *modular_ext, const unsigned char *exponent,
- unsigned char *result);
-void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
- unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
-
-/*
- * SHA-256 user interfaces
- */
-void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
-void sha2_starts(sha2_context *ctx);
-void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
-void sha2_finish(sha2_context *ctx, unsigned char* output);
-
-/*
- * Preprocessing interface (pre-computation of R*R mod M)
- */
-void modular_ext(const unsigned char *modular, unsigned char *res);
-
-void SetPpk(void );
-u32 AuthenticatePartition(u8 *Buffer, u32 Size);
-u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___RSA_H___ */
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/sd.c b/quad/xsdk_workspace/zybo_fsbl/src/sd.c
deleted file mode 100644
index b0e4b9ca34c35147259b83a15f7a2d7f63e12578..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/sd.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file sd.c
-*
-* Contains code for the SD card FLASH functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 04/28/11 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xparameters.h"
-#include "fsbl.h"
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-#include "xstatus.h"
-
-#include "ff.h"
-#include "sd.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-
-
-static FIL fil; /* File object */
-static FATFS fatfs;
-static char buffer[32];
-static char *boot_file = buffer;
-
-/******************************************************************************/
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the SD FLASH interface.
-*
-* @param filename of the file that is to be used
-*
-* @return
-* - XST_SUCCESS if the controller initializes correctly
-* - XST_FAILURE if the controller fails to initializes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 InitSD(const char *filename)
-{
-
- FRESULT rc;
-
- /* Register volume work area, initialize device */
- rc = f_mount(0, &fatfs);
- fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
-
- if (rc != FR_OK) {
- return XST_FAILURE;
- }
-
- strcpy_rom(buffer, filename);
- boot_file = (char *)buffer;
- FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
-
- rc = f_open(&fil, boot_file, FA_READ);
- if (rc) {
- fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the SD FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in OCM data space
-* @param LengthBytes is the number of bytes to move
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
-
- FRESULT rc; /* Result code */
- UINT br;
-
- rc = f_lseek(&fil, SourceAddress);
- if (rc) {
- fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %x\n", SourceAddress);
- return XST_FAILURE;
- }
-
- rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
-
- if (rc) {
- fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
- }
-
- return XST_SUCCESS;
-
-} /* End of SDAccess */
-
-
-/******************************************************************************/
-/**
-*
-* This function closes the file object
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void ReleaseSD(void) {
-
- f_close(&fil);
- return;
-
-
-}
-#endif
-
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/sd.h b/quad/xsdk_workspace/zybo_fsbl/src/sd.h
deleted file mode 100644
index 9de76281fcca143a55476b5e3002a146ee8a30c4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/sd.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file sd.h
-*
-* This file contains the interface for the Secure Digital (SD) card
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a bh 03/10/11 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___SD_H___
-#define ___SD_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-u32 InitSD(const char *);
-
-u32 SDAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthWords);
-
-void ReleaseSD(void);
-#endif
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___SD_H___ */
-
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/sd_hardware.h b/quad/xsdk_workspace/zybo_fsbl/src/sd_hardware.h
deleted file mode 100644
index 16872f4f9257779db8d3a9c2c67aa4106f6befb1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/sd_hardware.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file sd_hardware.h
-*
-* Controller register and bit definitions
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a bh 02/01/11 Initial version,
-* </pre>
-*
-* @note None.
-*
-******************************************************************************/
-#ifndef __SD_HARDWARE_H__
-#define __SD_HARDWARE_H__
-
-#define SD_BLOCK_SZ 0x200
-#define SD_CLK_400K 400000
-#define SD_CLK_50M 50000000
-#define SD_CLK_25M 25000000
-#define SD_HS_SUPPORT 0x2
-#define SD_4BIT_SUPPORT 0x5
-
-#define SD_DMA_ADDR_R 0x00
-#define SD_BLOCK_SZ_R 0x04
-#define SD_BLOCK_CNT_R 0x06
-
-#define SD_ARG_R 0x08
-
-#define SD_TRNS_MODE_R 0x0C
-#define SD_TRNS_DMA 0x01
-#define SD_TRNS_BLK_CNT_EN 0x02
-#define SD_TRNS_ACMD12 0x04
-#define SD_TRNS_READ 0x10
-#define SD_TRNS_MULTI 0x20
-
-#define SD_CMD_R 0x0E
-#define SD_CMD_RESP_NONE 0x00
-#define SD_CMD_RESP_136 0x01
-#define SD_CMD_RESP_48 0x02
-#define SD_CMD_RESP_48_BUSY 0x03
-#define SD_CMD_CRC 0x08
-#define SD_CMD_INDEX 0x10
-#define SD_CMD_DATA 0x20
-
-#define SD_RSP_R 0x10
-
-#define SD_BUFF_R 0x20
-
-#define SD_PRES_STATE_R 0x24
-#define SD_CMD_INHIBIT 0x00000001
-#define SD_DATA_INHIBIT 0x00000002
-#define SD_WRITE_ACTIVE 0x00000100
-#define SD_READ_ACTIVE 0x00000200
-#define SD_CARD_INS 0x00010000
-#define SD_CARD_WP 0x00080000
-
-#define SD_HOST_CTRL_R 0x28
-#define SD_HOST_4BIT 0x02
-#define SD_HOST_HS 0x04
-#define SD_HOST_ADMA1 0x08
-#define SD_HOST_ADMA2 0x10
-
-#define SD_PWR_CTRL_R 0x29
-#define SD_POWER_ON 0x01
-#define SD_POWER_18 0x0A
-#define SD_POWER_30 0x0C
-#define SD_POWER_33 0x0E
-
-#define SD_BLCK_GAP_CTL_R 0x2A
-
-#define SD_WAKE_CTL_R 0x2B
-
-#define SD_CLK_CTL_R 0x2C
-#define SD_DIV_SHIFT 8
-#define SD_CLK_SD_EN 0x0004
-#define SD_CLK_INT_STABLE 0x0002
-#define SD_CLK_INT_EN 0x0001
-
-#define SD_TIMEOUT_CTL_R 0x2E
-
-#define SD_SOFT_RST_R 0x2F
-#define SD_RST_ALL 0x01
-#define SD_RST_CMD 0x02
-#define SD_RST_DATA 0x04
-
-#define SD_INT_STAT_R 0x30
-#define SD_INT_ENA_R 0x34
-#define SD_SIG_ENA_R 0x38
-#define SD_INT_CMD_CMPL 0x00000001
-#define SD_INT_TRNS_CMPL 0x00000002
-#define SD_INT_DMA 0x00000008
-#define SD_INT_ERROR 0x00008000
-#define SD_INT_ERR_CTIMEOUT 0x00010000
-#define SD_INT_ERR_CCRC 0x00020000
-#define SD_INT_ERR_CEB 0x00040000
-#define SD_INT_ERR_IDX 0x00080000
-#define SD_INT_ERR_DTIMEOUT 0x00100000
-#define SD_INT_ERR_DCRC 0x00200000
-#define SD_INT_ERR_DEB 0x00400000
-#define SD_INT_ERR_CLMT 0x00800000
-#define SD_INT_ERR_ACMD12 0x01000000
-#define SD_INT_ERR_ADMA 0x02000000
-#define SD_INT_ERR_TRESP 0x10000000
-
-#define SD_CAPABILITIES_R 0x40
-
-#define SD_ADMA_ADDR_R 0x58
-#define DESC_ATBR_VALID (0x1 << 0)
-#define DESC_ATBR_END (0x1 << 1)
-#define DESC_ATBR_INT (0x1 << 2)
-#define DESC_ATBR_ACT_TRAN (0x2 << 4)
-#define DESC_ATBR_LEN_SHIFT 16
-
-#endif
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject b/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject
deleted file mode 100644
index 2ed788b9c962e8616019e7ed814e42f7ac4936cf..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.1193087237">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1193087237" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
- <externalSettings/>
- <extensions/>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-</cproject>
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/.project b/quad/xsdk_workspace/zybo_fsbl_bsp/.project
deleted file mode 100644
index 9b0b646a377bd2ee0bc4cb7321145a43ce57bf2a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/.project
+++ /dev/null
@@ -1,76 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>zybo_fsbl_bsp</name>
- <comment></comment>
- <projects>
- <project>sytem_hw_platform</project>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.make.core.makeBuilder</name>
- <arguments>
- <dictionary>
- <key>org.eclipse.cdt.core.errorOutputParser</key>
- <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.append_environment</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.arguments</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.command</key>
- <value>make</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.auto</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.clean</key>
- <value>clean</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.inc</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableFullBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.environment</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.stopOnError</key>
- <value>false</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
- <value>true</value>
- </dictionary>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>com.xilinx.sdk.sw.SwProjectNature</nature>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.make.core.makeNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/.sdkproject b/quad/xsdk_workspace/zybo_fsbl_bsp/.sdkproject
deleted file mode 100644
index 3135ec9f796f86108f3510421221835514fcc15f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/.sdkproject
+++ /dev/null
@@ -1,3 +0,0 @@
-THIRPARTY=false
-PROCESSOR=ps7_cortexa9_0
-MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/Makefile b/quad/xsdk_workspace/zybo_fsbl_bsp/Makefile
deleted file mode 100644
index fe2a0efc7cc39ff9edfdbb9064b229a72106cb58..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# Makefile generated by Xilinx SDK.
-
--include libgen.options
-
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-MSS = system.mss
-
-all: libs
- @echo 'Finished building libraries'
-
-libs: $(LIBRARIES)
-
-$(LIBRARIES): $(MSS)
- libgen -hw ${HWSPEC}\
- ${REPOSITORIES}\
- -pe ${PROCESSOR} \
- -log libgen.log \
- $(MSS)
-
-clean:
- rm -rf ${PROCESSOR}
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options b/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options
deleted file mode 100644
index c7623d91f4a1e0004da3838082aea20358655cc9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options
+++ /dev/null
@@ -1,3 +0,0 @@
-PROCESSOR=ps7_cortexa9_0
-REPOSITORIES=
-HWSPEC=../sytem_hw_platform/system.xml
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss b/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss
deleted file mode 100644
index 901e54a471058d3b3cfbef52689f574ae2ceb2d3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss
+++ /dev/null
@@ -1,297 +0,0 @@
-
- PARAMETER VERSION = 2.2.0
-
-
-BEGIN OS
- PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 3.11.a
- PARAMETER PROC_INSTANCE = ps7_cortexa9_0
- PARAMETER STDIN = ps7_uart_0
- PARAMETER STDOUT = ps7_uart_0
-END
-
-
-BEGIN PROCESSOR
- PARAMETER DRIVER_NAME = cpu_cortexa9
- PARAMETER DRIVER_VER = 1.01.a
- PARAMETER HW_INSTANCE = ps7_cortexa9_0
-END
-
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = tmrctr
- PARAMETER DRIVER_VER = 2.05.a
- PARAMETER HW_INSTANCE = axi_timer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 3.01.a
- PARAMETER HW_INSTANCE = btns_4bits_tri_io
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_afi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_afi_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_afi_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_afi_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_coresight_comp_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_ddr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_ddrc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = devcfg
- PARAMETER DRIVER_VER = 2.04.a
- PARAMETER HW_INSTANCE = ps7_dev_cfg_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 1.06.a
- PARAMETER HW_INSTANCE = ps7_dma_ns
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 1.06.a
- PARAMETER HW_INSTANCE = ps7_dma_s
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 1.05.a
- PARAMETER HW_INSTANCE = ps7_ethernet_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_globaltimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpiops
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = ps7_gpio_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_gpv_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 1.04.a
- PARAMETER HW_INSTANCE = ps7_i2c_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 1.04.a
- PARAMETER HW_INSTANCE = ps7_i2c_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_intc_dist_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_l2cachec_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_ocmc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = qspips
- PARAMETER DRIVER_VER = 2.03.a
- PARAMETER HW_INSTANCE = ps7_qspi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_qspi_linear_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_ram_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_ram_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_scuc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 1.05.a
- PARAMETER HW_INSTANCE = ps7_scugic_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scutimer
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = ps7_scutimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scuwdt
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = ps7_scuwdt_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_sd_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ps7_slcr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 1.05.a
- PARAMETER HW_INSTANCE = ps7_uart_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 1.05.a
- PARAMETER HW_INSTANCE = ps7_uart_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = usbps
- PARAMETER DRIVER_VER = 1.05.a
- PARAMETER HW_INSTANCE = ps7_usb_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = xadcps
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = ps7_xadc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_recorder_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_recorder_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_recorder_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_recorder_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_recorder_4
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_recorder_5
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_3
-END
-
-
diff --git a/quad/xsdk_workspace_vivado/RemoteSystemsTempFiles/.project b/quad/xsdk_workspace_vivado/RemoteSystemsTempFiles/.project
deleted file mode 100644
index 5447a64fa9d029de5bd06a0ad372bebc0db9a9c1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/RemoteSystemsTempFiles/.project
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>RemoteSystemsTempFiles</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- </buildSpec>
- <natures>
- <nature>org.eclipse.rse.ui.remoteSystemsTempNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/real_quad/.cproject b/quad/xsdk_workspace_vivado/real_quad/.cproject
deleted file mode 100644
index cb687f8596bdd56889ccb4956f1aa388891dd0ce..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/.cproject
+++ /dev/null
@@ -1,180 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="xilinx.gnu.armv7.exe.debug.1245217687">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.1245217687" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.debug.1245217687" name="Debug" parent="xilinx.gnu.armv7.exe.debug" prebuildStep="a9-linaro-pre-build-step">
- <folderInfo id="xilinx.gnu.armv7.exe.debug.1245217687." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.armv7.exe.debug.toolchain.998329507" name="Xilinx ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.debug.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.debug.1284634467" isAbstract="false" name="Debug Platform" superClass="xilinx.armv7.target.gnu.base.debug"/>
- <builder buildPath="${workspace_loc:/real_quad}/Debug" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.debug.1307414840" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.armv7.toolchain.builder.debug"/>
- <tool id="xilinx.gnu.armv7.c.toolchain.assembler.debug.1166376353" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.debug">
- <inputType id="xilinx.gnu.assembler.input.520283046" superClass="xilinx.gnu.assembler.input"/>
- </tool>
- <tool id="xilinx.gnu.armv7.c.toolchain.compiler.debug.537645504" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.816212278" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.2038946279" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1981775321" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- </option>
- <option id="xilinx.gnu.compiler.misc.other.693404765" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
- <option id="xilinx.gnu.compiler.dircategory.includes.824665764" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/commands}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/computation_graph}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/graph_blocks}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/quad_app}""/>
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ext/queue}""/>
- </option>
- <inputType id="xilinx.gnu.armv7.c.compiler.input.276088888" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
- </tool>
- <tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.debug.523403942" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1591080094" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.965983823" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.666259264" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- </option>
- </tool>
- <tool id="xilinx.gnu.armv7.toolchain.archiver.1116746044" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
- <tool id="xilinx.gnu.armv7.c.toolchain.linker.debug.1508513016" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1672422908" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.794065502" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.1187047196" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.ldflags.1918760372" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.251635495" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
- <listOptionValue builtIn="false" value="m"/>
- </option>
- <inputType id="xilinx.gnu.linker.input.1619669762" superClass="xilinx.gnu.linker.input">
- <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
- <additionalInput kind="additionalinput" paths="$(LIBS)"/>
- </inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.1314642764" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
- </tool>
- <tool id="xilinx.gnu.armv7.cxx.toolchain.linker.debug.1128697700" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.340934892" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.828101326" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.455382557" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- </tool>
- <tool id="xilinx.gnu.armv7.size.debug.1943743378" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.debug"/>
- </toolChain>
- </folderInfo>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- <cconfiguration id="xilinx.gnu.armv7.exe.release.5476642">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.release.5476642" moduleId="org.eclipse.cdt.core.settings" name="Release">
- <externalSettings/>
- <extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.release.5476642" name="Release" parent="xilinx.gnu.armv7.exe.release" prebuildStep="a9-linaro-pre-build-step">
- <folderInfo id="xilinx.gnu.armv7.exe.release.5476642." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.armv7.exe.release.toolchain.1615887378" name="Xilinx ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.release.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.release.1418200810" isAbstract="false" name="Release Platform" superClass="xilinx.armv7.target.gnu.base.release"/>
- <builder buildPath="${workspace_loc:/real_quad}/Release" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.release.1345190549" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.armv7.toolchain.builder.release"/>
- <tool id="xilinx.gnu.armv7.c.toolchain.assembler.release.544867390" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.release">
- <inputType id="xilinx.gnu.assembler.input.1854748968" superClass="xilinx.gnu.assembler.input"/>
- </tool>
- <tool id="xilinx.gnu.armv7.c.toolchain.compiler.release.1774347966" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.release">
- <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1109949560" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.1719497504" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.551039729" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- </option>
- <option id="xilinx.gnu.compiler.misc.other.1220258141" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
- <inputType id="xilinx.gnu.armv7.c.compiler.input.1905976603" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
- </tool>
- <tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.release.330353795" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.release">
- <option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1382654393" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.83616500" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.2075210092" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
- </option>
- </tool>
- <tool id="xilinx.gnu.armv7.toolchain.archiver.2045231509" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
- <tool id="xilinx.gnu.armv7.c.toolchain.linker.release.1233504244" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1007503113" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1633933097" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.1391503865" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.ldflags.1032159198" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
- <inputType id="xilinx.gnu.linker.input.2000592538" superClass="xilinx.gnu.linker.input">
- <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
- <additionalInput kind="additionalinput" paths="$(LIBS)"/>
- </inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.619596326" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
- </tool>
- <tool id="xilinx.gnu.armv7.cxx.toolchain.linker.release.906108567" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.359010680" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
- </option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1749622312" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
- <listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
- </option>
- <option id="xilinx.gnu.c.linker.option.lscript.1678598473" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- </tool>
- <tool id="xilinx.gnu.armv7.size.release.1171671789" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.release"/>
- </toolChain>
- </folderInfo>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="real_quad.xilinx.gnu.armv7.exe.673619442" name="Xilinx ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
- </storageModule>
- <storageModule moduleId="scannerConfiguration">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1245217687;xilinx.gnu.armv7.exe.debug.1245217687.;xilinx.gnu.armv7.c.toolchain.compiler.debug.537645504;xilinx.gnu.armv7.c.compiler.input.276088888">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.5476642;xilinx.gnu.armv7.exe.release.5476642.;xilinx.gnu.armv7.c.toolchain.compiler.release.1774347966;xilinx.gnu.armv7.c.compiler.input.1905976603">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.5476642;xilinx.gnu.armv7.exe.release.5476642.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1245217687;xilinx.gnu.armv7.exe.debug.1245217687.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- </storageModule>
- <storageModule moduleId="refreshScope" versionNumber="2">
- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/real_quad"/>
- </configuration>
- <configuration configurationName="Release">
- <resource resourceType="PROJECT" workspacePath="/real_quad"/>
- </configuration>
- </storageModule>
-</cproject>
diff --git a/quad/xsdk_workspace_vivado/real_quad/.gitignore b/quad/xsdk_workspace_vivado/real_quad/.gitignore
deleted file mode 100644
index 3df573fe623699c4038ba9501388748f93485913..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/quad/xsdk_workspace_vivado/real_quad/.project b/quad/xsdk_workspace_vivado/real_quad/.project
deleted file mode 100644
index e69d2ea837c367144dfd07b192011c7003aeaf8e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/.project
+++ /dev/null
@@ -1,190 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>real_quad</name>
- <comment>Created by SDK v2018.2. system_bsp - ps7_cortexa9_0</comment>
- <projects>
- <project>system_bsp</project>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
- <linkedResources>
- <link>
- <name>ext/commands</name>
- <type>2</type>
- <location>/local/ucart/MicroCART/quad/src/commands</location>
- </link>
- <link>
- <name>ext/computation_graph</name>
- <type>2</type>
- <location>/local/ucart/MicroCART/quad/src/computation_graph</location>
- </link>
- <link>
- <name>ext/graph_blocks</name>
- <type>2</type>
- <location>/local/ucart/MicroCART/quad/src/graph_blocks</location>
- </link>
- <link>
- <name>ext/quad_app</name>
- <type>2</type>
- <location>/local/ucart/MicroCART/quad/src/quad_app</location>
- </link>
- <link>
- <name>ext/queue</name>
- <type>2</type>
- <location>/local/ucart/MicroCART/quad/src/queue</location>
- </link>
- </linkedResources>
- <filteredResources>
- <filter>
- <id>1539639053206</id>
- <name>ext/commands</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639053211</id>
- <name>ext/commands</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639053214</id>
- <name>ext/commands</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639034966</id>
- <name>ext/computation_graph</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639034970</id>
- <name>ext/computation_graph</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639034973</id>
- <name>ext/computation_graph</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639011807</id>
- <name>ext/graph_blocks</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639011810</id>
- <name>ext/graph_blocks</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539639011815</id>
- <name>ext/graph_blocks</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539638989698</id>
- <name>ext/quad_app</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539638989701</id>
- <name>ext/quad_app</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539638989706</id>
- <name>ext/quad_app</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539638949606</id>
- <name>ext/queue</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.c</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539638949607</id>
- <name>ext/queue</name>
- <type>10</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1539638949610</id>
- <name>ext/queue</name>
- <type>5</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
- </matcher>
- </filter>
- </filteredResources>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/real_quad/.settings/org.eclipse.cdt.codan.core.prefs b/quad/xsdk_workspace_vivado/real_quad/.settings/org.eclipse.cdt.codan.core.prefs
deleted file mode 100644
index 8e0550446a2bb045d01a9f8b73d47305f777665c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/.settings/org.eclipse.cdt.codan.core.prefs
+++ /dev/null
@@ -1,34 +0,0 @@
-eclipse.preferences.version=1
-org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
-org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
-org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false}
-org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true}
-org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
-org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
-org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
-org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
diff --git a/quad/xsdk_workspace_vivado/real_quad/README.md b/quad/xsdk_workspace_vivado/real_quad/README.md
deleted file mode 100644
index 88089fe73a20d66069f58a28385db78db8ebed51..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/README.md
+++ /dev/null
@@ -1,10 +0,0 @@
-# The Real Quad
-_It is real, because it flies._
-
-Welcome to the most lame README in MicroCART. Everything we are about to say
-has already been said elsewhere, including [Our quad folder README][1], [xsdk_workspace README][2], and [HOW_TO_USE_XSDK markdown][3].
-So we aren't saying it here. Hence, this README is pretty empty. Hence... lame.
-
-[1]: ../README.md
-[2]: ../../README.md
-[3]: ../../doc/how_to_use_XSDK.md
diff --git a/quad/xsdk_workspace_vivado/real_quad/ext/__CAUTION__.md b/quad/xsdk_workspace_vivado/real_quad/ext/__CAUTION__.md
deleted file mode 100644
index 6f7e2a00feb6d7083997b71389dcad6b36a0d616..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/ext/__CAUTION__.md
+++ /dev/null
@@ -1,12 +0,0 @@
-****************************************
- Do not edit files in this directory!
-****************************************
-
-The fine print
-----
-
-Files in this directory are simlinked to external libraries. They exist here
-purely to help fascilitate the build process and permit debugging of those
-libraries within XSDK. Editing them here might build within XSDK, but it might
-break in its original context. Hence, don't edit these files within XSDK. Edit
-them within a workflow that uses the Makefile in the top-level quad folder.
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
deleted file mode 100644
index df4cd13a3180ba7fe76c125cc8a72ce89e9aaa8c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
+++ /dev/null
@@ -1,116 +0,0 @@
-#include "hw_impl_zybo.h"
-
-struct UARTDriver create_zybo_uart(int devId) {
- struct UARTDriver uart;
- uart.state = malloc(sizeof(struct ZyboUARTState));
- struct ZyboUARTState *state = uart.state;
- state->inst = malloc(sizeof(XUartPs));
- state->queue = queue_malloc(MAX_UART_BUFFER_SIZE);
- state->devId = devId;
-
- uart.reset = zybo_uart_reset;
- uart.write = zybo_uart_write;
- uart.read = zybo_uart_read;
- return uart;
-}
-
-struct GPSDriver create_zybo_gps(struct UARTDriver *uart) {
- struct GPSDriver gps;
- gps.uart = uart;
- gps.reset = zybo_gps_reset;
- gps.read = zybo_gps_read;
- return gps;
-}
-
-struct CommDriver create_zybo_comm(struct UARTDriver *uart) {
- struct CommDriver comm;
- comm.uart = uart;
- return comm;
-}
-
-struct MotorDriver create_zybo_motors() {
- struct MotorDriver motors;
- motors.state = NULL;
- motors.reset = zybo_motor_reset;
- motors.write = zybo_motor_write;
- return motors;
-}
-
-struct RCReceiverDriver create_zybo_rc_receiver() {
- struct RCReceiverDriver rc_receiver;
- rc_receiver.state = NULL;
- rc_receiver.reset = zybo_rc_receiver_reset;
- rc_receiver.read = zybo_rc_receiver_read;
- return rc_receiver;
-}
-
-struct I2CDriver create_zybo_i2c(int busId) {
- struct I2CDriver i2c;
- i2c.state = malloc(sizeof(struct ZyboI2CState));
- struct ZyboI2CState *state = i2c.state;
- state->inst = malloc(sizeof(XIicPs));
- state->busId = busId;
- i2c.reset = zybo_i2c_reset;
- i2c.write = zybo_i2c_write;
- i2c.read = zybo_i2c_read;
- return i2c;
-}
-
-struct TimerDriver create_zybo_global_timer() {
- struct TimerDriver global_timer;
- global_timer.state = NULL;
- global_timer.reset = zybo_global_timer_reset;
- global_timer.restart = zybo_global_timer_restart;
- global_timer.read = zybo_global_timer_read;
- return global_timer;
-}
-
-struct TimerDriver create_zybo_axi_timer() {
- struct TimerDriver axi_timer;
- axi_timer.state = NULL;
- axi_timer.reset = zybo_axi_timer_reset;
- axi_timer.restart = zybo_axi_timer_restart;
- axi_timer.read = zybo_axi_timer_read;
- return axi_timer;
-}
-
-struct LEDDriver create_zybo_mio7_led() {
- struct LEDDriver mio7_led;
- mio7_led.state = NULL;
- mio7_led.reset = zybo_mio7_led_reset;
- mio7_led.turn_on = zybo_mio7_led_turn_on;
- mio7_led.turn_off = zybo_mio7_led_turn_off;
- return mio7_led;
-}
-
-struct SystemDriver create_zybo_system() {
- struct SystemDriver sys;
- sys.state = NULL;
- sys.reset = zybo_system_reset;
- sys.sleep = zybo_system_sleep;
- return sys;
-}
-
-struct IMUDriver create_zybo_imu(struct I2CDriver *i2c) {
- struct IMUDriver imu;
- imu.i2c = i2c;
- imu.reset = zybo_imu_reset;
- imu.read = zybo_imu_read;
- return imu;
-}
-
-struct LidarDriver create_zybo_lidar(struct I2CDriver *i2c) {
- struct LidarDriver lidar;
- lidar.i2c = i2c;
- lidar.reset = zybo_lidar_reset;
- lidar.read = zybo_lidar_read;
- return lidar;
-}
-
-struct OpticalFlowDriver create_zybo_optical_flow(struct I2CDriver *i2c) {
- struct OpticalFlowDriver of;
- of.i2c = i2c;
- of.reset = zybo_optical_flow_reset;
- of.read = zybo_optical_flow_read;
- return of;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
deleted file mode 100644
index 5555a4adf8d527bd30b1d2837b3884e929f001d9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef HW_IMPL_ZYBO
-#define HW_IMPL_ZYBO
-
-#include "hw_iface.h"
-
-#include <sleep.h>
-#include <stdlib.h>
-#include <xtmrctr.h>
-#include <xgpiops.h>
-#include "xiicps.h"
-#include "xparameters.h"
-#include "xgpiops.h"
-#include "xil_types.h"
-#include "xscugic.h"
-#include "xtime_l.h"
-#include "xuartps.h"
-#include "queue.h"
-#include "platform.h"
-#include "sleep.h"
-#include "type_def.h"
-
-// Ideally, these defines would only be in the optical flow file, but
-// i2c needs it for a certain hack
-#define PX4FLOW_DEVICE_ADDR 0x42
-#define PX4FLOW_QUAL_MIN (100)
-
-#define MAX_UART_BUFFER_SIZE 2048
-
-#define QUAD_NUM 1
-
-#if QUAD_NUM==0
-#define IMU_ACCX_SIGN -1
-#define IMU_ACCY_SIGN 1
-#define IMU_ACCZ_SIGN 1
-
-#define IMU_GYRX_SIGN -1
-#define IMU_GYRY_SIGN 1
-#define IMU_GYRZ_SIGN 1
-
-
-#define MOTOR_FRONTLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR
-#define MOTOR_FRONTRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR
-#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
-#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
-
-#define ACCEL_X_BIAS 0.08f
-#define ACCEL_Y_BIAS -0.057f
-#define ACCEL_Z_BIAS 0.0f
-
-#define GYRO_X_BIAS -0.006f
-#define GYRO_Y_BIAS 0.0545f
-#define GYRO_Z_BIAS 0.005//0.0541f
-
-#endif
-
-#if QUAD_NUM==1
-
-#define IMU_ACCX_SIGN 1
-#define IMU_ACCY_SIGN 1
-#define IMU_ACCZ_SIGN 1
-
-#define IMU_GYRX_SIGN 1
-#define IMU_GYRY_SIGN 1
-#define IMU_GYRZ_SIGN 1
-
-
-#define MOTOR_FRONTLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR
-#define MOTOR_FRONTRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR
-#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
-#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
-
-#define ACCEL_X_BIAS -0.01f
-#define ACCEL_Y_BIAS 0.041f
-#define ACCEL_Z_BIAS 0.0f
-
-#define GYRO_X_BIAS -0.024f
-#define GYRO_Y_BIAS -0.013f
-#define GYRO_Z_BIAS 0.02//0.0541f
-
-#endif
-
-struct ZyboI2CState {
- XIicPs *inst;
- int busId;
-};
-
-struct ZyboUARTState {
- struct Queue *queue;
- XUartPs *inst;
- XScuGic xscugic;
- int devId;
-};
-
-int zybo_uart_reset(struct UARTDriver *self);
-int zybo_uart_write(struct UARTDriver *self, unsigned char c);
-int zybo_uart_read(struct UARTDriver *self, unsigned char *c);
-
-int zybo_motor_reset(struct MotorDriver *self);
-int zybo_motor_write(struct MotorDriver *self, unsigned int channel, float magnitude);
-
-int zybo_rc_receiver_reset(struct RCReceiverDriver *self);
-int zybo_rc_receiver_read(struct RCReceiverDriver *self, unsigned int channel, float *magnitude);
-
-int zybo_i2c_reset(struct I2CDriver *self);
-int zybo_i2c_write(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *data,
- unsigned int length);
-int zybo_i2c_read(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *buff,
- unsigned int length);
-
-int zybo_global_timer_reset(struct TimerDriver *self);
-int zybo_global_timer_restart(struct TimerDriver *self);
-int zybo_global_timer_read(struct TimerDriver *self, u64 *us);
-
-int zybo_axi_timer_reset(struct TimerDriver *self);
-int zybo_axi_timer_restart(struct TimerDriver *self);
-int zybo_axi_timer_read(struct TimerDriver *self, u64 *us);
-
-int zybo_mio7_led_reset(struct LEDDriver *self);
-int zybo_mio7_led_turn_on(struct LEDDriver *self);
-int zybo_mio7_led_turn_off(struct LEDDriver *self);
-
-int zybo_system_reset(struct SystemDriver *self);
-int zybo_system_sleep(struct SystemDriver *self, unsigned long us);
-
-int zybo_imu_reset(struct IMUDriver *self, struct gam *gam);
-int zybo_imu_read(struct IMUDriver *self, struct gam *gam);
-
-int zybo_lidar_reset(struct LidarDriver *self, struct lidar *lidar);
-int zybo_lidar_read(struct LidarDriver *self, struct lidar *lidar);
-
-int zybo_optical_flow_reset(struct OpticalFlowDriver *self, struct px4flow *of);
-int zybo_optical_flow_read(struct OpticalFlowDriver *self, struct px4flow *of);
-
-int zybo_gps_reset(struct GPSDriver *self, gps_t *gps);
-int zybo_gps_read(struct GPSDriver *self, gps_t *gps);
-
-struct UARTDriver create_zybo_uart(int devId);
-struct CommDriver create_zybo_comm(struct UARTDriver *uart);
-struct GPSDriver create_zybo_gps(struct UARTDriver *uart);
-struct MotorDriver create_zybo_motors();
-struct RCReceiverDriver create_zybo_rc_receiver();
-struct I2CDriver create_zybo_i2c(int busId);
-struct TimerDriver create_zybo_global_timer();
-struct TimerDriver create_zybo_axi_timer();
-struct LEDDriver create_zybo_mio7_led();
-struct SystemDriver create_zybo_system();
-struct IMUDriver create_zybo_imu(struct I2CDriver *i2c);
-struct LidarDriver create_zybo_lidar(struct I2CDriver *i2c);
-struct OpticalFlowDriver create_zybo_optical_flow(struct I2CDriver *i2c);
-
-int test_zybo_i2c();
-int test_zybo_mio7_led_and_system();
-int test_zybo_rc_receivers();
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_axi_timer.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_axi_timer.c
deleted file mode 100644
index fa4bb05a6a5bb0bea2167446297a9a29c0b6b9ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_axi_timer.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define PL_CLK_CNTS_PER_USEC 100
-
-int zybo_axi_timer_reset(struct TimerDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(XTmrCtr));
- }
- return XTmrCtr_Initialize(self->state, XPAR_AXI_TIMER_0_DEVICE_ID);
-}
-
-int zybo_axi_timer_restart(struct TimerDriver *self) {
- XTmrCtr_Reset(self->state, 0);
- XTmrCtr_Start(self->state, 0);
- return 0;
-}
-
-int zybo_axi_timer_read(struct TimerDriver *self, u64 *us) {
- // Returns the number of useconds
- *us = XTmrCtr_GetValue(self->state, 0) / PL_CLK_CNTS_PER_USEC;
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_global_timer.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_global_timer.c
deleted file mode 100644
index c1024a62f57e9e16eda073268e991012973ec35b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_global_timer.c
+++ /dev/null
@@ -1,18 +0,0 @@
-#include "hw_impl_zybo.h"
-
-int zybo_global_timer_reset(struct TimerDriver *self) {
- // Nothing to initialize
- return 0;
-}
-
-int zybo_global_timer_restart(struct TimerDriver *self) {
- XTime_SetTime(0);
- return 0;
-}
-
-int zybo_global_timer_read(struct TimerDriver *self, u64 *us) {
- XTime time;
- XTime_GetTime(&time);
- *us = ((u64)time * 1000000) / COUNTS_PER_SECOND; // (ticks)(1000000us/s)(s/ticks)
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_gps.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_gps.c
deleted file mode 100644
index ff495afdbc2a597e3e2ca9ba89343cefeee6ed09..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_gps.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-
-int zybo_gps_reset(struct GPSDriver *self, gps_t *gps) {
- // TODO
- return -1;
-}
-
-int zybo_gps_read(struct GPSDriver *self, gps_t *gps) {
- // TODO
- return -1;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_i2c.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_i2c.c
deleted file mode 100644
index 751ae4ccf5bbc741def8cea9ea0e555be8f230f0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_i2c.c
+++ /dev/null
@@ -1,485 +0,0 @@
-#include "hw_impl_zybo.h"
-#include "xiicps.h"
-// System configuration registers
-// (Please see Appendix B: System Level Control Registers in the Zybo TRM)
-#define IIC_SYSTEM_CONTROLLER_RESET_REG_ADDR (0xF8000224)
-#define IO_CLK_CONTROL_REG_ADDR (0xF800012C)
-
-// Error code could be returned on an iic read if the watchdog timer triggers
-#define IIC_RX_TIMEOUT_FAILURE (-88)
-/*
-// IIC0 Registers
-#define IIC0_CONTROL_REG_ADDR (0xE0004000)
-#define IIC0_STATUS_REG_ADDR (0xE0004004)
-#define IIC0_SLAVE_ADDR_REG (0xE0004008)
-#define IIC0_DATA_REG_ADDR (0xE000400C)
-#define IIC0_INTR_STATUS_REG_ADDR (0xE0004010)
-#define IIC0_TRANFER_SIZE_REG_ADDR (0xE0004014)
-#define IIC0_INTR_EN (0xE0004024)
-#define IIC0_TIMEOUT_REG_ADDR (0xE000401C)
-*/
-//Interrupt Status Register Masks
-#define ARB_LOST (0x200)
-#define RX_UNF (0x80)
-#define TX_OVF (0x40)
-#define RX_OVF (0x20)
-#define SLV_RDY (0x10)
-#define TIME_OUT (0x08)
-#define NACK (0x04)
-#define MORE_DAT (0x02)
-#define TRANS_COMPLETE (0x01)
-
-#define WRITE_INTR_MASK (ARB_LOST | TIME_OUT | RX_OVF | TX_OVF | NACK)
-#define READ_INTR_MASK (ARB_LOST | TIME_OUT | RX_OVF | RX_UNF | NACK)
-
-#define IO_CLK_CONTROL_REG_ADDR (0xF800012C)
-#define I2C0_CPU_1XCLKACT (0x00040000)
-#define I2C1_CPU_1XCLKACT (0x00080000)
-
-int XIicPs_MasterSendPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr);
-int XIicPs_MasterRecvPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr);
-int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role);
-
-int zybo_i2c_reset(struct I2CDriver *self) {
- // ensure all required memory is allocated
- struct ZyboI2CState *state = self->state;
- if (state == NULL) return -1;
- if (state->inst == NULL) return -1;
- if (state->busId > 1) return -1;
- int i2cID = state->busId;
- XIicPs *inst = state->inst;
-
- //Make sure CPU_1x clk is enabled fostatusr I2C controller
- u16 *aper_ctrl = (u16 *) IO_CLK_CONTROL_REG_ADDR;
- u32 aper_mask = (i2cID == 0) ? (I2C0_CPU_1XCLKACT) : (I2C1_CPU_1XCLKACT);
-
- if (*aper_ctrl & aper_mask){
- xil_printf("CPU_1x is set to I2C0\r\n");
- }
-
- else {
- xil_printf("CPU_1x is not set to I2C..Setting now\r\n");
- *aper_ctrl |= aper_mask;
- }
-
- // Look up
- XIicPs_Config *i2c_config = XIicPs_LookupConfig(i2cID);
- XStatus status = XIicPs_CfgInitialize(inst, i2c_config, i2c_config->BaseAddress);
-
- // Check if initialization was successful
- if(status != XST_SUCCESS){
- return -1;
- }
-
- // Reset the controller and set the clock to 400kHz
- XIicPs_Reset(inst);
- XIicPs_SetSClk(inst, 400000);
-
- return 0;
-}
-
-int zybo_i2c_write(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *data,
- unsigned int length) {
- struct ZyboI2CState *state = self->state;
- XIicPs *inst = state->inst;
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // If we are sending a request to optical flow, drop down to 100kHz
- XIicPs_SetSClk(inst, 100000);
- }
- int error = XIicPs_MasterSendPolled_ours(inst, data, length, device_addr);
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // Put it back to 400kHz
- XIicPs_SetSClk(inst, 400000);
- }
- usleep(5);
- return error;
-}
-
-int zybo_i2c_read(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *buff,
- unsigned int length) {
- struct ZyboI2CState *state = self->state;
- XIicPs *inst = state->inst;
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // If we are sending a request to optical flow, drop down to 100kHz
- XIicPs_SetSClk(inst, 100000);
- }
- int error = XIicPs_MasterRecvPolled_ours(inst, buff, length, device_addr);
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // Put it back to 400kHz
- XIicPs_SetSClk(inst, 400000);
- }
- usleep(5);
- return error;
-}
-
-/*****************************************************************************/
-/**
-* NOTE to MicroCART: This function is originally from the Xilinx library,
-* but we noticed that the original function didn't check for a NACK, which
-* would cause the original polling function to enter an infinite loop in the
-* event of a NACK. Notice that we have added that NACK check at the final
-* while loop of this function.
-*
-*
-* This function initiates a polled mode send in master mode.
-*u16 i2cID
-* It sends data to the FIFO and waits for the slave to pick them up.
-* If slave fails to remove data from FIFO, the send fails with
-* time out.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the send buffer.
-* @param ByteCount is the number of bytes to be sent.
-* @param SlaveAddr is the address of the slave we are sending to.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This send routine is for polled mode transfer only.
-*
-****************************************************************************/
-int XIicPs_MasterSendPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr)
-{
- u32 IntrStatusReg;
- u32 StatusReg;
- u32 BaseAddr;
- u32 Intrs;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->SendBufferPtr = MsgPtr;
- InstancePtr->SendByteCount = ByteCount;
-
- XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- /*
- * Intrs keeps all the error-related interrupts.
- */
- Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TX_OVR_MASK |
- XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK;
-
- /*
- * Clear the interrupt status register before use it to monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Transmit first FIFO full of data.
- */
- TransmitFifoFill(InstancePtr);
-
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-
- /*
- * Continue sending as long as there is more data and
- * there are no errors.
- */
- while ((InstancePtr->SendByteCount > 0) &&
- ((IntrStatusReg & Intrs) == 0)) {
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * Wait until transmit FIFO is empty.
- */
- if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- continue;
- }
-
- /*
- * Send more data out through transmit FIFO.
- */
- TransmitFifoFill(InstancePtr);
- }
-
- /*
- * Check for completion of transfer.
- */
- // NOTE for MicroCART: Corrected function. Original left for reference.
-// while ((XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET) &
-// XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK);
- while (!(IntrStatusReg & (Intrs | XIICPS_IXR_COMP_MASK))) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- }
-
- /*
- * If there is an error, tell the caller.
- */
- if (IntrStatusReg & Intrs) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-static XTime get_time() {
- XTime time;
- XTime_GetTime(&time);
- u64 us = (u64)time * (1000000 / COUNTS_PER_SECOND); // (ticks)(1000000us/s)(s/ticks)
- return us;
-}
-
-/*****************************************************************************/
-/**
-* This function initiates a polled mode receive in master mode.
-*
-* It repeatedly sets the transfer size register so the slave can
-* send data to us. It polls the data register for data to come in.
-* If slave fails to send us data, it fails with time out.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the receive buffer.
-* @param ByteCount is the number of bytes to be received.
-* @param SlaveAddr is the address of the slave we are receiving from.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This receive routine is for polled mode transfer only.
-*
-****************************************************************************/
-int XIicPs_MasterRecvPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr)
-{
- u32 IntrStatusReg;
- u32 Intrs;
- u32 StatusReg;
- u32 BaseAddr;
- int BytesToRecv;
- int BytesToRead;
- int TransSize;
- int Tmp;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->RecvBufferPtr = MsgPtr;
- InstancePtr->RecvByteCount = ByteCount;
-
- XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- /*
- * Intrs keeps all the error-related interrupts.
- */
- Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_OVR_MASK |
- XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TO_MASK |
- XIICPS_IXR_NACK_MASK;
-
- /*
- * Clear the interrupt status register before use it to monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Set up the transfer size register so the slave knows how much
- * to send to us.
- */
- if (ByteCount > XIICPS_FIFO_DEPTH) {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_FIFO_DEPTH);
- }else {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- ByteCount);
- }
-
-/* <--- MicroCART additions (iic watchdog timer hack) ---> */
- u32 iic_freq = XIicPs_GetSClk(InstancePtr);
- // (1000000 * 9 / iic_freq) is the number of microseconds required to send 1 byte of data
- // Using 5 times as an upper bound
- u32 max_usec_per_byte = 5 * 1000000 * 9 / iic_freq;
- u64 start_time = get_time();
-/* <--- End hack ---> */
-
- /*
- * Pull the interrupt status register to find the errors.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- while ((InstancePtr->RecvByteCount > 0) &&
- ((IntrStatusReg & Intrs) == 0) && !(IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
-/* <--- MicroCART additions (iic watchdog timer hack) ---> */
- u64 usec_passed = get_time() - start_time;
- // Add 1 so it has a chance to read
- if (usec_passed > max_usec_per_byte * (1 + ByteCount - InstancePtr->RecvByteCount)) {
- return IIC_RX_TIMEOUT_FAILURE;
- }
-/* <--- End hack ---> */
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * If there is no data in the FIFO, check the interrupt
- * status register for error, and continue.
- */
- if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- continue;
- }
-
- /*
- * The transfer size register shows how much more data slave
- * needs to send to us.
- */
- TransSize = XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET);
-
- BytesToRead = InstancePtr->RecvByteCount;
-
- /*
- * If expected number of bytes is greater than FIFO size,
- * the master needs to wait for data comes in and set the
- * transfer size register for slave to send more.
- */
- if (InstancePtr->RecvByteCount > XIICPS_FIFO_DEPTH) {
- /* wait slave to send data */
- while ((TransSize > 2) &&
- ((IntrStatusReg & Intrs) == 0)) {
- TransSize = XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET);
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- }
-
- /*
- * If timeout happened, it is an error.
- */
- if (IntrStatusReg & XIICPS_IXR_TO_MASK) {
- return XST_FAILURE;
- }
- TransSize = XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET);
-
- /*
- * Take trans size into account of how many more should
- * be received.
- */
- BytesToRecv = InstancePtr->RecvByteCount -
- XIICPS_FIFO_DEPTH + TransSize;
-
- /* Tell slave to send more to us */
- if (BytesToRecv > XIICPS_FIFO_DEPTH) {
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_FIFO_DEPTH);
- } else{
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET, BytesToRecv);
- }
-
- BytesToRead = XIICPS_FIFO_DEPTH - TransSize;
- }
-
- Tmp = 0;
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- while ((Tmp < BytesToRead) &&
- ((IntrStatusReg & Intrs) == 0)) {
- StatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_SR_OFFSET);
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
-
- if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
- /* No data in fifo */
- continue;
- }
- XIicPs_RecvByte(InstancePtr);
- Tmp ++;
- }
- }
-
- if ((IntrStatusReg & Intrs) || InstancePtr->RecvByteCount > 0) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/*
-* NOTE to MicroCART: This function is required by the send polling method above,
-* but it was originally static, so we had to copy it word-for-word here.
-*
-* This function prepares a device to transfers as a master.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @param Role specifies whether the device is sending or receiving.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if bus is busy.
-*
-* @note Interrupts are always disabled, device which needs to use
-* interrupts needs to setup interrupts after this call.
-*
-****************************************************************************/
-int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
-{
- u32 ControlReg;
- u32 BaseAddr;
- u32 EnabledIntr = 0x0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
-
-
- /*
- * Only check if bus is busy when repeated start option is not set.
- */
- if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
- if (XIicPs_BusIsBusy(InstancePtr)) {
- return XST_FAILURE;
- }
- }
-
- /*
- * Set up master, AckEn, nea and also clear fifo.
- */
- ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK |
- XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK;
-
- if (Role == RECVING_ROLE) {
- ControlReg |= XIICPS_CR_RD_WR_MASK;
- EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK;
- }else {
- ControlReg &= ~XIICPS_CR_RD_WR_MASK;
- }
- EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK;
-
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
-
- XIicPs_DisableAllInterrupts(BaseAddr);
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
deleted file mode 100644
index 5cf36172d7440dd44057acf6ad1c62026d0e56a8..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
+++ /dev/null
@@ -1,281 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-#include "type_def.h"
-
-#include <string.h>
-
-#define MPU9150_DEVICE_ADDR 0b01101000
-#define MPU9150_COMPASS_ADDR 0x0C
-
-#define ACCEL_GYRO_READ_SIZE 14 //Bytes
-#define ACCEL_GYRO_BASE_ADDR 0x3B //Starting register address
-
-#define MAG_READ_SIZE 6
-#define MAG_BASE_ADDR 0x03
-
-#define MAG_DRDY_TIMEOUT (10)
-
-#define RAD_TO_DEG 57.29578
-#define DEG_TO_RAD 0.0174533
-
-// Array indicies when reading from ACCEL_GYRO_BASE_ADDR
-#define ACC_X_H 0
-#define ACC_X_L 1
-#define ACC_Y_H 2
-#define ACC_Y_L 3
-#define ACC_Z_H 4
-#define ACC_Z_L 5
-
-#define GYR_X_H 8
-#define GYR_X_L 9
-#define GYR_Y_H 10
-#define GYR_Y_L 11
-#define GYR_Z_H 12
-#define GYR_Z_L 13
-
-#define MAG_X_L 0
-#define MAG_X_H 1
-#define MAG_Y_L 2
-#define MAG_Y_H 3
-#define MAG_Z_L 4
-#define MAG_Z_H 5
-
-// Gyro is configured for +/-2000dps
-// Sensitivity gain is based off MPU9150 datasheet (pg. 11)
-#define GYRO_SENS 16.4
-
-int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
-int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
-
-int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam);
-int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam);
-int mpu9150_read_gyro_accel(gam_t* gam);
-
-int zybo_imu_reset(struct IMUDriver *self, gam_t *gam) {
- memset(gam, 0, sizeof(gam_t));
-
- struct I2CDriver *i2c = self->i2c;
-
- // Device Reset & Wake up
- mpu9150_write(i2c, 0x6B, 0x80);
- usleep(5000);
-
- // Set clock reference to Z Gyro
- mpu9150_write(i2c, 0x6B, 0x03);
- // Configure Digital Low/High Pass filter
- mpu9150_write(i2c, 0x1A,0x03); // Level 3 low pass on gyroscope
-
- // Configure Gyro to 2000dps, Accel. to +/-8G
- mpu9150_write(i2c, 0x1B, 0x18);
- mpu9150_write(i2c, 0x1C, 0x10);
-
- // Enable I2C bypass for AUX I2C (Magnetometer)
- mpu9150_write(i2c, 0x37, 0x02);
-
- usleep(100000);
-
- //Calculate magnetometer sensitivities
- mpu9150_calc_mag_sensitivity(self, gam);
-
- usleep(10000);
-
- //Enable single measurement mode
- mpu9150_write(i2c, 0x0A, 0x00);
- mpu9150_write(i2c, 0x0A, 0x01);
-
- int i;
-
- // Do about 20 reads to warm up the device
- for(i=0; i < 20; ++i){
- self->read(self, gam);
- usleep(1000);
- }
-
- return 0;
-}
-
-int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
- u8 buf[3];
- u8 ASAX, ASAY, ASAZ;
-
- // Quickly read from the factory ROM to get correction coefficients
- int status = mpu9150_write(self->i2c, 0x0A, 0x1F);
- if(status != 0) {
- return status;
- }
-
- usleep(10000);
-
- // Read raw adjustment values
- status = mpu9150_read(self->i2c, buf, 0x10,3);
- if(status != 0) {
- return status;
- }
- ASAX = buf[0];
- ASAY = buf[1];
- ASAZ = buf[2];
-
- // Set the correction coefficients
- gam->magX_correction = (ASAX-128)*0.5/128 + 1;
- gam->magY_correction = (ASAY-128)*0.5/128 + 1;
- gam->magZ_correction = (ASAZ-128)*0.5/128 + 1;
-
- return 0;
-}
-
-int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
- struct I2CDriver *i2c = self->i2c;
- i16 raw_accel_x, raw_accel_y, raw_accel_z;
- i16 sensor_raw_accel_x, sensor_raw_accel_y, sensor_raw_accel_z;
- i16 gyro_x, gyro_y, gyro_z;
- i16 sensor_gyro_x, sensor_gyro_y, sensor_gyro_z;
-
- u8 sensor_data[ACCEL_GYRO_READ_SIZE] = {};
-
- int error = mpu9150_read(i2c, sensor_data, ACCEL_GYRO_BASE_ADDR, ACCEL_GYRO_READ_SIZE);
- if (error) return error;
-
- //Calculate accelerometer data
- sensor_raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
- sensor_raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
- sensor_raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
-
- // TODO: Update Matlab model with correct directions.
- raw_accel_x = sensor_raw_accel_y;
- raw_accel_y = -sensor_raw_accel_x;
- raw_accel_z = sensor_raw_accel_z;
-// raw_accel_x = sensor_raw_accel_y;
-// raw_accel_y = sensor_raw_accel_x;
-// raw_accel_z = sensor_raw_accel_z;
-
- // put in G's
- gam->accel_x = IMU_ACCX_SIGN * (raw_accel_x / 4096.0) + ACCEL_X_BIAS; // 4,096 is the gain per LSB of the measurement reading based on a configuration range of +-8g
- gam->accel_y = IMU_ACCY_SIGN * (raw_accel_y / 4096.0) + ACCEL_Y_BIAS;
- gam->accel_z = IMU_ACCZ_SIGN * (raw_accel_z / 4096.0) + ACCEL_Z_BIAS;
-
- //Convert gyro data to rate (we're only using the most 12 significant bits)
- sensor_gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
- sensor_gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
- sensor_gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
-
- //remap
- gyro_x = sensor_gyro_y;
- gyro_y = -sensor_gyro_x;
- gyro_z = sensor_gyro_z;
-// gyro_x = sensor_gyro_y;
-// gyro_y = sensor_gyro_x;
-// gyro_z = sensor_gyro_z;
-
- //Get the number of degrees
- //javey: converted to radians to following SI units
- gam->gyro_xVel_p = IMU_GYRX_SIGN * ((gyro_x / GYRO_SENS) * DEG_TO_RAD) + GYRO_X_BIAS;
- gam->gyro_yVel_q = IMU_GYRY_SIGN * ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
- gam->gyro_zVel_r = IMU_GYRZ_SIGN * ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
-
- // Magnometer
- mpu9150_read_mag(self, gam);
-
- return error;
-}
-
-//////////////////////
-// Helper functions
-/////////////////////
-
-int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data){
-
- u16 device_addr = MPU9150_DEVICE_ADDR;
- u8 buf[] = {register_addr, data};
-
- // Check if within register range
- if(register_addr < 0 || register_addr > 0x75){
- return -1;
- }
-
- if(register_addr <= 0x12){
- device_addr = MPU9150_COMPASS_ADDR;
- }
-
- return i2c->write(i2c, device_addr, buf, 2);
-}
-
-int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size){
-
- u16 device_addr = MPU9150_DEVICE_ADDR;
- u8 buf[] = {register_addr};
-
- // Check if within register range
- if(register_addr < 0 || register_addr > 0x75){
- }
-
- // Set device address to the if 0x00 <= register address <= 0x12
- if(register_addr <= 0x12){
- device_addr = MPU9150_COMPASS_ADDR;
- }
-
-
- int error = i2c->write(i2c, device_addr, buf, 1);
- if (error) return error;
- return i2c->read(i2c, device_addr, recv_buffer, size);
-}
-
-
-int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
- u8 mag_data[6];
- u8 mag_status;
- i16 raw_magX, raw_magY, raw_magZ;
- i16 sensor_raw_magX, sensor_raw_magY, sensor_raw_magZ;
-
- int trigger = 0;
-
- int status = mpu9150_read(self->i2c, mag_data, 0x02, 1);
- if(status != 0) {
- return status;
- }
-
- if(mag_data[0] & 0x01) {
- // Get mag data
- status = mpu9150_read(self->i2c, mag_data, 0x03, 6);
- if(status != 0) {
- return status;
- }
-
- status = mpu9150_read(self->i2c, &mag_status, 0x09, 1);
- if(status != 0) {
- return status;
- }
-
- sensor_raw_magX = (mag_data[1] << 8) | mag_data[0];
- sensor_raw_magY = (mag_data[3] << 8) | mag_data[2];
- sensor_raw_magZ = (mag_data[5] << 8) | mag_data[4];
-
- //remap
- raw_magX = -sensor_raw_magY;
- raw_magY = sensor_raw_magX;
- raw_magZ = sensor_raw_magZ;
-
- // Set magnetometer data to output
- gam->mag_x = raw_magX * gam->magX_correction;
- gam->mag_y = raw_magY * gam->magY_correction;
- gam->mag_z = raw_magZ * gam->magZ_correction;
-
- trigger = 1;
- }
- else {
- gam->magDRDYCount++;
-
- if(gam->magDRDYCount > MAG_DRDY_TIMEOUT) {
- gam->magDRDYCount = 0;
-
- trigger = 1;
- }
- }
-
- if(trigger) {
- //Start next reading
- mpu9150_write(self->i2c, 0x0A, 0x00);
- mpu9150_write(self->i2c, 0x0A, 0x01);
- }
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c
deleted file mode 100644
index 62caca7532156520b9cd8a05df605de7bd18d123..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c
+++ /dev/null
@@ -1,70 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-#include "type_def.h"
-#include <string.h>
-
-#define LIDARLITE_DEVICE_ADDR 0x62
-#define LIDAR_OFFSET (0.016666) // Distance from LiDAR sensor to ground, in meters
-
-int lidarlite_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
-int lidarlite_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
-
-int zybo_lidar_reset(struct LidarDriver *self, lidar_t *lidar) {
- // initialize lidar
- memset(lidar, 0, sizeof(lidar_t));
-
- struct I2CDriver *i2c = self->i2c;
-
- int error = 0;
- //Device wakeup if asleep.
- lidarlite_write(i2c, 0x00, 0x00);
- usleep(15000);
- // Device Reset & Wake up with default settings
- error = lidarlite_write(i2c, 0x00, 0x00);
- if (error) return error;
- usleep(15000);
-
- // Enable Free Running Mode and distance measurements with correction
- error = lidarlite_write(i2c, 0x11, 0xff);
- if (error) return error;
- error = lidarlite_write(i2c, 0x00, 0x04);
- return error;
-}
-
-int zybo_lidar_read(struct LidarDriver *self, lidar_t *lidar) {
- struct I2CDriver *i2c = self->i2c;
- u8 buf[2];
- int error = 0;
-
- // Read the sensor value
- error = lidarlite_read(i2c, buf, 0x8f, 2);
- if (error) return error;
- float distance_cm = (float)(buf[0] << 8 | buf[1]);
- lidar->distance_m = (distance_cm * 0.01) + LIDAR_OFFSET;
-
- return error;
-}
-
-////////////////////
-// Helper functions
-////////////////////
-
-int lidarlite_write(struct I2CDriver *i2c, u8 register_addr, u8 data) {
- u8 buf[] = {register_addr, data};
- return i2c->write(i2c, LIDARLITE_DEVICE_ADDR, buf, 2);
-}
-
-int lidarlite_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size) {
- u8 buf[] = {register_addr};
- int error = 0;
-
- error = i2c->write(i2c, LIDARLITE_DEVICE_ADDR, buf, 1);
- if (error) return error;
- error = i2c->read(i2c, LIDARLITE_DEVICE_ADDR, recv_buffer, size);
- return error;
-}
-
-// Maybe this will be useful?
-int lidarlite_sleep(struct I2CDriver *i2c) {
- return lidarlite_write(i2c, 0x65, 0x84);
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_mio7_led.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_mio7_led.c
deleted file mode 100644
index 03a192671114b7e0cbf224b84fbb4c0752bbcd97..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_mio7_led.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include "hw_impl_zybo.h"
-
-int zybo_mio7_led_reset(struct LEDDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(XGpioPs));
- }
-
- XGpioPs_Config *ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
- XGpioPs_CfgInitialize(self->state, ConfigPtr, ConfigPtr->BaseAddr);
- XGpioPs_SetDirectionPin(self->state, 7, 1);
- return 0;
-}
-
-int zybo_mio7_led_turn_on(struct LEDDriver *self) {
- XGpioPs_WritePin(self->state, 7, 0x01);
- return 0;
-}
-
-int zybo_mio7_led_turn_off(struct LEDDriver *self) {
- XGpioPs_WritePin(self->state, 7, 0x00);
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c
deleted file mode 100644
index 869bb7973be25a2cc2e004c02a900b339949a46a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define SYS_CLOCK_RATE 100000000 // ticks per second
-#define FREQUENCY 450
-#define PERIOD_WIDTH SYS_CLOCK_RATE/FREQUENCY
-#define PULSE_WIDTH_LOW SYS_CLOCK_RATE/1000 // 1 ms
-#define PULSE_WIDTH_HIGH SYS_CLOCK_RATE/500 // 2 ms
-#define PULSE_WIDTH_ADDR_OFFSET 1
-
-struct MotorDriverState {
- int *outputs[4];
-};
-
-int zybo_motor_reset(struct MotorDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(struct MotorDriverState));
- if (self->state == NULL) {
- return -1;
- }
- }
- struct MotorDriverState *state = self->state;
-
- state->outputs[0] = (int *) MOTOR_BACKRIGHT_BASEADDR;
- state->outputs[1] = (int *) MOTOR_FRONTRIGHT_BASEADDR;
- state->outputs[2] = (int *) MOTOR_BACKLEFT_BASEADDR;
- state->outputs[3] = (int *) MOTOR_FRONTLEFT_BASEADDR;
-
- // Set period width of PWM pulse
- *(state->outputs[0]) = PERIOD_WIDTH;
- *(state->outputs[1]) = PERIOD_WIDTH;
- *(state->outputs[2]) = PERIOD_WIDTH;
- *(state->outputs[3]) = PERIOD_WIDTH;
-
- // Set a low pulse (1 ms) so that outputs are off
- *(state->outputs[0] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
- *(state->outputs[1] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
- *(state->outputs[2] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
- *(state->outputs[3] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
-
- usleep(1000000);
- return 0;
-}
-
-int zybo_motor_write(struct MotorDriver *self,
- unsigned int channel,
- float magnitude) {
- if (magnitude > 1)
- magnitude = 1;
- if (magnitude < 0)
- magnitude = 0;
- struct MotorDriverState *state = self->state;
- unsigned long pulse_width_ticks = (unsigned long) (magnitude * (float) (PULSE_WIDTH_HIGH - PULSE_WIDTH_LOW)) + PULSE_WIDTH_LOW;
- *(state->outputs[channel] + PULSE_WIDTH_ADDR_OFFSET) = pulse_width_ticks;
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_optical_flow.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_optical_flow.c
deleted file mode 100644
index c45ca68a9c9063653b8eda70b4827c83e05fcea1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_optical_flow.c
+++ /dev/null
@@ -1,74 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-#include <stdint.h>
-#include <string.h>
-#include "type_def.h"
-
-int px4flow_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
-int px4flow_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
-
-int zybo_optical_flow_reset(struct OpticalFlowDriver *self, px4flow_t *of) {
- memset(of, 0, sizeof(px4flow_t));
-
- return 0;
-}
-
-int zybo_optical_flow_read(struct OpticalFlowDriver *self, px4flow_t *of) {
- struct I2CDriver *i2c = self->i2c;
- int error = 0;
-
- // Note: Despite documentation, do not mark this as a "packed" struct. The actual code does not pack it.
- struct i2c_integral_frame
- {
- uint16_t frame_count_since_last_readout;//number of flow measurements since last I2C readout [#frames]
- int16_t pixel_flow_x_integral;//accumulated flow in radians*10000 around x axis since last I2C readout [rad*10000]
- int16_t pixel_flow_y_integral;//accumulated flow in radians*10000 around y axis since last I2C readout [rad*10000]
- int16_t gyro_x_rate_integral;//accumulated gyro x rates in radians*10000 since last I2C readout [rad*10000]
- int16_t gyro_y_rate_integral;//accumulated gyro y rates in radians*10000 since last I2C readout [rad*10000]
- int16_t gyro_z_rate_integral;//accumulated gyro z rates in radians*10000 since last I2C readout [rad*10000]
- uint32_t integration_timespan;//accumulation timespan in microseconds since last I2C readout [microseconds]
- uint32_t sonar_timestamp;// time since last sonar update [microseconds]
- int16_t ground_distance;// Ground distance in meters*1000 [meters*1000]
- int16_t gyro_temperature;// Temperature * 100 in centi-degrees Celsius [degcelsius*100]
- uint8_t quality;// averaged quality of accumulated flow values [0:bad quality;255: max quality]
- } i2c_integral_frame;
-
- u8 buf[sizeof(i2c_integral_frame)];
-
- // Read the sensor value
- error = px4flow_read(i2c, buf, 0x16, 26);
-
- if(error == 0) {
- //Copy into struct
- memcpy(&i2c_integral_frame, buf, sizeof(i2c_integral_frame));
-
- of->flow_x_rad = 0.0001 * i2c_integral_frame.pixel_flow_x_integral;
- of->flow_y_rad = 0.0001 * i2c_integral_frame.pixel_flow_y_integral;
- of->quality = i2c_integral_frame.quality;
- of->dt = (double)i2c_integral_frame.integration_timespan / 1000000;
- }
- return error;
-}
-
-/////////////////////
-// Helper functions
-/////////////////////
-
-int px4flow_write(struct I2CDriver *i2c, u8 register_addr, u8 data) {
- u8 buf[] = {register_addr, data};
-
- return i2c->write(i2c, PX4FLOW_DEVICE_ADDR, buf, 2);
-}
-
-int px4flow_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size) {
- u8 buf[] = {register_addr};
- int error = 0;
-
- error = i2c->write(i2c, PX4FLOW_DEVICE_ADDR, buf, 1);
- if (error) {
- return error;
- }
- error = i2c->read(i2c, PX4FLOW_DEVICE_ADDR, recv_buffer, size);
- return error;
-}
-
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c
deleted file mode 100644
index 391333b0a65cc7d60213930ae36a37f0e7fef786..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c
+++ /dev/null
@@ -1,40 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define SYS_CLOCK_RATE 100000000 // ticks per second
-#define FREQUENCY 450
-#define PERIOD_WIDTH SYS_CLOCK_RATE/FREQUENCY
-#define PULSE_WIDTH_LOW SYS_CLOCK_RATE/1000 // 1 ms
-#define PULSE_WIDTH_HIGH SYS_CLOCK_RATE/500 // 2 ms
-#define PULSE_WIDTH_ADDR_OFFSET 1
-
-struct RCReceiverDriverState {
- int *channels[6];
-};
-
-int zybo_rc_receiver_reset(struct RCReceiverDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(struct RCReceiverDriverState));
- if (self->state == NULL) {
- return -1;
- }
- }
-
- // Save the addresses of the input PWM recorders
- struct RCReceiverDriverState *state = self->state;
- state->channels[0] = (int *) XPAR_PWM_RECORDER_0_S_AXI_BASEADDR;
- state->channels[1] = (int *) XPAR_PWM_RECORDER_1_S_AXI_BASEADDR;
- state->channels[2] = (int *) XPAR_PWM_RECORDER_2_S_AXI_BASEADDR;
- state->channels[3] = (int *) XPAR_PWM_RECORDER_3_S_AXI_BASEADDR;
- state->channels[4] = (int *) XPAR_PWM_RECORDER_4_S_AXI_BASEADDR;
- state->channels[5] = (int *) XPAR_PWM_RECORDER_5_S_AXI_BASEADDR;
- return 0;
-}
-
-int zybo_rc_receiver_read(struct RCReceiverDriver *self,
- unsigned int channel,
- float *magnitude) {
- struct RCReceiverDriverState *state = self->state;
- unsigned long pulse_width_ticks = (long) *((int *) state->channels[channel]);
- *magnitude = (float) (pulse_width_ticks - PULSE_WIDTH_LOW) / (float) (PULSE_WIDTH_HIGH - PULSE_WIDTH_LOW);
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_system.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_system.c
deleted file mode 100644
index 2adcc4007d4891b0f830b58cc03258abf63ef62d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_system.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include "hw_impl_zybo.h"
-
-int zybo_system_reset(struct SystemDriver *sys) {
- return 0;
-}
-
-int zybo_system_sleep(struct SystemDriver *sys, unsigned long us) {
- usleep(us);
- return 0;
-}
-
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
deleted file mode 100644
index ddc7971a52b063309245f92af66665241a228953..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
+++ /dev/null
@@ -1,368 +0,0 @@
-#include "hw_impl_zybo.h"
-#include "type_def.h"
-#include <stdio.h>
-
-/**
- * Test for the LEDDriver and SystemDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-int test_zybo_mio7_led_and_system() {
- struct LEDDriver mio7 = create_zybo_mio7_led();
- struct SystemDriver sys = create_zybo_system();
- mio7.reset(&mio7);
- sys.reset(&sys);
-
- while (1) {
- mio7.turn_on(&mio7);
- sys.sleep(&sys, 1000000);
- mio7.turn_off(&mio7);
- sys.sleep(&sys, 1000000);
- }
-
- return 0;
-}
-
-/**
- * Tests for the I2CDriver (one for each I2C device we use)
- *
- * Instructions:
- * 1) Connect Zybo Board to computer by USB cable.
- * 2) Prepare a breadboard to accomplish the following connections:
- * - Zybo GND <-> LIDAR GND
- * - Zybo WALL <-> LIDAR VCC
- * - Zybo VV5V0 <-> LIDAR VCC
- * - Zybo SDA/SCL <-> LIDAR SDA/SCL
- * - The Zybo I2C SCL and SDA pins are on pins 1 and 2 of PORT JF, respectively
- * 3) Place breakpoint in this test function, somewhere in the while loop.
- * 4) Set the RUN_TESTS macro in main.c
- * 5) Uncomment only this test in main.c
- * 6) Debug main.c
- * 7) Step through the while loop, observing x change as you physically change the
- * distance of the LIDAR sensor.
- */
-int test_zybo_i2c() {
- struct I2CDriver i2c = create_zybo_i2c(1);
- struct LidarDriver ld = create_zybo_lidar(&i2c);
- i2c.reset(&i2c);
-
- lidar_t lidar = { };
- if (ld.reset(&ld, &lidar)) return 0;
- while (1) {
- ld.read(&ld, &lidar);
- }
- return 0;
-}
-
-int test_zybo_i2c_imu() {
- struct I2CDriver i2c = create_zybo_i2c(0);
- struct IMUDriver imu = create_zybo_imu(&i2c);
- char buf[100];
- gam_t gam;
- if (i2c.reset(&i2c)) return 0;
- if (imu.reset(&imu, &gam)) return 0;
-
- int status = 0;
- while (!status) {
- status = imu.read(&imu, &gam);
- usleep(5000);
- }
- return 0;
-}
-
-int test_zybo_i2c_px4flow() {
- struct I2CDriver i2c = create_zybo_i2c(0);
- struct OpticalFlowDriver ofd = create_zybo_optical_flow(&i2c);
- i2c.reset(&i2c);
- px4flow_t of;
-
- if (ofd.reset(&ofd, &of)) return 0;
-
- int status = 0;
- while(!status) {
- usleep(5000);
- status = ofd.read(&ofd, &of);
- }
-
- return 0;
-}
-
-int test_zybo_i2c_lidar() {
- struct I2CDriver i2c = create_zybo_i2c(1);
- struct LidarDriver lidarDriver = create_zybo_lidar(&i2c);
- i2c.reset(&i2c);
- lidar_t lidar;
-
- if (lidarDriver.reset(&lidarDriver, &lidar))
- return 0;
-
- int status = 0;
- while(!status) {
- usleep(5000);
- status = lidarDriver.read(&lidarDriver, &lidar);
- }
-
- return 0;
-}
-
-int test_zybo_i2c_all() {
- struct I2CDriver i2c_0 = create_zybo_i2c(0);
- struct IMUDriver imu = create_zybo_imu(&i2c_0);
- struct I2CDriver i2c_1 = create_zybo_i2c(1);
- struct LidarDriver ld = create_zybo_lidar(&i2c_1);
- struct OpticalFlowDriver ofd = create_zybo_optical_flow(&i2c_0);
- i2c_0.reset(&i2c_0);
- i2c_1.reset(&i2c_1);
-
- lidar_t lidar;
- px4flow_t of;
- gam_t gam;
-
- if (ld.reset(&ld, &lidar)) return 0;
- if (imu.reset(&imu, &gam)) return 0;
- if (ofd.reset(&ofd, &of)) return 0;
-
-
- int lidarErrors = 0;
- int gamErrors = 0;
- int nLoops = 0;
- int of_errors = 0;
-
- for(;;) {
- ld.read(&ld, &lidar);
- imu.read(&imu, &gam);
- ofd.read(&ofd, &of);
-
- if (lidar.distance_m > 50) {
- lidarErrors += 1;
- }
- if (gam.accel_z > -0.8) {
- gamErrors += 1;
- }
- nLoops += 1;
- }
- return 0;
-}
-
-/**
- * Test for the PWMInputDriver.
- *
- * Instructions:
- * 1) Connect the quad Zybo board to computer using USB.
- * 2) Move jumper on Zybo board to use JTAG instead of SD.
- * 3) Turn on Zybo board and turn on Spektrum handheld controller.
- * - Verify receiver on quad pairs with controller (orange LED should turn on)
- * 3) Place breakpoint somewhere in the while loop of this function.
- * 4) Set the RUN_TESTS macro in main.c
- * 5) Uncomment only this test in main.c
- * 6) Debug main.
- * 7) Observe the values of pwm_inputs in debugger changing as you use the
- * Spektrum RC controller.
- */
-int test_zybo_rc_receiver() {
- struct RCReceiverDriver rc_receiver = create_zybo_rc_receiver();
- rc_receiver.reset(&rc_receiver);
-
- float pwms[6];
- while (1) {
- int i;
- for (i = 0; i < 6; i += 1) {
- rc_receiver.read(&rc_receiver, i, &pwms[i]);
- }
- continue;
- }
-}
-
-/**
- * Test for the PWMOutputDriver.
- *
- * Instructions:
- * 1) Connect the quad Zybo board to computer using USB.
- * 2) Move jumper on Zybo board to use JTAG instead of SD.
- * 3) Get an oscilloscope and observe PMOD outputs JE7-JE10
- * 4) Set the RUN_TESTS macro in main.c
- * 5) Uncomment only this test in main.c
- * 6) Run main.
- * 7) Observe the PWM width of those PMOD pins changing with time
- */
-int test_zybo_motors() {
- struct MotorDriver motors = create_zybo_motors();
- motors.reset(&motors);
-
- double j = 0;
- while (1) {
- for (j = 0; j < 1.0; j += 0.01) {
- int i = 0;
- for (i = 0; i < 4; i += 1) {
- motors.write(&motors, i, j);
- usleep(50000);
- }
- }
- }
- return 0;
-}
-
-/**
- * Test for the AXI timer, using LEDDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-int test_zybo_axi_timer() {
- struct TimerDriver axi = create_zybo_axi_timer();
- struct LEDDriver led = create_zybo_mio7_led();
- axi.reset(&axi);
- led.reset(&led);
-
- unsigned long time;
-
- while (1) {
- axi.restart(&axi);
- time = 0;
- while (time < 1000000) {
- axi.read(&axi, &time);
- }
- led.turn_off(&led);
- while (time < 2000000) {
- axi.read(&axi, &time);
- }
- led.turn_on(&led);
- }
-}
-
-/**
- * Test for the Global timer, using LEDDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-int test_zybo_global_timer() {
- struct TimerDriver global = create_zybo_global_timer();
- struct LEDDriver led = create_zybo_mio7_led();
- global.reset(&global);
- led.reset(&led);
-
- unsigned long time;
-
- while (1) {
- global.restart(&global);
- time = 0;
- while (time < 1000000) {
- global.read(&global, &time);
- }
- led.turn_off(&led);
- while (time < 2000000) {
- global.read(&global, &time);
- }
- led.turn_on(&led);
- }
-}
-
-/**
- * Communication tests using the UARTDriver.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Get a FTDI Basic Sparkfun board in order to connect the UART pins
- * on the Zybo to the computer by USB.
- * - Zybo PMOD JC2 (TX) <-> Sparkfun Board RX
- * - Zybo PMOD JC3 (RX) <-> sparkfun Board Tx
- * - Zybo PMOD JC5 (GND) <-> Sparkfun Board GDN
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Execute quad/scripts/tests/test_zybo_uart.py
- * - Observe test results on terminal
- * - You might be able to see LED MIO7 blink when it receives bytes
- */
-int test_zybo_uart_comm() {
- struct UARTDriver uart = create_zybo_uart(0);
- struct CommDriver comm = create_zybo_comm(&uart);
- struct LEDDriver led = create_zybo_mio7_led();
- uart.reset(&uart);
- led.reset(&led);
-
- unsigned char c;
- while (1) {
- if (comm.uart->read(comm.uart, &c)) {
- uart.write(&uart, 0x55);
- // read failed
- led.turn_off(&led);
- } else {
- // read successful
- led.turn_on(&led);
- uart.write(&uart, c);
- }
- }
-
- return 0;
-}
-
-
-int test_zybo_pcb() {
- struct UARTDriver uart = create_zybo_uart(0);
- struct LEDDriver led = create_zybo_mio7_led();
- struct RCReceiverDriver rc = create_zybo_rc_receiver();
- struct MotorDriver motors = create_zybo_motors();
- uart.reset(&uart);
- led.reset(&led);
- rc.reset(&rc);
- motors.reset(&motors);
-
- char stateMsg[100];
- unsigned char c;
- unsigned char led_state = 0;
- float channels[6];
- float pwm[4];
- int i;
- while (1) {
- if(uart.read(&uart, &c) >= 0) {
- if(led_state) {
- led.turn_off(&led);
- led_state = 0;
- } else {
- led.turn_on(&led);
- led_state = 1;
- }
- }
- for (i = 0; i < 6; i++) {
- rc.read(&rc, i, &channels[i]);
- }
- pwm[0] = channels[0]+channels[1]+channels[3];
- pwm[1] = channels[0]+channels[1]-channels[3];
- pwm[2] = channels[0]-channels[1]+channels[3];
- pwm[3] = channels[0]-channels[1]-channels[3];
- sprintf(stateMsg, "%5.2f %5.2f %5.2f %5.2f %5.2f %5.2f -> %5.2f %5.2f %5.2f %5.2f\r\n", channels[0], channels[1], channels[2], channels[3], channels[4], channels[5], pwm[0], pwm[1], pwm[2], pwm[2]);
- char* it;
- for (it = stateMsg; *it; it++) {
- uart.write(&uart, *it);
- }
- for (i = 0; i < 4; i++) {
- motors.write(&motors, i, pwm[i]);
- }
- }
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_uart.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_uart.c
deleted file mode 100644
index 9d3ff70509cdd8837a2278f4e721d6340bb3d77b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_uart.c
+++ /dev/null
@@ -1,282 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define BAUD_RATE 921600
-
-
-int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate);
-int SetupInterruptSystem(struct ZyboUARTState *state, u16 UartIntrId, Xil_ExceptionHandler handler);
-void uart_interrupt_handler(struct ZyboUARTState *state);
-
-int zybo_uart_reset(struct UARTDriver *self) {
- // Ensure all required memory is allocated
- struct ZyboUARTState *state = self->state;
- if (state == NULL) return -1;
- if (state->inst == NULL) return -1;
- if (state->queue == NULL) return -1;
-
- XUartPs *inst = state->inst;
-
- // Configure XUartPs instance
- XUartPs_Config* config = XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID);
- if (XUartPs_CfgInitialize(inst, config, config->BaseAddress) != XST_SUCCESS) {
- return -1;
- }
-
- // Set UART Baudrate
- if(XUartPs_SetBaudRate_ours(inst, BAUD_RATE) != XST_SUCCESS) {
- return -1;
- }
-
- // Clear Tx/Rx FIFOs
- int* uart_ctrl_reg = (int*) inst->Config.BaseAddress;
- *uart_ctrl_reg |= 0x00000003; // clear TX & RX
-
- // Setup Interrupts
- if (SetupInterruptSystem(state, XPAR_PS7_UART_0_INTR, (Xil_ExceptionHandler) uart_interrupt_handler) != XST_SUCCESS) {
- return -1;
- }
-
- // Interrupts selected: Rx FIFO threashold reached, RX overflow, timeout
- u32 IntrMask = XUARTPS_IXR_RXFULL | XUARTPS_IXR_RXOVR | XUARTPS_IXR_TOUT;
- XUartPs_SetInterruptMask(inst, IntrMask);
-
- /*
- * Set the receiver timeout. If it is not set, and the last few bytes
- * of data do not trigger the over-water or full interrupt, the bytes
- * will not be received. By default it is disabled.
- * Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
- * timeout function.
- *
- * The setting of 8 will timeout after 8 x 4 = 32 character times.
- * Increase the time out value if baud rate is high, decrease it if
- * baud rate is low.
- */
- XUartPs_SetRecvTimeout(inst, 8);
-
- // Second argument is the number of bytes to trigger an interrupt at
- XUartPs_SetFifoThreshold(inst, 48);
-
- return 0;
-}
-
-int zybo_uart_write(struct UARTDriver *self, unsigned char c) {
- struct ZyboUARTState *state = self->state;
- XUartPs *inst = state->inst;
- XUartPs_SendByte(inst->Config.BaseAddress, c);
- return 0;
-}
-
-int zybo_uart_read(struct UARTDriver *self, unsigned char *c) {
- struct ZyboUARTState *state = self->state;
- struct Queue *queue = state->queue;
- if (queue_remove(queue, c)) return -1;
- else return 0;
-}
-
-//This is copied from xuart driver
-/***************************************************/
-
-#define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
-int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate)
-{
- u8 IterBAUDDIV; /* Iterator for available baud divisor values */
- u32 BRGR_Value; /* Calculated value for baud rate generator */
- u32 CalcBaudRate; /* Calculated baud rate */
- u32 BaudError; /* Diff between calculated and requested baud rate */
- u32 Best_BRGR = 0; /* Best value for baud rate generator */
- u8 Best_BAUDDIV = 0; /* Best value for baud divisor */
- u32 Best_Error = 0xFFFFFFFF;
- u32 PercentError;
- u32 ModeReg;
- u32 InputClk;
-
- /*
- * Asserts validate the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- //Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE);
- Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE);
-
- /*
- * Make sure the baud rate is not impossilby large.
- * Fastest possible baud rate is Input Clock / 2.
- */
- if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
- return XST_UART_BAUD_ERROR;
- }
- /*
- * Check whether the input clock is divided by 8
- */
- ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- InputClk = InstancePtr->Config.InputClockHz;
- if(ModeReg & XUARTPS_MR_CLKSEL) {
- InputClk = InstancePtr->Config.InputClockHz / 8;
- }
-
- /*
- * Determine the Baud divider. It can be 4to 254.
- * Loop through all possible combinations
- */
- for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
-
- /*
- * Calculate the value for BRGR register
- */
- BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
-
- /*
- * Calculate the baud rate from the BRGR value
- */
- CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
-
- /*
- * Avoid unsigned integer underflow
- */
- if (BaudRate > CalcBaudRate) {
- BaudError = BaudRate - CalcBaudRate;
- }
- else {
- BaudError = CalcBaudRate - BaudRate;
- }
-
- /*
- * Find the calculated baud rate closest to requested baud rate.
- */
- if (Best_Error > BaudError) {
-
- Best_BRGR = BRGR_Value;
- Best_BAUDDIV = IterBAUDDIV;
- Best_Error = BaudError;
- }
- }
-
- /*
- * Make sure the best error is not too large.
- */
- PercentError = (Best_Error * 100) / BaudRate;
- if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
- return XST_UART_BAUD_ERROR;
- }
-
- /*
- * Disable TX and RX to avoid glitches when setting the baud rate.
- */
- XUartPs_DisableUart(InstancePtr);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
-
- /*
- * Enable device
- */
- XUartPs_EnableUart(InstancePtr);
-
- InstancePtr->BaudRate = BaudRate;
-
- return XST_SUCCESS;
-
-}
-
-void uart_interrupt_handler(struct ZyboUARTState *state) {
- u32 IsrStatus;
- XUartPs *InstancePtr = state->inst;
- struct Queue *queue = state->queue;
-
- /*
- * Read the interrupt ID register to determine which
- * interrupt is active
- */
- IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
-
- IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_ISR_OFFSET);
-
- /*
- * Read the Channel Status Register to determine if there is any data in
- * the RX FIFO
- */
-
- u32 CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- while (0 == (CsrRegister & XUARTPS_SR_RXEMPTY)) {
- u8 byte = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUARTPS_FIFO_OFFSET);
- queue_add(queue, byte);
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUARTPS_SR_OFFSET);
- }
-
- // Clear the interrupt status.
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
- IsrStatus);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets up the interrupt system so interrupts can occur for the
-* Uart. This function is application-specific.
-*
-* @param IntcInstancePtr is a pointer to the instance of the INTC.
-* @param UartInstancePtr contains a pointer to the instance of the UART
-* driver which is going to be connected to the interrupt
-* controller.
-* @param UartIntrId is the interrupt Id and is typically
-* XPAR_<UARTPS_instance>_INTR value from xparameters.h.
-*
-* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
-*
-* @note None.
-*
-****************************************************************************/
-int SetupInterruptSystem(struct ZyboUARTState *state, u16 UartIntrId, Xil_ExceptionHandler handler)
-{
- int Status;
- XScuGic_Config *IntcConfig; /* Config for interrupt controller */
-
- /* Initialize the interrupt controller driver */
- IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
- if (NULL == IntcConfig) {
- return XST_FAILURE;
- }
-
- memset(&state->xscugic, 0, sizeof(XScuGic));
- Status = XScuGic_CfgInitialize(&state->xscugic, IntcConfig,
- IntcConfig->CpuBaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Connect the interrupt controller interrupt handler to the
- * hardware interrupt handling logic in the processor.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler) XScuGic_InterruptHandler,
- &state->xscugic);
-
- /*
- * Connect a device driver handler that will be called when an
- * interrupt for the device occurs, the device driver handler
- * performs the specific interrupt processing for the device
- */
- Status = XScuGic_Connect(&state->xscugic, UartIntrId,
- handler,
- (void *) state);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /* Enable the interrupt for the device */
- XScuGic_Enable(&state->xscugic, UartIntrId);
-
- /* Enable interrupts */
- Xil_ExceptionEnable();
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/lscript.ld b/quad/xsdk_workspace_vivado/real_quad/src/lscript.ld
deleted file mode 100644
index a9e7524bb4b15ca61a3d8c76f6a001e3b4c86e9f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/lscript.ld
+++ /dev/null
@@ -1,284 +0,0 @@
-/*******************************************************************/
-/* */
-/* This file is automatically generated by linker script generator.*/
-/* */
-/* Version: Xilinx EDK 14.7 EDK_P.20131013 */
-/* */
-/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
-/* */
-/* Description : Cortex-A9 Linker Script */
-/* */
-/*******************************************************************/
-
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x100000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x6400000;
-
-_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
-_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
-_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
-_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
-
-/* Define Memories in the system */
-
-MEMORY
-{
- ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
- ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
- ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
-}
-
-/* Specify the default entry point to the program */
-
-ENTRY(_vector_table)
-
-/* Define the sections, and where they are mapped in memory */
-
-SECTIONS
-{
-.text : {
- *(.vectors)
- *(.boot)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
- *(.plt)
- *(.gnu_warning)
- *(.gcc_execpt_table)
- *(.glue_7)
- *(.glue_7t)
- *(.vfp11_veneer)
- *(.ARM.extab)
- *(.gnu.linkonce.armextab.*)
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.init : {
- KEEP (*(.init))
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.fini : {
- KEEP (*(.fini))
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.rodata : {
- __rodata_start = .;
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- __rodata_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.rodata1 : {
- __rodata1_start = .;
- *(.rodata1)
- *(.rodata1.*)
- __rodata1_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.sdata2 : {
- __sdata2_start = .;
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- __sdata2_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.sbss2 : {
- __sbss2_start = .;
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- __sbss2_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.data : {
- __data_start = .;
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- *(.jcr)
- *(.got)
- *(.got.plt)
- __data_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.data1 : {
- __data1_start = .;
- *(.data1)
- *(.data1.*)
- __data1_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.got : {
- *(.got)
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.ctors : {
- __CTOR_LIST__ = .;
- ___CTORS_LIST___ = .;
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- ___CTORS_END___ = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.dtors : {
- __DTOR_LIST__ = .;
- ___DTORS_LIST___ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- ___DTORS_END___ = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.fixup : {
- __fixup_start = .;
- *(.fixup)
- __fixup_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.eh_frame : {
- *(.eh_frame)
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.eh_framehdr : {
- __eh_framehdr_start = .;
- *(.eh_framehdr)
- __eh_framehdr_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.gcc_except_table : {
- *(.gcc_except_table)
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.mmu_tbl (ALIGN(16384)) : {
- __mmu_tbl_start = .;
- *(.mmu_tbl)
- __mmu_tbl_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.ARM.exidx : {
- __exidx_start = .;
- *(.ARM.exidx*)
- *(.gnu.linkonce.armexidix.*.*)
- __exidx_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.preinit_array : {
- __preinit_array_start = .;
- KEEP (*(SORT(.preinit_array.*)))
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.init_array : {
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.fini_array : {
- __fini_array_start = .;
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array))
- __fini_array_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.ARM.attributes : {
- __ARM.attributes_start = .;
- *(.ARM.attributes)
- __ARM.attributes_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.sdata : {
- __sdata_start = .;
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- __sdata_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.sbss (NOLOAD) : {
- __sbss_start = .;
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- __sbss_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.tdata : {
- __tdata_start = .;
- *(.tdata)
- *(.tdata.*)
- *(.gnu.linkonce.td.*)
- __tdata_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.tbss : {
- __tbss_start = .;
- *(.tbss)
- *(.tbss.*)
- *(.gnu.linkonce.tb.*)
- __tbss_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.bss (NOLOAD) : {
- __bss_start = .;
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- __bss_end = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
-
-_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
-
-/* Generate Stack and Heap definitions */
-
-.heap (NOLOAD) : {
- . = ALIGN(16);
- _heap = .;
- HeapBase = .;
- _heap_start = .;
- . += _HEAP_SIZE;
- _heap_end = .;
- HeapLimit = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-.stack (NOLOAD) : {
- . = ALIGN(16);
- _stack_end = .;
- . += _STACK_SIZE;
- _stack = .;
- __stack = _stack;
- . = ALIGN(16);
- _irq_stack_end = .;
- . += _STACK_SIZE;
- __irq_stack = .;
- _supervisor_stack_end = .;
- . += _SUPERVISOR_STACK_SIZE;
- . = ALIGN(16);
- __supervisor_stack = .;
- _abort_stack_end = .;
- . += _ABORT_STACK_SIZE;
- . = ALIGN(16);
- __abort_stack = .;
- _fiq_stack_end = .;
- . += _FIQ_STACK_SIZE;
- . = ALIGN(16);
- __fiq_stack = .;
- _undef_stack_end = .;
- . += _UNDEF_STACK_SIZE;
- . = ALIGN(16);
- __undef_stack = .;
-} > ps7_ddr_0_S_AXI_BASEADDR
-
-_end = .;
-}
-
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/main.c b/quad/xsdk_workspace_vivado/real_quad/src/main.c
deleted file mode 100644
index 0bbe1ed3cbd0be5f9a98b491e07428c1af3b9a65..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/main.c
+++ /dev/null
@@ -1,72 +0,0 @@
-#include <stdio.h>
-#include "hw_impl_zybo.h"
-#include "quad_app.h"
-#include "type_def.h"
-#include "platform.h"
-
-//#define RUN_TESTS
-
-/**
- * Create the hardware drivers, and place them on the hardware struct.
- *
- * Things to keep in mind:
- * - The CommDriver requires a UART. Hence, make the a UARTDriver first
- * and then give that instance to the CommDriver.
- * - Same for GPSDriver, except it needs a different hardware device.
- * - The I2C devices (IMU, LIDAR, Optical Flow), need a I2C bus. Hence
- * make a I2CDriver first, then give the appropariate instance the
- * device drivers.
- * - Currently, we are putting the Lidar on its own bus. Apparently,
- * when looking at an OScope with the Lidar on a bus with other
- * devices, it does not look right. The SCL line would never
- * go all the way back down to 0 volts
- */
-int setup_hardware(hardware_t *hardware) {
- hardware->rc_receiver = create_zybo_rc_receiver();
- hardware->motors = create_zybo_motors();
- hardware->uart_0 = create_zybo_uart(0);
- hardware->uart_1 = create_zybo_uart(1);
- hardware->comm = create_zybo_comm(&hardware->uart_0);
- hardware->gps = create_zybo_gps(&hardware->uart_1);
- hardware->global_timer = create_zybo_global_timer();
- hardware->axi_timer = create_zybo_axi_timer();
- hardware->mio7_led = create_zybo_mio7_led();
- hardware->sys = create_zybo_system();
- hardware->i2c_0 = create_zybo_i2c(0);
- hardware->i2c_1 = create_zybo_i2c(1);
- hardware->imu = create_zybo_imu(&hardware->i2c_0);
- hardware->lidar = create_zybo_lidar(&hardware->i2c_1);
- hardware->of = create_zybo_optical_flow(&hardware->i2c_0);
- return 0;
-}
-
-int main()
-{
- // Zynq initialization
- init_platform();
-
-#ifdef RUN_TESTS
- //test_zybo_mio7_led_and_system();
- //!test_zybo_i2c();
- //!test_zybo_i2c_imu();
- zybo_i2c_imu_self_test();
- //!test_zybo_i2c_px4flow();
- //!test_zybo_i2c_lidar();
- //!test_zybo_i2c_all();
- //!test_zybo_rc_receiver();
- //!test_zybo_motors();
- //test_zybo_axi_timer();
- //!test_zybo_uart_comm();
- return 0;
-#endif
-
- // Run the main quad application
- quad_main(setup_hardware);
-
- while(1) {
- volatile int i = 0;
- i++;
- }
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/platform.c b/quad/xsdk_workspace_vivado/real_quad/src/platform.c
deleted file mode 100644
index ea7849798004dd889c3c4bfa76a67c0867e023d3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/platform.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_cache.h"
-
-#include "platform_config.h"
-
-/*
- * Uncomment the following line if ps7 init source files are added in the
- * source directory for compiling example outside of SDK.
- */
-/*#include "ps7_init.h"*/
-
-#ifdef STDOUT_IS_16550
- #include "xuartns550_l.h"
-
- #define UART_BAUD 9600
-#endif
-
-void
-enable_caches()
-{
-#ifdef __PPC__
- Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
- Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
-#elif __MICROBLAZE__
-#ifdef XPAR_MICROBLAZE_USE_ICACHE
- Xil_ICacheEnable();
-#endif
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- Xil_DCacheEnable();
-#endif
-#endif
-}
-
-void
-disable_caches()
-{
- Xil_DCacheDisable();
- Xil_ICacheDisable();
-}
-
-void
-init_uart()
-{
-#ifdef STDOUT_IS_16550
- XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
- XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
-#endif
-#ifdef STDOUT_IS_PS7_UART
- /* Bootrom/BSP configures PS7 UART to 115200 bps */
-#endif
-}
-
-void
-init_platform()
-{
- /*
- * If you want to run this example outside of SDK,
- * uncomment the following line and also #include "ps7_init.h" at the top.
- * Make sure that the ps7_init.c and ps7_init.h files are included
- * along with this example source files for compilation.
- */
- /* ps7_init();*/
- enable_caches();
- init_uart();
-}
-
-void
-cleanup_platform()
-{
- disable_caches();
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/platform.h b/quad/xsdk_workspace_vivado/real_quad/src/platform.h
deleted file mode 100644
index efc90882b0b336c2038d1f8a0a02ffed7d6e7ae3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/platform.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2008 Xilinx, Inc. All rights reserved.
- *
- * Xilinx, Inc.
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
- * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
- * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
- * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
- * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
- * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-
-#ifndef __PLATFORM_H_
-#define __PLATFORM_H_
-
-#include "platform_config.h"
-
-void init_platform();
-void cleanup_platform();
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/platform_config.h b/quad/xsdk_workspace_vivado/real_quad/src/platform_config.h
deleted file mode 100644
index c07ab1cba9631113470838bd69dce3964dd386fa..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/platform_config.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __PLATFORM_CONFIG_H_
-#define __PLATFORM_CONFIG_H_
-
-#define STDOUT_IS_PS7_UART
-#define UART_DEVICE_ID 0
-#ifdef __PPC__
-#define CACHEABLE_REGION_MASK 0xf0000001
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.cproject b/quad/xsdk_workspace_vivado/system_bsp/.cproject
deleted file mode 100644
index 20bc66eca62b633b9c6459543730f5560d0c56f7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/.cproject
+++ /dev/null
@@ -1,13 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.1229250672">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1229250672" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
- <externalSettings/>
- <extensions/>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-</cproject>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.project b/quad/xsdk_workspace_vivado/system_bsp/.project
deleted file mode 100644
index 1773c9f5fef32c05d645b542adf3376c708cb66a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/.project
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>system_bsp</name>
- <comment>Created by SDK v2018.2</comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.make.core.makeBuilder</name>
- <arguments>
- <dictionary>
- <key>org.eclipse.cdt.core.errorOutputParser</key>
- <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.append_environment</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.arguments</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.command</key>
- <value>make</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.auto</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.clean</key>
- <value>clean</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.inc</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableFullBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.environment</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.stopOnError</key>
- <value>false</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
- <value>true</value>
- </dictionary>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>com.xilinx.sdk.sw.SwProjectNature</nature>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.make.core.makeNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
deleted file mode 100644
index dd82e57dd062516fb69638e72b1609d20aa13292..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
+++ /dev/null
@@ -1,4 +0,0 @@
-THIRPARTY=false
-HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_0
-PROCESSOR=ps7_cortexa9_0
-MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/system_bsp/Makefile b/quad/xsdk_workspace_vivado/system_bsp/Makefile
deleted file mode 100644
index 1e68922caaf26866fdd396178d91b437eadf7fb2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/Makefile
+++ /dev/null
@@ -1,35 +0,0 @@
-# Makefile generated by Xilinx.
-
-PROCESSOR = ps7_cortexa9_0
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
-SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
-
-ifneq (,$(findstring win,$(RDI_PLATFORM)))
- SHELL = CMD
-endif
-
-all: libs
- @echo 'Finished building libraries'
-
-include: $(addsuffix /make.include,$(SUBDIRS))
-
-libs: $(addsuffix /make.libs,$(SUBDIRS))
-
-clean: $(addsuffix /make.clean,$(SUBDIRS))
-
-$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
- cp -f $< $@
-
-%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
- @echo "Running Make include in $(subst /make.include,,$@)"
- $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
-
-%/make.libs: include
- @echo "Running Make libs in $(subst /make.libs,,$@)"
- $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
-
-%/make.clean:
- $(MAKE) -C $(subst /make.clean,,$@) -s clean
-clean:
- rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
deleted file mode 100644
index 2cee66b09ec02849f667a2e6731e44e6ab6163e4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_timer_hw.h:
-* Timer related functions
-*
-******************************************************************************/
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
deleted file mode 100644
index 7859b0eef626654613361272366cfb818a2a0bab..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
+++ /dev/null
@@ -1,45 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H /* prevent circular inclusions */
-#define BSPCONFIG_H /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-#endif /*end of __BSPCONFIG_H_*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
deleted file mode 100644
index 7096a92d804e8cbd2a660b78a32d5ea3a7256862..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/profile.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/profile.h
deleted file mode 100644
index 4cb07a7d3e230e647f9e6c5dbcb1447be4bfed5a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/profile.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef PROFILE_H
-#define PROFILE_H 1
-
-#include <stdio.h>
-#include "xil_types.h"
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(u32 frompc, u32 selfpc);
-void profile_intr_handler( void ) ;
-void _profile_init( void );
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define HISTCOUNTER u16
-
-struct tostruct {
- u32 selfpc;
- s32 count;
- s16 link;
- u16 pad;
-};
-
-struct fromstruct {
- u32 frompc ;
- s16 link ;
- u16 pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y) (((x)/(y))*(y))
-#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
- s32 state;
-
- /* Histogram Information */
- u16 *kcount; /* No. of bins in histogram */
- u32 kcountsize; /* Histogram samples */
-
- /* Call-graph Information */
- struct fromstruct *froms;
- u32 fromssize;
- struct tostruct *tos;
- u32 tossize;
-
- /* Initialization I/Ps */
- u32 lowpc;
- u32 highpc;
- u32 textsize;
- /* u32 cg_froms, */
- /* u32 cg_tos, */
-};
-extern struct gmonparam *_gmonparam;
-extern s32 n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define GMON_PROF_ON 0
-#define GMON_PROF_BUSY 1
-#define GMON_PROF_ERROR 2
-#define GMON_PROF_OFF 3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define GPROF_STATE 0 /* int: profiling enabling variable */
-#define GPROF_COUNT 1 /* struct: profile tick count buffer */
-#define GPROF_FROMS 2 /* struct: from location hash bucket */
-#define GPROF_TOS 3 /* struct: destination/count structure */
-#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PROFILE_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h
deleted file mode 100644
index f53b2d8c8e2c4c3d68702d7780654fc60e1950ea..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep rountines
-* function prototypes.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/smc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/smc.h
deleted file mode 100644
index 5a4d33608256f53d59b1c6470b9627803ea20b55..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/smc.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-* </pre>
-*
-* @note None.
-*
-******************************************************************************/
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET 0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/vectors.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/vectors.h
deleted file mode 100644
index bb599b5602601d799de56541046a0530075fedff..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/vectors.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-#if !defined (__aarch64__)
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-void UndefinedException(void);
-#else
-void SynchronousInterrupt(void);
-void SErrorInterrupt(void);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps.h
deleted file mode 100644
index 549bfff298f5c67a35b28b5231b1636dafd4396c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps.h
-* @addtogroup xadcps_v2_2
-* @{
-* @details
-*
-* The XAdcPs driver supports the Xilinx XADC/ADC device.
-*
-* The XADC/ADC device has the following features:
-* - 10-bit, 200-KSPS (kilo samples per second)
-* Analog-to-Digital Converter (ADC)
-* - Monitoring of on-chip supply voltages and temperature
-* - 1 dedicated differential analog-input pair and
-* 16 auxiliary differential analog-input pairs
-* - Automatic alarms based on user defined limits for the on-chip
-* supply voltages and temperature
-* - Automatic Channel Sequencer, programmable averaging, programmable
-* acquisition time for the external inputs, unipolar or differential
-* input selection for the external inputs
-* - Inbuilt Calibration
-* - Optional interrupt request generation
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the XADC/ADC device.
-*
-*
-* <b> XADC Channel Sequencer Modes </b>
-*
-* The XADC Channel Sequencer supports the following operating modes:
-*
-* - <b> Default </b>: This is the default mode after power up.
-* In this mode of operation the XADC operates in
-* a sequence mode, monitoring the on chip sensors:
-* Temperature, VCCINT, and VCCAUX.
-* - <b> One pass through sequence </b>: In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers for a single pass and then stops.
-* - <b> Continuous cycling of sequence </b>: In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers continuously.
-* - <b> Single channel mode</b>: In this mode the XADC Channel
-* Sequencer is disabled and the XADC operates in a
-* Single Channel Mode.
-* The XADC can operate either in a Continuous or Event
-* driven sampling mode in the single channel mode.
-* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
-* Sequencer will automatically sequence through eight fixed pairs
-* of auxiliary analog input channels for simulataneous conversion.
-* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
-* is used to implement a fixed monitoring mode similar to the
-* default mode but the alarm fucntions ar eenabled.
-* The second ADC (B) is available to be used with external analog
-* input channels only.
-*
-* Read the XADC spec for more information about the sequencer modes.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the XADC/ADC device.
-*
-* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
-* device. The user needs to first call the XAdcPs_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAdcPs_CfgInitialize() API.
-*
-*
-* <b>Interrupts</b>
-*
-* The XADC/ADC device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* The interrupt mode is available only if hardware is configured to support
-* interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* <b> Building the driver </b>
-*
-* The XAdcPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <b> Limitations of the driver </b>
-*
-* XADC/ADC device can be accessed through the JTAG port and the PLB
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to care of this situation
-* in the user application code.
-*
-* <br><br>
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4 /**< VREFP */
-#define XADCPS_CH_VREFN 0x5 /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-
-u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h
deleted file mode 100644
index 55a47a440a6a9933952aa7d70ad73b5e198c689b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_2
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */
-#define XADCPS_CFR2_CD_SHIFT 8 /**<Num of shift on division */
-#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
-#define XADCPS_CFR2_CD_MAX 255 /**<Maximum value of divisor */
-
-#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
-#define XADCPS_CFR2_PD_MASK 0x0030 /**<Power Down Mask */
-#define XADCPS_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */
-#define XADCPS_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down ADC1 Mask */
-#define XADCPS_CFR2_PD_SHIFT 4 /**<Power Down Shift */
-/*@}*/
-
-/**
- * @name Sequence Register (SEQ) Bit Definitions
- * @{
- */
-#define XADCPS_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */
-#define XADCPS_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */
-#define XADCPS_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */
-#define XADCPS_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */
-#define XADCPS_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */
-#define XADCPS_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */
-#define XADCPS_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */
-#define XADCPS_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */
-#define XADCPS_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */
-#define XADCPS_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */
-#define XADCPS_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series */
-#define XADCPS_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */
-#define XADCPS_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */
-#define XADCPS_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */
-#define XADCPS_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */
-#define XADCPS_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */
-#define XADCPS_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */
-#define XADCPS_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */
-#define XADCPS_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */
-#define XADCPS_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */
-#define XADCPS_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */
-#define XADCPS_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */
-#define XADCPS_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */
-#define XADCPS_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */
-#define XADCPS_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */
-#define XADCPS_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */
-#define XADCPS_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */
-
-#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */
-#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */
-#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
-#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
-#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-
-#define XADCPS_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */
-
-/*@}*/
-
-/**
- * @name OT Upper Alarm Threshold Register Bit Definitions
- * @{
- */
-
-#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */
-#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */
-#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */
-#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */
-#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */
-
-/*@}*/
-
-
-/**
- * @name JTAG DRP Bit Definitions
- * @{
- */
-#define XADCPS_JTAG_DATA_MASK 0x0000FFFF /**< Mask for the Data */
-#define XADCPS_JTAG_ADDR_MASK 0x03FF0000 /**< Mask for the Addr */
-#define XADCPS_JTAG_ADDR_SHIFT 16 /**< Shift for the Addr */
-#define XADCPS_JTAG_CMD_MASK 0x3C000000 /**< Mask for the Cmd */
-#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000 /**< Mask for CMD Write */
-#define XADCPS_JTAG_CMD_READ_MASK 0x04000000 /**< Mask for CMD Read */
-#define XADCPS_JTAG_CMD_SHIFT 26 /**< Shift for the Cmd */
-
-/*@}*/
-
-/** @name Unlock Register Definitions
- * @{
- */
- #define XADCPS_UNLK_OFFSET 0x034 /**< Unlock Register */
- #define XADCPS_UNLK_VALUE 0x757BDF0D /**< Unlock Value */
-
- /* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-*
-* Read a register of the XADC device. This macro provides register
-* access to all registers using the register offsets defined above.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset is the offset of the register to read.
-*
-* @return The contents of the register.
-*
-* @note C-style Signature:
-* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
-*
-******************************************************************************/
-#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-/*****************************************************************************/
-/**
-*
-* Write a register of the XADC device. This macro provides
-* register access to all registers using the register offsets defined above.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset is the offset of the register to write.
-* @param Data is the value to write to the register.
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XAdcPs_WriteReg(u32 BaseAddress,
-* u32 RegOffset,u32 Data)
-*
-******************************************************************************/
-#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Formats the data to be written to the the XADC registers.
-*
-* @param RegOffset is the offset of the Register
-* @param Data is the data to be written to the Register if it is
-* a write.
-* @param ReadWrite specifies whether it is a Read or a Write.
-* Use 0 for Read, 1 for Write.
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XAdcPs_FormatWriteData(u32 RegOffset,
-* u16 Data, int ReadWrite)
-*
-******************************************************************************/
-#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \
- ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
- ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
- (Data & XADCPS_JTAG_DATA_MASK))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xbasic_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xbasic_types.h
deleted file mode 100644
index 787212ca75ff368e405799266b103f095b0b22a1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xbasic_types.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef unsigned char Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef unsigned short Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef unsigned long Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include <linux/types.h>
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
deleted file mode 100644
index 67959e3274632a6ca7b5bd3225679cc0c3e1f10f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_4
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef __MICROBLAZE__
-#include <xil_types.h>
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
deleted file mode 100644
index 95c8ba5360707e6032e28cfc4847ee9df969fd1c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_5
-* @{
-* @details
-*
-* dummy file
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
-* parameter of cpu_cortexa9 in xparameters.h
-******************************************************************************/
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xddrps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xddrps.h
deleted file mode 100644
index c8804d2ed33d87cd0d678d73a63bb0ddedee86f1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xddrps.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*******************************************************************************
- *
- * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * Use of the Software is limited solely to applications:
- * (a) running on a Xilinx device, or
- * (b) that interact with a Xilinx device through a bus or interconnect.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Except as contained in this notice, the name of the Xilinx shall not be used
- * in advertising or otherwise to promote the sale, use or other dealings in
- * this Software without prior written authorization from Xilinx.
- *
-*******************************************************************************/
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_0
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note None.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- * </pre>
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdebug.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdebug.h
deleted file mode 100644
index 650946bd01f4555daaeaf12db9919130e4aecf7d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdebug.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef XDEBUG /* prevent circular inclusions */
-#define XDEBUG /* by using protection macros */
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL)
-
-#define xdbg_stmnt(x) x
-
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-#define xdbg_printf(...)
-
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#endif /* XDEBUG */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg.h
deleted file mode 100644
index b9a0111d695aeb71f09195025549f3df8283d9fb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.h
-* @addtogroup devcfg_v3_5
-* @{
-* @details
-*
-* The is the main header file for the Device Configuration Interface of the Zynq
-* device. The device configuration interface has three main functionality.
-* 1. AXI-PCAP
-* 2. Security Policy
-* 3. XADC
-* This current version of the driver supports only the AXI-PCAP and Security
-* Policy blocks. There is a separate driver for XADC.
-*
-* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
-* DMA embedded in the AXI PCAP provides the master interface to
-* the Device configuration block for any DMA transfers. The data transfer can
-* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
-* RAM/DDR/peripheral memory).
-*
-* The current driver only supports the downloading the FPGA bitstream and
-* readback of the decrypted image (sort of loopback).
-* The driver does not know what information needs to be written to the FPGA to
-* readback FPGA configuration register or memory data. The application above the
-* driver should take care of creating the data that needs to be downloaded to
-* the FPGA so that the bitstream can be readback.
-* This driver also does not support the reading of the internal registers of the
-* PCAP. The driver has no knowledge of the PCAP internals.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Device Configuration device.
-*
-* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
-* Interface. The user needs to first call the XDcfg_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XDcfg_CfgInitialize() API.
-*
-* <b>Interrupts</b>
-* The Driver implements an interrupt handler to support the interrupts provided
-* by this interface.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XDcfg driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-* </pre>
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
deleted file mode 100644
index c506ca59fc936b96086d96b074f85bee0959c104..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_3
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-* </pre>
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H /* prevent circular inclusions */
-#define XDCFG_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
- * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
- * Secure Reset
- */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
- * Reset FPGA
- */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
- * to FPGA every 4 PCAP
- * cycles
- */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
- * Status mask
- */
-#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
- * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
- * USER_MODE
- */
-#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
- * security config
- * including: DAP_En,
- * DBGEN,,
- * NIDEN, SPNIEN
- */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
- * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
- * Threshold Mask
- */
-#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
- * Mask
- */
-#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
- * clock edge
- */
-#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
- * clock edge
- */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
- * increment mask
- */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
- * address increment
- * mask
- */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
- * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
- * HIZ
- */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
- * done
- */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
- * configuration
- */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
- * reset
- */
-#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
- * or Data or response
- * timeout
- */
-#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
- * error
- */
-#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
- * response timeout
- */
-#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
- * error
- */
-#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
- * threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
- * threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
- * overflow
- */
-#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
- * transfers Done
- */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
- * length error
- */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
- * of Init Signal
- */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
- * of Init Signal
- */
-#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
- XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
- * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
- * Queue full
- */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
- * Queue empty
- */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
- * completed DMA
- * transfers
- */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
- * during HIZ
- */
-#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
- * done
- */
-#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
- * config
- */
-#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
- * POR Status
- */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
- * access
- */
-#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
- * reset status
- */
-#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
- * Status
- */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
- /**< BBRAM key
- * disable
- */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
- * Enable Status
- */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
- * Disable
- * status
- */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
- * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
- * address
- */
-#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps.h
deleted file mode 100644
index 5a0c1a28e3d1a6a35a13ffe728420c260da05f5b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps.h
-* @addtogroup dmaps_v2_3
-* @{
-* @details
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-/**
- * To avoid linking error,Declare all inline functions as extern for
- * IAR compiler
- */
-#ifdef __ICCARM__
-extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
-extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
deleted file mode 100644
index 628f1ec4f92b9a685afcb900029ac9d3d41c89fa..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_3
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps.h
deleted file mode 100644
index 6d4b15b24338a4618844512250528f0c1fc1897a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps.h
+++ /dev/null
@@ -1,809 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_7
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * <b>Driver Description</b>
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * <b>Initialization & Configuration</b>
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * <b>Interrupts and Asynchronous Callbacks</b>
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * <b>Virtual Memory</b>
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * <b>DMA</b>
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not suppoted from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * <b>Alignment & Data Cache Restrictions</b>
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * <b>Buffer Copying</b>
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * <b>Checksum Offloading</b>
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * <b>PHY Interfaces</b>
- *
- * RGMII 1.3 is the only interface supported.
- *
- * <b>Asserts</b>
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- *
- * </pre>
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * paramter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h
deleted file mode 100644
index 83f9a87fc1e6b6411f50a38931636c0a20f1144c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h
+++ /dev/null
@@ -1,804 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_7
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * <b>Buffer Descriptors</b>
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * <b>Performance</b>
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- *
- * </pre>
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include <string.h>
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within recevie BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
deleted file mode 100644
index b89e89885b9109f3db432b7592b1d71dd8c6e88d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.h
-* @addtogroup emacps_v3_7
-* @{
-*
-* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
-* DMA functionalities.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h
deleted file mode 100644
index e535470c2e5b0c663b26a7780c0e2c42ccdb5edb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_7
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
- transmitted */
-#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
- */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv.h
deleted file mode 100644
index 3d97bebd450eda76d8221c8a9b012bb723c9b6ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h
deleted file mode 100644
index f18601874bb5b8a84f10954730b4aca1bc988598..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include <string.h>
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implemention MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- * <br><br>
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio.h
deleted file mode 100644
index 582d94a76e6c510583040cf343851f3d50a5c556..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_3
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-*
-* </pre>
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /* Unique ID of device */
- UINTPTR BaseAddress; /* Device base address */
- int InterruptPresent; /* Are interrupts supported in h/w */
- int IsDual; /* Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /* Device base address */
- u32 IsReady; /* Device is initialized and ready */
- int InterruptPresent; /* Are interrupts supported in h/w */
- int IsDual; /* Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio_l.h
deleted file mode 100644
index 153fdfdf1674accc10904d2238d48db83ea4adae..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio_l.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_3
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/* @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/*@}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
-/*@}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32
-#define XGpio_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops.h
deleted file mode 100644
index fda562d9190651d7a655d00c57d930d13fad5232..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops.h
+++ /dev/null
@@ -1,277 +0,0 @@
-
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_3
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* <b>Driver Description</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* <b>Interrupts</b>
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* <b>Threads</b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b>Asserts</b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b>Building the driver</b>
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* </pre>
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/*@}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
-} XGpioPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
deleted file mode 100644
index ff01906750193cf49b097c7921a0c38c516c4641..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_3
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* </pre>
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
-/* @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
-/* @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(u32 BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps.h
deleted file mode 100644
index d3713de471faaa1242d156a58b25ab89ced025b7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps.h
-* @addtogroup iicps_v3_7
-* @{
-* @details
-*
-* This is an implementation of IIC driver in the PS block. The device can
-* be either a master or a slave on the IIC bus. This implementation supports
-* both interrupt mode transfer and polled mode transfer. Only 7-bit address
-* is used in the driver, although the hardware also supports 10-bit address.
-*
-* IIC is a 2-wire serial interface. The master controls the clock, so it can
-* regulate when it wants to send or receive data. The slave is under control of
-* the master, it must respond quickly since it has no control of the clock and
-* must send/receive data as fast or as slow as the master does.
-*
-* The higher level software must implement a higher layer protocol to inform
-* the slave what to send to the master.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XIicPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
-* the static configuration structure defined in xiicps_g.c. This is
-* setup by the tools. For some operating systems the config structure
-* will be initialized by the software and this call is not needed.
-*
-* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a
-* system with address translation, the provided virtual memory base
-* address replaces the physical address in the configuration
-* structure.
-*
-* <b>Multiple Masters</b>
-*
-* More than one master can exist, bus arbitration is defined in the IIC
-* standard. Lost of arbitration causes arbitration loss interrupt on the device.
-*
-* <b>Multiple Slaves</b>
-*
-* Multiple slaves are supported by selecting them with unique addresses. It is
-* up to the system designer to be sure all devices on the IIC bus have
-* unique addresses.
-*
-* <b>Addressing</b>
-*
-* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
-* ability to control which address size is sent in messages as a master to a
-* slave device.
-*
-* <b>FIFO Size </b>
-* The hardware FIFO is 32 bytes deep. The user must know the limitations of
-* other IIC devices on the bus. Some are only able to receive a limited number
-* of bytes in a single transfer.
-*
-* <b>Data Rates</b>
-*
-* The data rate is set by values in the control register. The formula for
-* determining the correct register values is:
-* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
-*
-* When the device is configured as a slave, the slck setting controls the
-* sample rate and so must be set to be at least as fast as the fastest scl
-* expected to be seen in the system.
-*
-* <b>Polled Mode Operation</b>
-*
-* This driver supports polled mode transfers.
-*
-* <b>Interrupts</b>
-*
-* The user must connect the interrupt handler of the driver,
-* XIicPs_InterruptHandler to an interrupt system such that it will be called
-* when an interrupt occurs. This function does not save and restore the
-* processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Transfer complete
-* - More Data
-* - Transfer not Acknowledged
-* - Transfer Time out
-* - Monitored slave ready - master mode only
-* - Receive Overflow
-* - Transmit FIFO overflow
-* - Receive FIFO underflow
-* - Arbitration lost
-*
-* <b>Bus Busy</b>
-*
-* Bus busy is checked before the setup of a master mode device, to avoid
-* unnecessary arbitration loss interrupt.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied by
-* the layer above this driver.
-*
-*<b>Repeated Start</b>
-*
-* The I2C controller does not indicate completion of a receive transfer if HOLD
-* bit is set. Due to this errata, repeated start cannot be used if a receive
-* transfer is followed by any other transfer.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00a drg/jz 01/30/08 First release
-* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
-* XIicPs_ClearOptions where the InstancePtr->Options
-* was not updated correctly.
-* Updated the InstancePtr->Options in the
-* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
-* Updated the XIicPs_SetupMaster to not check for
-* Bus Busy condition when the Hold Bit is set.
-* Removed some unused variables.
-* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
-* check for transfer completion is added, which indicates
-* the completion of current transfer.
-* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
-* to achieve I2C clock with minimum error for
-* CR #674195
-* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
-* This is fix for CR#704398 to remove warning.
-* 2.0 hk 03/07/14 Added check for error status in the while loop that
-* checks for completion.
-* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
-* Limited frequency set when 100KHz or 400KHz is
-* selected. This is a hardware limitation. CR#779290.
-* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
-* Explicitly reset CR and clear FIFO in Abort function
-* and state the same in the comments. CR# 784254.
-* Fix for CR# 761060 - provision for repeated start.
-* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
-* read mode and clear transfer size register.
-* Disable NACK to avoid interrupts on each retry.
-* 2.3 sk 10/07/14 Repeated start feature deleted.
-* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
-* in XIicPs_Reset.
-* 12/06/14 Implemented Repeated start feature.
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* 02/18/15 Implemented larger data transfer using repeated start
-* in Zynq UltraScale MP.
-* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
-* as per the other examples (CR#997545)
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIICPS_H /* prevent circular inclusions */
-#define XIICPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xiicps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options may be specified or retrieved for the device and
- * enable/disable additional features of the IIC. Each of the options
- * are bit fields, so more than one may be specified.
- *
- * @{
- */
-#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
-#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
-#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
-#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to an application
- * event handler from the driver. These constants are bit masks such that
- * more than one event can be passed to the handler.
- *
- * @{
- */
-#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
-#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
-#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
-#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
-#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
-#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
-#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
-#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
-#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
-#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
-/*@}*/
-
-/** @name Role constants
- *
- * These constants are used to pass into the device setup routines to
- * set up the device according to transfer direction.
- */
-#define SENDING_ROLE 1 /**< Transfer direction is sending */
-#define RECVING_ROLE 0 /**< Transfer direction is receiving */
-
-/* Maximum transfer size */
-#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
-
-/**************************** Type Definitions *******************************/
-
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* not important to the driver, so it is a void pointer.
-* @param StatusEvent indicates one or more status events that occurred.
-*/
-typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
-} XIicPs_Config;
-
-/**
- * The XIicPs driver instance data. The user is required to allocate a
- * variable of this type for each IIC device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XIicPs_Config Config; /* Configuration structure */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Options set in the device */
-
- u8 *SendBufferPtr; /* Pointer to send buffer */
- u8 *RecvBufferPtr; /* Pointer to recv buffer */
- s32 SendByteCount; /* Number of bytes still expected to send */
- s32 RecvByteCount; /* Number of bytes still expected to receive */
- s32 CurrByteCount; /* No. of bytes expected in current transfer */
-
- s32 UpdateTxSize; /* If tx size register has to be updated */
- s32 IsSend; /* Whether master is sending or receiving */
- s32 IsRepeatedStart; /* Indicates if user set repeated start */
-
- XIicPs_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XIicPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/*
-*
-* Place one byte into the transmit FIFO.
-*
-* @param InstancePtr is the instance of IIC
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_SendByte(XIicPs *InstancePtr)
-*
-*****************************************************************************/
-#define XIicPs_SendByte(InstancePtr) \
-{ \
- u8 Data; \
- Data = *((InstancePtr)->SendBufferPtr); \
- XIicPs_Out32((InstancePtr)->Config.BaseAddress \
- + (u32)(XIICPS_DATA_OFFSET), \
- (u32)(Data)); \
- (InstancePtr)->SendBufferPtr += 1; \
- (InstancePtr)->SendByteCount -= 1;\
-}
-
-/****************************************************************************/
-/*
-*
-* Receive one byte from FIFO.
-*
-* @param InstancePtr is the instance of IIC
-*
-* @return None.
-*
-* @note C-Style signature:
-* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
-*
-*****************************************************************************/
-#define XIicPs_RecvByte(InstancePtr) \
-{ \
- u8 *Data, Value; \
- Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
- + (u32)XIICPS_DATA_OFFSET)); \
- Data = &Value; \
- *(InstancePtr)->RecvBufferPtr = *Data; \
- (InstancePtr)->RecvBufferPtr += 1; \
- (InstancePtr)->RecvByteCount --; \
-}
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Function for configuration lookup, in xiicps_sinit.c
- */
-XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions for general setup, in xiicps.c
- */
-s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
- u32 EffectiveAddr);
-
-void XIicPs_Abort(XIicPs *InstancePtr);
-void XIicPs_Reset(XIicPs *InstancePtr);
-
-s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
-s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-/*
- * Functions for interrupts, in xiicps_intr.c
- */
-void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
- XIicPs_IntrHandler FunctionPtr);
-
-/*
- * Functions for device as master, in xiicps_master.c
- */
-void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
-void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
-void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
-
-/*
- * Functions for device as slave, in xiicps_slave.c
- */
-void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
-void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
-
-/*
- * Functions for selftest, in xiicps_selftest.c
- */
-s32 XIicPs_SelfTest(XIicPs *InstancePtr);
-
-/*
- * Functions for setting and getting data rate, in xiicps_options.c
- */
-s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
-s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
-u32 XIicPs_GetOptions(XIicPs *InstancePtr);
-
-s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
-u32 XIicPs_GetSClk(XIicPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h
deleted file mode 100644
index e9d63ec8f68e84d3d746dee4b0d7cabe4a6f9975..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_hw.h
-* @addtogroup iicps_v3_7
-* @{
-*
-* This header file contains the hardware definition for an IIC device.
-* It includes register definitions and interface functions to read/write
-* the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 1.04a kpc 11/07/13 Added function prototype.
-* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIICPS_HW_H /* prevent circular inclusions */
-#define XIICPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the IIC.
- * @{
- */
-#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
-#define XIICPS_SR_OFFSET 0x04U /**< Status */
-#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
-#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
-#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
-#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
-#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
-#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
-#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
-#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
-#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
-/* @} */
-
-/** @name Control Register
- *
- * This register contains various control bits that
- * affects the operation of the IIC controller. Read/Write.
- * @{
- */
-
-#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
-#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
-#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
-#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
-#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
-#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
-#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
-#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
- 0=terminate transfer */
-#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
- Master receiver*/
-#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
- 0=10 bit */
-#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
- 0=Slave */
-#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
- transfer 0=Transmitter,
- 1=Receiver*/
-#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
- register */
-/* @} */
-
-/** @name IIC Status Register
- *
- * This register is used to indicate status of the IIC controller. Read only
- * @{
- */
-#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
-#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
-#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
-#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
-#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
-/* @} */
-
-/** @name IIC Address Register
- *
- * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
- * A write access to this register always initiates a transfer if the IIC is in
- * master mode. Read/Write
- * @{
- */
-#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
-/* @} */
-
-/** @name IIC Data Register
- *
- * When written to, the data register sets data to transmit. When read from, the
- * data register reads the last received byte of data. Read/Write
- * @{
- */
-#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
-/* @} */
-
-/** @name IIC Interrupt Registers
- *
- * <b>IIC Interrupt Status Register</b>
- *
- * This register holds the interrupt status flags for the IIC controller. Some
- * of the flags are level triggered
- * - i.e. are set as long as the interrupt condition exists. Other flags are
- * edge triggered, which means they are set one the interrupt condition occurs
- * then remain set until they are cleared by software.
- * The interrupts are cleared by writing a one to the interrupt bit position
- * in the Interrupt Status Register. Read/Write.
- *
- * <b>IIC Interrupt Enable Register</b>
- *
- * This register is used to enable interrupt sources for the IIC controller.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * IIC Interrupt Mask register. Write only.
- *
- * <b>IIC Interrupt Disable Register </b>
- *
- * This register is used to disable interrupt sources for the IIC controller.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * IIC Interrupt Mask register. Write only.
- *
- * <b>IIC Interrupt Mask Register</b>
- *
- * This register shows the enabled/disabled status of each IIC controller
- * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
- * the status register. A bit set to 0 means the interrupt is enabled.
- * All mask bits are set and all interrupts are disabled after reset. Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Interrupt Status Register
- * @{
- */
-
-#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
- mask */
-#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
- Interrupt mask */
-#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
- Interrupt mask */
-#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
- mask */
-#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
- Interrupt mask */
-#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
- Interrupt mask */
-#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
-#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
-#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
- Interrupt mask */
-#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
-#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
-/* @} */
-
-
-/** @name IIC Transfer Size Register
-*
-* The register's meaning varies according to the operating mode as follows:
-* - Master transmitter mode: number of data bytes still not transmitted minus
-* one
-* - Master receiver mode: number of data bytes that are still expected to be
-* received
-* - Slave transmitter mode: number of bytes remaining in the FIFO after the
-* master terminates the transfer
-* - Slave receiver mode: number of valid data bytes in the FIFO
-*
-* This register is cleared if CLR_FIFO bit in the control register is set.
-* Read/Write
-* @{
-*/
-#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
-#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
-#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
-/* @} */
-
-
-/** @name IIC Slave Monitor Pause Register
-*
-* This register is associated with the slave monitor mode of the I2C interface.
-* It is meaningful only when the module is in master mode and bit SLVMON in the
-* control register is set.
-*
-* This register defines the pause interval between consecutive attempts to
-* address the slave once a write to an I2C address register is done by the
-* host. It represents the number of sclk cycles minus one between two attempts.
-*
-* The reset value of the register is 0, which results in the master repeatedly
-* trying to access the slave immediately after unsuccessful attempt.
-* Read/Write
-* @{
-*/
-#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
-/* @} */
-
-
-/** @name IIC Time Out Register
-*
-* The value of time out register represents the time out interval in number of
-* sclk cycles minus one.
-*
-* When the accessed slave holds the sclk line low for longer than the time out
-* period, thus prohibiting the I2C interface in master mode to complete the
-* current transfer, an interrupt is generated and TO interrupt flag is set.
-*
-* The reset value of the register is 0x1f.
-* Read/Write
-* @{
- */
-#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
-#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XIicPs_In32 Xil_In32
-#define XIicPs_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-* Read an IIC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to select the specific register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XIicPs_ReadReg(BaseAddress, RegOffset) \
- XIicPs_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write an IIC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to select the specific register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
-*
-******************************************************************************/
-#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/***************************************************************************/
-/**
-* Read the interrupt enable register.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return Current bit mask that represents currently enabled interrupts.
-*
-* @note C-Style signature:
-* u32 XIicPs_ReadIER(u32 BaseAddress)
-*
-******************************************************************************/
-#define XIicPs_ReadIER(BaseAddress) \
- XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
-
-/***************************************************************************/
-/**
-* Write to the interrupt enable register.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @param IntrMask is the interrupts to be enabled.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
-*
-******************************************************************************/
-#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
- XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
-
-/***************************************************************************/
-/**
-* Disable all interrupts.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
-*
-******************************************************************************/
-#define XIicPs_DisableAllInterrupts(BaseAddress) \
- XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
- XIICPS_IXR_ALL_INTR_MASK)
-
-/***************************************************************************/
-/**
-* Disable selected interrupts.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @param IntrMask is the interrupts to be disabled.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
-*
-******************************************************************************/
-#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
- XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
- (IntrMask))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the I2c interface
- */
-void XIicPs_ResetHw(u32 BaseAddress);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_assert.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_assert.h
deleted file mode 100644
index add4124e2c0c48a8844dfb3aad307c8ec5ae6e38..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_assert.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accomodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accomodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache.h
deleted file mode 100644
index b6614d5f992709379ce97da6e8be0cfb9eb80d8b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __GNUC__
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#elif defined (__ICCARM__)
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#endif
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h
deleted file mode 100644
index fa92c6b1c4087b05b80e256770a5c0d023d99fe2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
deleted file mode 100644
index 6e8cfa75fbfaa26744b0f9f9bf3114753dc9b5f8..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_errata.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_errata.h
deleted file mode 100644
index 490aebeabe7f0d17ed05105a8bfe9433f74515fd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_errata.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note
-* The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_exception.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_exception.h
deleted file mode 100644
index 83303875d43a0de16324293bade2e2050e7d1370..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_exception.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if !defined (__aarch64__) && !defined (ARMA53_32)
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_hal.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_hal.h
deleted file mode 100644
index d4434d07fa748457f2f476ebf82f9f8b20c93c91..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_hal.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_io.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_io.h
deleted file mode 100644
index 9c5aa43c7ecbc506145d0aaf5f409992bb08036e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_io.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* </pre>
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-u16 Xil_EndianSwap16(u16 Data);
-u32 Xil_EndianSwap32(u32 Data);
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_macroback.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_macroback.h
deleted file mode 100644
index ebafde87d7ff8a38bd28724a08ecca7701ea4f58..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_macroback.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*********************************************************************/
-/**
- * @file xil_macroback.h
- *
- * This header file is meant to bring back the removed _m macros.
- * This header file must be included last.
- * The following macros are not defined here due to the driver change:
- * XGpio_mSetDataDirection
- * XGpio_mGetDataReg
- * XGpio_mSetDataReg
- * XIIC_RESET
- * XIIC_CLEAR_STATS
- * XSpi_mReset
- * XSysAce_mSetCfgAddr
- * XSysAce_mIsCfgDone
- * XTft_mSetPixel
- * XTft_mGetPixel
- * XWdtTb_mEnableWdt
- * XWdtTb_mDisbleWdt
- * XWdtTb_mRestartWdt
- * XWdtTb_mGetTimebaseReg
- * XWdtTb_mHasReset
- *
- * Please refer the corresonding driver document for replacement.
- *
- *********************************************************************/
-
-#ifndef XIL_MACROBACK_H
-#define XIL_MACROBACK_H
-
-/*********************************************************************/
-/**
- * Macros for Driver XCan
- *
- *********************************************************************/
-#ifndef XCan_mReadReg
-#define XCan_mReadReg XCan_ReadReg
-#endif
-
-#ifndef XCan_mWriteReg
-#define XCan_mWriteReg XCan_WriteReg
-#endif
-
-#ifndef XCan_mIsTxDone
-#define XCan_mIsTxDone XCan_IsTxDone
-#endif
-
-#ifndef XCan_mIsTxFifoFull
-#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
-#endif
-
-#ifndef XCan_mIsHighPriorityBufFull
-#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
-#endif
-
-#ifndef XCan_mIsRxEmpty
-#define XCan_mIsRxEmpty XCan_IsRxEmpty
-#endif
-
-#ifndef XCan_mIsAcceptFilterBusy
-#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
-#endif
-
-#ifndef XCan_mCreateIdValue
-#define XCan_mCreateIdValue XCan_CreateIdValue
-#endif
-
-#ifndef XCan_mCreateDlcValue
-#define XCan_mCreateDlcValue XCan_CreateDlcValue
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDmaCentral
- *
- *********************************************************************/
-#ifndef XDmaCentral_mWriteReg
-#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
-#endif
-
-#ifndef XDmaCentral_mReadReg
-#define XDmaCentral_mReadReg XDmaCentral_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsAdc
- *
- *********************************************************************/
-#ifndef XDsAdc_mWriteReg
-#define XDsAdc_mWriteReg XDsAdc_WriteReg
-#endif
-
-#ifndef XDsAdc_mReadReg
-#define XDsAdc_mReadReg XDsAdc_ReadReg
-#endif
-
-#ifndef XDsAdc_mIsEmpty
-#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
-#endif
-
-#ifndef XDsAdc_mSetFstmReg
-#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
-#endif
-
-#ifndef XDsAdc_mGetFstmReg
-#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
-#endif
-
-#ifndef XDsAdc_mEnableConversion
-#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
-#endif
-
-#ifndef XDsAdc_mDisableConversion
-#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
-#endif
-
-#ifndef XDsAdc_mGetFifoOccyReg
-#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsDac
- *
- *********************************************************************/
-#ifndef XDsDac_mWriteReg
-#define XDsDac_mWriteReg XDsDac_WriteReg
-#endif
-
-#ifndef XDsDac_mReadReg
-#define XDsDac_mReadReg XDsDac_ReadReg
-#endif
-
-#ifndef XDsDac_mIsEmpty
-#define XDsDac_mIsEmpty XDsDac_IsEmpty
-#endif
-
-#ifndef XDsDac_mFifoIsFull
-#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
-#endif
-
-#ifndef XDsDac_mGetVacancy
-#define XDsDac_mGetVacancy XDsDac_GetVacancy
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XEmacLite
- *
- *********************************************************************/
-#ifndef XEmacLite_mReadReg
-#define XEmacLite_mReadReg XEmacLite_ReadReg
-#endif
-
-#ifndef XEmacLite_mWriteReg
-#define XEmacLite_mWriteReg XEmacLite_WriteReg
-#endif
-
-#ifndef XEmacLite_mGetTxStatus
-#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
-#endif
-
-#ifndef XEmacLite_mSetTxStatus
-#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
-#endif
-
-#ifndef XEmacLite_mGetRxStatus
-#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
-#endif
-
-#ifndef XEmacLite_mSetRxStatus
-#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
-#endif
-
-#ifndef XEmacLite_mIsTxDone
-#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
-#endif
-
-#ifndef XEmacLite_mIsRxEmpty
-#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
-#endif
-
-#ifndef XEmacLite_mNextTransmitAddr
-#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
-#endif
-
-#ifndef XEmacLite_mNextReceiveAddr
-#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
-#endif
-
-#ifndef XEmacLite_mIsMdioConfigured
-#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
-#endif
-
-#ifndef XEmacLite_mIsLoopbackConfigured
-#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
-#endif
-
-#ifndef XEmacLite_mGetReceiveDataLength
-#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
-#endif
-
-#ifndef XEmacLite_mGetTxActive
-#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
-#endif
-
-#ifndef XEmacLite_mSetTxActive
-#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XGpio
- *
- *********************************************************************/
-#ifndef XGpio_mWriteReg
-#define XGpio_mWriteReg XGpio_WriteReg
-#endif
-
-#ifndef XGpio_mReadReg
-#define XGpio_mReadReg XGpio_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XHwIcap
- *
- *********************************************************************/
-#ifndef XHwIcap_mFifoWrite
-#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
-#endif
-
-#ifndef XHwIcap_mFifoRead
-#define XHwIcap_mFifoRead XHwIcap_FifoRead
-#endif
-
-#ifndef XHwIcap_mSetSizeReg
-#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
-#endif
-
-#ifndef XHwIcap_mGetControlReg
-#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
-#endif
-
-#ifndef XHwIcap_mStartConfig
-#define XHwIcap_mStartConfig XHwIcap_StartConfig
-#endif
-
-#ifndef XHwIcap_mStartReadBack
-#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
-#endif
-
-#ifndef XHwIcap_mGetStatusReg
-#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
-#endif
-
-#ifndef XHwIcap_mIsTransferDone
-#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
-#endif
-
-#ifndef XHwIcap_mIsDeviceBusy
-#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
-#endif
-
-#ifndef XHwIcap_mIntrGlobalEnable
-#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
-#endif
-
-#ifndef XHwIcap_mIntrGlobalDisable
-#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
-#endif
-
-#ifndef XHwIcap_mIntrGetStatus
-#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
-#endif
-
-#ifndef XHwIcap_mIntrDisable
-#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
-#endif
-
-#ifndef XHwIcap_mIntrEnable
-#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
-#endif
-
-#ifndef XHwIcap_mIntrGetEnabled
-#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
-#endif
-
-#ifndef XHwIcap_mIntrClear
-#define XHwIcap_mIntrClear XHwIcap_IntrClear
-#endif
-
-#ifndef XHwIcap_mGetWrFifoVacancy
-#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
-#endif
-
-#ifndef XHwIcap_mGetRdFifoOccupancy
-#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
-#endif
-
-#ifndef XHwIcap_mSliceX2Col
-#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
-#endif
-
-#ifndef XHwIcap_mSliceY2Row
-#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
-#endif
-
-#ifndef XHwIcap_mSliceXY2Slice
-#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
-#endif
-
-#ifndef XHwIcap_mReadReg
-#define XHwIcap_mReadReg XHwIcap_ReadReg
-#endif
-
-#ifndef XHwIcap_mWriteReg
-#define XHwIcap_mWriteReg XHwIcap_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIic
- *
- *********************************************************************/
-#ifndef XIic_mReadReg
-#define XIic_mReadReg XIic_ReadReg
-#endif
-
-#ifndef XIic_mWriteReg
-#define XIic_mWriteReg XIic_WriteReg
-#endif
-
-#ifndef XIic_mEnterCriticalRegion
-#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIic_mExitCriticalRegion
-#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_GINTR_DISABLE
-#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIIC_GINTR_ENABLE
-#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_IS_GINTR_ENABLED
-#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
-#endif
-
-#ifndef XIIC_WRITE_IISR
-#define XIIC_WRITE_IISR XIic_WriteIisr
-#endif
-
-#ifndef XIIC_READ_IISR
-#define XIIC_READ_IISR XIic_ReadIisr
-#endif
-
-#ifndef XIIC_WRITE_IIER
-#define XIIC_WRITE_IIER XIic_WriteIier
-#endif
-
-#ifndef XIic_mClearIisr
-#define XIic_mClearIisr XIic_ClearIisr
-#endif
-
-#ifndef XIic_mSend7BitAddress
-#define XIic_mSend7BitAddress XIic_Send7BitAddress
-#endif
-
-#ifndef XIic_mDynSend7BitAddress
-#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
-#endif
-
-#ifndef XIic_mDynSendStartStopAddress
-#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
-#endif
-
-#ifndef XIic_mDynSendStop
-#define XIic_mDynSendStop XIic_DynSendStop
-#endif
-
-#ifndef XIic_mSend10BitAddrByte1
-#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
-#endif
-
-#ifndef XIic_mSend10BitAddrByte2
-#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
-#endif
-
-#ifndef XIic_mSend7BitAddr
-#define XIic_mSend7BitAddr XIic_Send7BitAddr
-#endif
-
-#ifndef XIic_mDisableIntr
-#define XIic_mDisableIntr XIic_DisableIntr
-#endif
-
-#ifndef XIic_mEnableIntr
-#define XIic_mEnableIntr XIic_EnableIntr
-#endif
-
-#ifndef XIic_mClearIntr
-#define XIic_mClearIntr XIic_ClearIntr
-#endif
-
-#ifndef XIic_mClearEnableIntr
-#define XIic_mClearEnableIntr XIic_ClearEnableIntr
-#endif
-
-#ifndef XIic_mFlushRxFifo
-#define XIic_mFlushRxFifo XIic_FlushRxFifo
-#endif
-
-#ifndef XIic_mFlushTxFifo
-#define XIic_mFlushTxFifo XIic_FlushTxFifo
-#endif
-
-#ifndef XIic_mReadRecvByte
-#define XIic_mReadRecvByte XIic_ReadRecvByte
-#endif
-
-#ifndef XIic_mWriteSendByte
-#define XIic_mWriteSendByte XIic_WriteSendByte
-#endif
-
-#ifndef XIic_mSetControlRegister
-#define XIic_mSetControlRegister XIic_SetControlRegister
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIntc
- *
- *********************************************************************/
-#ifndef XIntc_mMasterEnable
-#define XIntc_mMasterEnable XIntc_MasterEnable
-#endif
-
-#ifndef XIntc_mMasterDisable
-#define XIntc_mMasterDisable XIntc_MasterDisable
-#endif
-
-#ifndef XIntc_mEnableIntr
-#define XIntc_mEnableIntr XIntc_EnableIntr
-#endif
-
-#ifndef XIntc_mDisableIntr
-#define XIntc_mDisableIntr XIntc_DisableIntr
-#endif
-
-#ifndef XIntc_mAckIntr
-#define XIntc_mAckIntr XIntc_AckIntr
-#endif
-
-#ifndef XIntc_mGetIntrStatus
-#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XLlDma
- *
- *********************************************************************/
-#ifndef XLlDma_mBdRead
-#define XLlDma_mBdRead XLlDma_BdRead
-#endif
-
-#ifndef XLlDma_mBdWrite
-#define XLlDma_mBdWrite XLlDma_BdWrite
-#endif
-
-#ifndef XLlDma_mWriteReg
-#define XLlDma_mWriteReg XLlDma_WriteReg
-#endif
-
-#ifndef XLlDma_mReadReg
-#define XLlDma_mReadReg XLlDma_ReadReg
-#endif
-
-#ifndef XLlDma_mBdClear
-#define XLlDma_mBdClear XLlDma_BdClear
-#endif
-
-#ifndef XLlDma_mBdSetStsCtrl
-#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdGetStsCtrl
-#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdSetLength
-#define XLlDma_mBdSetLength XLlDma_BdSetLength
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mBdSetId
-#define XLlDma_mBdSetId XLlDma_BdSetId
-#endif
-
-#ifndef XLlDma_mBdGetId
-#define XLlDma_mBdGetId XLlDma_BdGetId
-#endif
-
-#ifndef XLlDma_mBdSetBufAddr
-#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetBufAddr
-#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mGetTxRing
-#define XLlDma_mGetTxRing XLlDma_GetTxRing
-#endif
-
-#ifndef XLlDma_mGetRxRing
-#define XLlDma_mGetRxRing XLlDma_GetRxRing
-#endif
-
-#ifndef XLlDma_mGetCr
-#define XLlDma_mGetCr XLlDma_GetCr
-#endif
-
-#ifndef XLlDma_mSetCr
-#define XLlDma_mSetCr XLlDma_SetCr
-#endif
-
-#ifndef XLlDma_mBdRingCntCalc
-#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
-#endif
-
-#ifndef XLlDma_mBdRingMemCalc
-#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
-#endif
-
-#ifndef XLlDma_mBdRingGetCnt
-#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
-#endif
-
-#ifndef XLlDma_mBdRingGetFreeCnt
-#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
-#endif
-
-#ifndef XLlDma_mBdRingSnapShotCurrBd
-#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
-#endif
-
-#ifndef XLlDma_mBdRingNext
-#define XLlDma_mBdRingNext XLlDma_BdRingNext
-#endif
-
-#ifndef XLlDma_mBdRingPrev
-#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
-#endif
-
-#ifndef XLlDma_mBdRingGetSr
-#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
-#endif
-
-#ifndef XLlDma_mBdRingSetSr
-#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
-#endif
-
-#ifndef XLlDma_mBdRingGetCr
-#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
-#endif
-
-#ifndef XLlDma_mBdRingSetCr
-#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
-#endif
-
-#ifndef XLlDma_mBdRingBusy
-#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
-#endif
-
-#ifndef XLlDma_mBdRingIntEnable
-#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
-#endif
-
-#ifndef XLlDma_mBdRingIntDisable
-#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
-#endif
-
-#ifndef XLlDma_mBdRingIntGetEnabled
-#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
-#endif
-
-#ifndef XLlDma_mBdRingGetIrq
-#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
-#endif
-
-#ifndef XLlDma_mBdRingAckIrq
-#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMbox
- *
- *********************************************************************/
-#ifndef XMbox_mWriteReg
-#define XMbox_mWriteReg XMbox_WriteReg
-#endif
-
-#ifndef XMbox_mReadReg
-#define XMbox_mReadReg XMbox_ReadReg
-#endif
-
-#ifndef XMbox_mWriteMBox
-#define XMbox_mWriteMBox XMbox_WriteMBox
-#endif
-
-#ifndef XMbox_mReadMBox
-#define XMbox_mReadMBox XMbox_ReadMBox
-#endif
-
-#ifndef XMbox_mFSLReadMBox
-#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
-#endif
-
-#ifndef XMbox_mFSLWriteMBox
-#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
-#endif
-
-#ifndef XMbox_mFSLIsEmpty
-#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
-#endif
-
-#ifndef XMbox_mFSLIsFull
-#define XMbox_mFSLIsFull XMbox_FSLIsFull
-#endif
-
-#ifndef XMbox_mIsEmpty
-#define XMbox_mIsEmpty XMbox_IsEmptyHw
-#endif
-
-#ifndef XMbox_mIsFull
-#define XMbox_mIsFull XMbox_IsFullHw
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMpmc
- *
- *********************************************************************/
-#ifndef XMpmc_mReadReg
-#define XMpmc_mReadReg XMpmc_ReadReg
-#endif
-
-#ifndef XMpmc_mWriteReg
-#define XMpmc_mWriteReg XMpmc_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMutex
- *
- *********************************************************************/
-#ifndef XMutex_mWriteReg
-#define XMutex_mWriteReg XMutex_WriteReg
-#endif
-
-#ifndef XMutex_mReadReg
-#define XMutex_mReadReg XMutex_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XPcie
- *
- *********************************************************************/
-#ifndef XPcie_mReadReg
-#define XPcie_mReadReg XPcie_ReadReg
-#endif
-
-#ifndef XPcie_mWriteReg
-#define XPcie_mWriteReg XPcie_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSpi
- *
- *********************************************************************/
-#ifndef XSpi_mIntrGlobalEnable
-#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
-#endif
-
-#ifndef XSpi_mIntrGlobalDisable
-#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
-#endif
-
-#ifndef XSpi_mIsIntrGlobalEnabled
-#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
-#endif
-
-#ifndef XSpi_mIntrGetStatus
-#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
-#endif
-
-#ifndef XSpi_mIntrClear
-#define XSpi_mIntrClear XSpi_IntrClear
-#endif
-
-#ifndef XSpi_mIntrEnable
-#define XSpi_mIntrEnable XSpi_IntrEnable
-#endif
-
-#ifndef XSpi_mIntrDisable
-#define XSpi_mIntrDisable XSpi_IntrDisable
-#endif
-
-#ifndef XSpi_mIntrGetEnabled
-#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
-#endif
-
-#ifndef XSpi_mSetControlReg
-#define XSpi_mSetControlReg XSpi_SetControlReg
-#endif
-
-#ifndef XSpi_mGetControlReg
-#define XSpi_mGetControlReg XSpi_GetControlReg
-#endif
-
-#ifndef XSpi_mGetStatusReg
-#define XSpi_mGetStatusReg XSpi_GetStatusReg
-#endif
-
-#ifndef XSpi_mSetSlaveSelectReg
-#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mGetSlaveSelectReg
-#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mEnable
-#define XSpi_mEnable XSpi_Enable
-#endif
-
-#ifndef XSpi_mDisable
-#define XSpi_mDisable XSpi_Disable
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysAce
- *
- *********************************************************************/
-#ifndef XSysAce_mGetControlReg
-#define XSysAce_mGetControlReg XSysAce_GetControlReg
-#endif
-
-#ifndef XSysAce_mSetControlReg
-#define XSysAce_mSetControlReg XSysAce_SetControlReg
-#endif
-
-#ifndef XSysAce_mOrControlReg
-#define XSysAce_mOrControlReg XSysAce_OrControlReg
-#endif
-
-#ifndef XSysAce_mAndControlReg
-#define XSysAce_mAndControlReg XSysAce_AndControlReg
-#endif
-
-#ifndef XSysAce_mGetErrorReg
-#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
-#endif
-
-#ifndef XSysAce_mGetStatusReg
-#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
-#endif
-
-#ifndef XSysAce_mWaitForLock
-#define XSysAce_mWaitForLock XSysAce_WaitForLock
-#endif
-
-#ifndef XSysAce_mEnableIntr
-#define XSysAce_mEnableIntr XSysAce_EnableIntr
-#endif
-
-#ifndef XSysAce_mDisableIntr
-#define XSysAce_mDisableIntr XSysAce_DisableIntr
-#endif
-
-#ifndef XSysAce_mIsReadyForCmd
-#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
-#endif
-
-#ifndef XSysAce_mIsMpuLocked
-#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
-#endif
-
-#ifndef XSysAce_mIsIntrEnabled
-#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysMon
- *
- *********************************************************************/
-#ifndef XSysMon_mIsEventSamplingModeSet
-#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
-#endif
-
-#ifndef XSysMon_mIsDrpBusy
-#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
-#endif
-
-#ifndef XSysMon_mIsDrpLocked
-#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
-#endif
-
-#ifndef XSysMon_mRawToTemperature
-#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
-#endif
-
-#ifndef XSysMon_mRawToVoltage
-#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
-#endif
-
-#ifndef XSysMon_mTemperatureToRaw
-#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
-#endif
-
-#ifndef XSysMon_mVoltageToRaw
-#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
-#endif
-
-#ifndef XSysMon_mReadReg
-#define XSysMon_mReadReg XSysMon_ReadReg
-#endif
-
-#ifndef XSysMon_mWriteReg
-#define XSysMon_mWriteReg XSysMon_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XTmrCtr
- *
- *********************************************************************/
-#ifndef XTimerCtr_mReadReg
-#define XTimerCtr_mReadReg XTimerCtr_ReadReg
-#endif
-
-#ifndef XTmrCtr_mWriteReg
-#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
-#endif
-
-#ifndef XTmrCtr_mSetControlStatusReg
-#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetControlStatusReg
-#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetTimerCounterReg
-#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mSetLoadReg
-#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
-#endif
-
-#ifndef XTmrCtr_mGetLoadReg
-#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
-#endif
-
-#ifndef XTmrCtr_mEnable
-#define XTmrCtr_mEnable XTmrCtr_Enable
-#endif
-
-#ifndef XTmrCtr_mDisable
-#define XTmrCtr_mDisable XTmrCtr_Disable
-#endif
-
-#ifndef XTmrCtr_mEnableIntr
-#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
-#endif
-
-#ifndef XTmrCtr_mDisableIntr
-#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
-#endif
-
-#ifndef XTmrCtr_mLoadTimerCounterReg
-#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mHasEventOccurred
-#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartLite
- *
- *********************************************************************/
-#ifndef XUartLite_mUpdateStats
-#define XUartLite_mUpdateStats XUartLite_UpdateStats
-#endif
-
-#ifndef XUartLite_mWriteReg
-#define XUartLite_mWriteReg XUartLite_WriteReg
-#endif
-
-#ifndef XUartLite_mReadReg
-#define XUartLite_mReadReg XUartLite_ReadReg
-#endif
-
-#ifndef XUartLite_mClearStats
-#define XUartLite_mClearStats XUartLite_ClearStats
-#endif
-
-#ifndef XUartLite_mSetControlReg
-#define XUartLite_mSetControlReg XUartLite_SetControlReg
-#endif
-
-#ifndef XUartLite_mGetStatusReg
-#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
-#endif
-
-#ifndef XUartLite_mIsReceiveEmpty
-#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
-#endif
-
-#ifndef XUartLite_mIsTransmitFull
-#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
-#endif
-
-#ifndef XUartLite_mIsIntrEnabled
-#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
-#endif
-
-#ifndef XUartLite_mEnableIntr
-#define XUartLite_mEnableIntr XUartLite_EnableIntr
-#endif
-
-#ifndef XUartLite_mDisableIntr
-#define XUartLite_mDisableIntr XUartLite_DisableIntr
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartNs550
- *
- *********************************************************************/
-#ifndef XUartNs550_mUpdateStats
-#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
-#endif
-
-#ifndef XUartNs550_mReadReg
-#define XUartNs550_mReadReg XUartNs550_ReadReg
-#endif
-
-#ifndef XUartNs550_mWriteReg
-#define XUartNs550_mWriteReg XUartNs550_WriteReg
-#endif
-
-#ifndef XUartNs550_mClearStats
-#define XUartNs550_mClearStats XUartNs550_ClearStats
-#endif
-
-#ifndef XUartNs550_mGetLineStatusReg
-#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
-#endif
-
-#ifndef XUartNs550_mGetLineControlReg
-#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
-#endif
-
-#ifndef XUartNs550_mSetLineControlReg
-#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
-#endif
-
-#ifndef XUartNs550_mEnableIntr
-#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
-#endif
-
-#ifndef XUartNs550_mDisableIntr
-#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
-#endif
-
-#ifndef XUartNs550_mIsReceiveData
-#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
-#endif
-
-#ifndef XUartNs550_mIsTransmitEmpty
-#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUsb
- *
- *********************************************************************/
-#ifndef XUsb_mReadReg
-#define XUsb_mReadReg XUsb_ReadReg
-#endif
-
-#ifndef XUsb_mWriteReg
-#define XUsb_mWriteReg XUsb_WriteReg
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mem.h
deleted file mode 100644
index a2d5e6681d9b82f40e81baa106789d512da27f6b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mem.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-* </pre>
-*
-*****************************************************************************/
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
deleted file mode 100644
index c228c988eb3035912db6e0d906d41609afac4b38..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register defintions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mmu.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mmu.h
deleted file mode 100644
index dd14b63b7057e38c5df9eadbab636379d684e30e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mmu.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02 /* Strongly ordered */
-#define DEVICE_MEMORY 0xC06 /* Device memory */
-#define RESERVED 0x0 /* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE (~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a9_mmu_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_printf.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_printf.h
deleted file mode 100644
index 016ae3b2f6b40423b9efe6063e2282dc1d9ffb74..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_printf.h
+++ /dev/null
@@ -1,48 +0,0 @@
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <ctype.h>
-#include <string.h>
-#include <stdarg.h>
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
deleted file mode 100644
index 4bfac0ac46f7d9516516cb2c0dbc6c85977e2cac..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-*
-* </pre>
-*****************************************************************************/
-
-#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H /* by using protection macros */
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT 32U
-#define XSleep_ReadCounterVal Xil_In32
-#define XCntrVal u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT 16U
-#define XSleep_ReadCounterVal Xil_In16
-#define XCntrVal u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#define RST_LPD_IOU2 0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
- /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
- /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
- /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
- /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
- /**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
- /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-#endif /* XIL_SLEEPTIMER_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testcache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testcache.h
deleted file mode 100644
index c35e9a463f05d7fa7e176b96369f5af1493d3127..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testcache.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* @addtogroup common_test_utils
-* <h2>Cache test </h2>
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-* <pre>
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testio.h
deleted file mode 100644
index ad68ead6430fef3b1a961165119aca5b8c557652..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testio.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities
-* <h2>I/O test </h2>
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTIO_H /* prevent circular inclusions */
-#define XIL_TESTIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 0
-#define XIL_TESTIO_LE 1
-#define XIL_TESTIO_BE 2
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testmem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testmem.h
deleted file mode 100644
index c204728223b2c15e57d4e9f8afc944ad02a40c76..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testmem.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils
-*
-* <h2>Memory test</h2>
-*
-* The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
-#define XIL_TESTMEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE 1U
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS 0x00U
-#define XIL_TESTMEM_INCREMENT 0x01U
-#define XIL_TESTMEM_WALKONES 0x02U
-#define XIL_TESTMEM_WALKZEROS 0x03U
-#define XIL_TESTMEM_INVERSEADDR 0x04U
-#define XIL_TESTMEM_FIXEDPATTERN 0x05U
-#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-
-extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_types.h
deleted file mode 100644
index 8143aff1ea4481ade21acf41eba4c361096081a9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_types.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#include <stdint.h>
-#include <stddef.h>
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include <linux/types.h>
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc.h
deleted file mode 100644
index 735e26dd4df8663a93b4f22ce5eb5cd712bc6653..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
deleted file mode 100644
index 8d0a61f07d193f41dc887b73052a3be9b1b5b78f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* </pre>
-*
-******************************************************************************/
-
-#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
-#define L2CCCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants define the event codes for the event counters.
- */
-#define XL2CC_CO 0x1
-#define XL2CC_DRHIT 0x2
-#define XL2CC_DRREQ 0x3
-#define XL2CC_DWHIT 0x4
-#define XL2CC_DWREQ 0x5
-#define XL2CC_DWTREQ 0x6
-#define XL2CC_IRHIT 0x7
-#define XL2CC_IRREQ 0x8
-#define XL2CC_WA 0x9
-#define XL2CC_IPFALLOC 0xa
-#define XL2CC_EPFHIT 0xb
-#define XL2CC_EPFALLOC 0xc
-#define XL2CC_SRRCVD 0xd
-#define XL2CC_SRCONF 0xe
-#define XL2CC_EPFRCVD 0xf
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
-void XL2cc_EventCtrStart(void);
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* L2CCCOUNTER_H */
-/**
-* @} End of "addtogroup l2_event_counter_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters.h
deleted file mode 100644
index 7fa149261c84b349f2992182d0dcd155d3e8bdae..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters.h
+++ /dev/null
@@ -1,632 +0,0 @@
-#ifndef XPARAMETERS_H /* prevent circular inclusions */
-#define XPARAMETERS_H /* by using protection macros */
-
-/* Definition for CPU ID */
-#define XPAR_CPU_ID 0U
-
-/* Definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-#include "xparameters_ps.h"
-
-#define STDIN_BASEADDRESS 0xE0000000
-#define STDOUT_BASEADDRESS 0xE0000000
-
-/******************************************************************/
-
-/* Platform specific definitions */
-#define PLATFORM_ZYNQ
-
-/* Definitions for sleep timer configuration */
-#define XSLEEP_TIMER_IS_DEFAULT_TIMER
-
-
-/******************************************************************/
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver DEVCFG */
-#define XPAR_XDCFG_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
-#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
-#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
-#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
-#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Definitions for driver DMAPS */
-#define XPAR_XDMAPS_NUM_INSTANCES 2
-
-/* Definitions for peripheral PS7_DMA_NS */
-#define XPAR_PS7_DMA_NS_DEVICE_ID 0
-#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
-#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
-
-
-/* Definitions for peripheral PS7_DMA_S */
-#define XPAR_PS7_DMA_S_DEVICE_ID 1
-#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
-#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DMA_NS */
-#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
-#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
-#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
-
-/* Canonical definitions for peripheral PS7_DMA_S */
-#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
-#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
-#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver EMACPS */
-#define XPAR_XEMACPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_ETHERNET_0 */
-#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
-#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
-#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
-#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
-#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
-
-
-/******************************************************************/
-
-#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
-/* Canonical definitions for peripheral PS7_ETHERNET_0 */
-#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
-#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
-#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
-#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
-#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
-
-
-/******************************************************************/
-
-
-/* Definitions for peripheral PS7_AFI_0 */
-#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
-#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
-
-
-/* Definitions for peripheral PS7_AFI_1 */
-#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
-#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
-
-
-/* Definitions for peripheral PS7_AFI_2 */
-#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
-#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
-
-
-/* Definitions for peripheral PS7_AFI_3 */
-#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
-#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
-
-
-/* Definitions for peripheral PS7_DDRC_0 */
-#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
-#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
-
-
-/* Definitions for peripheral PS7_GLOBALTIMER_0 */
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
-
-
-/* Definitions for peripheral PS7_GPV_0 */
-#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
-#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
-
-
-/* Definitions for peripheral PS7_INTC_DIST_0 */
-#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
-#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
-
-
-/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
-
-
-/* Definitions for peripheral PS7_L2CACHEC_0 */
-#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Definitions for peripheral PS7_OCMC_0 */
-#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
-#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
-
-
-/* Definitions for peripheral PS7_PL310_0 */
-#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Definitions for peripheral PS7_PMU_0 */
-#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
-#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
-
-
-/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
-
-
-/* Definitions for peripheral PS7_RAM_0 */
-#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
-
-
-/* Definitions for peripheral PS7_RAM_1 */
-#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
-#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
-/* Definitions for peripheral PS7_SCUC_0 */
-#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
-#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
-
-
-/* Definitions for peripheral PS7_SLCR_0 */
-#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
-#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIO */
-#define XPAR_XGPIO_NUM_INSTANCES 4
-
-/* Definitions for peripheral AXI_GPIO_3 */
-#define XPAR_AXI_GPIO_3_BASEADDR 0x41230000
-#define XPAR_AXI_GPIO_3_HIGHADDR 0x4123FFFF
-#define XPAR_AXI_GPIO_3_DEVICE_ID 0
-#define XPAR_AXI_GPIO_3_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_3_IS_DUAL 0
-
-
-/* Definitions for peripheral AXI_GPIO_BTNS */
-#define XPAR_AXI_GPIO_BTNS_BASEADDR 0x41220000
-#define XPAR_AXI_GPIO_BTNS_HIGHADDR 0x4122FFFF
-#define XPAR_AXI_GPIO_BTNS_DEVICE_ID 1
-#define XPAR_AXI_GPIO_BTNS_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_BTNS_IS_DUAL 0
-
-
-/* Definitions for peripheral AXI_GPIO_LEDS */
-#define XPAR_AXI_GPIO_LEDS_BASEADDR 0x41210000
-#define XPAR_AXI_GPIO_LEDS_HIGHADDR 0x4121FFFF
-#define XPAR_AXI_GPIO_LEDS_DEVICE_ID 2
-#define XPAR_AXI_GPIO_LEDS_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_LEDS_IS_DUAL 0
-
-
-/* Definitions for peripheral AXI_GPIO_SWS */
-#define XPAR_AXI_GPIO_SWS_BASEADDR 0x41200000
-#define XPAR_AXI_GPIO_SWS_HIGHADDR 0x4120FFFF
-#define XPAR_AXI_GPIO_SWS_DEVICE_ID 3
-#define XPAR_AXI_GPIO_SWS_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_SWS_IS_DUAL 0
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral AXI_GPIO_3 */
-#define XPAR_GPIO_0_BASEADDR 0x41230000
-#define XPAR_GPIO_0_HIGHADDR 0x4123FFFF
-#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_3_DEVICE_ID
-#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_0_IS_DUAL 0
-
-/* Canonical definitions for peripheral AXI_GPIO_BTNS */
-#define XPAR_GPIO_1_BASEADDR 0x41220000
-#define XPAR_GPIO_1_HIGHADDR 0x4122FFFF
-#define XPAR_GPIO_1_DEVICE_ID XPAR_AXI_GPIO_BTNS_DEVICE_ID
-#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_1_IS_DUAL 0
-
-/* Canonical definitions for peripheral AXI_GPIO_LEDS */
-#define XPAR_GPIO_2_BASEADDR 0x41210000
-#define XPAR_GPIO_2_HIGHADDR 0x4121FFFF
-#define XPAR_GPIO_2_DEVICE_ID XPAR_AXI_GPIO_LEDS_DEVICE_ID
-#define XPAR_GPIO_2_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_2_IS_DUAL 0
-
-/* Canonical definitions for peripheral AXI_GPIO_SWS */
-#define XPAR_GPIO_3_BASEADDR 0x41200000
-#define XPAR_GPIO_3_HIGHADDR 0x4120FFFF
-#define XPAR_GPIO_3_DEVICE_ID XPAR_AXI_GPIO_SWS_DEVICE_ID
-#define XPAR_GPIO_3_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_3_IS_DUAL 0
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIOPS */
-#define XPAR_XGPIOPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_GPIO_0 */
-#define XPAR_PS7_GPIO_0_DEVICE_ID 0
-#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
-#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_GPIO_0 */
-#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
-#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
-#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver IICPS */
-#define XPAR_XIICPS_NUM_INSTANCES 2
-
-/* Definitions for peripheral PS7_I2C_0 */
-#define XPAR_PS7_I2C_0_DEVICE_ID 0
-#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
-#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
-#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
-
-
-/* Definitions for peripheral PS7_I2C_1 */
-#define XPAR_PS7_I2C_1_DEVICE_ID 1
-#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
-#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
-#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_I2C_0 */
-#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
-#define XPAR_XIICPS_0_BASEADDR 0xE0004000
-#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
-#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
-
-/* Canonical definitions for peripheral PS7_I2C_1 */
-#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
-#define XPAR_XIICPS_1_BASEADDR 0xE0005000
-#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
-#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
-
-
-/******************************************************************/
-
-/* Definitions for driver PWM_RECORDER */
-#define XPAR_PWM_RECORDER_NUM_INSTANCES 6
-
-/* Definitions for peripheral PWM_RECORDER_0 */
-#define XPAR_PWM_RECORDER_0_DEVICE_ID 0
-#define XPAR_PWM_RECORDER_0_S_AXI_BASEADDR 0x76EA0000
-#define XPAR_PWM_RECORDER_0_S_AXI_HIGHADDR 0x76EAFFFF
-
-
-/* Definitions for peripheral PWM_RECORDER_1 */
-#define XPAR_PWM_RECORDER_1_DEVICE_ID 1
-#define XPAR_PWM_RECORDER_1_S_AXI_BASEADDR 0x76E80000
-#define XPAR_PWM_RECORDER_1_S_AXI_HIGHADDR 0x76E8FFFF
-
-
-/* Definitions for peripheral PWM_RECORDER_2 */
-#define XPAR_PWM_RECORDER_2_DEVICE_ID 2
-#define XPAR_PWM_RECORDER_2_S_AXI_BASEADDR 0x76E60000
-#define XPAR_PWM_RECORDER_2_S_AXI_HIGHADDR 0x76E6FFFF
-
-
-/* Definitions for peripheral PWM_RECORDER_3 */
-#define XPAR_PWM_RECORDER_3_DEVICE_ID 3
-#define XPAR_PWM_RECORDER_3_S_AXI_BASEADDR 0x76E40000
-#define XPAR_PWM_RECORDER_3_S_AXI_HIGHADDR 0x76E4FFFF
-
-
-/* Definitions for peripheral PWM_RECORDER_4 */
-#define XPAR_PWM_RECORDER_4_DEVICE_ID 4
-#define XPAR_PWM_RECORDER_4_S_AXI_BASEADDR 0x76E20000
-#define XPAR_PWM_RECORDER_4_S_AXI_HIGHADDR 0x76E2FFFF
-
-
-/* Definitions for peripheral PWM_RECORDER_5 */
-#define XPAR_PWM_RECORDER_5_DEVICE_ID 5
-#define XPAR_PWM_RECORDER_5_S_AXI_BASEADDR 0x76E00000
-#define XPAR_PWM_RECORDER_5_S_AXI_HIGHADDR 0x76E0FFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver PWM_SIGNAL_OUT */
-#define XPAR_PWM_SIGNAL_OUT_NUM_INSTANCES 4
-
-/* Definitions for peripheral PWM_SIGNAL_OUT_0 */
-#define XPAR_PWM_SIGNAL_OUT_0_DEVICE_ID 0
-#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR 0x79460000
-#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_HIGHADDR 0x7946FFFF
-
-
-/* Definitions for peripheral PWM_SIGNAL_OUT_1 */
-#define XPAR_PWM_SIGNAL_OUT_1_DEVICE_ID 1
-#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR 0x79440000
-#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_HIGHADDR 0x7944FFFF
-
-
-/* Definitions for peripheral PWM_SIGNAL_OUT_2 */
-#define XPAR_PWM_SIGNAL_OUT_2_DEVICE_ID 2
-#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR 0x79420000
-#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_HIGHADDR 0x7942FFFF
-
-
-/* Definitions for peripheral PWM_SIGNAL_OUT_3 */
-#define XPAR_PWM_SIGNAL_OUT_3_DEVICE_ID 3
-#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR 0x79400000
-#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_HIGHADDR 0x7940FFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver QSPIPS */
-#define XPAR_XQSPIPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_QSPI_0 */
-#define XPAR_PS7_QSPI_0_DEVICE_ID 0
-#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
-#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
-#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_PS7_QSPI_0_QSPI_MODE 0
-#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_QSPI_0 */
-#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
-#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
-#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
-#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_XQSPIPS_0_QSPI_MODE 0
-#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUGIC */
-#define XPAR_XSCUGIC_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
-#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
-#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUTIMER */
-#define XPAR_XSCUTIMER_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
-#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
-#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUWDT */
-#define XPAR_XSCUWDT_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
-#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
-#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Definitions for driver SDPS */
-#define XPAR_XSDPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SD_0 */
-#define XPAR_PS7_SD_0_DEVICE_ID 0
-#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
-#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
-#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
-#define XPAR_PS7_SD_0_HAS_CD 1
-#define XPAR_PS7_SD_0_HAS_WP 0
-#define XPAR_PS7_SD_0_BUS_WIDTH 0
-#define XPAR_PS7_SD_0_MIO_BANK 0
-#define XPAR_PS7_SD_0_HAS_EMIO 0
-
-
-/******************************************************************/
-
-#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
-/* Canonical definitions for peripheral PS7_SD_0 */
-#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
-#define XPAR_XSDPS_0_BASEADDR 0xE0100000
-#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
-#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
-#define XPAR_XSDPS_0_HAS_CD 1
-#define XPAR_XSDPS_0_HAS_WP 0
-#define XPAR_XSDPS_0_BUS_WIDTH 0
-#define XPAR_XSDPS_0_MIO_BANK 0
-#define XPAR_XSDPS_0_HAS_EMIO 0
-
-
-/******************************************************************/
-
-/* Definitions for driver TMRCTR */
-#define XPAR_XTMRCTR_NUM_INSTANCES 1U
-
-/* Definitions for peripheral AXI_TIMER_0 */
-#define XPAR_AXI_TIMER_0_DEVICE_ID 0U
-#define XPAR_AXI_TIMER_0_BASEADDR 0x42800000U
-#define XPAR_AXI_TIMER_0_HIGHADDR 0x4280FFFFU
-#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000U
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral AXI_TIMER_0 */
-#define XPAR_TMRCTR_0_DEVICE_ID 0U
-#define XPAR_TMRCTR_0_BASEADDR 0x42800000U
-#define XPAR_TMRCTR_0_HIGHADDR 0x4280FFFFU
-#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
-
-/******************************************************************/
-
-/* Definitions for driver UARTPS */
-#define XPAR_XUARTPS_NUM_INSTANCES 2
-
-/* Definitions for peripheral PS7_UART_0 */
-#define XPAR_PS7_UART_0_DEVICE_ID 0
-#define XPAR_PS7_UART_0_BASEADDR 0xE0000000
-#define XPAR_PS7_UART_0_HIGHADDR 0xE0000FFF
-#define XPAR_PS7_UART_0_UART_CLK_FREQ_HZ 100000000
-#define XPAR_PS7_UART_0_HAS_MODEM 0
-
-
-/* Definitions for peripheral PS7_UART_1 */
-#define XPAR_PS7_UART_1_DEVICE_ID 1
-#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
-#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
-#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
-#define XPAR_PS7_UART_1_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_UART_0 */
-#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_0_DEVICE_ID
-#define XPAR_XUARTPS_0_BASEADDR 0xE0000000
-#define XPAR_XUARTPS_0_HIGHADDR 0xE0000FFF
-#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
-#define XPAR_XUARTPS_0_HAS_MODEM 0
-
-/* Canonical definitions for peripheral PS7_UART_1 */
-#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
-#define XPAR_XUARTPS_1_BASEADDR 0xE0001000
-#define XPAR_XUARTPS_1_HIGHADDR 0xE0001FFF
-#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 100000000
-#define XPAR_XUARTPS_1_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Definitions for driver USBPS */
-#define XPAR_XUSBPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_USB_0 */
-#define XPAR_PS7_USB_0_DEVICE_ID 0
-#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
-#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_USB_0 */
-#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
-#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
-#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver XADCPS */
-#define XPAR_XADCPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_XADC_0 */
-#define XPAR_PS7_XADC_0_DEVICE_ID 0
-#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
-#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_XADC_0 */
-#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
-#define XPAR_XADCPS_0_BASEADDR 0xF8007100
-#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-/* Xilinx FAT File System Library (XilFFs) User Settings */
-#define FILE_SYSTEM_INTERFACE_SD
-#define FILE_SYSTEM_USE_MKFS
-#define FILE_SYSTEM_NUM_LOGIC_VOL 2
-#define FILE_SYSTEM_USE_STRFUNC 0
-#define FILE_SYSTEM_SET_FS_RPATH 0
-#define FILE_SYSTEM_WORD_ACCESS
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h
deleted file mode 100644
index 0fa77710d14ea0476deb274aaa458285bfb8cf84..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XPARAMETERS_PS_H_
-#define _XPARAMETERS_PS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************** Include Files *******************************/
-
-
-/************************** Constant Definitions *****************************/
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock
- */
-
-/* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR 0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
-
-/* Canonical definitions for Interrupts */
-#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
-#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
-#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
-#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
-#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
-
-
-#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
-#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
-
-
-
-/* Canonical definitions for DMAC */
-
-
-/* Canonical definitions for WDT */
-
-/* Canonical definitions for SLCR */
-#define XPAR_XSLCR_NUM_INSTANCES 1U
-#define XPAR_XSLCR_0_DEVICE_ID 0U
-#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
-
-/* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES 1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
-#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
-#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_ACK_BEFORE 0U
-
-/* Canonical definitions for Global Timer */
-#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
-#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
-#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
-#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
-
-
-/* Xilinx Parallel Flash Library (XilFlash) User Settings */
-#define XPAR_AXI_EMC
-
-
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock. These have been put for bacwards compatibilty
- */
-
-#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
-#define XPS_UART0_BASEADDR 0xE0000000U
-#define XPS_UART1_BASEADDR 0xE0001000U
-#define XPS_USB0_BASEADDR 0xE0002000U
-#define XPS_USB1_BASEADDR 0xE0003000U
-#define XPS_I2C0_BASEADDR 0xE0004000U
-#define XPS_I2C1_BASEADDR 0xE0005000U
-#define XPS_SPI0_BASEADDR 0xE0006000U
-#define XPS_SPI1_BASEADDR 0xE0007000U
-#define XPS_CAN0_BASEADDR 0xE0008000U
-#define XPS_CAN1_BASEADDR 0xE0009000U
-#define XPS_GPIO_BASEADDR 0xE000A000U
-#define XPS_GEM0_BASEADDR 0xE000B000U
-#define XPS_GEM1_BASEADDR 0xE000C000U
-#define XPS_QSPI_BASEADDR 0xE000D000U
-#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
-#define XPS_SDIO0_BASEADDR 0xE0100000U
-#define XPS_SDIO1_BASEADDR 0xE0101000U
-#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
-#define XPS_NAND_BASEADDR 0xE1000000U
-#define XPS_PARPORT0_BASEADDR 0xE2000000U
-#define XPS_PARPORT1_BASEADDR 0xE4000000U
-#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
-#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
-#define XPS_TTC0_BASEADDR 0xF8001000U
-#define XPS_TTC1_BASEADDR 0xF8002000U
-#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
-#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
-#define XPS_WDT_BASEADDR 0xF8005000U
-#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
-#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
-#define XPS_AFI0_BASEADDR 0xF8008000U
-#define XPS_AFI1_BASEADDR 0xF8009000U
-#define XPS_AFI2_BASEADDR 0xF800A000U
-#define XPS_AFI3_BASEADDR 0xF800B000U
-#define XPS_OCM_BASEADDR 0xF800C000U
-#define XPS_EFUSE_BASEADDR 0xF800D000U
-#define XPS_CORESIGHT_BASEADDR 0xF8800000U
-#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
-#define XPS_SCU_PERIPH_BASE 0xF8F00000U
-#define XPS_L2CC_BASEADDR 0xF8F02000U
-#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
-#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
-#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
-#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
-#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
-
-/* Shared Peripheral Interrupts (SPI) */
-#define XPS_CORE_PARITY0_INT_ID 32U
-#define XPS_CORE_PARITY1_INT_ID 33U
-#define XPS_L2CC_INT_ID 34U
-#define XPS_OCMINTR_INT_ID 35U
-#define XPS_ECC_INT_ID 36U
-#define XPS_PMU0_INT_ID 37U
-#define XPS_PMU1_INT_ID 38U
-#define XPS_SYSMON_INT_ID 39U
-#define XPS_DVC_INT_ID 40U
-#define XPS_WDT_INT_ID 41U
-#define XPS_TTC0_0_INT_ID 42U
-#define XPS_TTC0_1_INT_ID 43U
-#define XPS_TTC0_2_INT_ID 44U
-#define XPS_DMA0_ABORT_INT_ID 45U
-#define XPS_DMA0_INT_ID 46U
-#define XPS_DMA1_INT_ID 47U
-#define XPS_DMA2_INT_ID 48U
-#define XPS_DMA3_INT_ID 49U
-#define XPS_SMC_INT_ID 50U
-#define XPS_QSPI_INT_ID 51U
-#define XPS_GPIO_INT_ID 52U
-#define XPS_USB0_INT_ID 53U
-#define XPS_GEM0_INT_ID 54U
-#define XPS_GEM0_WAKE_INT_ID 55U
-#define XPS_SDIO0_INT_ID 56U
-#define XPS_I2C0_INT_ID 57U
-#define XPS_SPI0_INT_ID 58U
-#define XPS_UART0_INT_ID 59U
-#define XPS_CAN0_INT_ID 60U
-#define XPS_FPGA0_INT_ID 61U
-#define XPS_FPGA1_INT_ID 62U
-#define XPS_FPGA2_INT_ID 63U
-#define XPS_FPGA3_INT_ID 64U
-#define XPS_FPGA4_INT_ID 65U
-#define XPS_FPGA5_INT_ID 66U
-#define XPS_FPGA6_INT_ID 67U
-#define XPS_FPGA7_INT_ID 68U
-#define XPS_TTC1_0_INT_ID 69U
-#define XPS_TTC1_1_INT_ID 70U
-#define XPS_TTC1_2_INT_ID 71U
-#define XPS_DMA4_INT_ID 72U
-#define XPS_DMA5_INT_ID 73U
-#define XPS_DMA6_INT_ID 74U
-#define XPS_DMA7_INT_ID 75U
-#define XPS_USB1_INT_ID 76U
-#define XPS_GEM1_INT_ID 77U
-#define XPS_GEM1_WAKE_INT_ID 78U
-#define XPS_SDIO1_INT_ID 79U
-#define XPS_I2C1_INT_ID 80U
-#define XPS_SPI1_INT_ID 81U
-#define XPS_UART1_INT_ID 82U
-#define XPS_CAN1_INT_ID 83U
-#define XPS_FPGA8_INT_ID 84U
-#define XPS_FPGA9_INT_ID 85U
-#define XPS_FPGA10_INT_ID 86U
-#define XPS_FPGA11_INT_ID 87U
-#define XPS_FPGA12_INT_ID 88U
-#define XPS_FPGA13_INT_ID 89U
-#define XPS_FPGA14_INT_ID 90U
-#define XPS_FPGA15_INT_ID 91U
-
-/* Private Peripheral Interrupts (PPI) */
-#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
-#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
-#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
-#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
-#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
-
-
-/* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
-#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
-
-#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
-
-/* For backwards compatibilty */
-#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
-
-#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
-
-#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-#endif
-
-#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
-#endif
-
-#define XPAR_SCUTIMER_DEVICE_ID 0U
-#define XPAR_SCUWDT_DEVICE_ID 0U
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xplatform_info.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xplatform_info.h
deleted file mode 100644
index 0582222bc9d6b07a08f87199fc8f7622c6c3f6cb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xplatform_info.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
-#define XPLATFORM_INFO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define XPAR_CSU_VER_OFFSET 0x00000044U
-
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-
-#define XPLAT_INFO_MASK (0xF)
-#define XPLAT_INFO_SHIFT (0xC)
-#define XPS_VERSION_INFO_MASK (0xF)
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info();
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
-u32 XGetPSVersion_Info();
-#endif
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info();
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpm_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpm_counter.h
deleted file mode 100644
index 45f091982497d96d757ce80559712dbd227905e6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpm_counter.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include <stdint.h>
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface fuctions to access perfromance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
deleted file mode 100644
index 4ad9e5d73cf6aa041462b24325df210f40a23bd4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* </pre>
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
deleted file mode 100644
index 37971bc59d96983f89152b26e5bb97bdb58e62a5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
-#define XPSEUDO_ASM_GCC_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/* necessary for pre-processor */
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-#if defined (__aarch64__)
-/* pseudo assembler instructions */
-#define mfcpsr() ({u32 rval = 0U; \
- asm volatile("mrs %0, DAIF" : "=r" (rval));\
- rval;\
- })
-
-#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
-
-#define cpsiei() //__asm__ __volatile__("cpsie i\n")
-#define cpsidi() //__asm__ __volatile__("cpsid i\n")
-
-#define cpsief() //__asm__ __volatile__("cpsie f\n")
-#define cpsidf() //__asm__ __volatile__("cpsid f\n")
-
-
-
-#define mtgpr(rn, v) /*__asm__ __volatile__(\
- "mov r" stringify(rn) ", %0 \n"\
- : : "r" (v)\
- )*/
-
-#define mfgpr(rn) /*({u32 rval; \
- __asm__ __volatile__(\
- "mov %0,r" stringify(rn) "\n"\
- : "=r" (rval)\
- );\
- rval;\
- })*/
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb sy")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__("dsb sy")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__("dmb sy")
-
-
-/* Memory Operations */
-#define ldr(adr) ({u64 rval; \
- __asm__ __volatile__(\
- "ldr %0,[%1]"\
- : "=r" (rval) : "r" (adr)\
- );\
- rval;\
- })
-
-#define mfelrel3() ({u64 rval = 0U; \
- asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
- rval;\
- })
-
-#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
-
-#else
-
-/* pseudo assembler instructions */
-#define mfcpsr() ({u32 rval = 0U; \
- __asm__ __volatile__(\
- "mrs %0, cpsr\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
-
-#define mtcpsr(v) __asm__ __volatile__(\
- "msr cpsr,%0\n"\
- : : "r" (v)\
- )
-
-#define cpsiei() __asm__ __volatile__("cpsie i\n")
-#define cpsidi() __asm__ __volatile__("cpsid i\n")
-
-#define cpsief() __asm__ __volatile__("cpsie f\n")
-#define cpsidf() __asm__ __volatile__("cpsid f\n")
-
-
-
-#define mtgpr(rn, v) __asm__ __volatile__(\
- "mov r" stringify(rn) ", %0 \n"\
- : : "r" (v)\
- )
-
-#define mfgpr(rn) ({u32 rval; \
- __asm__ __volatile__(\
- "mov %0,r" stringify(rn) "\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
-
-
-/* Memory Operations */
-#define ldr(adr) ({u32 rval; \
- __asm__ __volatile__(\
- "ldr %0,[%1]"\
- : "=r" (rval) : "r" (adr)\
- );\
- rval;\
- })
-
-#endif
-
-#define ldrb(adr) ({u8 rval; \
- __asm__ __volatile__(\
- "ldrb %0,[%1]"\
- : "=r" (rval) : "r" (adr)\
- );\
- rval;\
- })
-
-#define str(adr, val) __asm__ __volatile__(\
- "str %0,[%1]\n"\
- : : "r" (val), "r" (adr)\
- )
-
-#define strb(adr, val) __asm__ __volatile__(\
- "strb %0,[%1]\n"\
- : : "r" (val), "r" (adr)\
- )
-
-/* Count leading zeroes (clz) */
-#define clz(arg) ({u8 rval; \
- __asm__ __volatile__(\
- "clz %0,%1"\
- : "=r" (rval) : "r" (arg)\
- );\
- rval;\
- })
-
-#if defined (__aarch64__)
-#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
-#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
-
-#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
-#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
-#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
-/* CP15 operations */
-#define mfcp(reg) ({u64 rval = 0U;\
- __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
- rval;\
- })
-
-#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
-
-#else
-/* CP15 operations */
-#define mtcp(rn, v) __asm__ __volatile__(\
- "mcr " rn "\n"\
- : : "r" (v)\
- );
-
-#define mfcp(rn) ({u32 rval = 0U; \
- __asm__ __volatile__(\
- "mrc " rn "\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
-#endif
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips.h
deleted file mode 100644
index 139ce4d3801b49f191a9b96ba36fa8f84a89f290..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips.h
+++ /dev/null
@@ -1,799 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_4
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* <b> Linear Mode </b>
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* <b>Multiple Masters</b>
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* <b>Modes of Operation</b>
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* <b>Interrupts</b>
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* <b>Polled Operation</b>
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* <b>Device Busy</b>
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* <b>Device Configuration</b>
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianess set to little-endian.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include <string.h>
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The <b>Active Low Clock option</b> configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The <b>Clock Phase option</b> configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The <b>Manual Start option</b> is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- RX FIFO full */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h
deleted file mode 100644
index 96c867ad3383fe4303731581d63f41db1ffb9231..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_4
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * <b>QSPI Status Register</b>
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * <b>QSPI Interrupt Enable Register</b>
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * <b>QSPI Interrupt Disable Register </b>
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * <b>QSPI Interrupt Mask Register</b>
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
deleted file mode 100644
index dc9a4ebd2c36ac3f03ad6816b05610129a6a7943..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XREG_CORTEXA9_H
-#define XREG_CORTEXA9_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* GPRs */
-#define XREG_GPR0 r0
-#define XREG_GPR1 r1
-#define XREG_GPR2 r2
-#define XREG_GPR3 r3
-#define XREG_GPR4 r4
-#define XREG_GPR5 r5
-#define XREG_GPR6 r6
-#define XREG_GPR7 r7
-#define XREG_GPR8 r8
-#define XREG_GPR9 r9
-#define XREG_GPR10 r10
-#define XREG_GPR11 r11
-#define XREG_GPR12 r12
-#define XREG_GPR13 r13
-#define XREG_GPR14 r14
-#define XREG_GPR15 r15
-#define XREG_CPSR cpsr
-
-/* Coprocessor number defines */
-#define XREG_CP0 0
-#define XREG_CP1 1
-#define XREG_CP2 2
-#define XREG_CP3 3
-#define XREG_CP4 4
-#define XREG_CP5 5
-#define XREG_CP6 6
-#define XREG_CP7 7
-#define XREG_CP8 8
-#define XREG_CP9 9
-#define XREG_CP10 10
-#define XREG_CP11 11
-#define XREG_CP12 12
-#define XREG_CP13 13
-#define XREG_CP14 14
-#define XREG_CP15 15
-
-/* Coprocessor control register defines */
-#define XREG_CR0 cr0
-#define XREG_CR1 cr1
-#define XREG_CR2 cr2
-#define XREG_CR3 cr3
-#define XREG_CR4 cr4
-#define XREG_CR5 cr5
-#define XREG_CR6 cr6
-#define XREG_CR7 cr7
-#define XREG_CR8 cr8
-#define XREG_CR9 cr9
-#define XREG_CR10 cr10
-#define XREG_CR11 cr11
-#define XREG_CR12 cr12
-#define XREG_CR13 cr13
-#define XREG_CR14 cr14
-#define XREG_CR15 cr15
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE 0x20
-#define XREG_CPSR_MODE_BITS 0x1F
-#define XREG_CPSR_SYSTEM_MODE 0x1F
-#define XREG_CPSR_UNDEFINED_MODE 0x1B
-#define XREG_CPSR_DATA_ABORT_MODE 0x17
-#define XREG_CPSR_SVC_MODE 0x13
-#define XREG_CPSR_IRQ_MODE 0x12
-#define XREG_CPSR_FIQ_MODE 0x11
-#define XREG_CPSR_USER_MODE 0x10
-
-#define XREG_CPSR_IRQ_ENABLE 0x80
-#define XREG_CPSR_FIQ_ENABLE 0x40
-
-#define XREG_CPSR_N_BIT 0x80000000
-#define XREG_CPSR_Z_BIT 0x40000000
-#define XREG_CPSR_C_BIT 0x20000000
-#define XREG_CPSR_V_BIT 0x10000000
-
-
-/* CP15 defines */
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
-#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
-#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
-
-#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
-#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
-
-#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
-#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
-#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
-#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
-#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
-
-#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
-#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
-#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
-
-#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
-#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
-#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
-
-#else /* RVCT */
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
-#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
-#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
-#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
-
-#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
-#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
-#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
-#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
-#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
-#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
-#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
-
-#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
-#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
-#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
-#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
-#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
-
-#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
-#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
-#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
-#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
-#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
-
-#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
-#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
-#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
-#endif
-
-/* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
-#define XREG_CP15_CONTROL_V_BIT 0x00002000U
-#define XREG_CP15_CONTROL_I_BIT 0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
-#define XREG_CP15_CONTROL_B_BIT 0x00000080U
-#define XREG_CP15_CONTROL_C_BIT 0x00000004U
-#define XREG_CP15_CONTROL_A_BIT 0x00000002U
-#define XREG_CP15_CONTROL_M_BIT 0x00000001U
-
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
-#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
-#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
-
-#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
-
-#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
-
-#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
-#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
-#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
-#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
-#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
-#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
-#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
-#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
-
-#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
-
-#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
-#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
-
-#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
-#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
-#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
-#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
-#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
-#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
-
-#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
-#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
-
-#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
-
-#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
-
-#else
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
-#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
-#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
-#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
-#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "cp15:0:c7:c0:4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
-
-#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
-
-#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
-#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
-
-#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
-#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
-#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
-#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
-#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
-#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
-#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
-#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
-#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
-#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
-#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
-#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
-#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
-#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
-
-#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
-#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
-#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
-
-#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
-#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
-
-#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
-#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
-#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
-#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
-#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
-#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
-
-#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
-#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
-
-#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
-
-#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
-#endif
-
-
-/* MPE register definitions */
-#define XREG_FPSID c0
-#define XREG_FPSCR c1
-#define XREG_MVFR1 c6
-#define XREG_MVFR0 c7
-#define XREG_FPEXC c8
-#define XREG_FPINST c9
-#define XREG_FPINST2 c10
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT (24)
-#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE (1<<23)
-#define XREG_FPSID_ARCH_BIT (16)
-#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT (8)
-#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT (4)
-#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT (0)
-#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT (1 << 31)
-#define XREG_FPSCR_Z_BIT (1 << 30)
-#define XREG_FPSCR_C_BIT (1 << 29)
-#define XREG_FPSCR_V_BIT (1 << 28)
-#define XREG_FPSCR_QC (1 << 27)
-#define XREG_FPSCR_AHP (1 << 26)
-#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
-#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
-#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
-#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
-#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
-#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
-#define XREG_FPSCR_RMODE_BIT (22)
-#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT (20)
-#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT (16)
-#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC (1 << 7)
-#define XREG_FPSCR_IXC (1 << 4)
-#define XREG_FPSCR_UFC (1 << 3)
-#define XREG_FPSCR_OFC (1 << 2)
-#define XREG_FPSCR_DZC (1 << 1)
-#define XREG_FPSCR_IOC (1 << 0)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT (28)
-#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT (24)
-#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT (20)
-#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT (16)
-#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT (12)
-#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT (8)
-#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT (4)
-#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT (0)
-#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX (1 << 31)
-#define XREG_FPEXC_EN (1 << 30)
-#define XREG_FPEXC_DEX (1 << 29)
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXA9_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic.h
deleted file mode 100644
index e22ee5bc283595250258993723a4d1b8aa28077b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v3_8
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-* - specific individual interrupt enabling/disabling
-* - specific individual interrupt acknowledging
-* - attaching specific callback function to handle interrupt source
-* - assigning desired priority to interrupt source if default is not
-* acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <b>Interrupt Vector Tables</b>
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs. The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* <b>Nested Interrupts Processing</b>
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET 0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
- Xil_InterruptHandler Handler;
- void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
- u16 DeviceId; /**< Unique ID of device */
- u32 CpuBaseAddress; /**< CPU Interface Register base address */
- u32 DistBaseAddress; /**< Distributor Register base address */
- XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
- Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
- XScuGic_Config *Config; /**< Configuration table entry */
- u32 IsReady; /**< Device is initialized and ready */
- u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
- (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32 XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h
deleted file mode 100644
index 08e65f456e41dcb0ea23b58e7bd3387a22cc6155..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h
+++ /dev/null
@@ -1,650 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v3_8
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef __ARM_NEON__
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
-#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
- Register */
-#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
- Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
- Register */
-#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
- Register */
-#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
- Register */
-#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
- Register */
-#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
- Register */
-#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
- Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
- Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
- 0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
- Register */
-#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
- Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
-#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
-/* @} */
-
-/** @name Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
-/* @} */
-
-/** @name Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
- Shared Peripheral
- Interrupts*/
-#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080. A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
- INT_ID */
-#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
- actually the lowest priority*/
-/* @} */
-
-/** @name SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI Read Only b10 always
- * PPI Read Only depending on how the PPIs are configured.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive
- * SPI LSB is read only.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
-/* @} */
-
-/** @name PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
-/* @} */
-
-/** @name SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
- input */
-/* @} */
-
-/** @name AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianess
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
- 1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
- 1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name Software Triggered Interrupt Register
- * Controls issueing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
- b00-Use the target List
- b01-All CPUs except requester
- b10-To Requester
- b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
- signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
- Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
- Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
- Binary Point Register */
-
-/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
- 0=separate registers,
- 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
- interrupts,
- 0= use IRQ for both,
- 1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-/** @name Priority Mask Register
- * Priority Mask register definitions
- * The CPU interface does not send interrupt if the level of the interrupt is
- * lower than the level of the register.
- * @{
- */
-/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
-/* @} */
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
- Value Secure Non-secure
- b000 0xFE 0xFF
- b001 0xFC 0xFE
- b010 0xF8 0xFC
- b011 0xF0 0xF8
- b100 0xE0 0xF0
- b101 0xC0 0xE0
- b110 0x80 0xC0
- b111 0x00 0x80
- */
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
-/* @} */
-
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interupt
- */
-#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
-/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param Register is the register offset for the clear/enable bank.
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
- ((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/****************************************************************************/
-/**
-*
-* Enable specific interrupt(s) in the interrupt controller.
-*
-* @param DistBaseAddress is the Distributor Register base address of the
-* device
-* @param Int_Id is the ID of the interrupt source and should be in the
-* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
- XScuGic_WriteReg((DistBaseAddress), \
- XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
- (0x00000001U << ((Int_Id) % 32U)))
-
-/****************************************************************************/
-/**
-*
-* Disable specific interrupt(s) in the interrupt controller.
-*
-* @param DistBaseAddress is the Distributor Register base address of the
-* device
-* @param Int_Id is the ID of the interrupt source and should be in the
-* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
- XScuGic_WriteReg((DistBaseAddress), \
- XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
- (0x00000001U << ((Int_Id) % 32U)))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32 XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer.h
deleted file mode 100644
index ea4ba79de086a74eb57b0ab5c22fe3441ee3ce1e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_1
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* <b> Interrupts </b>
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
deleted file mode 100644
index ac7b42934796aa41e49adfc510057e951e0b2e0d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_1
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt.h
deleted file mode 100644
index 372bbc3439aadbb94cf3fe04b97535757d4d1107..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_1
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* <b>Interrupts</b>
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /* prevent circular inclusions */
-#define XSCUWDT_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
deleted file mode 100644
index 2067d3a531870de0fe1851b65a2f653f58aa73f8..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_1
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
-#define XSCUWDT_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps.h
deleted file mode 100644
index b8d979d1d768214c5986d7899cbaa81ba5369c0d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_5
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Intialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in tranfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesytem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-*
-* </pre>
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include "xplatform_info.h"
-#include <string.h>
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
-#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
-
-/**************************** Type Definitions *******************************/
-
-typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u32 CardDetect; /**< Card Detect */
- u32 WriteProtect; /**< Write Protect */
- u32 BusWidth; /**< Bus Width */
- u32 BankNumber; /**< MIO Bank selection for SD */
- u32 HasEMIO; /**< If SD is connected to EMIO */
- u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
-} XSdPs_Config;
-
-/* ADMA2 descriptor table */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
-#ifdef __aarch64__
- u64 Address; /**< Address of current dma transfer */
-#else
- u32 Address; /**< Address of current dma transfer */
-#endif
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor;
-#pragma data_alignment = 4
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor;
-#endif
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XSdPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
- u32 Host_Caps; /**< Capabilities of host controller */
- u32 Host_CapsExt; /**< Extended Capabilities */
- u32 HCS; /**< High capacity support in card */
- u8 CardType; /**< Type of card - SD/MMC/eMMC */
- u8 Card_Version; /**< Card version */
- u8 HC_Version; /**< Host controller version */
- u8 BusWidth; /**< Current operating bus width */
- u32 BusSpeed; /**< Current operating bus speed */
- u8 Switch1v8; /**< 1.8V Switch support */
- u32 CardID[4]; /**< Card ID Register */
- u32 RelCardAddr; /**< Relative Card Address */
- u32 CardSpecData[4]; /**< Card Specific Data Register */
- u32 SectorCount; /**< Sector Count */
- u32 SdCardConfig; /**< Sd Card Configuration Register */
- u32 Mode; /**< Bus Speed Mode */
- XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
- /**< ADMA Descriptors */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
-#pragma data_alignment = 4
-#else
- XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Select_Card (XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
-void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps_hw.h
deleted file mode 100644
index c63d8f62afe518b28b3a3fadbeb820a323d9ee81..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps_hw.h
+++ /dev/null
@@ -1,1301 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_5
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/* @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/* @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
-#define XSDPS_CC_MAX_DIV_CNT 256U
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
-#define XSDPS_CC_EXT_DIV_SHIFT 6U
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U
-#define XSDPS_CC_DIV_SHIFT 8U
-
-/* @} */
-
-/** @name SD Interrupt Registers
- *
- * <b> Normal and Error Interrupt Status Register </b>
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * <b> Normal and Error Interrupt Status Enable Register </b>
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * <b> Normal and Error Interrupt Signal Enable Register </b>
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/* @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/* @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/* @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/* @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/* @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/* @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/* @} */
-
-/** @name Maximum Current Capablities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/* @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/* @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/* @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/* @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/* @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/* @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U
-#define XSDPS_HC_SPEC_V2 0x0001U
-#define XSDPS_HC_SPEC_V1 0x0000U
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U
-
-/* @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/* @} */
-
-/* Card Interface Conditions Definitions */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-
-/* Operation Conditions Register Definitions */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-
-/* SD Card Configuration Register Definitions */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-
-/* Card Status Register Definitions */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-
-/* Switch Function Definitions CMD6 */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-
-/* EXT_CSD field definitions */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/* @} */
-
-/* @400KHz, in usec */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
-#define XSDPS_CARD_DEF_ADDR 0x1234U
-
-#define XSDPS_CARD_SD 1U
-#define XSDPS_CARD_MMC 2U
-#define XSDPS_CARD_SDIO 3U
-#define XSDPS_CARD_SDCOMBO 4U
-#define XSDPS_CHIP_EMMC 5U
-
-
-/** @name ADMA2 Descriptor related definitions
- *
- * ADMA2 Descriptor related definitions
- * @{
- */
-
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/* @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U
-#define XSDPS_SCR_BLKSIZE 8U
-#define XSDPS_1_BIT_WIDTH 0x1U
-#define XSDPS_4_BIT_WIDTH 0x2U
-#define XSDPS_8_BIT_WIDTH 0x3U
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
-#define XSDPS_HIGH_SPEED_MODE 0x5U
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U
-#define XSDPS_HS200_MODE 0x7U
-#define XSDPS_DDR52_MODE 0x4U
-#define XSDPS_SWITCH_CMD_BLKCNT 1U
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
-#define XSDPS_TUNING_CMD_BLKCNT 1U
-#define XSDPS_TUNING_CMD_BLKSIZE 64U
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
-
-#define SD_DRIVER_TYPE_B 0x01U
-#define SD_DRIVER_TYPE_A 0x02U
-#define SD_DRIVER_TYPE_C 0x04U
-#define SD_DRIVER_TYPE_D 0x08U
-#define SD_SET_CURRENT_LIMIT_200 0U
-#define SD_SET_CURRENT_LIMIT_400 1U
-#define SD_SET_CURRENT_LIMIT_600 2U
-#define SD_SET_CURRENT_LIMIT_800 3U
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U
-/*
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U
-
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-
-#define XSDPS_SLOT_REM 0U
-#define XSDPS_SLOT_EMB 1U
-
-#define XSDPS_WIDTH_8 8U
-#define XSDPS_WIDTH_4 4U
-
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-
-#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD0_ITAPDLYSEL_SD50 0x00000014U
-#define SD0_OTAPDLYSEL_SD50 0x00000003U
-#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD0_ITAPDLYSEL_HSD 0x00000015U
-#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
-
-#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
-#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
-#define SD1_ITAPDLYSEL_SD50 0x00140000U
-#define SD1_OTAPDLYSEL_SD50 0x00030000U
-#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
-#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
-#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
-#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
-#define SD1_ITAPDLYSEL_HSD 0x00150000U
-#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
-#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
-
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64
-#define XSdPs_Out64 Xil_Out64
-
-#define XSdPs_In32 Xil_In32
-#define XSdPs_Out32 Xil_Out32
-
-#define XSdPs_In16 Xil_In16
-#define XSdPs_Out16 Xil_Out16
-
-#define XSdPs_In8 Xil_In8
-#define XSdPs_Out8 Xil_Out8
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xstatus.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xstatus.h
deleted file mode 100644
index 993747588d94aa9364dfacd1f14cd5970331d66a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xstatus.h
+++ /dev/null
@@ -1,535 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx® software status codes
-*
-* The xstatus.h file contains the Xilinx® software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtime_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtime_l.h
deleted file mode 100644
index 9b872b6cb696a54594707facec1b228bd9facc42..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtime_l.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
-#define GTIMER_CONTROL_OFFSET 0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr.h
deleted file mode 100644
index f30de60bc2a553deedbbf8ed5b1bbc0827125070..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr.h
-* @addtogroup tmrctr_v4_4
-* @{
-* @details
-*
-* The Xilinx timer/counter component. This component supports the Xilinx
-* timer/counter. More detailed description of the driver operation can
-* be found in the xtmrctr.c file.
-*
-* The Xilinx timer/counter supports the following features:
-* - Polled mode.
-* - Interrupt driven mode
-* - enabling and disabling specific timers
-* - PWM operation
-* - Cascade Operation (This is to be used for getting a 64 bit timer and this
-* feature is present in the latest versions of the axi_timer IP)
-*
-* The driver does not currently support the PWM operation of the device.
-*
-* The timer counter operates in 2 primary modes, compare and capture. In
-* either mode, the timer counter may count up or down, with up being the
-* default.
-*
-* Compare mode is typically used for creating a single time period or multiple
-* repeating time periods in the auto reload mode, such as a periodic interrupt.
-* When started, the timer counter loads an initial value, referred to as the
-* compare value, into the timer counter and starts counting down or up. The
-* timer counter expires when it rolls over/under depending upon the mode of
-* counting. An external compare output signal may be configured such that a
-* pulse is generated with this signal when it hits the compare value.
-*
-* Capture mode is typically used for measuring the time period between
-* external events. This mode uses an external capture input signal to cause
-* the value of the timer counter to be captured. When started, the timer
-* counter loads an initial value, referred to as the compare value,
-
-* The timer can be configured to either cause an interrupt when the count
-* reaches the compare value in compare mode or latch the current count
-* value in the capture register when an external input is asserted
-* in capture mode. The external capture input can be enabled/disabled using the
-* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
-* drive an external output when the compare value is reached in the count
-* register The external compare output can be enabled/disabled using the
-* XTmrCtr_SetOptions function.
-*
-* <b>Interrupts</b>
-*
-* It is the responsibility of the application to connect the interrupt
-* handler of the timer/counter to the interrupt source. The interrupt
-* handler function, XTmrCtr_InterruptHandler, is visible such that the user
-* can connect it to the interrupt source. Note that this interrupt handler
-* does not provide interrupt context save and restore processing, the user
-* must perform this processing.
-*
-* The driver services interrupts and passes timeouts to the upper layer
-* software through callback functions. The upper layer software must register
-* its callback functions during initialization. The driver requires callback
-* functions for timers.
-*
-* @note
-* The default settings for the timers are:
-* - Interrupt generation disabled
-* - Count up mode
-* - Compare mode
-* - Hold counter (will not reload the timer)
-* - External compare output disabled
-* - External capture input disabled
-* - Pulse width modulation disabled
-* - Timer disabled, waits for Start function to be called
-* <br><br>
-* A timer counter device may contain multiple timer counters. The symbol
-* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
-* The device currently contains 2 timer counters.
-* <br><br>
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta 03/21/07 Updated to new coding style.
-* 1.11a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-* for naming consistency (CR 559142).
-* 2.02a sdm 09/28/10 Updated the driver tcl to generate the xparameters
-* for the timer clock frequency (CR 572679).
-* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further
-* processing for CR 584557.
-* 2.04a sdm 07/12/11 Added support for cascade mode operation.
-* The cascade mode of operation is present in the latest
-* versions of the axi_timer IP. Please check the HW
-* Datasheet to see whether this feature is present in the
-* version of the IP that you are using.
-* 2.05a adk 15/05/13 Fixed the CR:693066
-* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-* XTmrCtr instance structure.
-* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-* the XTmrCtr_Start function.
-* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-* There will be no Initialization done in the
-* XTmrCtr_Initialize if both the timers have already started and
-* the XST_DEVICE_IS_STARTED Status is returned.
-* Removed the logic in the XTmrCtr_Initialize function
-* which was checking the Register Value to know whether
-* a timer has started or not.
-* 3.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.0 als 09/30/15 Updated initialization API.
-* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
-* Changed the prototype of XTmrCtr_CfgInitialize API.
-* 4.2 nsk 15/09/16 Updated tcl, to get correct device id for canonical defines,
-* when there exist more than one timer perepheral
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of tmrctr in xparameters.h
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_H /* prevent circular inclusions */
-#define XTMRCTR_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xtmrctr_l.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name Configuration options
- * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
- * @{
- */
-/**
- * Used to configure the timer counter device.
- * <pre>
- * XTC_CASCADE_MODE_OPTION Enables the Cascade Mode only valid for TCSRO.
- * XTC_ENABLE_ALL_OPTION Enables all timer counters at once.
- * XTC_DOWN_COUNT_OPTION Configures the timer counter to count down from
- * start value, the default is to count up.
- * XTC_CAPTURE_MODE_OPTION Configures the timer to capture the timer
- * counter value when the external capture line is
- * asserted. The default mode is compare mode.
- * XTC_INT_MODE_OPTION Enables the timer counter interrupt output.
- * XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer counter to
- * reload from the compare value. The default mode
- * causes the timer counter to hold when the
- * compare value is hit.
- * In capture mode, configures the timer counter to
- * not hold the previous capture value if a new
- * event occurs. The default mode cause the timer
- * counter to hold the capture value until
- * recognized.
- * XTC_EXT_COMPARE_OPTION Enables the external compare output signal.
- * </pre>
- */
-#define XTC_CASCADE_MODE_OPTION 0x00000080UL
-#define XTC_ENABLE_ALL_OPTION 0x00000040UL
-#define XTC_DOWN_COUNT_OPTION 0x00000020UL
-#define XTC_CAPTURE_MODE_OPTION 0x00000010UL
-#define XTC_INT_MODE_OPTION 0x00000008UL
-#define XTC_AUTO_RELOAD_OPTION 0x00000004UL
-#define XTC_EXT_COMPARE_OPTION 0x00000002UL
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Register base address */
- u32 SysClockFreqHz; /**< The AXI bus clock frequency */
-} XTmrCtr_Config;
-
-/**
- * Signature for the callback function.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the
- * upper layer when the callback is invoked. Its type is
- * unimportant to the driver, so it is a void pointer.
- * @param TmrCtrNumber is the number of the timer/counter within the
- * device. The device typically contains at least two
- * timer/counters. The timer number is a zero based number with a
- * range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
- */
-typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
-
-
-/**
- * Timer/Counter statistics
- */
-typedef struct {
- u32 Interrupts; /**< The number of interrupts that have occurred */
-} XTmrCtrStats;
-
-/**
- * The XTmrCtr driver instance data. The user is required to allocate a
- * variable of this type for every timer/counter device in the system. A
- * pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XTmrCtr_Config Config; /**< Core configuration. */
- XTmrCtrStats Stats; /**< Component Statistics */
- UINTPTR BaseAddress; /**< Base address of registers */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */
- u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */
-
- XTmrCtr_Handler Handler; /**< Callback function */
- void *CallBackRef; /**< Callback reference for handler */
-} XTmrCtr;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* Required functions, in file xtmrctr.c */
-void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
- UINTPTR EffectiveAddr);
-int XTmrCtr_InitHw(XTmrCtr *InstancePtr);
-int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
-void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
- u32 ResetValue);
-u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/* Lookup configuration in xtmrctr_sinit.c */
-XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
-
-/* Functions for options, in file xtmrctr_options.c */
-void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
-u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/* Functions for statistics, in file xtmrctr_stats.c */
-void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
-void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
-
-/* Functions for self-test, in file xtmrctr_selftest.c */
-int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/* Functions for interrupts, in file xtmrctr_intr.c */
-void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
- void *CallBackRef);
-void XTmrCtr_InterruptHandler(void *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr_i.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr_i.h
deleted file mode 100644
index b806f81f5693130465f7005a65d5a91380fa94ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr_i.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_i.h
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* This file contains data which is shared between files internal to the
-* XTmrCtr component. It is intended for internal use only.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 _m is removed from all the macro definitions.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_I_H /* prevent circular inclusions */
-#define XTMRCTR_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-extern u8 XTmrCtr_Offsets[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr_l.h
deleted file mode 100644
index 5842f5e9422617d01fa092a395d46bfed26e5fd5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtmrctr_l.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_l.h
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* High-level driver functions are defined in xtmrctr.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-* for naming consistency (CR 559142).
-* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the
-* cascade mode operation.
-* The cascade mode of operation is present in the latest
-* versions of the axi_timer IP. Please check the HW
-* Datasheet to see whether this feature is present in the
-* version of the IP that you are using.
-* 4.4 mus 07/21/17 Updated XTmrCtr_DisableIntr macro to not to clear
-* T0INT flag
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_L_H /* prevent circular inclusions */
-#define XTMRCTR_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * Defines the number of timer counters within a single hardware device. This
- * number is not currently parameterized in the hardware but may be in the
- * future.
- */
-#define XTC_DEVICE_TIMER_COUNT 2
-
-/* Each timer counter consumes 16 bytes of address space */
-
-#define XTC_TIMER_COUNTER_OFFSET 16
-
-/** @name Register Offset Definitions
- * Register offsets within a timer counter, there are multiple
- * timer counters within a single device
- * @{
- */
-
-#define XTC_TCSR_OFFSET 0 /**< Control/Status register */
-#define XTC_TLR_OFFSET 4 /**< Load register */
-#define XTC_TCR_OFFSET 8 /**< Timer counter register */
-
-/* @} */
-
-/** @name Control Status Register Bit Definitions
- * Control Status Register bit masks
- * Used to configure the timer counter device.
- * @{
- */
-
-#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */
-#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer
- counters */
-#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width
- Modulation */
-#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an
- interrupt has occured.
- If set and '1' is
- written to this bit
- position, bit is
- cleared. */
-#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the
- specific timer */
-#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt
- output. */
-#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using
- the load value provided
- earlier in the Load
- Register,
- XTC_TLR_OFFSET. */
-#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode,
- configures
- the timer counter to
- reload from the
- Load Register. The
- default mode
- causes the timer counter
- to hold when the compare
- value is hit. In capture
- mode, configures the
- timer counter to not
- hold the previous
- capture value if a new
- event occurs. The
- default mode cause the
- timer counter to hold
- the capture value until
- recognized. */
-#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the
- external input
- to the timer counter. */
-#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the
- external generate output
- for the timer. */
-#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer
- counter to count down
- from start value, the
- default is to count
- up.*/
-#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to
- capture the timer
- counter value when the
- external capture line is
- asserted. The default
- mode is compare mode.*/
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-extern u8 XTmrCtr_Offsets[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Read one of the timer counter registers.
-*
-* @param BaseAddress contains the base address of the timer counter
-* device.
-* @param TmrCtrNumber contains the specific timer counter within the
-* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegOffset contains the offset from the 1st register of the timer
-* counter to select the specific register of the timer counter.
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
- unsigned RegOffset);
-******************************************************************************/
-#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset))
-
-#ifndef XTimerCtr_ReadReg
-#define XTimerCtr_ReadReg XTmrCtr_ReadReg
-#endif
-
-/*****************************************************************************/
-/**
-* Write a specified value to a register of a timer counter.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegOffset contain the offset from the 1st register of the timer
-* counter to select the specific register of the timer counter.
-* @param ValueToWrite is the 32 bit value to be written to the register.
-*
-* @note C-Style signature:
-* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
-* unsigned RegOffset, u32 ValueToWrite);
-******************************************************************************/
-#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset)), (ValueToWrite))
-
-/****************************************************************************/
-/**
-*
-* Set the Control Status Register of a timer counter to the specified value.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegisterValue is the 32 bit value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
-* u8 TmrCtrNumber,u32 RegisterValue);
-*****************************************************************************/
-#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the Control Status Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
-* u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Get the Timer Counter Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
-* u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
-
-/****************************************************************************/
-/**
-*
-* Set the Load Register of a timer counter to the specified value.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegisterValue is the 32 bit value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
-* u32 RegisterValue);
-*****************************************************************************/
-#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the Load Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \
-XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable a timer counter such that it starts running.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
- XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable a timer counter such that it stops running.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
- XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
-
-/****************************************************************************/
-/**
-*
-* Enable the interrupt for a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the interrupt for a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) & ~ (XTC_CSR_ENABLE_INT_MASK \
- | XTC_CSR_INT_OCCURED_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Cause the timer counter to load it's Timer Counter Register with the value
-* in the Load Register.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
- u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
- XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Determine if a timer counter event has occurred. Events are defined to be
-* when a capture has occurred or the counter has roller over.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @note C-Style signature:
-* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \
- ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \
- XTC_CSR_INT_OCCURED_MASK)
-
-/************************** Function Prototypes ******************************/
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps.h
deleted file mode 100644
index 33758c23b3733d2ffce9e1b8a27bfbdc22e0f4d1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_5
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* <b>Initialization & Configuration</b>
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the parameter EffectiveAddr should be the
-* virtual address.
-*
-* <b>Baud Rate</b>
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. Ther input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-* <pre>
-* baud_rate = input_clock / (bgen * (bdiv + 1)
-* </pre>
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* <b>Interrupts</b>
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* <b>Data Transfer</b>
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-*
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 921600U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h
deleted file mode 100644
index 9a2bc430544035bcbde490106a1b9b1f2c4c09cd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h
+++ /dev/null
@@ -1,451 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_5
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H /* prevent circular inclusions */
-#define XUARTPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
-#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
-#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
-#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
-#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
-#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatabilty, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
-#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress) \
- !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress) \
- ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps.h
deleted file mode 100644
index b5c472ef9e3d912141993ac47da134013c9d3d06..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps.h
+++ /dev/null
@@ -1,1098 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xusbps.h
-* @addtogroup usbps_v2_4
-* @{
-* @details
- *
- * This file contains the implementation of the XUsbPs driver. It is the
- * driver for an USB controller in DEVICE or HOST mode.
- *
- * <h2>Introduction</h2>
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- * <h2>USB Controller Features</h2>
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- * <h2>Initialization & Configuration</h2>
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- * <h2>USB Device Endpoints</h2>
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- * <h2>Interrupt Handling</h2>
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler fucntions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- * <h2>Data buffer handling</h2>
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- * <h3>Zero copy</h3>
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- * <h2>DMA</h2>
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * </pre>
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
-
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the enpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occured on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
deleted file mode 100644
index 1cb0cfcd3e755d485abb3837c546125ee65b4418..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xusbps_endpoint.h
-* @addtogroup usbps_v2_4
-* @{
- *
- * This is an internal file containung the definitions for endpoints. It is
- * included by the xusbps_endpoint.c which is implementing the endpoint
- * functions and by xusbps_intr.c.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * </pre>
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h
deleted file mode 100644
index 69f3ebffb4fef5b1f9ff7ad459509df87b94882c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xusbps_hw.h
-* @addtogroup usbps_v2_4
-* @{
- *
- * This header file contains identifiers and low-level driver functions (or
- * macros) that can be used to access the device. High-level driver functions
- * are defined in xusbps.h.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * </pre>
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Regsiter offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
deleted file mode 100644
index 007162d8c2e9b11b94b26f6c2c791a9496f22d87..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner coresightps_dcc_comp_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling coresightps_dcc"
-
-coresightps_dcc_comp_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: coresightps_dcc_includes
-
-coresightps_dcc_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
deleted file mode 100644
index fca26ca2ec803781230884079bac6c232222947b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.c
-* @addtogroup coresightps_dcc_v1_4
-* @{
-*
-* Functions in this file are the minimum required functions for the
-* XCoreSightPs driver.
-*
-* @note None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.2 kvn 10/09/15 Add support for IAR Compiler.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifdef __MICROBLAZE__
-#warning "The driver is supported only for ARM architecture"
-#else
-
-#include <xil_types.h>
-#include <xpseudo_asm.h>
-
-#ifdef __ICCARM__
-#define INLINE
-#else
-#define INLINE __inline
-#endif
-
-/* DCC Status Bits */
-#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
-#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
-
-static INLINE u32 XCoresightPs_DccGetStatus(void);
-
-/****************************************************************************/
-/**
-*
-* This functions sends a single byte using the DCC. It is blocking in that it
-* waits for the transmitter to become non-full before it writes the byte to
-* the transmit register.
-*
-* @param BaseAddress is a dummy parameter to match the function proto
-* of functions for other stdio devices.
-* @param Data is the byte of data to send
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
-{
- (void) BaseAddress;
- while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
- dsb();
-#ifdef __aarch64__
- asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mcr p14, 0, %0, c0, c5, 0"
- : : "r" (Data));
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c5:0");
- Reg = Data;
- }
-#endif
- isb();
-
-}
-
-/****************************************************************************/
-/**
-*
-* This functions receives a single byte using the DCC. It is blocking in that
-* it waits for the receiver to become non-empty before it reads from the
-* receive register.
-*
-* @param BaseAddress is a dummy parameter to match the function proto
-* of functions for other stdio devices.
-*
-* @return The byte of data received.
-*
-* @note None.
-*
-******************************************************************************/
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
-{
- u8 Data = 0U;
- (void) BaseAddress;
-
- while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
- dsb();
-
-#ifdef __aarch64__
- asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mrc p14, 0, %0, c0, c5, 0"
- : "=r" (Data));
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c5:0");
- Data = Reg;
- }
-#endif
- isb();
-
- return Data;
-}
-
-
-/****************************************************************************/
-/**INLINE
-*
-* This functions read the status register of the DCC.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The contents of the Status Register.
-*
-* @note None.
-*
-******************************************************************************/
-static INLINE u32 XCoresightPs_DccGetStatus(void)
-{
- u32 Status = 0U;
-
-#ifdef __aarch64__
- asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mrc p14, 0, %0, c0, c1, 0"
- : "=r" (Status) : : "cc");
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c1:0");
- Status = Reg;
- }
-#endif
- return Status;
-#endif
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
deleted file mode 100644
index 67959e3274632a6ca7b5bd3225679cc0c3e1f10f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_4
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef __MICROBLAZE__
-#include <xil_types.h>
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile
deleted file mode 100644
index 7ea505c104e84321c18a0440179f06eb02bd72c5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I${INCLUDEDIR}
-
-OUTS = *.o
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-LIBSOURCES=*.c
-INCLUDEFILES=*.h
-
-libs:
- echo "Compiling cpu_cortexa9"
-
-.PHONY: include
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
deleted file mode 100644
index 95c8ba5360707e6032e28cfc4847ee9df969fd1c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_5
-* @{
-* @details
-*
-* dummy file
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
-* parameter of cpu_cortexa9 in xparameters.h
-******************************************************************************/
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
deleted file mode 100644
index 7b191dd922735c60827f378f0b5e70c922db76c9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xddrps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling ddrps"
-
-xddrps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xddrps_includes
-
-xddrps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
deleted file mode 100644
index c8804d2ed33d87cd0d678d73a63bb0ddedee86f1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*******************************************************************************
- *
- * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * Use of the Software is limited solely to applications:
- * (a) running on a Xilinx device, or
- * (b) that interact with a Xilinx device through a bus or interconnect.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Except as contained in this notice, the name of the Xilinx shall not be used
- * in advertising or otherwise to promote the sale, use or other dealings in
- * this Software without prior written authorization from Xilinx.
- *
-*******************************************************************************/
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_0
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note None.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- * </pre>
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
deleted file mode 100644
index 25ff740826e9f1dfe1de19d4602301ba9e400191..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xdevcfg_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling devcfg"
-
-xdevcfg_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xdevcfg_includes
-
-xdevcfg_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
deleted file mode 100644
index e9447e7e32f37a6d684164bd18db3087068aec2f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.c
-* @addtogroup devcfg_v3_5
-* @{
-*
-* This file contains the implementation of the interface functions for XDcfg
-* driver. Refer to the header file xdevcfg.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Updated the XDcfg_Transfer function to use the
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-*
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize the Device Config Interface driver. This function
-* must be called before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param ConfigPtr is the config structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note The very first APB access to the Device Configuration Interface
-* block needs to be a write to the UNLOCK register with the value
-* of 0x757BDF0D. This step is to be done once after reset, any
-* other APB access has to come after this. The APB access is
-* considered illegal if the step is not done or if it is done
-* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
-* the following additional actions would be carried out.
-* In other words, if all bits are low, the following steps are not
-* done.
-* 1. AES is disabled
-* 2. All APB writes disabled
-* 3. SoC debug fully enabled
-*
-******************************************************************************/
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Copy configuration into instance.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
- InstancePtr->IsStarted = 0;
-
-
- /* Unlock the Device Configuration Interface */
- XDcfg_Unlock(InstancePtr);
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* The functions enables the PCAP interface by setting the PCAP mode bit in the
-* control register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note Enable FPGA programming from PCAP interface. Enabling this bit
-* disables all the external interfaces from programming of FPGA
-* except for ICAP. The user needs to ensure that the FPGA is
-* programmed through either PCAP or ICAP.
-*
-*****************************************************************************/
-void XDcfg_EnablePCAP(XDcfg *InstancePtr)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The functions disables the PCAP interface by clearing the PCAP mode bit in
-* the control register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_DisablePCAP(XDcfg *InstancePtr)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the 32 bit mask data to be written to the Register.
-* The mask definitions are defined in the xdevcfg_hw.h file.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg | Mask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function Clears the specified bit positions of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the 32 bit value which holds the bit positions to be cleared.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg & ~Mask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Control
-* Register.
-* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Control Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Lock Register. These bits
-* can only be set to a 1. They will be cleared after a Power On Reset.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Lock Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Lock
-* Register.
-* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Lock Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Configuration Register with the
-* given value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Configuration Register with the
-* given value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Config
-* Register.
-* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Status
-* Register.
-* Use the XDCFG_STATUS_*_MASK constants defined in
-* xdevcfg_hw.h to interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Status Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the ROM Shadow Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note This register is can only be written and is used to control the
-* RAM shadow of 32 bit 4K page ROM pages in user mode
-*
-*****************************************************************************/
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
- Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Software ID Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return 32 Bit boot software ID.
-*
-* @note This register is locked for write once the system enters
-* usermode. Hence API for reading the register only is provided.
-*
-*****************************************************************************/
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Software ID Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the bit mask for the feature in Miscellaneous Control
-* Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the feature to be set.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
- (RegData | Mask));
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return 32 Bit boot software ID.
-*
-* @note This register is locked for write once the system enters
-* usermode. Hence API to reading the register only is provided.
-*
-*****************************************************************************/
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous Control Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
-}
-
-/******************************************************************************/
-/**
-*
-* This function checks if DMA command queue is full.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return XST_SUCCESS is the DMA is busy
-* XST_FAILURE if the DMA is idle
-*
-* @note The DMA queue has a depth of two.
-*
-****************************************************************************/
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
-{
-
- u32 RegData;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the PCAP status register for DMA status */
- RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_STATUS_OFFSET);
-
- if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
- XDCFG_STATUS_DMA_CMD_Q_F_MASK){
- return XST_SUCCESS;
- }
-
- return XST_FAILURE;
-}
-
-/******************************************************************************/
-/**
-*
-* This function initiates the DMA transfer.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-*
-* @return None.
-*
-* @note It is the responsibility of the caller function to ensure that
-* correct values are passed to this function.
-*
-* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
-* address when equal to 2�b01 indicates the last DMA command of
-* an overall transfer.
-*
-****************************************************************************/
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength)
-{
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_SRC_ADDR_OFFSET,
- SourcePtr);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_DEST_ADDR_OFFSET,
- DestPtr);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_SRC_LEN_OFFSET,
- SrcWordLength);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_DEST_LEN_OFFSET,
- DestWordLength);
-}
-
-/******************************************************************************/
-/**
-*
-* This function Implements the DMA Read Command. This command is used to
-* transfer the image data from FPGA to the external memory.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-*
-* @return - XST_INVALID_PARAM if source address/length is invalid.
-* - XST_SUCCESS if DMA transfer initiated properly.
-*
-* @note None.
-*
-****************************************************************************/
-static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
- u32 SrcWordLength, u32 DestPtr,
- u32 DestWordLength)
-{
- u32 IntrReg;
-
- /*
- * Send READ Frame command to FPGA
- */
- XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
- SrcWordLength, 0);
-
- /*
- * Store the enabled interrupts to enable before the actual read
- * transfer is initiated and Disable all the interrupts temporarily.
- */
- IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
- XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
-
- /*
- * Wait till you get the DMA done for the read command sent
- */
- while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET) &
- XDCFG_IXR_D_P_DONE_MASK) !=
- XDCFG_IXR_D_P_DONE_MASK);
- /*
- * Enable the previously stored Interrupts .
- */
- XDcfg_IntrEnable(InstancePtr, IntrReg);
-
- /*
- * Initiate the DMA write command.
- */
- XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
- 0, DestWordLength);
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function starts the DMA transfer. This function only starts the
-* operation and returns before the operation may be completed.
-* If the interrupt is enabled, an interrupt will be generated when the
-* operation is completed, otherwise it is necessary to poll the Status register
-* to determine when it is completed. It is the responsibility of the caller to
-* determine when the operation is completed by handling the generated interrupt
-* or polling the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-* @param TransferType contains the type of PCAP transfer being requested.
-* The definitions can be found in the xdevcfg.h file.
-* @return
-* - XST_SUCCESS.if DMA transfer initiated successfully
-* - XST_DEVICE_BUSY if DMA is busy
-* - XST_INVALID_PARAM if invalid Source / Destination address
-* is sent or an invalid Source / Destination length is
-* sent
-*
-* @note It is the responsibility of the caller to ensure that the cache
-* is flushed and invalidated both before the DMA operation is
-* started and after the DMA operation completes if the memory
-* pointed to is cached. The caller must also ensure that the
-* pointers contain physical address rather than a virtual address
-* if address translation is being used.
-*
-* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
-* address when equal to 2�b01 indicates the last DMA command of
-* an overall transfer.
-*
-*****************************************************************************/
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType)
-{
-
- u32 CtrlReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Check whether the fabric is in initialized state
- */
- if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
- & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
- /*
- * We don't need to check PCFG_INIT to be high for
- * non-encrypted loopback transfers.
- */
- if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
- return XST_FAILURE;
- }
- }
-
- if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
- (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
-
- /* Check for valid source pointer and length */
- if ((!SourcePtr) || (SrcWordLength == 0)) {
- return XST_INVALID_PARAM;
- }
-
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
- /*
- * Clear QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every clock
- */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET, (CtrlReg &
- ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
-
- }
- if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
- /*
- * AES engine handles only 8 bit data every clock cycle.
- * Hence, Encrypted PCAP data which is 32 bit data can
- * only be sent in every 4 clock cycles. Set the control
- * register QUARTER_PCAP_RATE_EN bit to achieve this
- * operation.
- */
- XDcfg_SetControlRegister(InstancePtr,
- XDCFG_CTRL_PCAP_RATE_EN_MASK);
- }
-
- XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
- (u32)DestPtr, SrcWordLength, DestWordLength);
-
- }
-
- if (TransferType == XDCFG_PCAP_READBACK) {
-
- if ((!DestPtr) || (DestWordLength == 0)) {
-
- return XST_INVALID_PARAM;
- }
-
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- /*
- * For PCAP readback of FPGA configuration register or memory,
- * the read command is first sent (written) to the FPGA fabric
- * which responds by returning the required read data. Read data
- * from the FPGA is captured if pcap_radata_v is active.A DMA
- * read transfer is required to obtain the readback command,
- * which is then sent to the FPGA, followed by a DMA write
- * transfer to support this mode of operation.
- */
- return XDcfg_PcapReadback(InstancePtr,
- (u32)SourcePtr, SrcWordLength,
- (u32)DestPtr, DestWordLength);
- }
-
-
- if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
- (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
-
- if ((!SourcePtr) || (SrcWordLength == 0) ||
- (!DestPtr) || (DestWordLength == 0)) {
- return XST_INVALID_PARAM;
- }
-
- if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
- /* Enable internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg |
- XDCFG_MCTRL_PCAP_LPBK_MASK));
-
- /*
- * Clear QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every clock
- */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET, (CtrlReg &
- ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
-
- }
- if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- /*
- * Set the QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every 4 clock
- * cycles, this is required for encrypted data.
- */
- XDcfg_SetControlRegister(InstancePtr,
- XDCFG_CTRL_PCAP_RATE_EN_MASK);
- }
-
- XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
- (u32)DestPtr, SrcWordLength, DestWordLength);
- }
-
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
deleted file mode 100644
index b9a0111d695aeb71f09195025549f3df8283d9fb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.h
-* @addtogroup devcfg_v3_5
-* @{
-* @details
-*
-* The is the main header file for the Device Configuration Interface of the Zynq
-* device. The device configuration interface has three main functionality.
-* 1. AXI-PCAP
-* 2. Security Policy
-* 3. XADC
-* This current version of the driver supports only the AXI-PCAP and Security
-* Policy blocks. There is a separate driver for XADC.
-*
-* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
-* DMA embedded in the AXI PCAP provides the master interface to
-* the Device configuration block for any DMA transfers. The data transfer can
-* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
-* RAM/DDR/peripheral memory).
-*
-* The current driver only supports the downloading the FPGA bitstream and
-* readback of the decrypted image (sort of loopback).
-* The driver does not know what information needs to be written to the FPGA to
-* readback FPGA configuration register or memory data. The application above the
-* driver should take care of creating the data that needs to be downloaded to
-* the FPGA so that the bitstream can be readback.
-* This driver also does not support the reading of the internal registers of the
-* PCAP. The driver has no knowledge of the PCAP internals.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Device Configuration device.
-*
-* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
-* Interface. The user needs to first call the XDcfg_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XDcfg_CfgInitialize() API.
-*
-* <b>Interrupts</b>
-* The Driver implements an interrupt handler to support the interrupts provided
-* by this interface.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XDcfg driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-* </pre>
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
deleted file mode 100644
index 320af47d83bff268576adca625235c1f4101fe63..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xdevcfg.h"
-
-/*
-* The configuration table for devices
-*/
-
-XDcfg_Config XDcfg_ConfigTable[] =
-{
- {
- XPAR_PS7_DEV_CFG_0_DEVICE_ID,
- XPAR_PS7_DEV_CFG_0_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
deleted file mode 100644
index bcb238f062cfddb05cca741e27512f6ec1f37d58..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.c
-* @addtogroup devcfg_v3_5
-* @{
-*
-* This file contains the implementation of the interface reset functionality
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 2.04a kpc 10/07/13 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given devcfg interface by
-* configuring the appropriate control bits in the devcfg specifc registers
-* the devcfg reset squence involves the following steps
-* Disable all the interuupts
-* Clear the status
-* Update relevant config registers with reset values
-* Disbale the looopback mode and pcap rate enable
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* devcfg controller
-******************************************************************************/
-void XDcfg_ResetHw(u32 BaseAddr)
-{
- u32 Regval = 0;
-
- /* Mask the interrupts */
- XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
- XDCFG_IXR_ALL_MASK);
- /* Clear the interuupt status */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
- XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
- /* Clear the source address register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
- /* Clear the destination address register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
- /* Clear the source length register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
- /* Clear the destination length register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
- /* Clear the loopback enable bit */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
- Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
- XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
- /*Reset the configuration register to reset value */
- XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
- XDCFG_CONFIG_RESET_VALUE);
- /*Disable the PCAP rate enable bit */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
- Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
- XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
deleted file mode 100644
index c506ca59fc936b96086d96b074f85bee0959c104..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_3
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-* </pre>
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H /* prevent circular inclusions */
-#define XDCFG_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
- * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
- * Secure Reset
- */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
- * Reset FPGA
- */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
- * to FPGA every 4 PCAP
- * cycles
- */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
- * Status mask
- */
-#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
- * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
- * USER_MODE
- */
-#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
- * security config
- * including: DAP_En,
- * DBGEN,,
- * NIDEN, SPNIEN
- */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
- * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
- * Threshold Mask
- */
-#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
- * Mask
- */
-#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
- * clock edge
- */
-#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
- * clock edge
- */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
- * increment mask
- */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
- * address increment
- * mask
- */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
- * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
- * HIZ
- */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
- * done
- */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
- * configuration
- */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
- * reset
- */
-#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
- * or Data or response
- * timeout
- */
-#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
- * error
- */
-#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
- * response timeout
- */
-#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
- * error
- */
-#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
- * threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
- * threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
- * overflow
- */
-#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
- * transfers Done
- */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
- * length error
- */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
- * of Init Signal
- */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
- * of Init Signal
- */
-#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
- XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
- * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
- * Queue full
- */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
- * Queue empty
- */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
- * completed DMA
- * transfers
- */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
- * during HIZ
- */
-#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
- * done
- */
-#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
- * config
- */
-#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
- * POR Status
- */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
- * access
- */
-#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
- * reset status
- */
-#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
- * Status
- */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
- /**< BBRAM key
- * disable
- */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
- * Enable Status
- */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
- * Disable
- * status
- */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
- * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
- * address
- */
-#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
deleted file mode 100644
index b41b7ea370b596df0e0af5b38c865f3d81a48c90..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_intr.c
-* @addtogroup devcfg_v3_5
-* @{
-*
-* Contains the implementation of interrupt related functions of the XDcfg
-* driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be enabled.
-* Bit positions of 1 will be enabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XDCFG_INT_* bits defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Enable the specified interrupts in the Interrupt Mask Register.
- */
- RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET);
- RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be disabled.
-* Bit positions of 1 will be disabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XDCFG_INT_* bits defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the specified interrupts in the Interrupt Mask Register.
- */
- RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET);
- RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET,
- RegValue);
-}
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Mask
-* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the IMR.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Mask Register.
- */
- return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Interrupt
-* Status register.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Status register.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be cleared.
-* Bit positions of 1 will be cleared. Bit positions of 0 will not
-* change the previous interrupt status. This mask is formed by
-* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET,
- Mask);
-
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for the Device Config Interface.
-*
-* Events are signaled to upper layer for proper handling.
-*
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XDcfg_InterruptHandler(XDcfg *InstancePtr)
-{
- u32 IntrStatusReg;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Interrupt status register.
- */
- IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET);
-
- /*
- * Write the status back to clear the interrupts so that no
- * subsequent interrupts are missed while processing this interrupt.
- * This also does the DMA acknowledgment automatically.
- */
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET, IntrStatusReg);
-
- /*
- * Signal application that there are events to handle.
- */
- InstancePtr->StatusHandler(InstancePtr->CallBackRef,
- IntrStatusReg);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param InstancePtr is a pointer to the XDcfg instance
-* @param CallBackFunc is the address of the callback function.
-* @param CallBackRef is a user data item that will be passed to the
-* callback function when it is invoked.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef)
-{
- /*
- * Asserts validate the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(CallBackFunc != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
- InstancePtr->CallBackRef = CallBackRef;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
deleted file mode 100644
index 40cf1de6abc45a9b9601651ccea7e3d9e2c6168a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_selftest.c
-* @addtogroup devcfg_v3_5
-* @{
-*
-* Contains diagnostic self-test functions for the XDcfg driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.02a nm 02/27/13 Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the Device Configuration Interface. This test does a
-* control register write and reads back the same value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if fails.
-*
-* @note None.
-*
-******************************************************************************/
-int XDcfg_SelfTest(XDcfg *InstancePtr)
-{
- u32 OldCfgReg;
- u32 CfgReg;
- int Status = XST_SUCCESS;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
-
- XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
-
- CfgReg = XDcfg_GetControlRegister(InstancePtr);
-
- if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
-
- Status = XST_FAILURE;
- }
-
- /*
- * Restore the original values of the register
- */
- XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
-
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
deleted file mode 100644
index bbc96a0c6bd98d5b331cf330da84e08b18d47b3c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xdevcfg_sinit.c
-* @addtogroup devcfg_v3_5
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 3.5 ms 08/07/17 Fixed compilation warnings.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
-{
- extern XDcfg_Config XDcfg_ConfigTable[];
- XDcfg_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
- if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XDcfg_ConfigTable[Index];
- break;
- }
- }
-
- return (CfgPtr);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
deleted file mode 100644
index d1240c586cd64556950a7826e73c46719a2ce887..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
+++ /dev/null
@@ -1,41 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xdmaps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling dmaps"
-
-xdmaps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xdmaps_includes
-
-xdmaps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
deleted file mode 100644
index 9db769284bdd6c4ac26be76d5eda1b758bdecece..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
+++ /dev/null
@@ -1,1982 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps.c
-* @addtogroup dmaps_v2_3
-* @{
-*
-* This file contains the implementation of the interface functions for XDmaPs
-* driver. Refer to the header file xdmaps.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/2010 First Release
-* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
-* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
-* since it is being defined in xil_io.h
-* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include <string.h>
-
-#include "xstatus.h"
-#include "xdmaps.h"
-#include "xil_io.h"
-#include "xil_cache.h"
-
-#include "xil_printf.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/* The following constant defines the amount of error that is allowed for
- * a specified baud rate. This error is the difference between the actual
- * baud rate that will be generated using the specified clock and the
- * desired baud rate.
- */
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
- unsigned int Channel,
- unsigned int Thread);
-
-static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
-
-static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
-
-static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
-static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
-static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
- unsigned CacheLength);
-
-static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
-
-
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* Initializes a specific XDmaPs instance such that it is ready to be used.
-* The data format of the device is setup for 8 data bits, 1 stop bit, and no
-* parity by default. The baud rate is set to a default value specified by
-* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
-* receive FIFO threshold is set for 8 bytes. The default operating mode of the
-* driver is polled mode.
-*
-* @param InstPtr is a pointer to the XDmaPs instance.
-* @param Config is a reference to a structure containing information
-* about a specific XDmaPs driver.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the
-* address mapping from EffectiveAddr to the device physical base
-* address unchanged once this function is invoked. Unexpected
-* errors may occur if the address mapping changes after this
-* function is called. If address translation is not used, pass in
-* the physical address instead.
-*
-* @return
-*
-* - XST_SUCCESS on initialization completion
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr)
-{
- int Status = XST_SUCCESS;
- unsigned int CacheLength = 0;
- u32 CfgReg;
- unsigned Channel;
- XDmaPs_ChannelData *ChanData;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Config != NULL);
-
- /*
- * Setup the driver instance using passed in parameters
- */
- InstPtr->Config.DeviceId = Config->DeviceId;
- InstPtr->Config.BaseAddress = EffectiveAddr;
-
- CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
- CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
- if (CacheLength < 2 || CacheLength > 5)
- CacheLength = 0;
- else
- CacheLength = 1 << CacheLength;
-
- InstPtr->CacheLength = CacheLength;
-
- memset(InstPtr->Chans, 0,
- sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
-
- for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
- ChanData = InstPtr->Chans + Channel;
- ChanData->ChanId = Channel;
- ChanData->DevId = Config->DeviceId;
- }
-
- InstPtr->IsReady = 1;
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Reset the DMA Manager.
-*
-* @param InstPtr is the DMA instance.
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ResetManager(XDmaPs *InstPtr)
-{
- int Status;
- Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
- 0, 0);
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Reset the specified DMA Channel.
-*
-* @param InstPtr is the DMA instance.
-* @param Channel is the channel to be reset.
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
-{
- int Status;
- Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
- Channel, 1);
-
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver fault interrupt service routine
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_FaultISR(XDmaPs *InstPtr)
-{
-
- void *DmaProgBuf;
- u32 Fsm; /* Fault status DMA manager register value */
- u32 Fsc; /* Fault status DMA channel register value */
- u32 FaultType; /* Fault type DMA manager register value */
-
- u32 BaseAddr = InstPtr->Config.BaseAddress;
-
- u32 Pc; /* DMA Pc or channel Pc */
- XDmaPs_ChannelData *ChanData;
-
- unsigned Chan;
- unsigned DevId;
-
- XDmaPs_Cmd *DmaCmd;
-
- Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
- Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
-
-
- DevId = InstPtr->Config.DeviceId;
-
- if (Fsm) {
- /*
- * if DMA manager is fault
- */
- FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
- Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
-
- xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
- DevId,
- FaultType, Pc);
-
- /* kill the DMA manager thread */
- /* Should we disable interrupt?*/
- XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
- }
-
- /*
- * check which channel faults and kill the channel thread
- */
- for (Chan = 0;
- Chan < XDMAPS_CHANNELS_PER_DEV;
- Chan++) {
- if (Fsc & (0x01 << Chan)) {
- FaultType =
- XDmaPs_ReadReg(BaseAddr,
- XDmaPs_FTCn_OFFSET(Chan));
- Pc = XDmaPs_ReadReg(BaseAddr,
- XDmaPs_CPCn_OFFSET(Chan));
-
- /* kill the channel thread */
- /* Should we disable interrupt? */
- XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
-
- /*
- * get the fault type and fault Pc and invoke the
- * fault callback.
- */
- ChanData = InstPtr->Chans + Chan;
-
- DmaCmd = ChanData->DmaCmdToHw;
-
- /* Should we check DmaCmd is not null */
- DmaCmd->DmaStatus = -1;
- DmaCmd->ChanFaultType = FaultType;
- DmaCmd->ChanFaultPCAddr = Pc;
- ChanData->DmaCmdFromHw = DmaCmd;
- ChanData->DmaCmdToHw = NULL;
-
- if (!ChanData->HoldDmaProg) {
- DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
- if (DmaProgBuf)
- XDmaPs_BufPool_Free(ChanData->ProgBufPool,
- DmaProgBuf);
- DmaCmd->GeneratedDmaProg = NULL;
- }
-
- if (InstPtr->FaultHandler)
- InstPtr->FaultHandler(Chan,
- DmaCmd,
- InstPtr->FaultRef);
-
- }
- }
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the done handler for a channel.
-*
-* @param InstPtr is the DMA instance.
-* @param Channel is the channel number.
-* @param DoneHandler is the done interrupt handler.
-* @param CallbackRef is the callback reference data.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef)
-{
- XDmaPs_ChannelData *ChanData;
-
- Xil_AssertNonvoid(InstPtr != NULL);
-
- if (Channel >= XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
-
- ChanData = InstPtr->Chans + Channel;
-
- ChanData->DoneHandler = DoneHandler;
- ChanData->DoneRef = CallbackRef;
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the fault handler for a channel.
-*
-* @param InstPtr is the DMA instance.
-* @param FaultHandler is the fault interrupt handler.
-* @param CallbackRef is the callback reference data.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef)
-{
- Xil_AssertNonvoid(InstPtr != NULL);
-
- InstPtr->FaultHandler = FaultHandler;
- InstPtr->FaultRef = CallbackRef;
-
- return XST_SUCCESS;
-}
-
-
-
-/****************************************************************************/
-/**
-* Construction function for DMAEND instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg the DMA program buffer, it's the starting address for
-* the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
-{
- /*
- * DMAEND encoding:
- * 7 6 5 4 3 2 1 0
- * 0 0 0 0 0 0 0 0
- */
- *DmaProg = 0x0;
-
- return 1;
-}
-
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
-{
- *Dst = *Src;
- *(Dst + 1) = *(Src + 1);
- *(Dst + 2) = *(Src + 2);
- *(Dst + 3) = *(Src + 3);
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAGO instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param Cn is the Channel number, 0 - 7
-* @param Imm is 32-bit immediate number written to the Channel Program
-* Counter.
-* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
-* the Non-secure state. If Ns is 0, the execution depends on the
-* security state of the DMA manager:
-* DMA manager is in the Secure state, DMA channel operates in the
-* Secure state.
-* DMA manager is in the Non-secure state, DMAC aborts.
-*
-* @return The number of bytes for this instruction which is 6.
-*
-* @note None
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns)
-{
- /*
- * DMAGO encoding:
- * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
- * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0
- *
- * 47 ... 16
- * imm[32:0]
- */
- *DmaProg = 0xA0 | ((Ns << 1) & 0x02);
-
- *(DmaProg + 1) = (u8)(Cn & 0x07);
-
- // *((u32 *)(DmaProg + 2)) = Imm;
- XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
-
- /* success */
- return 6;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMALD instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg the DMA program buffer, it's the starting address for the
-* instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
-{
- /*
- * DMALD encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 0 0 1 bs x
- *
- * Note: this driver doesn't support conditional load or store,
- * so the bs bit is 0 and x bit is 0.
- */
- *DmaProg = 0x04;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMALP instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param Lc is the Loop counter register, can either be 0 or 1.
-* @param LoopIterations: the number of interations, LoopInterations - 1
-* will be encoded in the DMALP instruction.
-*
-* @return The number of bytes for this instruction which is 2.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations)
-{
- /*
- * DMALP encoding
- * 15 ... 8 7 6 5 4 3 2 1 0
- * | iter[7:0] |0 0 1 0 0 0 lc 0
- */
- *DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
- *(DmaProg + 1) = (u8)(LoopIterations - 1);
- return 2;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMALPEND instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param BodyStart is the starting address of the loop body. It is used
-* to calculate the bytes of backward jump.
-* @param Lc is the Loop counter register, can either be 0 or 1.
-*
-* @return The number of bytes for this instruction which is 2.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
-{
- /*
- * DMALPEND encoding
- * 15 ... 8 7 6 5 4 3 2 1 0
- * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
- *
- * lc: loop counter
- * nf is for loop forever. The driver does not support loop forever,
- * so nf is 1.
- * The driver does not support conditional LPEND, so bs is 0, x is 0.
- */
- *DmaProg = 0x38 | ((Lc & 1) << 2);
- *(DmaProg + 1) = (u8)(DmaProg - BodyStart);
-
- return 2;
-}
-
-/*
- * Register number for the DMAMOV instruction
- */
-#define XDMAPS_MOV_SAR 0x0
-#define XDMAPS_MOV_CCR 0x1
-#define XDMAPS_MOV_DAR 0x2
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAMOV instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
-* @param Imm is the 32-bit immediate number
-*
-* @return The number of bytes for this instruction which is 6.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
-{
- /*
- * DMAMOV encoding
- * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
- * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
- *
- * 47 ... 16
- * imm[32:0]
- *
- * rd: b000 for SAR, b001 CCR, b010 DAR
- */
- *DmaProg = 0xBC;
- *(DmaProg + 1) = Rd & 0x7;
- // *((u32 *)(DmaProg + 2)) = Imm;
- XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
-
- return 6;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMANOP instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
-{
- /*
- * DMANOP encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 1 1 0 0 0
- */
- *DmaProg = 0x18;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMARMB instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg)
-{
- /*
- * DMARMB encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 1 0 0 1 0
- */
- *DmaProg = 0x12;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMASEV instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param EventNumber is the Event number to signal.
-*
-* @return The number of bytes for this instruction which is 2.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
-{
- /*
- * DMASEV encoding
- * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0
- * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
- */
- *DmaProg = 0x34;
- *(DmaProg + 1) = (u8)(EventNumber << 3);
-
- return 2;
-}
-
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAST instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
-{
- /*
- * DMAST encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 0 1 0 bs x
- *
- * Note: this driver doesn't support conditional load or store,
- * so the bs bit is 0 and x bit is 0.
- */
- *DmaProg = 0x08;
- return 1;
-}
-
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAWMB instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg)
-{
- /*
- * DMAWMB encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 1 0 0 1 0
- */
- *DmaProg = 0x13;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Conversion function from the endian swap size to the bit encoding of the CCR
-*
-* @param EndianSwapSize is the endian swap size, in terms of bits, it
-* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
-*
-* @return The endian swap size bit encoding for the CCR.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
-{
- switch (EndianSwapSize) {
- case 0:
- case 8:
- return 0;
- case 16:
- return 1;
- case 32:
- return 2;
- case 64:
- return 3;
- case 128:
- return 4;
- default:
- return 0;
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* Conversion function from the burst size to the bit encoding of the CCR
-*
-* @param BurstSize is the burst size. It's the data width.
-* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
-* It must be no larger than the bus width.
-* (We are using DMA assembly syntax.)
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
-{
- switch (BurstSize) {
- case 1:
- return 0;
- case 2:
- return 1;
- case 4:
- return 2;
- case 8:
- return 3;
- case 16:
- return 4;
- case 32:
- return 5;
- case 64:
- return 6;
- case 128:
- return 7;
- default:
- return 0;
- }
-}
-
-
-/****************************************************************************/
-/**
-*
-* Conversion function from PL330 bus transfer descriptors to CCR value. All the
-* values passed to the functions are in terms of assembly languages, not in
-* terms of the register bit encoding.
-*
-* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl.
-*
-* @return The 32-bit CCR value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
-{
- /*
- * Channel Control Register encoding
- * [31:28] - endian_swap_size
- * [27:25] - dst_cache_ctrl
- * [24:22] - dst_prot_ctrl
- * [21:18] - dst_burst_len
- * [17:15] - dst_burst_size
- * [14] - dst_inc
- * [13:11] - src_cache_ctrl
- * [10:8] - src_prot_ctrl
- * [7:4] - src_burst_len
- * [3:1] - src_burst_size
- * [0] - src_inc
- */
-
- unsigned es =
- XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
-
- unsigned dst_burst_size =
- XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
- unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
- unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
- | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
- unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
- unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
-
- unsigned src_burst_size =
- XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
- unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
- unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
- | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
- unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
- unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
-
- u32 ccr_value = (es << 28)
- | (dst_cache_ctrl << 25)
- | (dst_prot_ctrl << 22)
- | (dst_burst_len << 18)
- | (dst_burst_size << 15)
- | (dst_inc_bit << 14)
- | (src_cache_ctrl << 11)
- | (src_prot_ctrl << 8)
- | (src_burst_len << 4)
- | (src_burst_size << 1)
- | (src_inc_bit);
-
- return ccr_value;
-}
-
-/****************************************************************************/
-/**
-* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
-* The function also makes sure the loop body and the lpend is in the same
-* cache line.
-*
-* @param DmaProgStart is the very start address of the DMA program.
-* This is used to calculate whether the loop is in a cache line.
-* @param CacheLength is the icache line length, in terms of bytes.
-* If it's zero, the performance enhancement feature will be
-* turned off.
-* @param DmaProgLoopStart The starting address of the loop (DMALP).
-* @param LoopCount The inner loop count. Loop count - 1 will be used to
-* initialize the loop counter.
-*
-* @return The number of bytes the loop has.
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
- int CacheLength,
- char *DmaProgLoopStart,
- int LoopCount)
-{
- int CacheStartOffset;
- int CacheEndOffset;
- int NumNops;
- char *DmaProgBuf = DmaProgLoopStart;
-
- DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
-
- if (CacheLength > 0) {
- /*
- * the CacheLength > 0 switch is ued to turn on/off nop
- * insertion
- */
- CacheStartOffset = DmaProgBuf - DmaProgStart;
- CacheEndOffset = CacheStartOffset + 3;
-
- /*
- * check whether the body and lpend fit in one cache line
- */
- if (CacheStartOffset / CacheLength
- != CacheEndOffset / CacheLength) {
- /* insert the nops */
- NumNops = CacheLength
- - CacheStartOffset % CacheLength;
- while (NumNops--) {
- DmaProgBuf +=
- XDmaPs_Instr_DMANOP(DmaProgBuf);
- }
- }
- }
-
- DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
- DmaProgBuf - 2, 0);
-
- return DmaProgBuf - DmaProgLoopStart;
-}
-
-/****************************************************************************/
-/**
-* Construct a nested loop with only DMALD and DMAST in the inner loop body.
-* It uses loop counter 1 for the outer loop and loop counter 0 for the
-* inner loop.
-*
-* @param DmaProgStart is the very start address of the DMA program.
-* This is used to calculate whether the loop is in a cache line.
-* @param CacheLength is the icache line length, in terms of bytes.
-* If it's zero, the performance enhancement feature will be
-* turned off.
-* @param DmaProgLoopStart The starting address of the loop (DMALP).
-* @param LoopCountOuter The outer loop count. Loop count - 1 will be
-* used to initialize the loop counter.
-* @param LoopCountInner The inner loop count. Loop count - 1 will be
-* used to initialize the loop counter.
-*
-* @return The number byes the nested loop program has.
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
- int CacheLength,
- char *DmaProgLoopStart,
- unsigned int LoopCountOuter,
- unsigned int LoopCountInner)
-{
- int CacheStartOffset;
- int CacheEndOffset;
- int NumNops;
- char *InnerLoopStart;
- char *DmaProgBuf = DmaProgLoopStart;
-
- DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
- InnerLoopStart = DmaProgBuf;
-
- if (CacheLength > 0) {
- /*
- * the CacheLength > 0 switch is ued to turn on/off nop
- * insertion
- */
- if (CacheLength < 8) {
- /*
- * if the cache line is too small to fit both loops
- * just align the inner loop
- */
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- LoopCountInner);
- /* outer loop end */
- DmaProgBuf +=
- XDmaPs_Instr_DMALPEND(DmaProgBuf,
- InnerLoopStart,
- 1);
-
- /*
- * the nested loop is constructed for
- * smaller cache line
- */
- return DmaProgBuf - DmaProgLoopStart;
- }
-
- /*
- * Now let's handle the case where a cache line can
- * fit the nested loops.
- */
- CacheStartOffset = DmaProgBuf - DmaProgStart;
- CacheEndOffset = CacheStartOffset + 7;
-
- /*
- * check whether the body and lpend fit in one cache line
- */
- if (CacheStartOffset / CacheLength
- != CacheEndOffset / CacheLength) {
- /* insert the nops */
- NumNops = CacheLength
- - CacheStartOffset % CacheLength;
- while (NumNops--) {
- DmaProgBuf +=
- XDmaPs_Instr_DMANOP(DmaProgBuf);
- }
- }
- }
-
- /* insert the inner DMALP */
- DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
-
- /* DMALD and DMAST instructions */
- DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
-
- /* inner DMALPEND */
- DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
- DmaProgBuf - 2, 0);
- /* outer DMALPEND */
- DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
- InnerLoopStart, 1);
-
- /* return the number of bytes */
- return DmaProgBuf - DmaProgLoopStart;
-}
-
-/*
- * [31:28] endian_swap_size b0000
- * [27:25] dst_cache_ctrl b000
- * [24:22] dst_prot_ctrl b000
- * [21:18] dst_burst_len b0000
- * [17:15] dst_burst_size b000
- * [14] dst_inc b0
- * [27:25] src_cache_ctrl b000
- * [24:22] src_prot_ctrl b000
- * [21:18] src_burst_len b0000
- * [17:15] src_burst_size b000
- * [14] src_inc b0
- */
-#define XDMAPS_CCR_SINGLE_BYTE (0x0)
-#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1)
-
-
-/****************************************************************************/
-/**
-*
-* Construct the DMA program based on the descriptions of the DMA transfer.
-* The function handles memory to memory DMA transfers.
-* It also handles unalgined head and small amount of residue tail.
-*
-* @param Channel DMA channel number
-* @param Cmd is the DMA command.
-* @param CacheLength is the icache line length, in terms of bytes.
-* If it's zero, the performance enhancement feature will be
-* turned off.
-*
-* @returns The number of bytes for the program.
-*
-* @note None.
-*
-*****************************************************************************/
-static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
- unsigned CacheLength)
-{
- /*
- * unpack arguments
- */
- char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
- unsigned DevChan = Channel;
- unsigned long DmaLength = Cmd->BD.Length;
- u32 SrcAddr = Cmd->BD.SrcAddr;
-
- unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
- u32 DstAddr = Cmd->BD.DstAddr;
- unsigned DstInc = Cmd->ChanCtrl.DstInc;
-
- char *DmaProgStart = DmaProgBuf;
-
- unsigned int BurstBytes;
- unsigned int LoopCount;
- unsigned int LoopCount1 = 0;
- unsigned int LoopResidue = 0;
- unsigned int TailBytes;
- unsigned int TailWords;
- int DmaProgBytes;
- u32 CCRValue;
- unsigned int Unaligned;
- unsigned int UnalignedCount;
- unsigned int MemBurstSize = 1;
- u32 MemAddr = 0;
- unsigned int Index;
- unsigned int SrcUnaligned = 0;
- unsigned int DstUnaligned = 0;
-
- XDmaPs_ChanCtrl *ChanCtrl;
- XDmaPs_ChanCtrl WordChanCtrl;
- static XDmaPs_ChanCtrl Mem2MemByteCC;
-
- Mem2MemByteCC.EndianSwapSize = 0;
- Mem2MemByteCC.DstCacheCtrl = 0;
- Mem2MemByteCC.DstProtCtrl = 0;
- Mem2MemByteCC.DstBurstLen = 1;
- Mem2MemByteCC.DstBurstSize = 1;
- Mem2MemByteCC.DstInc = 1;
- Mem2MemByteCC.SrcCacheCtrl = 0;
- Mem2MemByteCC.SrcProtCtrl = 0;
- Mem2MemByteCC.SrcBurstLen = 1;
- Mem2MemByteCC.SrcBurstSize = 1;
- Mem2MemByteCC.SrcInc = 1;
-
- ChanCtrl = &Cmd->ChanCtrl;
-
- /* insert DMAMOV for SAR and DAR */
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_SAR,
- SrcAddr);
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_DAR,
- DstAddr);
-
-
- if (ChanCtrl->SrcInc)
- SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
-
- if (ChanCtrl->DstInc)
- DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
-
- if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
- ChanCtrl = &Mem2MemByteCC;
- }
-
- if (ChanCtrl->SrcInc) {
- MemBurstSize = ChanCtrl->SrcBurstSize;
- MemAddr = SrcAddr;
-
- } else if (ChanCtrl->DstInc) {
- MemBurstSize = ChanCtrl->DstBurstSize;
- MemAddr = DstAddr;
- }
-
- /* check whether the head is aligned or not */
- Unaligned = MemAddr % MemBurstSize;
-
- if (Unaligned) {
- /* if head is unaligned, transfer head in bytes */
- UnalignedCount = MemBurstSize - Unaligned;
- CCRValue = XDMAPS_CCR_SINGLE_BYTE
- | (SrcInc & 1)
- | ((DstInc & 1) << 14);
-
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
-
- for (Index = 0; Index < UnalignedCount; Index++) {
- DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
- }
-
- DmaLength -= UnalignedCount;
- }
-
- /* now the burst transfer part */
- CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
-
- BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
-
- LoopCount = DmaLength / BurstBytes;
- TailBytes = DmaLength % BurstBytes;
-
- /*
- * the loop count register is 8-bit wide, so if we need
- * a larger loop, we need to have nested loops
- */
- if (LoopCount > 256) {
- LoopCount1 = LoopCount / 256;
- if (LoopCount1 > 256) {
- xil_printf("DMA operation cannot fit in a 2-level "
- "loop for channel %d, please reduce the "
- "DMA length or increase the burst size or "
- "length",
- Channel);
- return 0;
- }
- LoopResidue = LoopCount % 256;
-
- if (LoopCount1 > 1)
- DmaProgBuf +=
- XDmaPs_ConstructNestedLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- LoopCount1,
- 256);
- else
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- 256);
-
- /* there will be some that cannot be covered by
- * nested loops
- */
- LoopCount = LoopResidue;
- }
-
- if (LoopCount > 0) {
- DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- LoopCount);
- }
-
- if (TailBytes) {
- /* handle the tail */
- TailWords = TailBytes / MemBurstSize;
- TailBytes = TailBytes % MemBurstSize;
-
- if (TailWords) {
- WordChanCtrl = *ChanCtrl;
- /*
- * if we can transfer the tail in words, we will
- * transfer words as much as possible
- */
- WordChanCtrl.SrcBurstSize = MemBurstSize;
- WordChanCtrl.SrcBurstLen = 1;
- WordChanCtrl.DstBurstSize = MemBurstSize;
- WordChanCtrl.DstBurstLen = 1;
-
-
- /*
- * the burst length is 1
- */
- CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
-
- DmaProgBuf +=
- XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- TailWords);
-
- }
-
- if (TailBytes) {
- /*
- * for the rest, we'll tranfer in bytes
- */
- /*
- * So far just to be safe, the tail bytes
- * are transfered in a loop. We can optimize a little
- * to perform a burst.
- */
- CCRValue = XDMAPS_CCR_SINGLE_BYTE
- | (SrcInc & 1)
- | ((DstInc & 1) << 14);
-
- DmaProgBuf +=
- XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
-
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- TailBytes);
-
- }
- }
-
- DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
- DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
-
- DmaProgBytes = DmaProgBuf - DmaProgStart;
-
- Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
-
- return DmaProgBytes;
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* Generate a DMA program based for the DMA command, the buffer will be pointed
-* by the GeneratedDmaProg field of the command.
-*
-* @param InstPtr is then DMA instance.
-* @param Channel is the DMA channel number.
-* @param Cmd is the DMA command.
-*
-* @return - XST_SUCCESS on success.
-* - XST_FAILURE if it fails
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
-{
- void *Buf;
- int ProgLen;
- XDmaPs_ChannelData *ChanData;
- XDmaPs_ChanCtrl *ChanCtrl;
-
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Cmd != NULL);
-
-
- if (Channel > XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
- ChanData = InstPtr->Chans + Channel;
- ChanCtrl = &Cmd->ChanCtrl;
-
- if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
- != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
- return XST_FAILURE;
- }
-
-
- /*
- * unaligned fixed address is not supported
- */
- if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
- return XST_FAILURE;
- }
-
- if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
- return XST_FAILURE;
- }
-
- Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
- if (Buf == NULL) {
- return XST_FAILURE;
- }
-
- Cmd->GeneratedDmaProg = Buf;
- ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
- InstPtr->CacheLength);
- Cmd->GeneratedDmaProgLength = ProgLen;
-
-
-#ifdef XDMAPS_DEBUG
- XDmaPs_Print_DmaProg(Cmd);
-#endif
-
- if (ProgLen <= 0) {
- /* something wrong, release the buffer */
- XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
- Cmd->GeneratedDmaProgLength = 0;
- Cmd->GeneratedDmaProg = NULL;
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
- * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
- * of the command.
- *
- * @param InstPtr is then DMA instance.
- * @param Channel is the DMA channel number.
- * @param Cmd is the DMA command.
- *
- * @return XST_SUCCESS on success.
- * XST_FAILURE if there is any error.
- *
- * @note None.
- *
- ****************************************************************************/
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
-{
-
- void *Buf;
- XDmaPs_ChannelData *ChanData;
-
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Cmd != NULL);
-
- if (Channel > XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
- Buf = (void *)Cmd->GeneratedDmaProg;
- ChanData = InstPtr->Chans + Channel;
-
- if (Buf) {
- XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
- Cmd->GeneratedDmaProg = 0;
- Cmd->GeneratedDmaProgLength = 0;
- }
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* Start a DMA command. The command can only be invoked when the channel
-* is idle. The driver takes the command, generates DMA program if needed,
-* then pass the program to DMAC to execute.
-*
-* @param InstPtr is then DMA instance.
-* @param Channel is the DMA channel number.
-* @param Cmd is the DMA command.
-* @param HoldDmaProg is tag indicating whether the driver can release
-* the allocated DMA buffer or not. If a user wants to examine the
-* generated DMA program, the flag should be set to 1. After the
-* DMA program is finished, a user needs to explicity free the
-* buffer.
-*
-* @return
-* - XST_SUCCESS on success
-* - XST_DEVICE_BUSY if DMA is busy
-* - XST_FAILURE on other failures
-*
-* @note None.
-*
-****************************************************************************/
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg)
-{
- int Status;
- u32 DmaProg = 0;
- u32 Inten;
-
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Cmd != NULL);
-
-
- Cmd->DmaStatus = XST_FAILURE;
-
- if (XDmaPs_IsActive(InstPtr, Channel))
- return XST_DEVICE_BUSY;
-
- if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
- Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
- if (Status)
- return XST_FAILURE;
- }
-
- InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
-
- if (Cmd->UserDmaProg)
- DmaProg = (u32)Cmd->UserDmaProg;
- else if (Cmd->GeneratedDmaProg)
- DmaProg = (u32)Cmd->GeneratedDmaProg;
-
- if (DmaProg) {
- /* enable the interrupt */
- Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTEN_OFFSET);
- Inten |= 0x01 << Channel; /* set the correpsonding bit */
- XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTEN_OFFSET,
- Inten);
- Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTEN_OFFSET);
-
- InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
-
- if (Cmd->ChanCtrl.SrcInc) {
- Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
- }
- if (Cmd->ChanCtrl.DstInc) {
- Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
- Cmd->BD.Length);
- }
-
- Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
- Channel, DmaProg);
- }
- else {
- InstPtr->Chans[Channel].DmaCmdToHw = NULL;
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Checks whether the DMA channel is active or idle.
-*
-* @param InstPtr is the DMA instance.
-* @param Channel is the DMA channel number.
-*
-* @return 0: if the channel is idle
-* 1: otherwise
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
-{
- Xil_AssertNonvoid(InstPtr != NULL);
-
- /* Need to assert Channel is in range */
- if (Channel > XDMAPS_CHANNELS_PER_DEV)
- return 0;
-
- return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
-}
-
-
-
-/****************************************************************************/
-/**
-*
-* Allocate a buffer of the DMA program buffer from the pool.
-*
-* @param Pool the DMA program pool.
-*
-* @return The allocated buffer, NULL if there is any error.
-*
-* @note None.
-*
-*****************************************************************************/
-static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
-{
- int Index;
-
- Xil_AssertNonvoid(Pool != NULL);
-
- for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
- if (!Pool[Index].Allocated) {
- Pool[Index].Allocated = 1;
- return Pool[Index].Buf;
- }
- }
-
- return NULL;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 0. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 0);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 1. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 1);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 2. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 2);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 3. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 3);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 4. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 4);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 5. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 5);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 6. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 6);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 7. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 7);
-}
-
-#ifndef XDMAPS_MAX_WAIT
-#define XDMAPS_MAX_WAIT 4000
-#endif
-
-/****************************************************************************/
-/**
-* Use the debug registers to kill the DMA thread.
-*
-* @param BaseAddr is DMA device base address.
-* @param Channel is the DMA channel number.
-* @param Thread is Debug thread encoding.
-* 0: DMA manager thread, 1: DMA channel.
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-*****************************************************************************/
-static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
- unsigned int Channel,
- unsigned int Thread)
-{
- u32 DbgInst0;
- int WaitCount;
-
- DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
-
- /* wait while debug status is busy */
- WaitCount = 0;
- while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT))
- WaitCount++;
-
- if (WaitCount >= XDMAPS_MAX_WAIT) {
- /* wait time out */
- xil_printf("PL330 device at %x debug status busy time out\n",
- BaseAddr);
-
- return -1;
- }
-
- /* write debug instruction 0 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
-
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
-
-
- /* run the command in DbgInst0 and DbgInst1 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
-
- return 0;
-}
-
-/****************************************************************************/
-/**
-*
-*
-* Free a buffer of the DMA program buffer.
-* @param Pool the DMA program pool.
-* @param Buf the DMA program buffer to be release.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
-{
- int Index;
- Xil_AssertVoid(Pool != NULL);
-
- for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
- if (Pool[Index].Buf == Buf) {
- if (Pool[Index].Allocated) {
- Pool[Index].Allocated = 0;
- }
- }
- }
-}
-
-/*****************************************************************************/
-/**
-* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
-*
-* @param BaseAddr PL330 device base address
-* @param Channel Channel number for the device
-* @param DmaProg DMA program starting address, this should be DMA address
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-****************************************************************************/
-static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
-{
- char DmaGoProg[8];
- u32 DbgInst0;
- u32 DbgInst1;
-
- int WaitCount;
-
- XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
-
- DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
- DbgInst1 = (u32)DmaProg;
-
- /* wait while debug status is busy */
- WaitCount = 0;
- while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT)) {
-
- WaitCount++;
- }
-
- if (WaitCount >= XDMAPS_MAX_WAIT) {
- xil_printf("PL330 device at %x debug status busy time out\r\n",
- BaseAddr);
- return -1;
- }
-
- /* write debug instruction 0 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
- /* write debug instruction 1 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
-
-
- /* wait while the DMA Manager is busy */
- WaitCount = 0;
- while ((XDmaPs_ReadReg(BaseAddr,
- XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
- != XDMAPS_DS_DMA_STATUS_STOPPED
- && WaitCount <= XDMAPS_MAX_WAIT) {
- WaitCount++;
- }
-
- if (WaitCount >= XDMAPS_MAX_WAIT) {
- xil_printf("PL330 device at %x debug status busy time out\r\n",
- BaseAddr);
- return -1;
- }
-
- /* run the command in DbgInst0 and DbgInst1 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
-
- return 0;
-}
-
-
-/****************************************************************************/
-/**
-*
-* It's the generic Done ISR.
-* @param InstPtr is the DMA instance.
-* @param Channel is the DMA channel numer.
-*
-* @return None.*
-*
-* @note None.
-*
-*****************************************************************************/
-static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
-{
-
- void *DmaProgBuf;
- XDmaPs_ChannelData *ChanData;
- XDmaPs_Cmd *DmaCmd;
- //u32 Value;
-
- ChanData = InstPtr->Chans + Channel;
-
- /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTSTATUS_OFFSET);*/
-
- /* clear the interrupt status */
- XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTCLR_OFFSET,
- 1 << ChanData->ChanId);
-
- /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTSTATUS_OFFSET);*/
-
-
- DmaCmd = ChanData->DmaCmdToHw;
- if (DmaCmd) {
- if (!ChanData->HoldDmaProg) {
- DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
- if (DmaProgBuf)
- XDmaPs_BufPool_Free(ChanData->ProgBufPool,
- DmaProgBuf);
- DmaCmd->GeneratedDmaProg = NULL;
- }
-
- DmaCmd->DmaStatus = 0;
- ChanData->DmaCmdToHw = NULL;
- ChanData->DmaCmdFromHw = DmaCmd;
-
- if (ChanData->DoneHandler)
- ChanData->DoneHandler(Channel, DmaCmd,
- ChanData->DoneRef);
- }
-
-}
-
-
-/****************************************************************************/
-/**
-* Prints the content of the buffer in bytes
-* @param Buf is the buffer.
-* @param Length is the length of the DMA program.
-*
-* @return None.
-*
-* @note None.
-****************************************************************************/
-static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
-{
- int Index;
- for (Index = 0; Index < Length; Index++)
- xil_printf("[%x] %x\r\n", Index, Buf[Index]);
-
-}
-/****************************************************************************/
-/**
-* Print the Dma Prog Contents.
-*
-* @param Cmd is the command buffer.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
- void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
-{
- if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
- xil_printf("Generated DMA program (%d):\r\n",
- Cmd->GeneratedDmaProgLength);
- XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
- Cmd->GeneratedDmaProgLength);
- }
-
- if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
- xil_printf("User defined DMA program (%d):\r\n",
- Cmd->UserDmaProgLength);
- XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
- Cmd->UserDmaProgLength);
- }
-}
-
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
deleted file mode 100644
index 5a0c1a28e3d1a6a35a13ffe728420c260da05f5b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps.h
-* @addtogroup dmaps_v2_3
-* @{
-* @details
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-/**
- * To avoid linking error,Declare all inline functions as extern for
- * IAR compiler
- */
-#ifdef __ICCARM__
-extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
-extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
deleted file mode 100644
index 3bfe837e0ef1e40efbd23b458e8bcfd229590ca2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
+++ /dev/null
@@ -1,59 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xdmaps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_DMA_NS_DEVICE_ID,
- XPAR_PS7_DMA_NS_BASEADDR
- },
- {
- XPAR_PS7_DMA_S_DEVICE_ID,
- XPAR_PS7_DMA_S_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
deleted file mode 100644
index 4c0cfbfd216fa02e31d004cd2bd5e8e593c3a618..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps_hw.c
-* @addtogroup dmaps_v2_3
-* @{
-*
-* This file contains the implementation of the interface reset functionality
-* for XDmaPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.06a kpc 10/07/13 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-#ifndef XDMAPS_MAX_WAIT
-#define XDMAPS_MAX_WAIT 4000
-#endif
-/************************** Function Prototypes *****************************/
-
-/************************** Variable Definitions ****************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given dmaps interface by
-* configuring the appropriate control bits in the dmaps specifc registers
-* the dmaps reset squence involves the following steps
-* Disable all the interuupts
-* Clear the pending interrupts
-* Kill all the active channel threads
-* Kill the manager thread
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* dmaps controller
-******************************************************************************/
-void XDmaPs_ResetHw(u32 BaseAddress)
-{
- u32 DbgInst;
- u32 WaitCount = 0;
- u32 ChanIndex;
-
- /* Disable all the interrupts */
- XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
- /* Clear the interrupts */
- XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
- /* Kill the dma channel threads */
- for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
- while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT))
- WaitCount++;
-
- DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
- }
- /* Kill the manager thread */
- DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
-}
-
-
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
deleted file mode 100644
index 628f1ec4f92b9a685afcb900029ac9d3d41c89fa..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_3
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
deleted file mode 100644
index daebd9903f1d438672b0354b46fac2a3ad827134..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps_selftest.c
-* @addtogroup dmaps_v2_3
-* @{
-*
-* This file contains the self-test functions for the XDmaPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 hbm 03/29/2010 First Release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xdmaps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param InstPtr is a pointer to the XDmaPs instance
-*
-* @return
-*
-* - XST_SUCCESS if the test was successful
-* - XST_FAILURE if the test failed
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-int XDmaPs_SelfTest(XDmaPs *InstPtr)
-{
- u32 BaseAddr = InstPtr->Config.BaseAddress;
- int i;
-
- if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- return XST_FAILURE;
-
- for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
- if (XDmaPs_ReadReg(BaseAddr,
- XDmaPs_CSn_OFFSET(i)))
- return XST_FAILURE;
- }
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
deleted file mode 100644
index b92ee5311093796dfd0fbf6d8d41c1018a808c71..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xdmaps_sinit.c
-* @addtogroup dmaps_v2_3
-* @{
-*
-* The implementation of the XDmaPs driver's static initialzation
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/13/10 First Release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xdmaps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-extern XDmaPs_Config XDmaPs_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device
-*
-* @return
-*
-* A pointer to the configuration structure or NULL if the specified device
-* is not in the system.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
-{
- XDmaPs_Config *CfgPtr = NULL;
-
- int i;
-
- for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
- if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XDmaPs_ConfigTable[i];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile
deleted file mode 100644
index 7002e6223103acee2fa1224c2c241cde4bd095ab..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xemacps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling emacps"
-
-xemacps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xemacps_includes
-
-xemacps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
deleted file mode 100644
index c013c4946a7ac561d37d20a92e0dee47290ee764..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps.c
-* @addtogroup emacps_v3_7
-* @{
-*
-* The XEmacPs driver. Functions in this file are the minimum required functions
-* for this driver. See xemacps.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
-* 64-bit changes.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
-* Disable extended mode. Perform all 64 bit changes under
-* check for arch64.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
-* 3.5 hk 08/14/17 Update cache coherency information of the interface in
-* its config structure.
-*
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-void XEmacPs_StubHandler(void); /* Default handler routine */
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-* Initialize a specific XEmacPs instance/driver. The initialization entails:
-* - Initialize fields of the XEmacPs instance structure
-* - Reset hardware and apply default options
-* - Configure the DMA channels
-*
-* The PHY is setup independently from the device. Use the MII or whatever other
-* interface may be present for setup.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param CfgPtr is the device configuration structure containing required
-* hardware build data.
-* @param EffectiveAddress is the base address of the device. If address
-* translation is not utilized, this parameter can be passed in using
-* CfgPtr->Config.BaseAddress to specify the physical base address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-******************************************************************************/
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
- UINTPTR EffectiveAddress)
-{
- /* Verify arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- /* Set device base address and ID */
- InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddress;
- InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
-
- /* Set callbacks to an initial stub routine */
- InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
- InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
- InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
-
- /* Reset the hardware and set default options */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- XEmacPs_Reset(InstancePtr);
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
-* Start the Ethernet controller as follows:
-* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
-* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
-* - Start the SG DMA send and receive channels and enable the device
-* interrupt
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return N/A
-*
-* @note
-* Hardware is configured with scatter-gather DMA, the driver expects to start
-* the scatter-gather channels and expects that the user has previously set up
-* the buffer descriptor lists.
-*
-* This function makes use of internal resources that are shared between the
-* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
-* device options while another is trying to start the device, the user is
-* required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* This function must not be preempted by an interrupt that may service the
-* device.
-*
-******************************************************************************/
-void XEmacPs_Start(XEmacPs *InstancePtr)
-{
- u32 Reg;
-
- /* Assert bad arguments and conditions */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Start DMA */
- /* When starting the DMA channels, both transmit and receive sides
- * need an initialized BD list.
- */
- if (InstancePtr->Version == 2) {
- Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
- Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXQBASE_OFFSET,
- InstancePtr->RxBdRing.BaseBdAddr);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQBASE_OFFSET,
- InstancePtr->TxBdRing.BaseBdAddr);
- }
-
- /* clear any existed int status */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- /* Enable transmitter if not already enabled */
- if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
- }
- }
-
- /* Enable receiver if not already enabled */
- if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
- }
- }
-
- /* Enable TX and RX interrupts */
- XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
- XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
- (u32)XEMACPS_IXR_TXCOMPL_MASK));
-
- /* Enable TX Q1 Interrupts */
- if (InstancePtr->Version > 2)
- XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
-
- /* Mark as started */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-
- return;
-}
-
-
-/*****************************************************************************/
-/**
-* Gracefully stop the Ethernet MAC as follows:
-* - Disable all interrupts from this device
-* - Stop DMA channels
-* - Disable the tansmitter and receiver
-*
-* Device options currently in effect are not changed.
-*
-* This function will disable all interrupts. Default interrupts settings that
-* had been enabled will be restored when XEmacPs_Start() is called.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @note
-* This function makes use of internal resources that are shared between the
-* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
-* setting device options while another is trying to start the device, the user
-* is required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* Stopping the DMA channels causes this function to block until the DMA
-* operation is complete.
-*
-******************************************************************************/
-void XEmacPs_Stop(XEmacPs *InstancePtr)
-{
- u32 Reg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Disable all interrupts */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- /* Disable the receiver & transmitter */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
-
- /* Mark as stopped */
- InstancePtr->IsStarted = 0U;
-}
-
-
-/*****************************************************************************/
-/**
-* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
-* transmitter, and the receiver.
-*
-* Steps to reset
-* - Stops transmit and receive channels
-* - Stops DMA
-* - Configure transmit and receive buffer size to default
-* - Clear transmit and receive status register and counters
-* - Clear all interrupt sources
-* - Clear phy (if there is any previously detected) address
-* - Clear MAC addresses (1-4) as well as Type IDs and hash value
-*
-* All options are placed in their default state. Any frames in the
-* descriptor lists will remain in the lists. The side effect of doing
-* this is that after a reset and following a restart of the device, frames
-* were in the list before the reset may be transmitted or received.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the MAC after the reset. Note also that driver statistics
-* are not cleared on reset. It is up to the upper layer software to clear the
-* statistics if needed.
-*
-* When a reset is required, the driver notifies the upper layer software of
-* this need through the ErrorHandler callback and specific status codes.
-* The upper layer software is responsible for calling this Reset function
-* and then re-configuring the device.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-******************************************************************************/
-void XEmacPs_Reset(XEmacPs *InstancePtr)
-{
- u32 Reg;
- u8 i;
- s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Stop the device and reset hardware */
- XEmacPs_Stop(InstancePtr);
- InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
-
- InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
-
- InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
-
- InstancePtr->MaxMtuSize = XEMACPS_MTU;
- InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
- XEMACPS_TRL_SIZE;
- InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
- XEMACPS_HDR_VLAN_SIZE;
- InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
-
- /* Setup hardware with default values */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- (XEMACPS_NWCTRL_STATCLR_MASK |
- XEMACPS_NWCTRL_MDEN_MASK) &
- (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
-
- Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
- (u32)XEMACPS_NWCFG_FDEN_MASK |
- (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
- if (InstancePtr->Version > 2) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
- (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
- XEMACPS_NWCFG_DWIDTH_64_MASK));
- }
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET,
- (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
- (((((u32)XEMACPS_RX_BUF_SIZE %
- (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
- (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
- (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
- (u32)XEMACPS_DMACR_RXSIZE_MASK |
- (u32)XEMACPS_DMACR_TXSIZE_MASK);
-
-
- /* Single bursts */
- /* FIXME: Why Single bursts? */
- if (InstancePtr->Version > 2) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
- (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
-#ifdef __aarch64__
- (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
-#endif
- (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
- }
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET, 0x0U);
-
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
- if (InstancePtr->Version > 2)
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET, 0x0U);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_ISR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- Reg);
-
- XEmacPs_ClearHash(InstancePtr);
-
- for (i = 1U; i < 5U; i++) {
- (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
- (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
- }
-
- /* clear all counters */
- for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
- i++) {
- (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
- }
-
- /* Disable the receiver */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
-
- /* Sync default options with hardware but leave receiver and
- * transmitter disabled. They get enabled with XEmacPs_Start() if
- * XEMACPS_TRANSMITTER_ENABLE_OPTION and
- * XEMACPS_RECEIVER_ENABLE_OPTION are set.
- */
- (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
- ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
-
- (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
-}
-
-
-/******************************************************************************/
-/**
- * This is a stub for the asynchronous callbacks. The stub is here in case the
- * upper layer forgot to set the handler(s). On initialization, all handlers are
- * set to this callback. It is considered an error for this handler to be
- * invoked.
- *
- ******************************************************************************/
-void XEmacPs_StubHandler(void)
-{
- Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-* This function sets the start address of the transmit/receive buffer queue.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @QPtr Address of the Queue to be written
-* @QueueNum Buffer Queue Index
-* @Direction Transmit/Recive
-*
-* @note
-* The buffer queue addresses has to be set before starting the transfer, so
-* this function has to be called in prior to XEmacPs_Start()
-*
-******************************************************************************/
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction)
-{
- /* Assert bad arguments and conditions */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* If already started, then there is nothing to do */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- return;
- }
-
- if (QueueNum == 0x00U) {
- if (Direction == XEMACPS_SEND) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQBASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- } else {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXQBASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- }
- }
- else {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQ1BASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- }
-#ifdef __aarch64__
- if (Direction == XEMACPS_SEND) {
- /* Set the MSB of TX Queue start address */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_MSBBUF_TXQBASE_OFFSET,
- (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
- } else {
- /* Set the MSB of RX Queue start address */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_MSBBUF_RXQBASE_OFFSET,
- (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
- }
-#endif
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
deleted file mode 100644
index 6d4b15b24338a4618844512250528f0c1fc1897a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
+++ /dev/null
@@ -1,809 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_7
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * <b>Driver Description</b>
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * <b>Initialization & Configuration</b>
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * <b>Interrupts and Asynchronous Callbacks</b>
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * <b>Virtual Memory</b>
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * <b>DMA</b>
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not suppoted from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * <b>Alignment & Data Cache Restrictions</b>
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * <b>Buffer Copying</b>
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * <b>Checksum Offloading</b>
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * <b>PHY Interfaces</b>
- *
- * RGMII 1.3 is the only interface supported.
- *
- * <b>Asserts</b>
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- *
- * </pre>
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * paramter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
-* each bit set to 1 in <i>Mask</i>, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
deleted file mode 100644
index 83f9a87fc1e6b6411f50a38931636c0a20f1144c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
+++ /dev/null
@@ -1,804 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_7
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * <b>Buffer Descriptors</b>
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * <b>Performance</b>
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- *
- * </pre>
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include <string.h>
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within recevie BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
deleted file mode 100644
index 3536873dc9971f1572d48453363862fc92e66ed6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.c
-* @addtogroup emacps_v3_7
-* @{
-*
-* This file implements buffer descriptor ring related functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
-* Earlier it used to search in "BdLimit" number of BDs to
-* know which BDs are processed. Now one more check is
-* added. It looks for BDs till the current BD pointer
-* reaches HwTail. By doing this processing time is saved.
-* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
-* xemacps_bdring.c is modified. Now start of packet is
-* searched for returning the number of BDs processed.
-* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
-* removed. It is expected that all BDs are allocated in
-* from uncached area. Fix for CR #663885.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
-* pointers
-*
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_cache.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************
- * Compute the virtual address of a descriptor from its physical address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Virtual address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
- ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Compute the physical address of a descriptor from its virtual address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Physical address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
- ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
- * to the beginning of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is greater than
- * the high address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- * final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
- { \
- UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
- \
- Addr += ((RingPtr)->Separation * (NumBd)); \
- if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
- { \
- Addr -= (RingPtr)->Length; \
- } \
- \
- (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
- }
-
-/****************************************************************************
- * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
- * around to the end of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is less than
- * the base address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- * final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
- { \
- UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
- \
- Addr -= ((RingPtr)->Separation * (NumBd)); \
- if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
- { \
- Addr += (RingPtr)->Length; \
- } \
- \
- (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
- }
-
-
-/************************** Function Prototypes ******************************/
-
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
- * Using a memory segment allocated by the caller, create and setup the BD list
- * for the given DMA channel.
- *
- * @param RingPtr is the instance to be worked on.
- * @param PhysAddr is the physical base address of user memory region.
- * @param VirtAddr is the virtual base address of the user memory region. If
- * address translation is not being utilized, then VirtAddr should be
- * equivalent to PhysAddr.
- * @param Alignment governs the byte alignment of individual BDs. This function
- * will enforce a minimum alignment of 4 bytes with no maximum as long
- * as it is specified as a power of 2.
- * @param BdCount is the number of BDs to setup in the user memory region. It
- * is assumed the region is large enough to contain the BDs.
- *
- * @return
- *
- * - XST_SUCCESS if initialization was successful
- * - XST_NO_FEATURE if the provided instance is a non DMA type
- * channel.
- * - XST_INVALID_PARAM under any of the following conditions:
- * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
- * parameter.
- * 2) Alignment parameter does not meet minimum requirements or is not a
- * power of 2 value.
- * 3) BdCount is 0.
- * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
- * over address 0x00000000 in virtual address space.
- *
- * @note
- * Make sure to pass in the right alignment value.
- *****************************************************************************/
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
-{
- u32 i;
- UINTPTR BdVirtAddr;
- UINTPTR BdPhyAddr;
- UINTPTR VirtAddrLoc = VirtAddr;
-
- /* In case there is a failure prior to creating list, make sure the
- * following attributes are 0 to prevent calls to other functions
- * from doing anything.
- */
- RingPtr->AllCnt = 0U;
- RingPtr->FreeCnt = 0U;
- RingPtr->HwCnt = 0U;
- RingPtr->PreCnt = 0U;
- RingPtr->PostCnt = 0U;
-
- /* Make sure Alignment parameter meets minimum requirements */
- if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Make sure Alignment is a power of 2 */
- if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Make sure PhysAddr and VirtAddr are on same Alignment */
- if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Is BdCount reasonable? */
- if (BdCount == 0x00000000U) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Figure out how many bytes will be between the start of adjacent BDs */
- RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
-
- /* Must make sure the ring doesn't span address 0x00000000. If it does,
- * then the next/prev BD traversal macros will fail.
- */
- if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Initial ring setup:
- * - Clear the entire space
- * - Setup each BD's BDA field with the physical address of the next BD
- */
- (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
-
- BdVirtAddr = VirtAddrLoc;
- BdPhyAddr = PhysAddr + RingPtr->Separation;
- for (i = 1U; i < BdCount; i++) {
- BdVirtAddr += RingPtr->Separation;
- BdPhyAddr += RingPtr->Separation;
- }
-
- /* Setup and initialize pointers and counters */
- RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
- RingPtr->BaseBdAddr = VirtAddrLoc;
- RingPtr->PhysBaseAddr = PhysAddr;
- RingPtr->HighBdAddr = BdVirtAddr;
- RingPtr->Length =
- ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
- RingPtr->AllCnt = (u32)BdCount;
- RingPtr->FreeCnt = (u32)BdCount;
- RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
- RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Clone the given BD into every BD in the list.
- * every field of the source BD is replicated in every BD of the list.
- *
- * This function can be called only when all BDs are in the free group such as
- * they are immediately after initialization with XEmacPs_BdRingCreate().
- * This prevents modification of BDs while they are in use by hardware or the
- * user.
- *
- * @param RingPtr is the pointer of BD ring instance to be worked on.
- * @param SrcBdPtr is the source BD template to be cloned into the list. This
- * BD will be modified.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- * which direction.
- *
- * @return
- * - XST_SUCCESS if the list was modified.
- * - XST_DMA_SG_NO_LIST if a list has not been created.
- * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
- * hardware or user control.
- * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction)
-{
- u32 i;
- UINTPTR CurBd;
-
- /* Can't do this function if there isn't a ring */
- if (RingPtr->AllCnt == 0x00000000U) {
- return (LONG)(XST_DMA_SG_NO_LIST);
- }
-
- /* Can't do this function with the channel running */
- if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
- return (LONG)(XST_DEVICE_IS_STARTED);
- }
-
- /* Can't do this function with some of the BDs in use */
- if (RingPtr->FreeCnt != RingPtr->AllCnt) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Starting from the top of the ring, save BD.Next, overwrite the entire
- * BD with the template, then restore BD.Next
- */
- CurBd = RingPtr->BaseBdAddr;
- for (i = 0U; i < RingPtr->AllCnt; i++) {
- memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
- CurBd += RingPtr->Separation;
- }
-
- CurBd -= RingPtr->Separation;
-
- if (Direction == XEMACPS_RECV) {
- XEmacPs_BdSetRxWrap(CurBd);
- }
- else {
- XEmacPs_BdSetTxWrap(CurBd);
- }
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Reserve locations in the BD list. The set of returned BDs may be modified
- * in preparation for future DMA transaction(s). Once the BDs are ready to be
- * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
- * order which they were allocated here. Example:
- *
- * <pre>
- * NumBd = 2,
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
- *
- * if (Status != XST_SUCCESS)
- * {
- * *Not enough BDs available for the request*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i<NumBd; i++)
- * {
- * * Prepare CurBd *.....
- *
- * * Onto next BD *
- * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
- * }
- *
- * * Give list to hardware *
- * Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),
- * </pre>
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be allocated and given to hardware in the correct sequence:
- * <pre>
- * * Legal *
- * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
- *
- * * Legal *
- * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
- * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
- * XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
- *
- * * Not legal *
- * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
- * XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
- * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
- * </pre>
- *
- * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
- * of the BD set can be done using XEmacPs_BdRingNext() and
- * XEmacPs_BdRingPrev().
- *
- * @param RingPtr is a pointer to the BD ring instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for modification.
- *
- * @return
- * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
- * parameter.
- * - XST_FAILURE if there were not enough free BDs to satisfy the request.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- * @note Do not modify more BDs than the number requested with the NumBd
- * parameter. Doing so will lead to data corruption and system
- * instability.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr)
-{
- LONG Status;
- /* Enough free BDs available for the request? */
- if (RingPtr->FreeCnt < NumBd) {
- Status = (LONG)(XST_FAILURE);
- } else {
- /* Set the return argument and move FreeHead forward */
- *BdSetPtr = RingPtr->FreeHead;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
- RingPtr->FreeCnt -= NumBd;
- RingPtr->PreCnt += NumBd;
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
- * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
- * transferred to hardware with XEmacPs_BdRingToHw().
- *
- * This function helps out in situations when an unrelated error occurs after
- * BDs have been allocated but before they have been given to hardware.
- * An example of this type of error would be an OS running out of resources.
- *
- * This function is not the same as XEmacPs_BdRingFree(). The Free function
- * returns BDs to the free list after they have been processed by hardware,
- * while UnAlloc returns them before being processed by hardware.
- *
- * There are two scenarios where this function can be used. Full UnAlloc or
- * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
- *
- * <pre>
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
- * ...
- * if (Error)
- * {
- * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
- * }
- * </pre>
- *
- * A partial UnAlloc means some of the BDs Alloc'd will be returned:
- *
- * <pre>
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
- * BdsLeft = 10,
- * CurBdPtr = BdPtr,
- *
- * while (BdsLeft)
- * {
- * if (Error)
- * {
- * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
- * }
- *
- * CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
- * BdsLeft--,
- * }
- * </pre>
- *
- * A partial UnAlloc must include the last BD in the list that was Alloc'd.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for modification.
- *
- * @return
- * - XST_SUCCESS if the BDs were unallocated.
- * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
- * the preprocessing state.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- LONG Status;
- (void) BdSetPtr;
- Xil_AssertNonvoid(RingPtr != NULL);
- Xil_AssertNonvoid(BdSetPtr != NULL);
-
- /* Enough BDs in the free state for the request? */
- if (RingPtr->PreCnt < NumBd) {
- Status = (LONG)(XST_FAILURE);
- } else {
- /* Set the return argument and move FreeHead backward */
- XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
- RingPtr->FreeCnt += NumBd;
- RingPtr->PreCnt -= NumBd;
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Enqueue a set of BDs to hardware that were previously allocated by
- * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
- * under hardware control. Any changes made to these BDs after this point will
- * corrupt the BD list leading to data corruption and system instability.
- *
- * The set will be rejected if the last BD of the set does not mark the end of
- * a packet (see XEmacPs_BdSetLast()).
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs in the set.
- * @param BdSetPtr is the first BD of the set to commit to hardware.
- *
- * @return
- * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
- * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
- * did not have its "last" bit set.
- * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- * XEmacPs_BdRingAlloc().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 i;
- LONG Status;
- /* if no bds to process, simply return. */
- if (0U == NumBd){
- Status = (LONG)(XST_SUCCESS);
- } else {
- /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
- if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
- Status = (LONG)(XST_DMA_SG_LIST_ERROR);
- } else {
- CurBdPtr = BdSetPtr;
- for (i = 0U; i < NumBd; i++) {
- CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
- }
- /* Adjust ring pointers & counters */
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
- RingPtr->PreCnt -= NumBd;
- RingPtr->HwTail = CurBdPtr;
- RingPtr->HwCnt += NumBd;
-
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- * <pre>
- * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
- * if (NumBd == 0)
- * {
- * * hardware has nothing ready for us yet*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i<NumBd; i++)
- * {
- * * Examine CurBd for post processing *.....
- *
- * * Onto next BD *
- * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
- * }
- *
- * XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet), *Return list*
- * }
- * </pre>
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- * <pre>
- * * Legal *
- * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- *
- * * Legal *
- * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- *
- * * Not legal *
- * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- * </pre>
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for examination.
- *
- * @return
- * The number of BDs processed by hardware. A value of 0 indicates that no
- * data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 BdStr = 0U;
- u32 BdCount;
- u32 BdPartialCount;
- u32 Sop = 0U;
- u32 Status;
- u32 BdLimitLoc = BdLimit;
- CurBdPtr = RingPtr->HwHead;
- BdCount = 0U;
- BdPartialCount = 0U;
-
- /* If no BDs in work group, then there's nothing to search */
- if (RingPtr->HwCnt == 0x00000000U) {
- *BdSetPtr = NULL;
- Status = 0U;
- } else {
-
- if (BdLimitLoc > RingPtr->HwCnt){
- BdLimitLoc = RingPtr->HwCnt;
- }
- /* Starting at HwHead, keep moving forward in the list until:
- * - A BD is encountered with its new/used bit set which means
- * hardware has not completed processing of that BD.
- * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
- * - The number of requested BDs has been processed
- */
- while (BdCount < BdLimitLoc) {
- /* Read the status */
- if(CurBdPtr != NULL){
- BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
- }
-
- if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
- Sop = 1U;
- }
- if (Sop == 0x00000001U) {
- BdCount++;
- BdPartialCount++;
- }
-
- /* hardware has processed this BD so check the "last" bit.
- * If it is clear, then there are more BDs for the current
- * packet. Keep a count of these partial packet BDs.
- */
- if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
- Sop = 0U;
- BdPartialCount = 0U;
- }
-
- /* Move on to next BD in work group */
- CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
- }
-
- /* Subtract off any partial packet BDs found */
- BdCount -= BdPartialCount;
-
- /* If BdCount is non-zero then BDs were found to return. Set return
- * parameters, update pointers and counters, return success
- */
- if (BdCount > 0x00000000U) {
- *BdSetPtr = RingPtr->HwHead;
- RingPtr->HwCnt -= BdCount;
- RingPtr->PostCnt += BdCount;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
- Status = (BdCount);
- } else {
- *BdSetPtr = NULL;
- Status = 0U;
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- * <pre>
- * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
- *
- * if (NumBd == 0)
- * {
- * *hardware has nothing ready for us yet*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i<NumBd; i++)
- * {
- * * Examine CurBd for post processing *.....
- *
- * * Onto next BD *
- * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
- * }
- *
- * XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet), * Return list *
- * }
- * </pre>
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- * <pre>
- * * Legal *
- * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- *
- * * Legal *
- * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- *
- * * Not legal *
- * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
- * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
- * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
- * </pre>
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for examination.
- *
- * @return
- * The number of BDs processed by hardware. A value of 0 indicates that no
- * data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 BdStr = 0U;
- u32 BdCount;
- u32 BdPartialCount;
- u32 Status;
-
- CurBdPtr = RingPtr->HwHead;
- BdCount = 0U;
- BdPartialCount = 0U;
-
- /* If no BDs in work group, then there's nothing to search */
- if (RingPtr->HwCnt == 0x00000000U) {
- *BdSetPtr = NULL;
- Status = 0U;
- } else {
-
- /* Starting at HwHead, keep moving forward in the list until:
- * - A BD is encountered with its new/used bit set which means
- * hardware has completed processing of that BD.
- * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
- * - The number of requested BDs has been processed
- */
- while (BdCount < BdLimit) {
-
- /* Read the status */
- if(CurBdPtr!=NULL){
- BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
- }
- if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
- break;
- }
-
- BdCount++;
-
- /* hardware has processed this BD so check the "last" bit. If
- * it is clear, then there are more BDs for the current packet.
- * Keep a count of these partial packet BDs.
- */
- if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
- BdPartialCount = 0U;
- } else {
- BdPartialCount++;
- }
-
- /* Move on to next BD in work group */
- CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
- }
-
- /* Subtract off any partial packet BDs found */
- BdCount -= BdPartialCount;
-
- /* If BdCount is non-zero then BDs were found to return. Set return
- * parameters, update pointers and counters, return success
- */
- if (BdCount > 0x00000000U) {
- *BdSetPtr = RingPtr->HwHead;
- RingPtr->HwCnt -= BdCount;
- RingPtr->PostCnt += BdCount;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
- Status = (BdCount);
- }
- else {
- *BdSetPtr = NULL;
- Status = 0U;
- }
-}
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Frees a set of BDs that had been previously retrieved with
- * XEmacPs_BdRingFromHw().
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to free.
- * @param BdSetPtr is the head of a list of BDs returned by
- * XEmacPs_BdRingFromHw().
- *
- * @return
- * - XST_SUCCESS if the set of BDs was freed.
- * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- * XEmacPs_BdRingFromHw().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- LONG Status;
- /* if no bds to process, simply return. */
- if (0x00000000U == NumBd){
- Status = (LONG)(XST_SUCCESS);
- } else {
- /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
- if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
- Status = (LONG)(XST_DMA_SG_LIST_ERROR);
- } else {
- /* Update pointers and counters */
- RingPtr->FreeCnt += NumBd;
- RingPtr->PostCnt -= NumBd;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Check the internal data structures of the BD ring for the provided channel.
- * The following checks are made:
- *
- * - Is the BD ring linked correctly in physical address space.
- * - Do the internal pointers point to BDs in the ring.
- * - Do the internal counters add up.
- *
- * The channel should be stopped prior to calling this function.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- * which direction.
- *
- * @return
- * - XST_SUCCESS if the set of BDs was freed.
- * - XST_DMA_SG_NO_LIST if the list has not been created.
- * - XST_IS_STARTED if the channel is not stopped.
- * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
- * structures. If this value is returned, the channel should be reset to
- * avoid data corruption or system instability.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
-{
- UINTPTR AddrV, AddrP;
- u32 i;
-
- if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Is the list created */
- if (RingPtr->AllCnt == 0x00000000U) {
- return (LONG)(XST_DMA_SG_NO_LIST);
- }
-
- /* Can't check if channel is running */
- if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
- return (LONG)(XST_IS_STARTED);
- }
-
- /* RunState doesn't make sense */
- if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify internal pointers point to correct memory space */
- AddrV = (UINTPTR) RingPtr->FreeHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->PreHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->HwHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->HwTail;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->PostHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify internal counters add up */
- if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
- RingPtr->PostCnt) != RingPtr->AllCnt) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify BDs are linked correctly */
- AddrV = RingPtr->BaseBdAddr;
- AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
-
- for (i = 1U; i < RingPtr->AllCnt; i++) {
- /* Check BDA for this BD. It should point to next physical addr */
- if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Move on to next BD */
- AddrV += RingPtr->Separation;
- AddrP += RingPtr->Separation;
- }
-
- /* Last BD should have wrap bit set */
- if (XEMACPS_SEND == Direction) {
- if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
- }
- else { /* XEMACPS_RECV */
- if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
- }
-
- /* No problems found */
- return (LONG)(XST_SUCCESS);
-}
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
-{
- u32 DataValueRx;
- u32 *TempPtr;
-
- BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
- TempPtr = (u32 *)BdPtr;
- if(TempPtr != NULL) {
- DataValueRx = *TempPtr;
- DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
- *TempPtr = DataValueRx;
- }
-}
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
-{
- u32 DataValueTx;
- u32 *TempPtr;
-
- BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
- TempPtr = (u32 *)BdPtr;
- if(TempPtr != NULL) {
- DataValueTx = *TempPtr;
- DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
- *TempPtr = DataValueTx;
- }
-}
-
-/*****************************************************************************/
-/**
- * Reset BD ring head and tail pointers.
- *
- * @param RingPtr is the instance to be worked on.
- * @param VirtAddr is the virtual base address of the user memory region.
- *
- * @note
- * Should be called after XEmacPs_Stop()
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
- *
- *****************************************************************************/
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
-{
- RingPtr->FreeHead = virtaddrloc;
- RingPtr->PreHead = virtaddrloc;
- RingPtr->HwHead = virtaddrloc;
- RingPtr->HwTail = virtaddrloc;
- RingPtr->PostHead = virtaddrloc;
-}
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
deleted file mode 100644
index b89e89885b9109f3db432b7592b1d71dd8c6e88d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.h
-* @addtogroup emacps_v3_7
-* @{
-*
-* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
-* DMA functionalities.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
deleted file mode 100644
index 8217a45218239110247292b1bcfac9b2001e3fda..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
+++ /dev/null
@@ -1,1174 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xemacps_control.c
-* @addtogroup emacps_v3_7
-* @{
- *
- * Functions in this file implement general purpose command and control related
- * functionality. See xemacps.h for a detailed description of the driver.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * register. Added a new API for setting the BURST length
- * in DMACR register.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * </pre>
- *****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Set the MAC address for this driver/device. The address is a 48-bit value.
- * The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- * @param Index is a index to which MAC (1-4) address.
- *
- * @return
- * - XST_SUCCESS if the MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- *****************************************************************************/
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
- u32 MacAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 IndexLoc = Index;
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Aptr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- }
- else{
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- /* Set the MAC bits [31:0] in BOT */
- MacAddr = *(Aptr);
- MacAddr |= ((u32)(*(Aptr+1)) << 8U);
- MacAddr |= ((u32)(*(Aptr+2)) << 16U);
- MacAddr |= ((u32)(*(Aptr+3)) << 24U);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
- /* There are reserved bits in TOP so don't affect them */
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
-
- MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
-
- /* Set MAC bits [47:32] in TOP */
- MacAddr |= (u32)(*(Aptr+4));
- MacAddr |= (u32)(*(Aptr+5)) << 8U;
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Get the MAC address for this driver/device.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is an output parameter, and is a pointer to a buffer into
- * which the current MAC address will be copied.
- * @param Index is a index to which MAC (1-4) address.
- *
- *****************************************************************************/
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
- u32 MacAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 IndexLoc = Index;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Aptr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
- *Aptr = (u8) MacAddr;
- *(Aptr+1) = (u8) (MacAddr >> 8U);
- *(Aptr+2) = (u8) (MacAddr >> 16U);
- *(Aptr+3) = (u8) (MacAddr >> 24U);
-
- /* Read MAC bits [47:32] in TOP */
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
- *(Aptr+4) = (u8) MacAddr;
- *(Aptr+5) = (u8) (MacAddr >> 8U);
-}
-
-
-/*****************************************************************************/
-/**
- * Set 48-bit MAC addresses in hash table.
- * The device must be stopped before calling this function.
- *
- * The hash address register is 64 bits long and takes up two locations in
- * the memory map. The least significant bits are stored in hash register
- * bottom and the most significant bits in hash register top.
- *
- * The unicast hash enable and the multicast hash enable bits in the network
- * configuration register enable the reception of hash matched frames. The
- * destination address is reduced to a 6 bit index into the 64 bit hash
- * register using the following hash function. The hash function is an XOR
- * of every sixth bit of the destination address.
- *
- * <pre>
- * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
- * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
- * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
- * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
- * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
- * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
- * </pre>
- *
- * da[0] represents the least significant bit of the first byte received,
- * that is, the multicast/unicast indicator, and da[47] represents the most
- * significant bit of the last byte received.
- *
- * If the hash index points to a bit that is set in the hash register then
- * the frame will be matched according to whether the frame is multicast
- * or unicast.
- *
- * A multicast match will be signaled if the multicast hash enable bit is
- * set, da[0] is logic 1 and the hash index points to a bit set in the hash
- * register.
- *
- * A unicast match will be signaled if the unicast hash enable bit is set,
- * da[0] is logic 0 and the hash index points to a bit set in the hash
- * register.
- *
- * To receive all multicast frames, the hash register should be set with
- * all ones and the multicast hash enable bit should be set in the network
- * configuration register.
- *
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- *
- * @return
- * - XST_SUCCESS if the HASH MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
- * requirement after calculation
- *
- * @note
- * Having Aptr be unsigned type prevents the following operations from sign
- * extending.
- *****************************************************************************/
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
-{
- u32 HashAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
- u32 Result;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(AddressPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- } else {
- Temp1 = (*(Aptr+0)) & 0x3FU;
- Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
-
- Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
- Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
- Temp5 = (*(Aptr+3)) & 0x3FU;
- Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
- Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
- Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
-
- Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
- (u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
-
- if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
- Status = (LONG)(XST_INVALID_PARAM);
- } else {
-
- if (Result < (u32)32) {
- HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHL_OFFSET);
- HashAddr |= (u32)(0x00000001U << Result);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHL_OFFSET, HashAddr);
- } else {
- HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHH_OFFSET);
- HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHH_OFFSET, HashAddr);
- }
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * Delete 48-bit MAC addresses in hash table.
- * The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- *
- * @return
- * - XST_SUCCESS if the HASH MAC address was deleted successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
- * requirement after calculation
- *
- * @note
- * Having Aptr be unsigned type prevents the following operations from sign
- * extending.
- *****************************************************************************/
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
-{
- u32 HashAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
- u32 Result;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Aptr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- } else {
- Temp1 = (*(Aptr+0)) & 0x3FU;
- Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
- Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
- Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
- Temp5 = (*(Aptr+3)) & 0x3FU;
- Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
- Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
- Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
-
- Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
- (u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
-
- if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
- Status = (LONG)(XST_INVALID_PARAM);
- } else {
- if (Result < (u32)32) {
- HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHL_OFFSET);
- HashAddr &= (u32)(~(0x00000001U << Result));
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHL_OFFSET, HashAddr);
- } else {
- HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHH_OFFSET);
- HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHH_OFFSET, HashAddr);
- }
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-/*****************************************************************************/
-/**
- * Clear the Hash registers for the mac address pointed by AddressPtr.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- *
- *****************************************************************************/
-void XEmacPs_ClearHash(XEmacPs *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHL_OFFSET, 0x0U);
-
- /* write bits [63:32] in TOP */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHH_OFFSET, 0x0U);
-}
-
-
-/*****************************************************************************/
-/**
- * Get the Hash address for this driver/device.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is an output parameter, and is a pointer to a buffer into
- * which the current HASH MAC address will be copied.
- *
- *****************************************************************************/
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
-{
- u32 *Aptr = (u32 *)(void *)AddressPtr;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(AddressPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- *(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHL_OFFSET);
-
- /* Read Hash bits [63:32] in TOP */
- *(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_HASHH_OFFSET);
-}
-
-
-/*****************************************************************************/
-/**
- * Set the Type ID match for this driver/device. The register is a 32-bit
- * value. The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Id_Check is type ID to be configured.
- * @param Index is a index to which Type ID (1-4).
- *
- * @return
- * - XST_SUCCESS if the MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- *****************************************************************************/
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
-{
- u8 IndexLoc = Index;
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- } else {
-
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- /* Set the ID bits in MATCHx register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * Set options for the driver/device. The driver should be stopped with
- * XEmacPs_Stop() before changing options.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Options are the options to set. Multiple options can be set by OR'ing
- * XTE_*_OPTIONS constants together. Options not specified are not
- * affected.
- *
- * @return
- * - XST_SUCCESS if the options were set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- * @note
- * See xemacps.h for a description of the available options.
- *
- *****************************************************************************/
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
-{
- u32 Reg; /* Generic register contents */
- u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */
- u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- } else {
-
- /* Many of these options will change the NET_CONFIG registers.
- * To reduce the amount of IO to the device, group these options here
- * and change them all at once.
- */
-
- /* Grab current register contents */
- RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- RegNewNetCfg = RegNetCfg;
-
- /*
- * It is configured to max 1536.
- */
- if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
- RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
- }
-
- /* Turn on VLAN packet only, only VLAN tagged will be accepted */
- if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
- }
-
- /* Turn on FCS stripping on receive packets */
- if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
- }
-
- /* Turn on length/type field checking on receive packets */
- if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
- }
-
- /* Turn on flow control */
- if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
- }
-
- /* Turn on promiscuous frame filtering (all frames are received) */
- if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
- }
-
- /* Allow broadcast address reception */
- if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
- }
-
- /* Allow multicast address filtering */
- if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
- }
-
- /* enable RX checksum offload */
- if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
- }
-
- /* Enable jumbo frames */
- if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
- (InstancePtr->Version > 2)) {
- RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
- Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
- Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
- (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
- (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
- (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
- (u32)(XEMACPS_DMACR_RXBUF_MASK));
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET, Reg);
- InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
- InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
- XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
- InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
- XEMACPS_HDR_VLAN_SIZE;
- InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
- }
-
- if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
- (InstancePtr->Version > 2)) {
- RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
- XEMACPS_NWCFG_PCSSEL_MASK);
- }
-
- /* Officially change the NET_CONFIG registers if it needs to be
- * modified.
- */
- if (RegNetCfg != RegNewNetCfg) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
- }
-
- /* Enable TX checksum offload */
- if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
- Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET, Reg);
- }
-
- /* Enable transmitter */
- if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg |= XEMACPS_NWCTRL_TXEN_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
- }
-
- /* Enable receiver */
- if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg |= XEMACPS_NWCTRL_RXEN_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
- }
-
- /* The remaining options not handled here are managed elsewhere in the
- * driver. No register modifications are needed at this time. Reflecting
- * the option in InstancePtr->Options is good enough for now.
- */
-
- /* Set options word to its new value */
- InstancePtr->Options |= Options;
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Clear options for the driver/device
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Options are the options to clear. Multiple options can be cleared by
- * OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
- * are not affected.
- *
- * @return
- * - XST_SUCCESS if the options were set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- * @note
- * See xemacps.h for a description of the available options.
- *
- *****************************************************************************/
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
-{
- u32 Reg; /* Generic */
- u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */
- u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- } else {
-
- /* Many of these options will change the NET_CONFIG registers.
- * To reduce the amount of IO to the device, group these options here
- * and change them all at once.
- */
-
- /* Grab current register contents */
- RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- RegNewNetCfg = RegNetCfg;
-
- /* There is only RX configuration!?
- * It is configured in two different length, upto 1536 and 10240 bytes
- */
- if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
- }
-
- /* Turn off VLAN packet only */
- if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
- }
-
- /* Turn off FCS stripping on receive packets */
- if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
- }
-
- /* Turn off length/type field checking on receive packets */
- if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
- }
-
- /* Turn off flow control */
- if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
- }
-
- /* Turn off promiscuous frame filtering (all frames are received) */
- if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
- }
-
- /* Disallow broadcast address filtering => broadcast reception */
- if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
- RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
- }
-
- /* Disallow multicast address filtering */
- if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
- }
-
- /* Disable RX checksum offload */
- if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
- }
-
- /* Disable jumbo frames */
- if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
- (InstancePtr->Version > 2)) {
- RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
- Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
- Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
- (((((u32)XEMACPS_RX_BUF_SIZE %
- (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
- (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
- (u32)(XEMACPS_DMACR_RXBUF_MASK));
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET, Reg);
- InstancePtr->MaxMtuSize = XEMACPS_MTU;
- InstancePtr->MaxFrameSize = XEMACPS_MTU +
- XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
- InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
- XEMACPS_HDR_VLAN_SIZE;
- InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
- }
-
- if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
- (InstancePtr->Version > 2)) {
- RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
- XEMACPS_NWCFG_PCSSEL_MASK));
- }
-
- /* Officially change the NET_CONFIG registers if it needs to be
- * modified.
- */
- if (RegNetCfg != RegNewNetCfg) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
- }
-
- /* Disable TX checksum offload */
- if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
- Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET, Reg);
- }
-
- /* Disable transmitter */
- if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
- }
-
- /* Disable receiver */
- if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
- }
-
- /* The remaining options not handled here are managed elsewhere in the
- * driver. No register modifications are needed at this time. Reflecting
- * option in InstancePtr->Options is good enough for now.
- */
-
- /* Set options word to its new value */
- InstancePtr->Options &= ~Options;
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Get current option settings
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- *
- * @return
- * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
- * as a set opion.
- *
- * @note
- * See xemacps.h for a description of the available options.
- *
- *****************************************************************************/
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- return (InstancePtr->Options);
-}
-
-
-/*****************************************************************************/
-/**
- * Send a pause packet
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- *
- * @return
- * - XST_SUCCESS if pause frame transmission was initiated
- * - XST_DEVICE_IS_STOPPED if the device has not been started.
- *
- *****************************************************************************/
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
-{
- u32 Reg;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Make sure device is ready for this operation */
- if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STOPPED);
- } else {
- /* Send flow control frame */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
- * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
- *
- * @param InstancePtr references the TEMAC channel on which to operate.
- *
- * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
- * megabits per second.
- *
- * @note
- *
- *****************************************************************************/
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
-{
- u32 Reg;
- u16 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
-
- if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
- Status = (u16)(1000);
- } else {
- if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
- Status = (u16)(100);
- } else {
- Status = (u16)(10);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
- * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
- * link speed.
- *
- * @param InstancePtr references the TEMAC channel on which to operate.
- * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
- * or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
- *
- * @note
- *
- *****************************************************************************/
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
-{
- u32 Reg;
- u16 Status;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
-
- switch (Speed) {
- case (u16)10:
- Status = 0U;
- break;
-
- case (u16)100:
- Status = 0U;
- Reg |= XEMACPS_NWCFG_100_MASK;
- break;
-
- case (u16)1000:
- Status = 0U;
- Reg |= XEMACPS_NWCFG_1000_MASK;
- break;
-
- default:
- Status = 1U;
- break;
- }
- if(Status == (u16)1){
- return;
- }
-
- /* Set register and return */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
-}
-
-
-/*****************************************************************************/
-/**
- * Set the MDIO clock divisor.
- *
- * Calculating the divisor:
- *
- * <pre>
- * f[HOSTCLK]
- * f[MDC] = -----------------
- * (1 + Divisor) * 2
- * </pre>
- *
- * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
- * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
- * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
- * access. Here is the table to show values to generate MDC,
- *
- * <pre>
- * 000 : divide pclk by 8 (pclk up to 20 MHz)
- * 001 : divide pclk by 16 (pclk up to 40 MHz)
- * 010 : divide pclk by 32 (pclk up to 80 MHz)
- * 011 : divide pclk by 48 (pclk up to 120 MHz)
- * 100 : divide pclk by 64 (pclk up to 160 MHz)
- * 101 : divide pclk by 96 (pclk up to 240 MHz)
- * 110 : divide pclk by 128 (pclk up to 320 MHz)
- * 111 : divide pclk by 224 (pclk up to 540 MHz)
- * </pre>
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
- *
- *****************************************************************************/
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
-{
- u32 Reg;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- /* clear these three bits, could be done with mask */
- Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
-
- Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
-}
-
-
-/*****************************************************************************/
-/**
-* Read the current value of the PHY register indicated by the PhyAddress and
-* the RegisterNum parameters. The MAC provides the driver with the ability to
-* talk to a PHY that adheres to the Media Independent Interface (MII) as
-* defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be read (supports multiple
-* PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-* to read
-* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
-* which the current value of the register will be copied.
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was read from successfully
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the read is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr)
-{
- u32 Mgtcr;
- volatile u32 Ipisr;
- u32 IpReadTemp;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Make sure no other PHY operation is currently in progress */
- if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET) &
- XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
- Status = (LONG)(XST_EMAC_MII_BUSY);
- } else {
-
- /* Construct Mgtcr mask for the operation */
- Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
- (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
- (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
-
- /* Write Mgtcr and wait for completion */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
- do {
- Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET);
- IpReadTemp = Ipisr;
- } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
- /* Read data */
- *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET);
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-* Write data to the specified PHY register. The Ethernet driver does not
-* require the device to be stopped before writing to the PHY. Although it is
-* probably a good idea to stop the device, it is the responsibility of the
-* application to deem this necessary. The MAC provides the driver with the
-* ability to talk to a PHY that adheres to the Media Independent Interface
-* (MII) as defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be written (supports multiple
-* PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-* to write
-* @param PhyData is the 16-bit value that will be written to the register
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
-* status from the MAC on a write, the user should read the PHY to verify the
-* write was successful.
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the write is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData)
-{
- u32 Mgtcr;
- volatile u32 Ipisr;
- u32 IpWriteTemp;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Make sure no other PHY operation is currently in progress */
- if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET) &
- XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
- Status = (LONG)(XST_EMAC_MII_BUSY);
- } else {
- /* Construct Mgtcr mask for the operation */
- Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
- (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
- (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
-
- /* Write Mgtcr and wait for completion */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
- do {
- Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET);
- IpWriteTemp = Ipisr;
- } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* API to update the Burst length in the DMACR register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param BLength is the length in bytes for the dma burst.
-*
-* @return None
-*
-******************************************************************************/
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
-{
- u32 Reg;
- u32 RegUpdateVal;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
- (BLength == XEMACPS_4BYTE_BURST) ||
- (BLength == XEMACPS_8BYTE_BURST) ||
- (BLength == XEMACPS_16BYTE_BURST));
-
- switch (BLength) {
- case XEMACPS_SINGLE_BURST:
- RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
- break;
-
- case XEMACPS_4BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
- break;
-
- case XEMACPS_8BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
- break;
-
- case XEMACPS_16BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
- break;
-
- default:
- RegUpdateVal = 0x00000000U;
- break;
- }
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
-
- Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
- Reg |= RegUpdateVal;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
- Reg);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
deleted file mode 100644
index 0987122615b0139e167a23f1d96571e95806e7ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
+++ /dev/null
@@ -1,56 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xemacps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_ETHERNET_0_DEVICE_ID,
- XPAR_PS7_ETHERNET_0_BASEADDR,
- XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
deleted file mode 100644
index 00e79a58d4366895b81d3efc6c47fff5c703b9a6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.c
-* @addtogroup emacps_v3_7
-* @{
-*
-* This file contains the implementation of the ethernet interface reset sequence
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.05a kpc 28/06/13 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps_hw.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given emacps interface by
-* configuring the appropriate control bits in the emacps specifc registers.
-* the emacps reset squence involves the following steps
-* Disable all the interuupts
-* Clear the status registers
-* Disable Rx and Tx engines
-* Update the Tx and Rx descriptor queue registers with reset values
-* Update the other relevant control registers with reset value
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* emacps controller
-******************************************************************************/
-void XEmacPs_ResetHw(u32 BaseAddr)
-{
- u32 RegVal;
-
- /* Disable the interrupts */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
-
- /* Stop transmission,disable loopback and Stop tx and Rx engines */
- RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
- RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
- (u32)XEMACPS_NWCTRL_RXEN_MASK|
- (u32)XEMACPS_NWCTRL_HALTTX_MASK|
- (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
- /* Clear the statistic registers, flush the packets in DPRAM*/
- RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
- XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
- XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
- /* Clear the interrupt status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
- /* Clear the tx status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
- (u32)XEMACPS_TXSR_TXCOMPL_MASK|
- (u32)XEMACPS_TXSR_TXGO_MASK));
- /* Clear the rx status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
- XEMACPS_RXSR_FRAMERX_MASK);
- /* Clear the tx base address */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
- /* Clear the rx base address */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
- /* Update the network config register with reset value */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
- /* Update the hash address registers with reset value */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
- XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
deleted file mode 100644
index e535470c2e5b0c663b26a7780c0e2c42ccdb5edb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_7
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
- transmitted */
-#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
- */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
deleted file mode 100644
index 9c355a1637b433df11d1cc19a18bd6822163a74e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_intr.c
-* @addtogroup emacps_v3_7
-* @{
-*
-* Functions in this file implement general purpose interrupt processing related
-* functionality. See xemacps.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
-* Rx errors. Under heavy Rx traffic, there will be a large
-* number of errors related to receive buffer not available.
-* Because of a HW bug (SI #692601), under such heavy errors,
-* the Rx data path can become unresponsive. To reduce the
-* probabilities for hitting this HW bug, the SW writes to
-* bit 18 to flush a packet from Rx DPRAM immediately. The
-* changes for it are done in the function
-* XEmacPs_IntrHandler.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
-* and 64-bit changes.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
-* there is no error. CR# 869403
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Install an asynchronious handler function for the given HandlerType:
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param HandlerType indicates what interrupt handler type is.
- * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
- * XEMACPS_HANDLER_ERROR.
- * @param FuncPointer is the pointer to the callback function
- * @param CallBackRef is the upper layer callback reference passed back when
- * when the callback function is invoked.
- *
- * @return
- *
- * None.
- *
- * @note
- * There is no assert on the CallBackRef since the driver doesn't know what
- * it is.
- *
- *****************************************************************************/
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef)
-{
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(FuncPointer != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- switch (HandlerType) {
- case XEMACPS_HANDLER_DMASEND:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
- InstancePtr->SendRef = CallBackRef;
- break;
- case XEMACPS_HANDLER_DMARECV:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
- InstancePtr->RecvRef = CallBackRef;
- break;
- case XEMACPS_HANDLER_ERROR:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
- InstancePtr->ErrorRef = CallBackRef;
- break;
- default:
- Status = (LONG)(XST_INVALID_PARAM);
- break;
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* Master interrupt handler for EMAC driver. This routine will query the
-* status of the device, bump statistics, and invoke user callbacks.
-*
-* This routine must be connected to an interrupt controller using OS/BSP
-* specific methods.
-*
-* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
-* interrupt.
-*
-******************************************************************************/
-void XEmacPs_IntrHandler(void *XEmacPsPtr)
-{
- u32 RegISR;
- u32 RegSR;
- u32 RegCtrl;
- u32 RegQ1ISR = 0U;
- XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* This ISR will try to handle as many interrupts as it can in a single
- * call. However, in most of the places where the user's error handler
- * is called, this ISR exits because it is expected that the user will
- * reset the device in nearly all instances.
- */
- RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_ISR_OFFSET);
-
- /* Read Transmit Q1 ISR */
-
- if (InstancePtr->Version > 2)
- RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET);
-
- /* Clear the interrupt status register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- RegISR);
-
- /* Receive complete interrupt */
- if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
- /* Clear RX status register RX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET,
- ((u32)XEMACPS_RXSR_FRAMERX_MASK |
- (u32)XEMACPS_RXSR_BUFFNA_MASK));
- InstancePtr->RecvHandler(InstancePtr->RecvRef);
- }
-
- /* Transmit Q1 complete interrupt */
- if ((InstancePtr->Version > 2) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear TX status register TX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET,
- XEMACPS_INTQ1SR_TXCOMPL_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET,
- ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
- (u32)XEMACPS_TXSR_USEDREAD_MASK));
- InstancePtr->SendHandler(InstancePtr->SendRef);
- }
-
- /* Transmit complete interrupt */
- if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
- /* Clear TX status register TX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET,
- ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
- (u32)XEMACPS_TXSR_USEDREAD_MASK));
- InstancePtr->SendHandler(InstancePtr->SendRef);
- }
-
- /* Receive error conditions interrupt */
- if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
- /* Clear RX status register */
- RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET, RegSR);
-
- /* Fix for CR # 692702. Write to bit 18 of net_ctrl
- * register to flush a packet out of Rx SRAM upon
- * an error for receive buffer not available. */
- if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
- RegCtrl =
- XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, RegCtrl);
- }
-
- if(RegSR != 0) {
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
- XEMACPS_RECV, RegSR);
- }
- }
-
- /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
- * will be asserted the same time.
- * Have to distinguish this bit to handle the real error condition.
- */
- /* Transmit Q1 error conditions interrupt */
- if ((InstancePtr->Version > 2) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear Interrupt Q1 status register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
- RegQ1ISR);
- }
-
- /* Transmit error conditions interrupt */
- if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
- (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear TX status register */
- RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET, RegSR);
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
- RegSR);
- }
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
deleted file mode 100644
index e2d2078af1a501356e901d70b9f38c8b013ff103..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemacps_sinit.c
-* @addtogroup emacps_v3_7
-* @{
-*
-* This file contains lookup method by device ID when success, it returns
-* pointer to config table to be used to initialize the device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 New
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/*************************** Variable Definitions *****************************/
-extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return
-* A pointer to the configuration table entry corresponding to the given
-* device ID, or NULL if no match is found.
-*
-******************************************************************************/
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
-{
- XEmacPs_Config *CfgPtr = NULL;
- u32 i;
-
- for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
- if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XEmacPs_ConfigTable[i];
- break;
- }
- }
-
- return (XEmacPs_Config *)(CfgPtr);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
deleted file mode 100644
index a88927f81af19f95afa2ff292bb3675aed0f3da0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=xgpio_l.h xgpio.h
-
-LIBSOURCES=*.c
-OUTS = *.o
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs:
- echo "Compiling gpio"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
- make clean
-
-include:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
deleted file mode 100644
index 9b7210064a3d8f8b57f3518b328b247b0014e613..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio.c
-* @addtogroup gpio_v4_3
-* @{
-*
-* The implementation of the XGpio driver's basic functionality. See xgpio.h
-* for more information about the driver.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
-* CfgInitialize() take a pointer to a config structure
-* instead of a device id. Moved Initialize() into
-* xgpio_sinit.c, and had Initialize() call CfgInitialize()
-* after it retrieved the config structure using the device
-* id. Removed include of xparameters.h along with any
-* dependencies on xparameters.h and the _g.c config table.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
-* macros to remove _m from the name.
-* 4.1 lks 11/18/15 Clean up of the comments in the code and
-* removed support for DCR bridge
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given configuration data.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the driver through the XGpio API must be
-* made with this pointer.
-* @param Config is a reference to a structure containing information
-* about a specific GPIO device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config. This function can initialize multiple
-* instance objects with the use of multiple calls giving different
-* Config information on each call.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if the initialization is successfull.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr)
-{
- /* Assert arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Set some default values. */
- InstancePtr->BaseAddress = EffectiveAddr;
-
- InstancePtr->InterruptPresent = Config->InterruptPresent;
- InstancePtr->IsDual = Config->IsDual;
-
- /*
- * Indicate the instance is now ready to use, initialized without error
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- return (XST_SUCCESS);
-}
-
-
-/****************************************************************************/
-/**
-* Set the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param DirectionMask is a bitmask specifying which discretes are input
-* and which are output. Bits set to 0 are output and bits set to 1
-* are input.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
- DirectionMask);
-}
-
-/****************************************************************************/
-/**
-* Get the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Bitmask specifying which discretes are input and
-* which are output. Bits set to 0 are output and bits set to 1 are
-* input.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-*****************************************************************************/
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) &&
- (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Read state of discretes for the specified GPIO channnel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Current copy of the discretes register.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) +
- XGPIO_DATA_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Write to discretes register for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Data is the value to be written to the discretes register.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert. See also XGpio_DiscreteSet() and
-* XGpio_DiscreteClear().
-*
-*****************************************************************************/
-void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
- Data);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
deleted file mode 100644
index 582d94a76e6c510583040cf343851f3d50a5c556..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_3
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-*
-* </pre>
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /* Unique ID of device */
- UINTPTR BaseAddress; /* Device base address */
- int InterruptPresent; /* Are interrupts supported in h/w */
- int IsDual; /* Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /* Device base address */
- u32 IsReady; /* Device is initialized and ready */
- int InterruptPresent; /* Are interrupts supported in h/w */
- int IsDual; /* Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
deleted file mode 100644
index 5ce0b58e9f977a13463d6fbffb76b1c1804fe4aa..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_extra.c
-* @addtogroup gpio_v4_3
-* @{
-*
-* The implementation of the XGpio driver's advanced discrete functions.
-* See xgpio.h for more information about the driver.
-*
-* @note
-*
-* These APIs can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 1 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 1 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /* Calculate the offset to the data register of the GPIO */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current |= Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 0 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 0 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /* Calculate the offset to the data register of the GPIO */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current &= ~Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
deleted file mode 100644
index d6e9244b00b0bebe61df367d3dbcdb5934d318f1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
+++ /dev/null
@@ -1,75 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xgpio.h"
-
-/*
-* The configuration table for devices
-*/
-
-XGpio_Config XGpio_ConfigTable[XPAR_XGPIO_NUM_INSTANCES] =
-{
- {
- XPAR_AXI_GPIO_3_DEVICE_ID,
- XPAR_AXI_GPIO_3_BASEADDR,
- XPAR_AXI_GPIO_3_INTERRUPT_PRESENT,
- XPAR_AXI_GPIO_3_IS_DUAL
- },
- {
- XPAR_AXI_GPIO_BTNS_DEVICE_ID,
- XPAR_AXI_GPIO_BTNS_BASEADDR,
- XPAR_AXI_GPIO_BTNS_INTERRUPT_PRESENT,
- XPAR_AXI_GPIO_BTNS_IS_DUAL
- },
- {
- XPAR_AXI_GPIO_LEDS_DEVICE_ID,
- XPAR_AXI_GPIO_LEDS_BASEADDR,
- XPAR_AXI_GPIO_LEDS_INTERRUPT_PRESENT,
- XPAR_AXI_GPIO_LEDS_IS_DUAL
- },
- {
- XPAR_AXI_GPIO_SWS_DEVICE_ID,
- XPAR_AXI_GPIO_SWS_BASEADDR,
- XPAR_AXI_GPIO_SWS_INTERRUPT_PRESENT,
- XPAR_AXI_GPIO_SWS_IS_DUAL
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
deleted file mode 100644
index 0e64915e9749f9b03a18d7f666da333e3253e5b4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-* @addtogroup gpio_v4_3
-* @{
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-* </pre>
-******************************************************************************/
-
-#ifndef XGPIO_I_H /* prevent circular inclusions */
-#define XGPIO_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions ****************************/
-
-extern XGpio_Config XGpio_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
deleted file mode 100644
index 887932a2a2355a907f8304a4161bb3487640a09e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_intr.c
-* @addtogroup gpio_v4_3
-* @{
-*
-* Implements GPIO interrupt processing functions for the XGpio driver.
-* See xgpio.h for more information about the driver.
-*
-* The functions in this file require the hardware device to be built with
-* interrupt capabilities. The functions will assert if called using hardware
-* that does not have interrupt capabilities.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.00a jhl 11/26/03 Initial release
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Enable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will not be passed through until the global enable
-* bit is set by this function. This function is designed to allow all
-* interrupts (both channels) to be enabled easily for exiting a critical
-* section. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
- XGPIO_GIE_GINTR_ENABLE_MASK);
-}
-
-
-/****************************************************************************/
-/**
-* Disable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will no longer be passed through until the global
-* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
-* designed to allow all interrupts (both channels) to be disabled easily for
-* entering a critical section. This function will assert if the hardware
-* device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
-
-}
-
-
-/****************************************************************************/
-/**
-* Enable interrupts. The global interrupt must also be enabled by calling
-* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
-* assert if the hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to enable. Bit positions of 1 are enabled.
-* This mask is formed by OR'ing bits from XGPIO_IR* bits which
-* are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only enable the specified
- * interrupts without disabling or enabling any others.
- */
-
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register | Mask);
-
-}
-
-
-/****************************************************************************/
-/**
-* Disable interrupts. This function allows specific interrupts for each
-* channel to be disabled. This function will assert if the hardware device
-* has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to disable. Bits set to 1 are disabled. This
-* mask is formed by OR'ing bits from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only disable the specified
- * interrupts without enabling or disabling any others.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register & (~Mask));
-
-}
-
-/****************************************************************************/
-/**
-* Clear pending interrupts with the provided mask. This function should be
-* called after the software has serviced the interrupts that are pending.
-* This function will assert if the hardware device has not been built with
-* interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to clear pending interrupts for. Bit positions
-* of 1 are cleared. This mask is formed by OR'ing bits from
-* XGPIO_IR* bits which are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt status register and only clear the interrupts
- * that are specified without affecting any others. Since the register
- * is a toggle on write, make sure any bits to be written are already
- * set.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
- Register & Mask);
-
-
-}
-
-
-/****************************************************************************/
-/**
-* Returns the interrupt enable mask. This function will assert if the
-* hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A mask of bits made from XGPIO_IR* bits which are contained in
-* xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-* Returns the status of interrupt signals. Any bit in the mask set to 1
-* indicates that the channel associated with the bit has asserted an interrupt
-* condition. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @note
-*
-* The interrupt status indicates the status of the device irregardless if
-* the interrupts from the devices have been enabled or not through
-* XGpio_InterruptEnable().
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
deleted file mode 100644
index 153fdfdf1674accc10904d2238d48db83ea4adae..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_3
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/* @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/*@}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
-/*@}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32
-#define XGpio_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
deleted file mode 100644
index 8b1d75fe6f246be7a9bdcd674606339d828a9e78..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_selftest.c
-* @addtogroup gpio_v4_3
-* @{
-*
-* The implementation of the XGpio driver's self test function.
-* See xgpio.h for more information about the driver.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/******************************************************************************/
-/**
-* Run a self-test on the driver/device. This function does a minimal test
-* in which the data register is read. It only does a read without any kind
-* of test because the hardware has been parameterized such that it may be only
-* an input such that the state of the inputs won't be known.
-*
-* All other hardware features of the device are not guaranteed to be in the
-* hardware since they are parameterizable.
-*
-*
-* @param InstancePtr is a pointer to the XGpio instance to be worked on.
-* This parameter must have been previously initialized with
-* XGpio_Initialize().
-*
-* @return XST_SUCCESS always. If the GPIO device was not present in the
-* hardware a bus error could be generated. Other indicators of a
-* bus error, such as registers in bridges or buses, may be
-* necessary to determine if this function caused a bus error.
-*
-* @note None.
-*
-******************************************************************************/
-int XGpio_SelfTest(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read from the data register of channel 1 which is always guaranteed
- * to be in the hardware device. Since the data may be configured as
- * all inputs, there is not way to guarantee the value read so don't
- * test it.
- */
- (void) XGpio_DiscreteRead(InstancePtr, 1);
-
- return (XST_SUCCESS);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
deleted file mode 100644
index 4d825b3eb9a78637b899b4bea5b1d10d875dd329..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2003 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_sinit.c
-* @addtogroup gpio_v4_3
-* @{
-*
-* The implementation of the XGpio driver's static initialzation
-* functionality.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.01a jvb 10/13/05 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-* 4.0 sha 07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not
-* defined in xparameters.h
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-#ifndef XPAR_XGPIO_NUM_INSTANCES
-#define XPAR_XGPIO_NUM_INSTANCES 0
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/******************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* ConfigTable contains the configuration info for each device in the system.
-*
-* @param DeviceId is the device identifier to lookup.
-*
-* @return
-* - A pointer of data type XGpio_Config which points to the
-* device configuration if DeviceID is found.
-* - NULL if DeviceID is not found.
-*
-* @note None.
-*
-******************************************************************************/
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
-{
- XGpio_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
- if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XGpio_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given DeviceID.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the instance/driver through the XGpio API
-* must be made with this pointer.
-* @param DeviceId is the unique id of the device controlled by this XGpio
-* instance. Passing in a device id associates the generic XGpio
-* instance to a specific device, as chosen by the caller or
-* application developer.
-*
-* @return
-* - XST_SUCCESS if the initialization was successfull.
-* - XST_DEVICE_NOT_FOUND if the device configuration data was not
-* found for a device with the supplied device ID.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
-{
- XGpio_Config *ConfigPtr;
-
- /*
- * Assert arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Lookup configuration data in the device configuration table.
- * Use this configuration info down below when initializing this
- * driver.
- */
- ConfigPtr = XGpio_LookupConfig(DeviceId);
- if (ConfigPtr == (XGpio_Config *) NULL) {
- InstancePtr->IsReady = 0;
- return (XST_DEVICE_NOT_FOUND);
- }
-
- return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
- ConfigPtr->BaseAddress);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile
deleted file mode 100644
index 8601ce4c7ccc85be4806137993703475251fb65e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xgpiops_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling gpiops"
-
-xgpiops_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xgpiops_includes
-
-xgpiops_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
deleted file mode 100644
index 7b6fe2e46010b2aafc4eabe582176a2c5d8295e5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.c
-* @addtogroup gpiops_v3_3
-* @{
-*
-* The XGpioPs driver. Functions in this file are the minimum required functions
-* for this driver. See xgpiops.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device. The interrupts are disabled
-* for output pins on all banks during initialization.
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
-
-/*****************************************************************************/
-/*
-*
-* This function initializes a XGpioPs instance/driver.
-* All members of the XGpioPs instance structure are initialized and
-* StubHandlers are assigned to the Bank Status Handlers.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param ConfigPtr points to the XGpioPs device configuration structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address should be passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return XST_SUCCESS always.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status = XST_SUCCESS;
- u8 i;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- Xil_AssertNonvoid(EffectiveAddr != (u32)0);
- /*
- * Set some default values for instance data, don't indicate the device
- * is ready to use until everything has been initialized successfully.
- */
- InstancePtr->IsReady = 0U;
- InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
- InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Handler = StubHandler;
- InstancePtr->Platform = XGetPlatform_Info();
-
- /* Initialize the Bank data based on platform */
- if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
- /*
- * Max pins in the ZynqMP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
- InstancePtr->MaxPinNum = (u32)174;
- InstancePtr->MaxBanks = (u8)6;
- } else {
- /*
- * Max pins in the GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
- InstancePtr->MaxPinNum = (u32)118;
- InstancePtr->MaxBanks = (u8)4;
- }
-
- /*
- * By default, interrupts are not masked in GPIO. Disable
- * interrupts for all pins in all the 4 banks.
- */
- for (i=0;i<InstancePtr->MaxBanks;i++) {
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
- }
-
- /* Indicate the component is now ready to use. */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Read the Data register of the specified GPIO bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Current value of the Data register.
-*
-* @note This function is used for reading the state of all the GPIO pins
-* of specified bank.
-*
-*****************************************************************************/
-u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_RO_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Read Data from the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the data has to be read.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* See xgpiops.h for the mapping of the pin numbers in the banks.
-*
-* @return Current value of the Pin (0 or 1).
-*
-* @note This function is used for reading the state of the specified
-* GPIO pin.
-*
-*****************************************************************************/
-u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
-
-}
-
-/****************************************************************************/
-/**
-*
-* Write to the Data register of the specified GPIO bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Data is the value to be written to the Data register.
-*
-* @return None.
-*
-* @note This function is used for writing to all the GPIO pins of
-* the bank. The previous state of the pins is not maintained.
-*
-*****************************************************************************/
-void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_OFFSET, Data);
-}
-
-/****************************************************************************/
-/**
-*
-* Write data to the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param Data is the data to be written to the specified pin (0 or 1).
-*
-* @return None.
-*
-* @note This function does a masked write to the specified pin of
-* the specified GPIO bank. The previous state of other pins
-* is maintained.
-*
-*****************************************************************************/
-void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
-{
- u32 RegOffset;
- u32 Value;
- u8 Bank;
- u8 PinNumber;
- u32 DataVar = Data;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- if (PinNumber > 15U) {
- /* There are only 16 data bits in bit maskable register. */
- PinNumber -= (u8)16;
- RegOffset = XGPIOPS_DATA_MSW_OFFSET;
- } else {
- RegOffset = XGPIOPS_DATA_LSW_OFFSET;
- }
-
- /*
- * Get the 32 bit value to be written to the Mask/Data register where
- * the upper 16 bits is the mask and lower 16 bits is the data.
- */
- DataVar &= (u32)0x01;
- Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
- RegOffset, Value);
-}
-
-
-
-/****************************************************************************/
-/**
-*
-* Set the Direction of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Direction is the 32 bit mask of the Pin direction to be set for
-* all the pins in the Bank. Bits with 0 are set to Input mode,
-* bits with 1 are set to Output Mode.
-*
-* @return None.
-*
-* @note This function is used for setting the direction of all the pins
-* in the specified bank. The previous state of the pins is
-* not maintained.
-*
-*****************************************************************************/
-void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET, Direction);
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Direction of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param Direction is the direction to be set for the specified pin.
-* Valid values are 0 for Input Direction, 1 for Output Direction.
-*
-* @return None.
-*
-*****************************************************************************/
-void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
-{
- u8 Bank;
- u8 PinNumber;
- u32 DirModeReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(Direction <= (u32)1);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET);
-
- if (Direction!=(u32)0) { /* Output Direction */
- DirModeReg |= ((u32)1 << (u32)PinNumber);
- } else { /* Input Direction */
- DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET, DirModeReg);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Direction of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* return Returns a 32 bit mask of the Direction register. Bits with 0 are
-* in Input mode, bits with 1 are in Output Mode.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Direction of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the Direction is to be
-* retrieved.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return Direction of the specified pin.
-* - 0 for Input Direction
-* - 1 for Output Direction
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Output Enable of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param OpEnable is the 32 bit mask of the Output Enables to be set for
-* all the pins in the Bank. The Output Enable of bits with 0 are
-* disabled, the Output Enable of bits with 1 are enabled.
-*
-* @return None.
-*
-* @note This function is used for setting the Output Enables of all the
-* pins in the specified bank. The previous state of the Output
-* Enables is not maintained.
-*
-*****************************************************************************/
-void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET, OpEnable);
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Output Enable of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param OpEnable specifies whether the Output Enable for the specified
-* pin should be enabled.
-* Valid values are 0 for Disabling Output Enable,
-* 1 for Enabling Output Enable.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
-{
- u8 Bank;
- u8 PinNumber;
- u32 OpEnableReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(OpEnable <= (u32)1);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET);
-
- if (OpEnable != (u32)0) { /* Enable Output Enable */
- OpEnableReg |= ((u32)1 << (u32)PinNumber);
- } else { /* Disable Output Enable */
- OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET, OpEnableReg);
-}
-/****************************************************************************/
-/**
-*
-* Get the Output Enable status of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* return Returns a a 32 bit mask of the Output Enable register.
-* Bits with 0 are in Disabled state, bits with 1 are in
-* Enabled State.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Output Enable status of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the Output Enable status is to
-* be retrieved.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return Output Enable of the specified pin.
-* - 0 if Output Enable is disabled for this pin
-* - 1 if Output Enable is enabled for this pin
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
-}
-
-/****************************************************************************/
-/*
-*
-* Get the Bank number and the Pin number in the Bank, for the given PinNumber
-* in the GPIO device.
-*
-* @param PinNumber is the Pin number in the GPIO device.
-* @param BankNumber returns the Bank in which this GPIO pin is present.
-* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
-* @param PinNumberInBank returns the Pin Number within the Bank.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
-{
- u32 XGpioPsPinTable[6] = {0};
- u32 Platform = XGetPlatform_Info();
-
- if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
- /*
- * This structure defines the mapping of the pin numbers to the banks when
- * the driver APIs are used for working on the individual pins.
- */
-
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
- XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
- XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
- XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
- XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
-
- *BankNumber = 0U;
- while (*BankNumber < 6U) {
- if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
- break;
- }
- (*BankNumber)++;
- }
- } else {
- XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
- XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
- XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
- XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
-
- *BankNumber = 0U;
- while (*BankNumber < 4U) {
- if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
- break;
- }
- (*BankNumber)++;
- }
- }
- if (*BankNumber == (u8)0) {
- *PinNumberInBank = PinNumber;
- } else {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
- }
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
deleted file mode 100644
index fda562d9190651d7a655d00c57d930d13fad5232..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
+++ /dev/null
@@ -1,277 +0,0 @@
-
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_3
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* <b>Driver Description</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* <b>Interrupts</b>
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* <b>Threads</b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b>Asserts</b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b>Building the driver</b>
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-* <br><br>
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* </pre>
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/*@}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
-} XGpioPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
deleted file mode 100644
index 25b9b1fafe923ad99066d2fc97f5bcea5e50ac49..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xgpiops.h"
-
-/*
-* The configuration table for devices
-*/
-
-XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_GPIO_0_DEVICE_ID,
- XPAR_PS7_GPIO_0_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
deleted file mode 100644
index 8961c4287d45ebcc218a7c30b2674bc50d54bdb0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.c
-* @addtogroup gpiops_v3_3
-* @{
-*
-* This file contains low level GPIO functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.02a hk 08/22/13 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops_hw.h"
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/*
-*
-* This function resets the GPIO module by writing reset values to
-* all registers
-*
-* @param Base address of GPIO module
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XGpioPs_ResetHw(u32 BaseAddress)
-{
- u32 BankCount;
- u32 Platform,MaxBanks;
-
- Platform = XGetPlatform_Info();
- if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
- MaxBanks = (u32)6;
- } else {
- MaxBanks = (u32)4;
- }
- /* Write reset values to all mask data registers */
- for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
-
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
- XGPIOPS_DATA_LSW_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
- XGPIOPS_DATA_MSW_OFFSET), 0x0U);
- }
- /* Write reset values to all output data registers */
- for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
-
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_OFFSET), 0x0U);
- }
-
- /* Reset all registers of all GPIO banks */
- for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
-
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET), 0x0U);
- XGpioPs_WriteReg(BaseAddress,
- ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET), 0x0U);
- }
-
- /* Bank 0 Int type */
- XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
- XGPIOPS_INTTYPE_BANK0_RESET);
- /* Bank 1 Int type */
- XGpioPs_WriteReg(BaseAddress,
- ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
- XGPIOPS_INTTYPE_BANK1_RESET);
- /* Bank 2 Int type */
- XGpioPs_WriteReg(BaseAddress,
- (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
- XGPIOPS_INTTYPE_BANK2_RESET);
- /* Bank 3 Int type */
- XGpioPs_WriteReg(BaseAddress,
- (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
- XGPIOPS_INTTYPE_BANK3_RESET);
-
- if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
- /* Bank 4 Int type */
- XGpioPs_WriteReg(BaseAddress,
- (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
- XGPIOPS_INTTYPE_BANK4_RESET);
- /* Bank 5 Int type */
- XGpioPs_WriteReg(BaseAddress,
- (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
- XGPIOPS_INTTYPE_BANK5_RESET);
- }
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
deleted file mode 100644
index ff01906750193cf49b097c7921a0c38c516c4641..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_3
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* </pre>
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
-/* @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
-/* @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(u32 BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
deleted file mode 100644
index a8b0a5626d591b03ac9036b19ef788effaeeb175..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
+++ /dev/null
@@ -1,731 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_intr.c
-* @addtogroup gpiops_v3_3
-* @{
-*
-* This file contains functions related to GPIO interrupt handling.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/18/10 First Release
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to API's. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
-
-/****************************************************************************/
-/**
-*
-* This function enables the interrupts for the specified pins in the specified
-* bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the bit mask of the pins for which interrupts are to
-* be enabled. Bit positions of 1 will be enabled. Bit positions
-* of 0 will keep the previous setting.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the interrupt for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt is to be enabled.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg = 0U;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- IntrReg = ((u32)1 << (u32)PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the interrupts for the specified pins in the specified
-* bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the bit mask of the pins for which interrupts are
-* to be disabled. Bit positions of 1 will be disabled. Bit
-* positions of 0 will keep the previous setting.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the interrupts for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt is to be disabled.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg = 0U;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- IntrReg = ((u32)1 << (u32)PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt enable status for a bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
-* indicate that the interrupt for that pin is enabled, bit
-* positions with 0 indicate that the interrupt for that pin is
-* disabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
-{
- u32 IntrMask;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-
- IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET);
- return (~IntrMask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns whether interrupts are enabled for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt enable status
-* is to be known.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return
-* - TRUE if the interrupt is enabled.
-* - FALSE if the interrupt is disabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET);
-
- return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns interrupt status read from Interrupt Status Register.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return The value read from Interrupt Status Register.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns interrupt enable status of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt enable status
-* is to be known.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return
-* - TRUE if the interrupt has occurred.
-* - FALSE if the interrupt has not occurred.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-
- return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears pending interrupt(s) with the provided mask. This
-* function should be called after the software has serviced the interrupts
-* that are pending.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the mask of the interrupts to be cleared. Bit positions
-* of 1 will be cleared. Bit positions of 0 will not change the
-* previous interrupt status.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- /* Clear the currently pending interrupts. */
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified pending interrupt. This function should be
-* called after the software has serviced the interrupts that are pending.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt status is to be
-* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- /* Clear the specified pending interrupts. */
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-
- IntrReg &= ((u32)1 << PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for setting the Interrupt Type, Interrupt Polarity and
-* Interrupt On Any for the specified GPIO Bank pins.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param IntrType is the 32 bit mask of the interrupt type.
-* 0 means Level Sensitive and 1 means Edge Sensitive.
-* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
-* 0 means Active Low or Falling Edge and 1 means Active High or
-* Rising Edge.
-* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
-* edge triggered interrupts. 0 means trigger on single edge using
-* the configured interrupt polarity and 1 means trigger on both
-* edges.
-*
-* @return None.
-*
-* @note This function is used for setting the interrupt related
-* properties of all the pins in the specified bank. The previous
-* state of the pins is not maintained.
-* To change the Interrupt properties of a single GPIO pin, use the
-* function XGpioPs_SetPinIntrType().
-*
-*****************************************************************************/
-void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET, IntrType);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET, IntrPolarity);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET, IntrOnAny);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for getting the Interrupt Type, Interrupt Polarity and
-* Interrupt On Any for the specified GPIO Bank pins.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param IntrType returns the 32 bit mask of the interrupt type.
-* 0 means Level Sensitive and 1 means Edge Sensitive.
-* @param IntrPolarity returns the 32 bit mask of the interrupt
-* polarity. 0 means Active Low or Falling Edge and 1 means
-* Active High or Rising Edge.
-* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
-* edge triggered interrupts. 0 means trigger on single edge using
-* the configured interrupt polarity and 1 means trigger on both
-* edges.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny)
-
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-
- *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET);
-
- *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET);
-
- *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for setting the IRQ Type of a single GPIO pin.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Pin is the pin number whose IRQ type is to be set.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
-* defined in xgpiops.h to specify the IRQ type.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
-{
- u32 IntrTypeReg;
- u32 IntrPolReg;
- u32 IntrOnAnyReg;
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET);
-
- IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET);
-
- IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET);
-
- switch (IrqType) {
- case XGPIOPS_IRQ_TYPE_EDGE_RISING:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrPolReg |= ((u32)1 << (u32)PinNumber);
- IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrPolReg &= ~((u32)1 << (u32)PinNumber);
- IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
- IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
- IntrPolReg |= ((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
- IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
- IntrPolReg &= ~((u32)1 << (u32)PinNumber);
- break;
- default:
- /**< Default statement is added for MISRA C compliance. */
- break;
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET, IntrPolReg);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the IRQ Type of a given GPIO pin.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Pin is the pin number whose IRQ type is to be obtained.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
-* returned by this function.
-*
-*****************************************************************************/
-u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
-{
- u32 IntrType;
- u32 IntrPol;
- u32 IntrOnAny;
- u8 Bank;
- u8 PinNumber;
- u8 IrqType;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-
- IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
-
- if (IntrType == ((u32)1 << PinNumber)) {
-
- IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
-
- IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
-
-
- if (IntrOnAny == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
- } else if (IntrPol == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
- } else {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
- }
- } else {
-
- IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
-
- if (IntrPol == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
- } else {
- IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
- }
- }
-
- return IrqType;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the status callback function. The callback function is
-* called by the XGpioPs_IntrHandler when an interrupt occurs.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
-*
-*
-* @return None.
-*
-* @note The handler is called within interrupt context, so it should do
-* its work quickly and queue potentially time-consuming work to a
-* task-level thread.
-*
-******************************************************************************/
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPointer != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = FuncPointer;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is the interrupt handler for GPIO interrupts.It checks the
-* interrupt status registers of all the banks to determine the actual bank in
-* which an interrupt has been triggered. It then calls the upper layer callback
-* handler set by the function XGpioPs_SetBankHandler(). The callback is called
-* when an interrupt
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-*
-* @return None.
-*
-* @note This function does not save and restore the processor context
-* such that the user must provide this processing.
-*
-******************************************************************************/
-void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
-{
- u8 Bank;
- u32 IntrStatus;
- u32 IntrEnabled;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
- IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
- if (IntrStatus != (u32)0) {
- IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
- Bank);
- XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
- (IntrStatus & IntrEnabled));
- InstancePtr->Handler(InstancePtr->
- CallBackRef, Bank,
- (IntrStatus & IntrEnabled));
- }
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers do not set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param Bank is the GPIO Bank in which an interrupt occurred.
-* @param Status is the Interrupt status of the GPIO bank.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
-{
- (void) CallBackRef;
- (void) Bank;
- (void) Status;
-
- Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
deleted file mode 100644
index 378524c14311e14230df5b92c3d2fb0a4168919e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_selftest.c
-* @addtogroup gpiops_v3_3
-* @{
-*
-* This file contains a diagnostic self-test function for the XGpioPs driver.
-*
-* Read xgpiops.h file for more information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/18/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xgpiops.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function runs a self-test on the GPIO driver/device. This function
-* does a register read/write test on some of the Interrupt Registers.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-*
-* @return
-* - XST_SUCCESS if the self-test passed.
-* - XST_FAILURE otherwise.
-*
-*
-******************************************************************************/
-s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
-{
- s32 Status = XST_SUCCESS;
- u32 IntrEnabled;
- u32 CurrentIntrType = 0U;
- u32 CurrentIntrPolarity = 0U;
- u32 CurrentIntrOnAny = 0U;
- u32 IntrType = 0U;
- u32 IntrPolarity = 0U;
- u32 IntrOnAny = 0U;
- u32 IntrTestValue = 0x22U;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Disable the Interrupts for Bank 0 . */
- IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
- XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
-
- /*
- * Get the Current Interrupt properties for Bank 0.
- * Set them to a known value, read it back and compare.
- */
- XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
- &CurrentIntrPolarity, &CurrentIntrOnAny);
-
- XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
- IntrTestValue, IntrTestValue);
-
- XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
- &IntrPolarity, &IntrOnAny);
-
- if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
- (IntrOnAny != IntrTestValue)) {
-
- Status = XST_FAILURE;
- }
-
- /*
- * Restore the contents of all the interrupt registers modified in this
- * test.
- */
- XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
- CurrentIntrPolarity, CurrentIntrOnAny);
-
- XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
-
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
deleted file mode 100644
index 4cc0c390f29b76c680c9eb42dfd61fc09894c3c3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_sinit.c
-* @addtogroup gpiops_v3_3
-* @{
-*
-* This file contains the implementation of the XGpioPs driver's static
-* initialization functionality.
-*
-* @note None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* This function looks for the device configuration based on the unique device
-* ID. The table XGpioPs_ConfigTable[] contains the configuration information
-* for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
-{
- XGpioPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
- if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XGpioPs_ConfigTable[Index];
- break;
- }
- }
-
- return (XGpioPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/Makefile
deleted file mode 100644
index 8c16c35aef36d4f0fda42e7679b98a8941e04a80..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xiicps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling iicps"
-
-xiicps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xiicps_includes
-
-xiicps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
deleted file mode 100644
index 9546b5490216ff792e5afe9f38c957b99d30de90..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* Contains implementation of required functions for the XIicPs driver.
-* See xiicps.h for detailed description of the device and driver.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- --------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 1.00a sdm 09/21/11 Updated the InstancePtr->Options in the
-* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
-* 2.1 hk 04/25/14 Explicitly reset CR and clear FIFO in Abort function
-* and state the same in the comments. CR# 784254.
-* Fix for CR# 761060 - provision for repeated start.
-* 2.3 sk 10/07/14 Repeated start feature removed.
-* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
-* in XIicPs_Reset.
-* 12/06/14 Implemented Repeated start feature.
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef, u32 StatusEvent);
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XIicPs instance such that the driver is ready to use.
-*
-* The state of the device after initialization is:
-* - Device is disabled
-* - Slave mode
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific IIC device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->BaseAddress for this parameter, passing the physical
-* address instead.
-*
-* @return The return value is XST_SUCCESS if successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * Set some default values.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
- InstancePtr->StatusHandler = StubHandler;
- InstancePtr->CallBackRef = NULL;
-
- InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
-
- /*
- * Reset the IIC device to get it into its initial state. It is expected
- * that device configuration will take place after this initialization
- * is done, but before the device is started.
- */
- XIicPs_Reset(InstancePtr);
-
- /*
- * Keep a copy of what options this instance has.
- */
- InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
-
- /* Initialize repeated start flag to 0 */
- InstancePtr->IsRepeatedStart = 0;
-
- return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* Check whether the I2C bus is busy
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return
-* - TRUE if the bus is busy.
-* - FALSE if the bus is not busy.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
-{
- u32 StatusReg;
- s32 Status;
-
- StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_SR_OFFSET);
- if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
- Status = (s32)TRUE;
- }else {
- Status = (s32)FALSE;
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference.
-* @param StatusEvent is the event that just occurred.
-* @param ByteCount is the number of bytes transferred up until the event
-* occurred.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef, u32 StatusEvent)
-{
- (void) ((void *)CallBackRef);
- (void) StatusEvent;
- Xil_AssertVoidAlways();
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
-* cleared.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIicPs_Abort(XIicPs *InstancePtr)
-{
- u32 IntrMaskReg;
- u32 IntrStatusReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /*
- * Enter a critical section, so disable the interrupts while we clear
- * the FIFO and the status register.
- */
- IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_IMR_OFFSET);
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
-
- /*
- * Reset the settings in config register and clear the FIFOs.
- */
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
- (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
-
- /*
- * Read, then write the interrupt status to make sure there are no
- * pending interrupts.
- */
- IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Restore the interrupt state.
- */
- IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_IER_OFFSET, IntrMaskReg);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the IIC device. Reset must only be called after the driver has been
-* initialized. The configuration of the device after reset is the same as its
-* configuration after initialization. Any data transfer that is in progress is
-* aborted.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and reenabling interrupts for the IIC device after the reset.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIicPs_Reset(XIicPs *InstancePtr)
-{
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /*
- * Abort any transfer that is in progress.
- */
- XIicPs_Abort(InstancePtr);
-
- /*
- * Reset any values so the software state matches the hardware device.
- */
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
- XIICPS_CR_RESET_VALUE);
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
- XIICPS_IXR_ALL_INTR_MASK);
-
-}
-/*****************************************************************************/
-/**
-* Put more data into the transmit FIFO, number of bytes is ether expected
-* number of bytes for this transfer or available space in FIFO, which ever
-* is less.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return Number of bytes left for this instance.
-*
-* @note This is function is shared by master and slave.
-*
-******************************************************************************/
-s32 TransmitFifoFill(XIicPs *InstancePtr)
-{
- u8 AvailBytes;
- s32 LoopCnt;
- s32 NumBytesToSend;
-
- /*
- * Determine number of bytes to write to FIFO.
- */
- AvailBytes = (u8)XIICPS_FIFO_DEPTH -
- (u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_TRANS_SIZE_OFFSET);
-
- if (InstancePtr->SendByteCount > (s32)AvailBytes) {
- NumBytesToSend = (s32)AvailBytes;
- } else {
- NumBytesToSend = InstancePtr->SendByteCount;
- }
-
- /*
- * Fill FIFO with amount determined above.
- */
- for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
- XIicPs_SendByte(InstancePtr);
- }
-
- return InstancePtr->SendByteCount;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
deleted file mode 100644
index d3713de471faaa1242d156a58b25ab89ced025b7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps.h
-* @addtogroup iicps_v3_7
-* @{
-* @details
-*
-* This is an implementation of IIC driver in the PS block. The device can
-* be either a master or a slave on the IIC bus. This implementation supports
-* both interrupt mode transfer and polled mode transfer. Only 7-bit address
-* is used in the driver, although the hardware also supports 10-bit address.
-*
-* IIC is a 2-wire serial interface. The master controls the clock, so it can
-* regulate when it wants to send or receive data. The slave is under control of
-* the master, it must respond quickly since it has no control of the clock and
-* must send/receive data as fast or as slow as the master does.
-*
-* The higher level software must implement a higher layer protocol to inform
-* the slave what to send to the master.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XIicPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
-* the static configuration structure defined in xiicps_g.c. This is
-* setup by the tools. For some operating systems the config structure
-* will be initialized by the software and this call is not needed.
-*
-* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a
-* system with address translation, the provided virtual memory base
-* address replaces the physical address in the configuration
-* structure.
-*
-* <b>Multiple Masters</b>
-*
-* More than one master can exist, bus arbitration is defined in the IIC
-* standard. Lost of arbitration causes arbitration loss interrupt on the device.
-*
-* <b>Multiple Slaves</b>
-*
-* Multiple slaves are supported by selecting them with unique addresses. It is
-* up to the system designer to be sure all devices on the IIC bus have
-* unique addresses.
-*
-* <b>Addressing</b>
-*
-* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
-* ability to control which address size is sent in messages as a master to a
-* slave device.
-*
-* <b>FIFO Size </b>
-* The hardware FIFO is 32 bytes deep. The user must know the limitations of
-* other IIC devices on the bus. Some are only able to receive a limited number
-* of bytes in a single transfer.
-*
-* <b>Data Rates</b>
-*
-* The data rate is set by values in the control register. The formula for
-* determining the correct register values is:
-* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
-*
-* When the device is configured as a slave, the slck setting controls the
-* sample rate and so must be set to be at least as fast as the fastest scl
-* expected to be seen in the system.
-*
-* <b>Polled Mode Operation</b>
-*
-* This driver supports polled mode transfers.
-*
-* <b>Interrupts</b>
-*
-* The user must connect the interrupt handler of the driver,
-* XIicPs_InterruptHandler to an interrupt system such that it will be called
-* when an interrupt occurs. This function does not save and restore the
-* processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Transfer complete
-* - More Data
-* - Transfer not Acknowledged
-* - Transfer Time out
-* - Monitored slave ready - master mode only
-* - Receive Overflow
-* - Transmit FIFO overflow
-* - Receive FIFO underflow
-* - Arbitration lost
-*
-* <b>Bus Busy</b>
-*
-* Bus busy is checked before the setup of a master mode device, to avoid
-* unnecessary arbitration loss interrupt.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied by
-* the layer above this driver.
-*
-*<b>Repeated Start</b>
-*
-* The I2C controller does not indicate completion of a receive transfer if HOLD
-* bit is set. Due to this errata, repeated start cannot be used if a receive
-* transfer is followed by any other transfer.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00a drg/jz 01/30/08 First release
-* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
-* XIicPs_ClearOptions where the InstancePtr->Options
-* was not updated correctly.
-* Updated the InstancePtr->Options in the
-* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
-* Updated the XIicPs_SetupMaster to not check for
-* Bus Busy condition when the Hold Bit is set.
-* Removed some unused variables.
-* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
-* check for transfer completion is added, which indicates
-* the completion of current transfer.
-* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
-* to achieve I2C clock with minimum error for
-* CR #674195
-* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
-* This is fix for CR#704398 to remove warning.
-* 2.0 hk 03/07/14 Added check for error status in the while loop that
-* checks for completion.
-* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
-* Limited frequency set when 100KHz or 400KHz is
-* selected. This is a hardware limitation. CR#779290.
-* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
-* Explicitly reset CR and clear FIFO in Abort function
-* and state the same in the comments. CR# 784254.
-* Fix for CR# 761060 - provision for repeated start.
-* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
-* read mode and clear transfer size register.
-* Disable NACK to avoid interrupts on each retry.
-* 2.3 sk 10/07/14 Repeated start feature deleted.
-* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
-* in XIicPs_Reset.
-* 12/06/14 Implemented Repeated start feature.
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* 02/18/15 Implemented larger data transfer using repeated start
-* in Zynq UltraScale MP.
-* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
-* as per the other examples (CR#997545)
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIICPS_H /* prevent circular inclusions */
-#define XIICPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xiicps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options may be specified or retrieved for the device and
- * enable/disable additional features of the IIC. Each of the options
- * are bit fields, so more than one may be specified.
- *
- * @{
- */
-#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
-#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
-#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
-#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to an application
- * event handler from the driver. These constants are bit masks such that
- * more than one event can be passed to the handler.
- *
- * @{
- */
-#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
-#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
-#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
-#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
-#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
-#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
-#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
-#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
-#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
-#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
-/*@}*/
-
-/** @name Role constants
- *
- * These constants are used to pass into the device setup routines to
- * set up the device according to transfer direction.
- */
-#define SENDING_ROLE 1 /**< Transfer direction is sending */
-#define RECVING_ROLE 0 /**< Transfer direction is receiving */
-
-/* Maximum transfer size */
-#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
-
-/**************************** Type Definitions *******************************/
-
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* not important to the driver, so it is a void pointer.
-* @param StatusEvent indicates one or more status events that occurred.
-*/
-typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
-} XIicPs_Config;
-
-/**
- * The XIicPs driver instance data. The user is required to allocate a
- * variable of this type for each IIC device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XIicPs_Config Config; /* Configuration structure */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Options set in the device */
-
- u8 *SendBufferPtr; /* Pointer to send buffer */
- u8 *RecvBufferPtr; /* Pointer to recv buffer */
- s32 SendByteCount; /* Number of bytes still expected to send */
- s32 RecvByteCount; /* Number of bytes still expected to receive */
- s32 CurrByteCount; /* No. of bytes expected in current transfer */
-
- s32 UpdateTxSize; /* If tx size register has to be updated */
- s32 IsSend; /* Whether master is sending or receiving */
- s32 IsRepeatedStart; /* Indicates if user set repeated start */
-
- XIicPs_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XIicPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/*
-*
-* Place one byte into the transmit FIFO.
-*
-* @param InstancePtr is the instance of IIC
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_SendByte(XIicPs *InstancePtr)
-*
-*****************************************************************************/
-#define XIicPs_SendByte(InstancePtr) \
-{ \
- u8 Data; \
- Data = *((InstancePtr)->SendBufferPtr); \
- XIicPs_Out32((InstancePtr)->Config.BaseAddress \
- + (u32)(XIICPS_DATA_OFFSET), \
- (u32)(Data)); \
- (InstancePtr)->SendBufferPtr += 1; \
- (InstancePtr)->SendByteCount -= 1;\
-}
-
-/****************************************************************************/
-/*
-*
-* Receive one byte from FIFO.
-*
-* @param InstancePtr is the instance of IIC
-*
-* @return None.
-*
-* @note C-Style signature:
-* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
-*
-*****************************************************************************/
-#define XIicPs_RecvByte(InstancePtr) \
-{ \
- u8 *Data, Value; \
- Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
- + (u32)XIICPS_DATA_OFFSET)); \
- Data = &Value; \
- *(InstancePtr)->RecvBufferPtr = *Data; \
- (InstancePtr)->RecvBufferPtr += 1; \
- (InstancePtr)->RecvByteCount --; \
-}
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Function for configuration lookup, in xiicps_sinit.c
- */
-XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions for general setup, in xiicps.c
- */
-s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
- u32 EffectiveAddr);
-
-void XIicPs_Abort(XIicPs *InstancePtr);
-void XIicPs_Reset(XIicPs *InstancePtr);
-
-s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
-s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-/*
- * Functions for interrupts, in xiicps_intr.c
- */
-void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
- XIicPs_IntrHandler FunctionPtr);
-
-/*
- * Functions for device as master, in xiicps_master.c
- */
-void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr);
-void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
-void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
-void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
-
-/*
- * Functions for device as slave, in xiicps_slave.c
- */
-void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
-void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
-void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
-
-/*
- * Functions for selftest, in xiicps_selftest.c
- */
-s32 XIicPs_SelfTest(XIicPs *InstancePtr);
-
-/*
- * Functions for setting and getting data rate, in xiicps_options.c
- */
-s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
-s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
-u32 XIicPs_GetOptions(XIicPs *InstancePtr);
-
-s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
-u32 XIicPs_GetSClk(XIicPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
deleted file mode 100644
index e821c1a134918abe540d6f36caaf92d94ce299fb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
+++ /dev/null
@@ -1,61 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xiicps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_I2C_0_DEVICE_ID,
- XPAR_PS7_I2C_0_BASEADDR,
- XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ
- },
- {
- XPAR_PS7_I2C_1_DEVICE_ID,
- XPAR_PS7_I2C_1_BASEADDR,
- XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
deleted file mode 100644
index ce81d92ab9c8f67358ea4f28e57427789c455f95..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_hw.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* Contains implementation of required functions for providing the reset sequence
-* to the i2c interface
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- --------------------------------------------
-* 1.04a kpc 11/07/13 First release
-* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps_hw.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given I2c interface by
-* configuring the appropriate control bits in the I2c specifc registers
-* the i2cps reset squence involves the following steps
-* Disable all the interuupts
-* Clear the status
-* Clear FIFO's and disable hold bit
-* Clear the line status
-* Update relevant config registers with reset values
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* I2c controller
-******************************************************************************/
-void XIicPs_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Disable all the interrupts */
- XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
- /* Clear the interrupt status */
- RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
- /* Clear the hold bit,master enable bit and ack bit */
- RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
- RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
- /* Clear the fifos */
- RegVal |= XIICPS_CR_CLR_FIFO_MASK;
- XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
- /* Clear the timeout register */
- XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
- /* Clear the transfer size register */
- XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
- /* Clear the status register */
- RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
- XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
- /* Update the configuraqtion register with reset value */
- XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
deleted file mode 100644
index e9d63ec8f68e84d3d746dee4b0d7cabe4a6f9975..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_hw.h
-* @addtogroup iicps_v3_7
-* @{
-*
-* This header file contains the hardware definition for an IIC device.
-* It includes register definitions and interface functions to read/write
-* the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 1.04a kpc 11/07/13 Added function prototype.
-* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIICPS_HW_H /* prevent circular inclusions */
-#define XIICPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the IIC.
- * @{
- */
-#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
-#define XIICPS_SR_OFFSET 0x04U /**< Status */
-#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
-#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
-#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
-#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
-#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
-#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
-#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
-#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
-#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
-/* @} */
-
-/** @name Control Register
- *
- * This register contains various control bits that
- * affects the operation of the IIC controller. Read/Write.
- * @{
- */
-
-#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
-#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
-#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
-#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
-#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
-#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
-#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
-#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
- 0=terminate transfer */
-#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
- Master receiver*/
-#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
- 0=10 bit */
-#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
- 0=Slave */
-#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
- transfer 0=Transmitter,
- 1=Receiver*/
-#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
- register */
-/* @} */
-
-/** @name IIC Status Register
- *
- * This register is used to indicate status of the IIC controller. Read only
- * @{
- */
-#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
-#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
-#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
-#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
-#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
-/* @} */
-
-/** @name IIC Address Register
- *
- * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
- * A write access to this register always initiates a transfer if the IIC is in
- * master mode. Read/Write
- * @{
- */
-#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
-/* @} */
-
-/** @name IIC Data Register
- *
- * When written to, the data register sets data to transmit. When read from, the
- * data register reads the last received byte of data. Read/Write
- * @{
- */
-#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
-/* @} */
-
-/** @name IIC Interrupt Registers
- *
- * <b>IIC Interrupt Status Register</b>
- *
- * This register holds the interrupt status flags for the IIC controller. Some
- * of the flags are level triggered
- * - i.e. are set as long as the interrupt condition exists. Other flags are
- * edge triggered, which means they are set one the interrupt condition occurs
- * then remain set until they are cleared by software.
- * The interrupts are cleared by writing a one to the interrupt bit position
- * in the Interrupt Status Register. Read/Write.
- *
- * <b>IIC Interrupt Enable Register</b>
- *
- * This register is used to enable interrupt sources for the IIC controller.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * IIC Interrupt Mask register. Write only.
- *
- * <b>IIC Interrupt Disable Register </b>
- *
- * This register is used to disable interrupt sources for the IIC controller.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * IIC Interrupt Mask register. Write only.
- *
- * <b>IIC Interrupt Mask Register</b>
- *
- * This register shows the enabled/disabled status of each IIC controller
- * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
- * the status register. A bit set to 0 means the interrupt is enabled.
- * All mask bits are set and all interrupts are disabled after reset. Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Interrupt Status Register
- * @{
- */
-
-#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
- mask */
-#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
- Interrupt mask */
-#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
- Interrupt mask */
-#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
- mask */
-#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
- Interrupt mask */
-#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
- Interrupt mask */
-#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
-#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
-#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
- Interrupt mask */
-#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
-#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
-/* @} */
-
-
-/** @name IIC Transfer Size Register
-*
-* The register's meaning varies according to the operating mode as follows:
-* - Master transmitter mode: number of data bytes still not transmitted minus
-* one
-* - Master receiver mode: number of data bytes that are still expected to be
-* received
-* - Slave transmitter mode: number of bytes remaining in the FIFO after the
-* master terminates the transfer
-* - Slave receiver mode: number of valid data bytes in the FIFO
-*
-* This register is cleared if CLR_FIFO bit in the control register is set.
-* Read/Write
-* @{
-*/
-#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
-#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
-#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
-/* @} */
-
-
-/** @name IIC Slave Monitor Pause Register
-*
-* This register is associated with the slave monitor mode of the I2C interface.
-* It is meaningful only when the module is in master mode and bit SLVMON in the
-* control register is set.
-*
-* This register defines the pause interval between consecutive attempts to
-* address the slave once a write to an I2C address register is done by the
-* host. It represents the number of sclk cycles minus one between two attempts.
-*
-* The reset value of the register is 0, which results in the master repeatedly
-* trying to access the slave immediately after unsuccessful attempt.
-* Read/Write
-* @{
-*/
-#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
-/* @} */
-
-
-/** @name IIC Time Out Register
-*
-* The value of time out register represents the time out interval in number of
-* sclk cycles minus one.
-*
-* When the accessed slave holds the sclk line low for longer than the time out
-* period, thus prohibiting the I2C interface in master mode to complete the
-* current transfer, an interrupt is generated and TO interrupt flag is set.
-*
-* The reset value of the register is 0x1f.
-* Read/Write
-* @{
- */
-#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
-#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XIicPs_In32 Xil_In32
-#define XIicPs_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-* Read an IIC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to select the specific register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XIicPs_ReadReg(BaseAddress, RegOffset) \
- XIicPs_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write an IIC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to select the specific register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
-*
-******************************************************************************/
-#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/***************************************************************************/
-/**
-* Read the interrupt enable register.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return Current bit mask that represents currently enabled interrupts.
-*
-* @note C-Style signature:
-* u32 XIicPs_ReadIER(u32 BaseAddress)
-*
-******************************************************************************/
-#define XIicPs_ReadIER(BaseAddress) \
- XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
-
-/***************************************************************************/
-/**
-* Write to the interrupt enable register.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @param IntrMask is the interrupts to be enabled.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
-*
-******************************************************************************/
-#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
- XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
-
-/***************************************************************************/
-/**
-* Disable all interrupts.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
-*
-******************************************************************************/
-#define XIicPs_DisableAllInterrupts(BaseAddress) \
- XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
- XIICPS_IXR_ALL_INTR_MASK)
-
-/***************************************************************************/
-/**
-* Disable selected interrupts.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @param IntrMask is the interrupts to be disabled.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
-*
-******************************************************************************/
-#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
- XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
- (IntrMask))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the I2c interface
- */
-void XIicPs_ResetHw(u32 BaseAddress);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
deleted file mode 100644
index 6dccff4c8820b184bab8ca32dc9dfd2a863a3a69..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_intr.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* Contains functions of the XIicPs driver for interrupt-driven transfers.
-* See xiicps.h for a detailed description of the device and driver.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************* Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function sets the status callback function, the status handler, which the
-* driver calls when it encounters conditions that should be reported to the
-* higher layer software. The handler executes in an interrupt context, so
-* the amount of processing should be minimized
-*
-* Refer to the xiicps.h file for a list of the Callback events. The events are
-* defined to start with XIICPS_EVENT_*.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FunctionPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note
-*
-* The handler is called within interrupt context, so it should finish its
-* work quickly.
-*
-******************************************************************************/
-void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
- XIicPs_IntrHandler FunctionPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FunctionPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = FunctionPtr;
- InstancePtr->CallBackRef = CallBackRef;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
deleted file mode 100644
index 5554209102455ce05b11f62b0bca2729dd89aaa3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
+++ /dev/null
@@ -1,999 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_master.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* Handles master mode transfers.
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a jz 01/30/10 First release
-* 1.00a sdm 09/21/11 Updated the XIicPs_SetupMaster to not check for
-* Bus Busy condition when the Hold Bit is set.
-* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
-* check for transfer completion is added, which indicates
-* the completion of current transfer.
-* 2.0 hk 03/07/14 Added check for error status in the while loop that
-* checks for completion. CR# 762244, 764875.
-* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
-* Fix for CR# 761060 - provision for repeated start.
-* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
-* read mode and clear transfer size register.
-* Disable NACK to avoid interrupts on each retry.
-* 2.3 sk 10/06/14 Fill transmit fifo before address register when sending.
-* Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
-* Repeated start feature removed.
-* 3.0 sk 12/06/14 Implemented Repeated start feature.
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* 02/18/15 Implemented larger data transfer using repeated start
-* in Zynq UltraScale MP.
-* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
-* before slave address. Fix for CR996440.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
-static void MasterSendData(XIicPs *InstancePtr);
-
-/************************* Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function initiates an interrupt-driven send in master mode.
-*
-* It tries to send the first FIFO-full of data, then lets the interrupt
-* handler to handle the rest of the data if there is any.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the send buffer.
-* @param ByteCount is the number of bytes to be sent.
-* @param SlaveAddr is the address of the slave we are sending to.
-*
-* @return None.
-*
-* @note This send routine is for interrupt-driven transfer only.
-*
- ****************************************************************************/
-void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr)
-{
- u32 BaseAddr;
- u32 Platform = XGetPlatform_Info();
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsgPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->SendBufferPtr = MsgPtr;
- InstancePtr->SendByteCount = ByteCount;
- InstancePtr->RecvBufferPtr = NULL;
- InstancePtr->IsSend = 1;
-
- /*
- * Set repeated start if sending more than FIFO of data.
- */
- if (((InstancePtr->IsRepeatedStart) != 0)||
- ((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
- XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
- (u32)XIICPS_CR_HOLD_MASK);
- }
-
- /*
- * Setup as a master sending role.
- */
- (void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
-
- (void)TransmitFifoFill(InstancePtr);
-
- XIicPs_EnableInterrupts(BaseAddr,
- (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
- (u32)XIICPS_IXR_ARB_LOST_MASK);
- /*
- * Do the address transfer to notify the slave.
- */
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
- /* Clear the Hold bit in ZYNQ if receive byte count is less than
- * the FIFO depth to get the completion interrupt properly.
- */
- if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
- {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
- (u32)(~XIICPS_CR_HOLD_MASK));
- }
-
-}
-
-/*****************************************************************************/
-/**
-* This function initiates an interrupt-driven receive in master mode.
-*
-* It sets the transfer size register so the slave can send data to us.
-* The rest of the work is managed by interrupt handler.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the receive buffer.
-* @param ByteCount is the number of bytes to be received.
-* @param SlaveAddr is the address of the slave we are receiving from.
-*
-* @return None.
-*
-* @note This receive routine is for interrupt-driven transfer only.
-*
-****************************************************************************/
-void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
- u16 SlaveAddr)
-{
- u32 BaseAddr;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsgPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->RecvBufferPtr = MsgPtr;
- InstancePtr->RecvByteCount = ByteCount;
- InstancePtr->SendBufferPtr = NULL;
- InstancePtr->IsSend = 0;
-
- if ((ByteCount > XIICPS_FIFO_DEPTH) ||
- ((InstancePtr->IsRepeatedStart) !=0))
- {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
- (u32)XIICPS_CR_HOLD_MASK);
- }
-
- /*
- * Initialize for a master receiving role.
- */
- (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
- /*
- * Setup the transfer size register so the slave knows how much
- * to send to us.
- */
- if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_MAX_TRANSFER_SIZE);
- InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
- InstancePtr->UpdateTxSize = 1;
- }else {
- InstancePtr->CurrByteCount = ByteCount;
- XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
- (u32)ByteCount);
- InstancePtr->UpdateTxSize = 0;
- }
-
- XIicPs_EnableInterrupts(BaseAddr,
- (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
- (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
- (u32)XIICPS_IXR_ARB_LOST_MASK);
- /*
- * Do the address transfer to signal the slave.
- */
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
-}
-
-/*****************************************************************************/
-/**
-* This function initiates a polled mode send in master mode.
-*
-* It sends data to the FIFO and waits for the slave to pick them up.
-* If slave fails to remove data from FIFO, the send fails with
-* time out.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the send buffer.
-* @param ByteCount is the number of bytes to be sent.
-* @param SlaveAddr is the address of the slave we are sending to.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This send routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
- s32 ByteCount, u16 SlaveAddr)
-{
- u32 IntrStatusReg;
- u32 StatusReg;
- u32 BaseAddr;
- u32 Intrs;
- _Bool Value;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->SendBufferPtr = MsgPtr;
- InstancePtr->SendByteCount = ByteCount;
-
- if (((InstancePtr->IsRepeatedStart) != 0) ||
- ((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
- (u32)XIICPS_CR_HOLD_MASK);
- }
-
- (void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
-
- /*
- * Intrs keeps all the error-related interrupts.
- */
- Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
- (u32)XIICPS_IXR_NACK_MASK;
-
- /*
- * Clear the interrupt status register before use it to monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Transmit first FIFO full of data.
- */
- (void)TransmitFifoFill(InstancePtr);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-
- /*
- * Continue sending as long as there is more data and
- * there are no errors.
- */
- Value = ((InstancePtr->SendByteCount > (s32)0) &&
- ((IntrStatusReg & Intrs) == (u32)0U));
- while (Value != FALSE) {
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * Wait until transmit FIFO is empty.
- */
- if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- Value = ((InstancePtr->SendByteCount > (s32)0) &&
- ((IntrStatusReg & Intrs) == (u32)0U));
- continue;
- }
-
- /*
- * Send more data out through transmit FIFO.
- */
- (void)TransmitFifoFill(InstancePtr);
- Value = ((InstancePtr->SendByteCount > (s32)0) &&
- ((IntrStatusReg & Intrs) == (u32)0U));
- }
-
- /*
- * Check for completion of transfer.
- */
- while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
-
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- /*
- * If there is an error, tell the caller.
- */
- if ((IntrStatusReg & Intrs) != 0U) {
- return (s32)XST_FAILURE;
- }
- }
-
- if ((!(InstancePtr->IsRepeatedStart)) != 0) {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
-
- return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function initiates a polled mode receive in master mode.
-*
-* It repeatedly sets the transfer size register so the slave can
-* send data to us. It polls the data register for data to come in.
-* If slave fails to send us data, it fails with time out.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the receive buffer.
-* @param ByteCount is the number of bytes to be received.
-* @param SlaveAddr is the address of the slave we are receiving from.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This receive routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
- s32 ByteCount, u16 SlaveAddr)
-{
- u32 IntrStatusReg;
- u32 Intrs;
- u32 StatusReg;
- u32 BaseAddr;
- s32 Result;
- s32 IsHold;
- s32 UpdateTxSize = 0;
- s32 ByteCountVar = ByteCount;
- u32 Platform;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->RecvBufferPtr = MsgPtr;
- InstancePtr->RecvByteCount = ByteCountVar;
-
- Platform = XGetPlatform_Info();
-
- if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
- ((InstancePtr->IsRepeatedStart) !=0))
- {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
- (u32)XIICPS_CR_HOLD_MASK);
- IsHold = 1;
- } else {
- IsHold = 0;
- }
-
- (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
-
- /*
- * Clear the interrupt status register before use it to monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
-
- /*
- * Set up the transfer size register so the slave knows how much
- * to send to us.
- */
- if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_MAX_TRANSFER_SIZE);
- ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
- UpdateTxSize = 1;
- }else {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- ByteCountVar);
- }
-
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- /*
- * Intrs keeps all the error-related interrupts.
- */
- Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
- (u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
- /*
- * Poll the interrupt status register to find the errors.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- while ((InstancePtr->RecvByteCount > 0) &&
- ((IntrStatusReg & Intrs) == 0U)) {
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
- if (((InstancePtr->RecvByteCount <
- XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
- ((!InstancePtr->IsRepeatedStart) != 0) &&
- (UpdateTxSize == 0)) {
- IsHold = 0;
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,
- XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
- XIicPs_RecvByte(InstancePtr);
- ByteCountVar --;
-
- if (Platform == (u32)XPLAT_ZYNQ) {
- if ((UpdateTxSize != 0) &&
- (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
- break;
- }
- }
-
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
- }
- if (Platform == (u32)XPLAT_ZYNQ) {
- if ((UpdateTxSize != 0) &&
- (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
- /* wait while fifo is full */
- while (XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET) !=
- (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
- }
-
- if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
- (s32)XIICPS_MAX_TRANSFER_SIZE) {
-
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_MAX_TRANSFER_SIZE);
- ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
- XIICPS_FIFO_DEPTH;
- } else {
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- InstancePtr->RecvByteCount -
- XIICPS_FIFO_DEPTH);
- UpdateTxSize = 0;
- ByteCountVar = InstancePtr->RecvByteCount;
- }
- }
- } else {
- if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
- /*
- * Clear the interrupt status register before use it to
- * monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- if ((InstancePtr->RecvByteCount) >
- (s32)XIICPS_MAX_TRANSFER_SIZE) {
-
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_MAX_TRANSFER_SIZE);
- ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
- } else {
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- InstancePtr->RecvByteCount);
- UpdateTxSize = 0;
- ByteCountVar = InstancePtr->RecvByteCount;
- }
- }
- }
-
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- }
-
- if ((!(InstancePtr->IsRepeatedStart)) != 0) {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
- if ((IntrStatusReg & Intrs) != 0x0U) {
- Result = (s32)XST_FAILURE;
- }
- else {
- Result = (s32)XST_SUCCESS;
- }
-
- return Result;
-}
-
-/*****************************************************************************/
-/**
-* This function enables the slave monitor mode.
-*
-* It enables slave monitor in the control register and enables
-* slave ready interrupt. It then does an address transfer to slave.
-* Interrupt handler will signal the caller if slave responds to
-* the address transfer.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param SlaveAddr is the address of the slave we want to contact.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
-{
- u32 BaseAddr;
- u32 ConfigReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
-
- /* Clear transfer size register */
- XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
-
- /*
- * Enable slave monitor mode in control register.
- */
- ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
- ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
- (u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
- ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
-
- XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
-
- /*
- * Set up interrupt flag for slave monitor interrupt.
- * Dont enable NACK.
- */
- XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
-
- /*
- * Initialize the slave monitor register.
- */
- XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
-
- /*
- * Set the slave address to start the slave address transmission.
- */
- XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
- return;
-}
-
-/*****************************************************************************/
-/**
-* This function disables slave monitor mode.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
-{
- u32 BaseAddr;
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
-
- /*
- * Clear slave monitor control bit.
- */
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
- & (~XIICPS_CR_SLVMON_MASK));
-
- /*
- * wait for slv monitor control bit to be clear
- */
- while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
- & XIICPS_CR_SLVMON_MASK);
- /*
- * Clear interrupt flag for slave monitor interrupt.
- */
- XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
-
- return;
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for the master mode. It does the protocol handling for
-* the interrupt-driven transfers.
-*
-* Completion events and errors are signaled to upper layer for proper handling.
-*
-* <pre>
-* The interrupts that are handled are:
-* - DATA
-* This case is handled only for master receive data.
-* The master has to request for more data (if there is more data to
-* receive) and read the data from the FIFO .
-*
-* - COMP
-* If the Master is transmitting data and there is more data to be
-* sent then the data is written to the FIFO. If there is no more data to
-* be transmitted then a completion event is signalled to the upper layer
-* by calling the callback handler.
-*
-* If the Master is receiving data then the data is read from the FIFO and
-* the Master has to request for more data (if there is more data to
-* receive). If all the data has been received then a completion event
-* is signalled to the upper layer by calling the callback handler.
-* It is an error if the amount of received data is more than expected.
-*
-* - NAK and SLAVE_RDY
-* This is signalled to the upper layer by calling the callback handler.
-*
-* - All Other interrupts
-* These interrupts are marked as error. This is signalled to the upper
-* layer by calling the callback handler.
-*
-* </pre>
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
-{
- u32 IntrStatusReg;
- u32 StatusEvent = 0U;
- u32 BaseAddr;
- u16 SlaveAddr;
- s32 ByteCnt;
- s32 IsHold;
- u32 Platform;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
-
- Platform = XGetPlatform_Info();
-
- /*
- * Read the Interrupt status register.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- (u32)XIICPS_ISR_OFFSET);
-
- /*
- * Write the status back to clear the interrupts so no events are
- * missed while processing this interrupt.
- */
- XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Use the Mask register AND with the Interrupt Status register so
- * disabled interrupts are not processed.
- */
- IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
-
- ByteCnt = InstancePtr->CurrByteCount;
-
- IsHold = 0;
- if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
- IsHold = 1;
- }
-
- /*
- * Send
- */
- if (((InstancePtr->IsSend) != 0) &&
- ((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
- if (InstancePtr->SendByteCount > 0) {
- MasterSendData(InstancePtr);
- } else {
- StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
- }
- }
-
-
- /*
- * Receive
- */
- if (((!(InstancePtr->IsSend))!= 0) &&
- ((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
- (0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
-
- while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
- XIICPS_SR_RXDV_MASK) != 0U) {
- if (((InstancePtr->RecvByteCount <
- XIICPS_DATA_INTR_DEPTH)!= 0U) && (IsHold != 0) &&
- ((!InstancePtr->IsRepeatedStart)!= 0) &&
- (InstancePtr->UpdateTxSize == 0)) {
- IsHold = 0;
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,
- XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
- XIicPs_RecvByte(InstancePtr);
- ByteCnt--;
-
- if (Platform == (u32)XPLAT_ZYNQ) {
- if ((InstancePtr->UpdateTxSize != 0) &&
- (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
- break;
- }
- }
- }
-
- if (Platform == (u32)XPLAT_ZYNQ) {
- if ((InstancePtr->UpdateTxSize != 0) &&
- (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
- /* wait while fifo is full */
- while (XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET) !=
- (u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
- }
-
- if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
- (s32)XIICPS_MAX_TRANSFER_SIZE) {
-
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_MAX_TRANSFER_SIZE);
- ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
- XIICPS_FIFO_DEPTH;
- } else {
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- InstancePtr->RecvByteCount -
- XIICPS_FIFO_DEPTH);
- InstancePtr->UpdateTxSize = 0;
- ByteCnt = InstancePtr->RecvByteCount;
- }
- }
- } else {
- if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
- /*
- * Clear the interrupt status register before use it to
- * monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- if ((InstancePtr->RecvByteCount) >
- (s32)XIICPS_MAX_TRANSFER_SIZE) {
-
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_MAX_TRANSFER_SIZE);
- ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
- } else {
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- InstancePtr->RecvByteCount);
- InstancePtr->UpdateTxSize = 0;
- ByteCnt = InstancePtr->RecvByteCount;
- }
- XIicPs_EnableInterrupts(BaseAddr,
- (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
- (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
- (u32)XIICPS_IXR_ARB_LOST_MASK);
- }
- }
- InstancePtr->CurrByteCount = ByteCnt;
- }
-
- if (((!(InstancePtr->IsSend)) != 0) &&
- (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
- /*
- * If all done, tell the application.
- */
- if (InstancePtr->RecvByteCount == 0){
- if ((!(InstancePtr->IsRepeatedStart)) != 0) {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,
- XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
- StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
- }
- }
-
-
- /*
- * Slave ready interrupt, it is only meaningful for master mode.
- */
- if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
- StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
- }
-
- if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
- if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,
- XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
- StatusEvent |= XIICPS_EVENT_NACK;
- }
-
- /*
- * Arbitration lost interrupt
- */
- if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
- StatusEvent |= XIICPS_EVENT_ARB_LOST;
- }
-
- /*
- * All other interrupts are treated as error.
- */
- if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
- XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
- XIICPS_IXR_RX_OVR_MASK))) {
- if ((!(InstancePtr->IsRepeatedStart)) != 0) {
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- XIicPs_ReadReg(BaseAddr,
- XIICPS_CR_OFFSET) &
- (~XIICPS_CR_HOLD_MASK));
- }
- StatusEvent |= XIICPS_EVENT_ERROR;
- }
-
- /*
- * Signal application if there are any events.
- */
- if (StatusEvent != 0U) {
- InstancePtr->StatusHandler(InstancePtr->CallBackRef,
- StatusEvent);
- }
-
-}
-
-/*****************************************************************************/
-/*
-* This function prepares a device to transfers as a master.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @param Role specifies whether the device is sending or receiving.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if bus is busy.
-*
-* @note Interrupts are always disabled, device which needs to use
-* interrupts needs to setup interrupts after this call.
-*
-****************************************************************************/
-static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
-{
- u32 ControlReg;
- u32 BaseAddr;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
-
-
- /*
- * Only check if bus is busy when repeated start option is not set.
- */
- if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
- if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
- return (s32)XST_FAILURE;
- }
- }
-
- /*
- * Set up master, AckEn, nea and also clear fifo.
- */
- ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
- (u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
-
- if (Role == RECVING_ROLE) {
- ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
- }else {
- ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
- }
-
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
-
- XIicPs_DisableAllInterrupts(BaseAddr);
-
- return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-* This function handles continuation of sending data. It is invoked
-* from interrupt handler.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-static void MasterSendData(XIicPs *InstancePtr)
-{
- (void)TransmitFifoFill(InstancePtr);
-
- /*
- * Clear hold bit if done, so stop can be sent out.
- */
- if (InstancePtr->SendByteCount == 0) {
-
- /*
- * If user has enabled repeated start as an option,
- * do not disable it.
- */
- if ((!(InstancePtr->IsRepeatedStart)) != 0) {
-
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- (u32)XIICPS_CR_OFFSET,
- XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- (u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
- }
- }
-
- return;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
deleted file mode 100644
index 4ef69a1a0d0beff86be8068dd10a9a43164acb10..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_options.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* Contains functions for the configuration of the XIccPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
-* to achieve I2C clock with minimum error.
-* This is a fix for CR #674195
-* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
-* This is fix for CR#704398 to remove warning.
-* 2.0 hk 03/07/14 Limited frequency set when 100KHz or 400KHz is
-* selected. This is a hardware limitation. CR#779290.
-* 2.1 hk 04/24/14 Fix for CR# 761060 - provision for repeated start.
-* 2.3 sk 10/07/14 Repeated start feature removed.
-* 3.0 sk 12/06/14 Implemented Repeated start feature.
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} OptionsMap;
-
-static OptionsMap OptionsTable[] = {
- {XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
- {XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
- {XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
- {XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
-};
-
-#define XIICPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the IIC device driver. The options control
-* how the device behaves relative to the IIC bus. The device must be idle
-* rather than busy transferring data before setting these device options.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param Options contains the specified options to be set. This is a bit
-* mask where a 1 means to turn the option on. One or more bit
-* values may be contained in the mask. See the bit definitions
-* named XIICPS_*_OPTION in xiicps.h.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_IS_STARTED if the device is currently transferring
-* data. The transfer must complete or be aborted before setting
-* options.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
-{
- u32 ControlReg;
- u32 Index;
- u32 OptionsVar = Options;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_CR_OFFSET);
-
- /*
- * If repeated start option is requested, set the flag.
- * The hold bit in CR will be written by driver when the next transfer
- * is initiated.
- */
- if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
- InstancePtr->IsRepeatedStart = 1;
- OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
- }
-
- /*
- * Loop through the options table, turning the option on.
- */
- for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
- if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
- /*
- * 10-bit option is specially treated, because it is
- * using the 7-bit option, so turning it on means
- * turning 7-bit option off.
- */
- if ((OptionsTable[Index].Option &
- XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
- /* Turn 7-bit off */
- ControlReg &= ~OptionsTable[Index].Mask;
- } else {
- /* Turn 7-bit on */
- ControlReg |= OptionsTable[Index].Mask;
- }
- }
- }
-
- /*
- * Now write to the control register. Leave it to the upper layers
- * to restart the device.
- */
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
- ControlReg);
-
- /*
- * Keep a copy of what options this instance has.
- */
- InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
-
- return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function clears the options for the IIC device driver. The options
-* control how the device behaves relative to the IIC bus. The device must be
-* idle rather than busy transferring data before setting these device options.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param Options contains the specified options to be cleared. This is a
-* bit mask where a 1 means to turn the option off. One or more bit
-* values may be contained in the mask. See the bit definitions
-* named XIICPS_*_OPTION in xiicps.h.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_IS_STARTED if the device is currently transferring
-* data. The transfer must complete or be aborted before setting
-* options.
-*
-* @note None
-*
-******************************************************************************/
-s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
-{
- u32 ControlReg;
- u32 Index;
- u32 OptionsVar = Options;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_CR_OFFSET);
-
- /*
- * If repeated start option is cleared, set the flag.
- * The hold bit in CR will be cleared by driver when the
- * following transfer ends.
- */
- if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
- InstancePtr->IsRepeatedStart = 0;
- OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
- }
-
- /*
- * Loop through the options table and clear the specified options.
- */
- for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
- if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
-
- /*
- * 10-bit option is specially treated, because it is
- * using the 7-bit option, so clearing it means turning
- * 7-bit option on.
- */
- if ((OptionsTable[Index].Option &
- XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
-
- /* Turn 7-bit on */
- ControlReg |= OptionsTable[Index].Mask;
- } else {
-
- /* Turn 7-bit off */
- ControlReg &= ~OptionsTable[Index].Mask;
- }
- }
- }
-
-
- /*
- * Now write the control register. Leave it to the upper layers
- * to restart the device.
- */
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
- ControlReg);
-
- /*
- * Keep a copy of what options this instance has.
- */
- InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the options for the IIC device. The options control how
-* the device behaves relative to the IIC bus.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return 32 bit mask of the options, where a 1 means the option is on,
-* and a 0 means to the option is off. One or more bit values may
-* be contained in the mask. See the bit definitions named
-* XIICPS_*_OPTION in the file xiicps.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XIicPs_GetOptions(XIicPs *InstancePtr)
-{
- u32 OptionsFlag = 0U;
- u32 ControlReg;
- u32 Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /*
- * Read control register to find which options are currently set.
- */
- ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_CR_OFFSET);
-
- /*
- * Loop through the options table to determine which options are set.
- */
- for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
- if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
- OptionsFlag |= OptionsTable[Index].Option;
- }
- if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
- OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
- }
- }
-
- if (InstancePtr->IsRepeatedStart != 0 ) {
- OptionsFlag |= XIICPS_REP_START_OPTION;
- }
- return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the serial clock rate for the IIC device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* The data rate is set by values in the control register. The formula for
-* determining the correct register values is:
-* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
-* See the hardware data sheet for a full explanation of setting the serial
-* clock rate.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param FsclHz is the clock frequency in Hz. The two most common clock
-* rates are 100KHz and 400KHz.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_IS_STARTED if the device is currently transferring
-* data. The transfer must complete or be aborted before setting
-* options.
-* - XST_FAILURE if the Fscl frequency can not be set.
-*
-* @note The clock can not be faster than the input clock divide by 22.
-*
-******************************************************************************/
-s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
-{
- u32 Div_a;
- u32 Div_b;
- u32 ActualFscl;
- u32 Temp;
- u32 TempLimit;
- u32 LastError;
- u32 BestError;
- u32 CurrentError;
- u32 ControlReg;
- u32 CalcDivA;
- u32 CalcDivB;
- u32 BestDivA;
- u32 BestDivB;
- u32 FsclHzVar = FsclHz;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(FsclHzVar > 0U);
-
- if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
- XIICPS_TRANS_SIZE_OFFSET)) {
- return (s32)XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
- */
- Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
-
- /*
- * If the answer is negative or 0, the Fscl input is out of range.
- */
- if ((u32)(0U) == Temp) {
- return (s32)XST_FAILURE;
- }
-
- /*
- * If frequency 400KHz is selected, 384.6KHz should be set.
- * If frequency 100KHz is selected, 90KHz should be set.
- * This is due to a hardware limitation.
- */
- if(FsclHzVar > (u32)384600U) {
- FsclHzVar = (u32)384600U;
- }
-
- if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
- FsclHzVar = (u32)90000U;
- }
-
- /*
- * TempLimit helps in iterating over the consecutive value of Temp to
- * find the closest clock rate achievable with divisors.
- * Iterate over the next value only if fractional part is involved.
- */
- TempLimit = (((InstancePtr->Config.InputClockHz) %
- ((u32)22 * FsclHzVar)) != (u32)0x0U) ?
- Temp + (u32)1U : Temp;
- BestError = FsclHzVar;
-
- BestDivA = 0U;
- BestDivB = 0U;
- for ( ; Temp <= TempLimit ; Temp++)
- {
- LastError = FsclHzVar;
- CalcDivA = 0U;
- CalcDivB = 0U;
-
- for (Div_b = 0U; Div_b < 64U; Div_b++) {
-
- Div_a = Temp / (Div_b + 1U);
-
- if (Div_a != 0U){
- Div_a = Div_a - (u32)1U;
- }
- if (Div_a > 3U){
- continue;
- }
- ActualFscl = (InstancePtr->Config.InputClockHz) /
- (22U * (Div_a + 1U) * (Div_b + 1U));
-
- if (ActualFscl > FsclHzVar){
- CurrentError = (ActualFscl - FsclHzVar);}
- else{
- CurrentError = (FsclHzVar - ActualFscl);}
-
- if (LastError > CurrentError) {
- CalcDivA = Div_a;
- CalcDivB = Div_b;
- LastError = CurrentError;
- }
- }
-
- /*
- * Used to capture the best divisors.
- */
- if (LastError < BestError) {
- BestError = LastError;
- BestDivA = CalcDivA;
- BestDivB = CalcDivB;
- }
- }
-
-
- /*
- * Read the control register and mask the Divisors.
- */
- ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- (u32)XIICPS_CR_OFFSET);
- ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
- ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
- (BestDivB << XIICPS_CR_DIV_B_SHIFT);
-
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
- ControlReg);
-
- return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the serial clock rate for the IIC device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return The value of the IIC clock to the nearest Hz based on the
-* control register settings. The actual value may not be exact to
-* to integer math rounding errors.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XIicPs_GetSClk(XIicPs *InstancePtr)
-{
- u32 ControlReg;
- u32 ActualFscl;
- u32 Div_a;
- u32 Div_b;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_CR_OFFSET);
-
- Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
- Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
-
- ActualFscl = (InstancePtr->Config.InputClockHz) /
- (22U * (Div_a + 1U) * (Div_b + 1U));
-
- return ActualFscl;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
deleted file mode 100644
index 3e68cb62ac11e58cae8dce66a1c57e71075eea1c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_selftest.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* This component contains the implementation of selftest functions for the
-* XIicPs driver component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 1.00a sdm 09/22/11 Removed unused code
-* 3.0 sk 11/03/14 Removed TimeOut Register value check
-* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-#define REG_TEST_VALUE 0x00000005U
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. The self-test is destructive in that
-* a reset of the device is performed in order to check the reset values of
-* the registers and to get the device into a known state.
-*
-* Upon successful return from the self-test, the device is reset.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_REGISTER_ERROR indicates a register did not read or write
-* correctly
-*
-* @note None.
-*
-******************************************************************************/
-s32 XIicPs_SelfTest(XIicPs *InstancePtr)
-{
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /*
- * All the IIC registers should be in their default state right now.
- */
- if ((XIICPS_CR_RESET_VALUE !=
- XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_CR_OFFSET)) ||
- (XIICPS_IXR_ALL_INTR_MASK !=
- XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_IMR_OFFSET))) {
- return (s32)XST_FAILURE;
- }
-
- XIicPs_Reset(InstancePtr);
-
- /*
- * Write, Read then write a register
- */
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
-
- if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
- XIICPS_SLV_PAUSE_OFFSET)) {
- return (s32)XST_FAILURE;
- }
-
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_SLV_PAUSE_OFFSET, 0U);
-
- XIicPs_Reset(InstancePtr);
-
- return (s32)XST_SUCCESS;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
deleted file mode 100644
index a5724c246a5cc6b99957cdf52a591b71a36017eb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiicps_sinit.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* The implementation of the XIicPs component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- --------------------------------------------
-* 1.00a drg/jz 01/30/10 First release
-* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return A pointer to the configuration found or NULL if the specified
-* device ID was not found. See xiicps.h for the definition of
-* XIicPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
-{
- XIicPs_Config *CfgPtr = NULL;
- s32 Index;
-
- for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
- if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XIicPs_ConfigTable[Index];
- break;
- }
- }
-
- return (XIicPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
deleted file mode 100644
index fb891920120edee398a98827118d1b48d0d1736e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
+++ /dev/null
@@ -1,595 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xiicps_slave.c
-* @addtogroup iicps_v3_7
-* @{
-*
-* Handles slave transfers
-*
-* <pre> MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -- -------- ---------------------------------------------
-* 1.00a jz 01/30/10 First release
-* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
-* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
-* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xiicps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-extern s32 TransmitFifoFill(XIicPs *InstancePtr);
-
-static s32 SlaveRecvData(XIicPs *InstancePtr);
-
-/************************* Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function sets up the device to be a slave.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param SlaveAddr is the address of the slave we are receiving from.
-*
-* @return None.
-*
-* @note
-* Interrupt is always enabled no matter the tranfer is interrupt-
-* driven or polled mode. Whether device will be interrupted or not
-* depends on whether the device is connected to an interrupt
-* controller and interrupt for the device is enabled.
-*
-****************************************************************************/
-void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
-{
- u32 ControlReg;
- u32 BaseAddr;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
-
- ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
-
- /*
- * Set up master, AckEn, nea and also clear fifo.
- */
- ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
- ControlReg |= (u32)XIICPS_CR_NEA_MASK;
- ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
- ControlReg);
-
- XIicPs_DisableAllInterrupts(BaseAddr);
-
- XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
- XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
-
- return;
-}
-
-/*****************************************************************************/
-/**
-* This function setup a slave interrupt-driven send. It set the repeated
-* start for the device is the tranfer size is larger than FIFO depth.
-* Data processing for the send is initiated by the interrupt handler.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the send buffer.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return None.
-*
-* @note This send routine is for interrupt-driven transfer only.
-*
-****************************************************************************/
-void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
- u32 BaseAddr;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsgPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->SendBufferPtr = MsgPtr;
- InstancePtr->SendByteCount = ByteCount;
- InstancePtr->RecvBufferPtr = NULL;
-
- XIicPs_EnableInterrupts(BaseAddr,
- (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
- (u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
- (u32)XIICPS_IXR_TX_OVR_MASK);
-}
-
-/*****************************************************************************/
-/**
-* This function setup a slave interrupt-driven receive.
-* Data processing for the receive is handled by the interrupt handler.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the receive buffer.
-* @param ByteCount is the number of bytes to be received.
-*
-* @return None.
-*
-* @note This routine is for interrupt-driven transfer only.
-*
-****************************************************************************/
-void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsgPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-
- InstancePtr->RecvBufferPtr = MsgPtr;
- InstancePtr->RecvByteCount = ByteCount;
- InstancePtr->SendBufferPtr = NULL;
-
- XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
- (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
- (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
- (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
-
-}
-
-/*****************************************************************************/
-/**
-* This function sends a buffer in polled mode as a slave.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the send buffer.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if master sends us data or master terminates the
-* transfer before all data has sent out.
-*
-* @note This send routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
- u32 IntrStatusReg;
- u32 StatusReg;
- u32 BaseAddr;
- s32 Tmp;
- s32 BytesToSend;
- s32 Error = 0;
- s32 Status = (s32)XST_SUCCESS;
- _Bool Value;
- _Bool Result;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->SendBufferPtr = MsgPtr;
- InstancePtr->SendByteCount = ByteCount;
-
- /*
- * Use RXRW bit in status register to wait master to start a read.
- */
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
- Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
- (Error == 0));
- while (Result != FALSE) {
-
- /*
- * If master tries to send us data, it is an error.
- */
- if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
- Error = 1;
- }
-
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
- Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
- (Error == 0));
- }
-
- if (Error != 0) {
- Status = (s32)XST_FAILURE;
- } else {
-
- /*
- * Clear the interrupt status register.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Send data as long as there is more data to send and
- * there are no errors.
- */
- Value = (InstancePtr->SendByteCount > (s32)0) &&
- ((Error == 0));
- while (Value != FALSE) {
-
- /*
- * Find out how many can be sent.
- */
- BytesToSend = InstancePtr->SendByteCount;
- if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
- BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
- }
-
- for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
- XIicPs_SendByte(InstancePtr);
- }
-
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * Wait for master to read the data out of fifo.
- */
- while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
- (Error == 0)) {
-
- /*
- * If master terminates the transfer before all data is
- * sent, it is an error.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
- Error = 1;
- }
-
- /* Clear ISR.
- */
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
- IntrStatusReg);
-
- StatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_SR_OFFSET);
- }
- Value = ((InstancePtr->SendByteCount > (s32)0) &&
- (Error == 0));
- }
- }
- if (Error != 0) {
- Status = (s32)XST_FAILURE;
- }
-
- return Status;
-}
-/*****************************************************************************/
-/**
-* This function receives a buffer in polled mode as a slave.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the receive buffer.
-* @param ByteCount is the number of bytes to be received.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This receive routine is for polled mode transfer only.
-*
-****************************************************************************/
-s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
-{
- u32 IntrStatusReg;
- u32 StatusReg;
- u32 BaseAddr;
- s32 Count;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->RecvBufferPtr = MsgPtr;
- InstancePtr->RecvByteCount = ByteCount;
-
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * Clear the interrupt status register.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Clear the status register.
- */
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
-
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
- Count = InstancePtr->RecvByteCount;
- while (Count > (s32)0) {
-
- /* Wait for master to put data */
- while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * If master terminates the transfer before we get all
- * the data or the master tries to read from us,
- * it is an error.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
- XIICPS_IXR_COMP_MASK))!=0x0U) &&
- ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
- ((InstancePtr->RecvByteCount > 0) != 0x0U)) {
-
- return (s32)XST_FAILURE;
- }
-
- /*
- * Clear the interrupt status register.
- */
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
- IntrStatusReg);
- }
-
- /*
- * Read all data from FIFO.
- */
- while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
- ((InstancePtr->RecvByteCount > 0) != 0x0U)){
-
- XIicPs_RecvByte(InstancePtr);
-
- StatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_SR_OFFSET);
- }
- Count = InstancePtr->RecvByteCount;
- }
-
- return (s32)XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for slave mode. It does the protocol handling for
-* the interrupt-driven transfers.
-*
-* Completion events and errors are signaled to upper layer for proper
-* handling.
-*
-* <pre>
-*
-* The interrupts that are handled are:
-* - DATA
-* If the instance is sending, it means that the master wants to read more
-* data from us. Send more data, and check whether we are done with this
-* send.
-*
-* If the instance is receiving, it means that the master has writen
-* more data to us. Receive more data, and check whether we are done with
-* with this receive.
-*
-* - COMP
-* This marks that stop sequence has been sent from the master, transfer
-* is about to terminate. However, for receiving, the master may have
-* written us some data, so receive that first.
-*
-* It is an error if the amount of transfered data is less than expected.
-*
-* - NAK
-* This marks that master does not want our data. It is for send only.
-*
-* - Other interrupts
-* These interrupts are marked as error.
-*
-* </pre>
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
-{
- u32 IntrStatusReg;
- u32 IsSend = 0U;
- u32 StatusEvent = 0U;
- s32 LeftOver;
- u32 BaseAddr;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
-
- /*
- * Read the Interrupt status register.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-
- /*
- * Write the status back to clear the interrupts so no events are missed
- * while processing this interrupt.
- */
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Use the Mask register AND with the Interrupt Status register so
- * disabled interrupts are not processed.
- */
- IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
-
- /*
- * Determine whether the device is sending.
- */
- if (InstancePtr->RecvBufferPtr == NULL) {
- IsSend = 1U;
- }
-
- /* Data interrupt
- *
- * This means master wants to do more data transfers.
- * Also check for completion of transfer, signal upper layer if done.
- */
- if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
- if (IsSend != 0x0U) {
- LeftOver = TransmitFifoFill(InstancePtr);
- /*
- * We may finish send here
- */
- if (LeftOver == 0) {
- StatusEvent |=
- XIICPS_EVENT_COMPLETE_SEND;
- }
- } else {
- LeftOver = SlaveRecvData(InstancePtr);
-
- /* We may finish the receive here */
- if (LeftOver == 0) {
- StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
- }
- }
- }
-
- /*
- * Complete interrupt.
- *
- * In slave mode, it means the master has done with this transfer, so
- * we signal the application using completion event.
- */
- if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
- if (IsSend != 0x0U) {
- if (InstancePtr->SendByteCount > 0) {
- StatusEvent |= XIICPS_EVENT_ERROR;
- }else {
- StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
- }
- } else {
- LeftOver = SlaveRecvData(InstancePtr);
- if (LeftOver > 0) {
- StatusEvent |= XIICPS_EVENT_ERROR;
- } else {
- StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
- }
- }
- }
-
- /*
- * Nack interrupt, pass this information to application.
- */
- if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
- StatusEvent |= XIICPS_EVENT_NACK;
- }
-
- /*
- * All other interrupts are treated as error.
- */
- if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
- XIICPS_IXR_RX_UNF_MASK |
- XIICPS_IXR_TX_OVR_MASK |
- XIICPS_IXR_RX_OVR_MASK))){
-
- StatusEvent |= XIICPS_EVENT_ERROR;
- }
-
- /*
- * Signal application if there are any events.
- */
- if ((u32)0U != StatusEvent) {
- InstancePtr->StatusHandler(InstancePtr->CallBackRef,
- StatusEvent);
- }
-}
-
-/*****************************************************************************/
-/*
-*
-* This function handles continuation of receiving data. It is invoked
-* from interrupt handler.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @return Number of bytes still expected by the instance.
-*
-* @note None.
-*
-****************************************************************************/
-static s32 SlaveRecvData(XIicPs *InstancePtr)
-{
- u32 StatusReg;
- u32 BaseAddr;
-
- BaseAddr = InstancePtr->Config.BaseAddress;
-
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
- ((InstancePtr->RecvByteCount > 0) != 0x0U)) {
- XIicPs_RecvByte(InstancePtr);
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
- }
-
- return InstancePtr->RecvByteCount;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
deleted file mode 100644
index cedcc1e5074066ee8d882c8034363d639255f7dd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
+++ /dev/null
@@ -1,79 +0,0 @@
-
-#ifndef PWM_RECORDER_H
-#define PWM_RECORDER_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define PWM_RECORDER_S_AXI_SLV_REG0_OFFSET 0
-#define PWM_RECORDER_S_AXI_SLV_REG1_OFFSET 4
-#define PWM_RECORDER_S_AXI_SLV_REG2_OFFSET 8
-#define PWM_RECORDER_S_AXI_SLV_REG3_OFFSET 12
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a PWM_RECORDER register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param BaseAddress is the base address of the PWM_RECORDERdevice.
- * @param RegOffset is the register offset from the base to write to.
- * @param Data is the data written to the register.
- *
- * @return None.
- *
- * @note
- * C-style signature:
- * void PWM_RECORDER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define PWM_RECORDER_mWriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a PWM_RECORDER register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param BaseAddress is the base address of the PWM_RECORDER device.
- * @param RegOffset is the register offset from the base to write to.
- *
- * @return Data is the data from the register.
- *
- * @note
- * C-style signature:
- * u32 PWM_RECORDER_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define PWM_RECORDER_mReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param baseaddr_p is the base address of the PWM_RECORDER instance to be worked on.
- *
- * @return
- *
- * - XST_SUCCESS if all self-test code passed
- * - XST_FAILURE if any self-test code failed
- *
- * @note Caching must be turned off for this function to work.
- * @note Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus PWM_RECORDER_Reg_SelfTest(void * baseaddr_p);
-
-#endif // PWM_RECORDER_H
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
deleted file mode 100644
index 4a80786f653d5f83b9b3dd6e992e4f6e5afab37a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
+++ /dev/null
@@ -1,79 +0,0 @@
-
-#ifndef PWM_SIGNAL_OUT_H
-#define PWM_SIGNAL_OUT_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG0_OFFSET 0
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG1_OFFSET 4
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG2_OFFSET 8
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG3_OFFSET 12
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a PWM_SIGNAL_OUT register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param BaseAddress is the base address of the PWM_SIGNAL_OUTdevice.
- * @param RegOffset is the register offset from the base to write to.
- * @param Data is the data written to the register.
- *
- * @return None.
- *
- * @note
- * C-style signature:
- * void PWM_SIGNAL_OUT_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define PWM_SIGNAL_OUT_mWriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a PWM_SIGNAL_OUT register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param BaseAddress is the base address of the PWM_SIGNAL_OUT device.
- * @param RegOffset is the register offset from the base to write to.
- *
- * @return Data is the data from the register.
- *
- * @note
- * C-style signature:
- * u32 PWM_SIGNAL_OUT_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define PWM_SIGNAL_OUT_mReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param baseaddr_p is the base address of the PWM_SIGNAL_OUT instance to be worked on.
- *
- * @return
- *
- * - XST_SUCCESS if all self-test code passed
- * - XST_FAILURE if any self-test code failed
- *
- * @note Caching must be turned off for this function to work.
- * @note Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus PWM_SIGNAL_OUT_Reg_SelfTest(void * baseaddr_p);
-
-#endif // PWM_SIGNAL_OUT_H
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile
deleted file mode 100644
index 360092897d0444300c671d62d1838fa8be36008e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xqspips_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling qspips"
-
-xqspips_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xqspips_includes
-
-xqspips_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
deleted file mode 100644
index c33322c73a3a6b80f888f41aecd78b16e520134e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
+++ /dev/null
@@ -1,1571 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips.c
-* @addtogroup qspips_v3_4
-* @{
-*
-* Contains implements the interface functions of the XQspiPs driver.
-* See xqspips.h for a detailed description of the device and driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added logic to XQspiPs_GetReadData to handle data
-* shift for normal data reads and instruction/status
-* reads differently based on the ShiftReadData flag.
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* This version of the driver fixes CRs 670197/663787.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-*
-* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
-* function
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added (#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141
-*
-* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef defines qspi flash instruction format
- */
-typedef struct {
- u8 OpCode; /**< Operational code of the instruction */
- u8 InstSize; /**< Size of the instruction including address bytes */
- u8 TxOffset; /**< Register address where instruction has to be
- written */
-} XQspiPsInstFormat;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0]))
-
-/************************** Function Prototypes ******************************/
-static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/************************** Variable Definitions *****************************/
-
-/*
- * List of all the QSPI instructions and its format
- */
-static XQspiPsInstFormat FlashInst[] = {
- { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
- /* Add all the instructions supported by the flash device */
-};
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XQspiPs instance such that the driver is ready to use.
-*
-* The state of the device after initialization is:
-* - Master mode
-* - Active high clock polarity
-* - Clock phase 0
-* - Baud rate divisor 2
-* - Transfer width 32
-* - Master reference clock = pclk
-* - No chip select active
-* - Manual CS and Manual Start disabled
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific QSPI device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_DEVICE_IS_STARTED if the device is already started.
-* It must be stopped to re-initialize.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is busy, disallow the initialize and return a status
- * indicating it is already started. This allows the user to stop the
- * device and re-initialize, but prevents a user from inadvertently
- * initializing. This assumes the busy flag is cleared at startup.
- */
- if (InstancePtr->IsBusy == TRUE) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Set some default values.
- */
- InstancePtr->IsBusy = FALSE;
-
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->StatusHandler = StubStatusHandler;
-
- InstancePtr->SendBufferPtr = NULL;
- InstancePtr->RecvBufferPtr = NULL;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->RemainingBytes = 0;
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
-
- /*
- * Reset the QSPI device to get it into its initial state. It is
- * expected that device configuration will take place after this
- * initialization is done, but before the device is started.
- */
- XQspiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the QSPI device. Reset must only be called after the driver has been
-* initialized. Any data transfer that is in progress is aborted.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the QSPI device after the reset.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_Reset(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Abort any transfer that is in progress
- */
- XQspiPs_Abort(InstancePtr);
-
- /*
- * Write default value to configuration register.
- * Do not modify reserved bits.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
- ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
- ConfigReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
-* The byte counts are cleared, the busy flag is cleared.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note
-*
-* This function does a read/modify/write of the config register. The user of
-* this function needs to take care of critical sections.
-*
-******************************************************************************/
-void XQspiPs_Abort(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
- u32 IsLock;
-
- XQspiPs_Disable(InstancePtr);
-
- /*
- * De-assert slave select lines.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * QSPI Software Reset
- */
- IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
- if (IsLock) {
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
- SLCR_UNLOCK_MASK);
- }
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
- LQSPI_RST_CTRL_MASK);
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
- if (IsLock) {
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
- SLCR_LOCK_MASK);
- }
-
- /*
- * Set the RX and TX FIFO threshold to reset value (one)
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
-
- InstancePtr->RemainingBytes = 0;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->IsBusy = FALSE;
-}
-
-/*****************************************************************************/
-/**
-*
-* Transfers specified data on the QSPI bus. Initiates bus communication and
-* sends/receives data to/from the selected QSPI slave. For every byte sent,
-* a byte is received.
-*
-* The caller has the option of providing two different buffers for send and
-* receive, or one buffer for both send and receive, or no buffer for receive.
-* The receive buffer must be at least as big as the send buffer to prevent
-* unwanted memory writes. This implies that the byte count passed in as an
-* argument must be the smaller of the two buffers if they differ in size.
-* Here are some sample usages:
-* <pre>
-* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
-* The caller wishes to send and receive, and provides two different
-* buffers for send and receive.
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
-* The caller wishes only to send and does not care about the received
-* data. The driver ignores the received data in this case.
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
-* The caller wishes to send and receive, but provides the same buffer
-* for doing both. The driver sends the data and overwrites the send
-* buffer with received data as it transfers the data.
-*
-* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
-* The caller wishes to only receive and does not care about sending
-* data. In this case, the caller must still provide a send buffer, but
-* it can be the same as the receive buffer if the caller does not care
-* what it sends. The device must send N bytes of data if it wishes to
-* receive N bytes of data.
-* </pre>
-* Although this function takes entire buffers as arguments, the driver can only
-* transfer a limited number of bytes at a time, limited by the size of the
-* FIFO. A call to this function only starts the transfer, then subsequent
-* transfers of the data is performed by the interrupt service routine until
-* the entire buffer has been transferred. The status callback function is
-* called when the entire buffer has been sent/received.
-*
-* This function is non-blocking. The SetSlaveSelect function must be called
-* prior to this function.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param SendBufPtr is a pointer to a data buffer that needs to be
-* transmitted. This buffer must not be NULL.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* This argument can be NULL if do not care about receiving.
-* @param ByteCount contains the number of bytes to send/receive.
-* The number of bytes received always equals the number of bytes
-* sent.
-*
-* @return
-* - XST_SUCCESS if the buffers are successfully handed off to the
-* device for transfer.
-* - XST_DEVICE_BUSY indicates that a data transfer is already in
-* progress. This is determined by the driver.
-*
-* @note
-*
-* This function is not thread-safe. The higher layer software must ensure that
-* no two threads are transferring data on the QSPI bus at the same time.
-*
-******************************************************************************/
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount)
-{
- u32 StatusReg;
- u32 ConfigReg;
- u8 Instruction;
- u32 Data;
- unsigned int Index;
- u8 TransCount = 0;
- XQspiPsInstFormat *CurrInst;
- XQspiPsInstFormat NewInst[2];
- u8 SwitchFlag = 0;
-
- CurrInst = &NewInst[0];
-
- /*
- * The RecvBufPtr argument can be null
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check whether there is another transfer in progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared in the ISR when the
- * transfer is entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * The first byte with every chip-select assertion is always
- * expected to be an instruction for flash interface mode
- */
- Instruction = *InstancePtr->SendBufferPtr;
-
- for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
- if (Instruction == FlashInst[Index].OpCode) {
- break;
- }
- }
-
- /*
- * Set the RX FIFO threshold
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
-
- /*
- * If the slave select is "Forced" or under manual control,
- * set the slave select now, before beginning the transfer.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XQspiPs_Enable(InstancePtr);
-
- /*
- * Clear all the interrrupts.
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
- XQSPIPS_IXR_WR_TO_CLR_MASK);
-
- if (Index < ARRAY_SIZE(FlashInst)) {
- CurrInst = &FlashInst[Index];
- /*
- * Check for WRSR instruction which has different size for
- * Spansion (3 bytes) and Micron (2 bytes)
- */
- if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
- (ByteCount == 3) ) {
- CurrInst->InstSize = 3;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- }
- }
-
- /*
- * If instruction not present in table
- */
- if (Index == ARRAY_SIZE(FlashInst)) {
- /*
- * Assign current instruction, size and TXD register to be used
- * The InstSize mentioned in case of instructions greater than
- * 4 bytes is not the actual size, but is indicative of
- * the TXD register used.
- * The remaining bytes of the instruction will be transmitted
- * through TXD0 below.
- */
- switch(ByteCount%4)
- {
- case XQSPIPS_SIZE_ONE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_ONE;
- CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
- if(ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_TWO:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_TWO;
- CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
- if(ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_THREE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_THREE;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- if(ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- default:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
- CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
- break;
- }
- }
-
- /*
- * If the instruction size in not 4 bytes then the data received needs
- * to be shifted
- */
- if( CurrInst->InstSize != 4 ) {
- InstancePtr->ShiftReadData = 1;
- } else {
- InstancePtr->ShiftReadData = 0;
- }
-
- /* Get the complete command (flash inst + address/data) */
- Data = *((u32 *)InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr += CurrInst->InstSize;
- InstancePtr->RemainingBytes -= CurrInst->InstSize;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
-
- /* Write the command to the FIFO */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- CurrInst->TxOffset, Data);
- TransCount++;
-
- /*
- * If switching from TXD1/2/3 to TXD0, then start transfer and
- * check for FIFO empty
- */
- if(SwitchFlag == 1) {
- SwitchFlag = 0;
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- /*
- * Wait for the transfer to finish by polling Tx fifo status.
- */
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
-
- }
-
- /*
- * Fill the Tx FIFO with as many bytes as it takes (or as many as
- * we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_FIFO_DEPTH)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
- InstancePtr->SendBufferPtr += 4;
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- TransCount++;
- }
-
- /*
- * Enable QSPI interrupts (connecting to the interrupt controller and
- * enabling interrupts should have been done by the caller).
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
-
- /*
- * If, in Manual Start mode, Start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* Transfers specified data on the QSPI bus in polled mode.
-*
-* The caller has the option of providing two different buffers for send and
-* receive, or one buffer for both send and receive, or no buffer for receive.
-* The receive buffer must be at least as big as the send buffer to prevent
-* unwanted memory writes. This implies that the byte count passed in as an
-* argument must be the smaller of the two buffers if they differ in size.
-* Here are some sample usages:
-* <pre>
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
-* The caller wishes to send and receive, and provides two different
-* buffers for send and receive.
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
-* The caller wishes only to send and does not care about the received
-* data. The driver ignores the received data in this case.
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
-* The caller wishes to send and receive, but provides the same buffer
-* for doing both. The driver sends the data and overwrites the send
-* buffer with received data as it transfers the data.
-*
-* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
-* The caller wishes to only receive and does not care about sending
-* data. In this case, the caller must still provide a send buffer, but
-* it can be the same as the receive buffer if the caller does not care
-* what it sends. The device must send N bytes of data if it wishes to
-* receive N bytes of data.
-*
-* </pre>
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param SendBufPtr is a pointer to a data buffer that needs to be
-* transmitted. This buffer must not be NULL.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* This argument can be NULL if do not care about receiving.
-* @param ByteCount contains the number of bytes to send/receive.
-* The number of bytes received always equals the number of bytes
-* sent.
-* @return
-* - XST_SUCCESS if the buffers are successfully handed off to the
-* device for transfer.
-* - XST_DEVICE_BUSY indicates that a data transfer is already in
-* progress. This is determined by the driver.
-*
-* @note
-*
-* This function is not thread-safe. The higher layer software must ensure that
-* no two threads are transferring data on the QSPI bus at the same time.
-*
-******************************************************************************/
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount)
-{
- u32 StatusReg;
- u32 ConfigReg;
- u8 Instruction;
- u32 Data;
- u8 TransCount;
- unsigned int Index;
- XQspiPsInstFormat *CurrInst;
- XQspiPsInstFormat NewInst[2];
- u8 SwitchFlag = 0;
- u8 IsManualStart = FALSE;
- u32 RxCount = 0;
-
- CurrInst = &NewInst[0];
- /*
- * The RecvBufPtr argument can be NULL.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check whether there is another transfer in progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared when the transfer is
- * entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * The first byte with every chip-select assertion is always
- * expected to be an instruction for flash interface mode
- */
- Instruction = *InstancePtr->SendBufferPtr;
-
- for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
- if (Instruction == FlashInst[Index].OpCode) {
- break;
- }
- }
-
- /*
- * Set the RX FIFO threshold
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
-
- /*
- * If the slave select is "Forced" or under manual control,
- * set the slave select now, before beginning the transfer.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XQspiPs_Enable(InstancePtr);
-
- if (Index < ARRAY_SIZE(FlashInst)) {
-
- CurrInst = &FlashInst[Index];
- /*
- * Check for WRSR instruction which has different size for
- * Spansion (3 bytes) and Micron (2 bytes)
- */
- if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
- (ByteCount == 3) ) {
- CurrInst->InstSize = 3;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- }
- }
-
- /*
- * If instruction not present in table
- */
- if (Index == ARRAY_SIZE(FlashInst)) {
- /*
- * Assign current instruction, size and TXD register to be used.
- * The InstSize mentioned in case of instructions greater than 4 bytes
- * is not the actual size, but is indicative of the TXD register used.
- * The remaining bytes of the instruction will be transmitted
- * through TXD0 below.
- */
- switch(ByteCount%4)
- {
- case XQSPIPS_SIZE_ONE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_ONE;
- CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
- if(ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_TWO:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_TWO;
- CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
- if(ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_THREE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_THREE;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- if(ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- default:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
- CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
- break;
- }
- }
-
- /*
- * If the instruction size in not 4 bytes then the data received needs
- * to be shifted
- */
- if( CurrInst->InstSize != 4 ) {
- InstancePtr->ShiftReadData = 1;
- } else {
- InstancePtr->ShiftReadData = 0;
- }
- TransCount = 0;
- /* Get the complete command (flash inst + address/data) */
- Data = *((u32 *)InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr += CurrInst->InstSize;
- InstancePtr->RemainingBytes -= CurrInst->InstSize;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
-
- /* Write the command to the FIFO */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- CurrInst->TxOffset, Data);
- ++TransCount;
-
- /*
- * If switching from TXD1/2/3 to TXD0, then start transfer and
- * check for FIFO empty
- */
- if(SwitchFlag == 1) {
- SwitchFlag = 0;
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- /*
- * Wait for the transfer to finish by polling Tx fifo status.
- */
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
-
- }
-
- /*
- * Check if manual start is selected and store it in a
- * local varibale for reference. This is to avoid reading
- * the config register everytime.
- */
- IsManualStart = XQspiPs_IsManualStart(InstancePtr);
-
- /*
- * Fill the DTR/FIFO with as many bytes as it will take (or as
- * many as we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_FIFO_DEPTH)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
- InstancePtr->SendBufferPtr += 4;
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- ++TransCount;
- }
-
- while((InstancePtr->RemainingBytes > 0) ||
- (InstancePtr->RequestedBytes > 0)) {
-
- /*
- * Fill the TX FIFO with RX threshold no. of entries (or as
- * many as we have to send, in case that's less).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
- InstancePtr->SendBufferPtr += 4;
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- ++TransCount;
- }
-
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (IsManualStart == TRUE) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Reset TransCount - this is only used to fill TX FIFO
- * in the above loop;
- * RxCount is used to keep track of data received
- */
- TransCount = 0;
-
- /*
- * Wait for RX FIFO to reach threshold (or)
- * TX FIFO to become empty.
- * The latter check is required for
- * small transfers (<32 words) and
- * when the last chunk in a large data transfer is < 32 words.
- */
-
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
- ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) );
-
- /*
- * A transmit has just completed. Process received data
- * and check for more data to transmit.
- * First get the data received as a result of the
- * transmit that just completed. Receive data based on the
- * count obtained while filling tx fifo. Always get
- * the received data, but only fill the receive
- * buffer if it points to something (the upper layer
- * software may not care to receive data).
- */
- while ((InstancePtr->RequestedBytes > 0) &&
- (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) {
- u32 Data;
-
- RxCount++;
-
- if (InstancePtr->RecvBufferPtr != NULL) {
- if (InstancePtr->RequestedBytes < 4) {
- Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- XQspiPs_GetReadData(InstancePtr, Data,
- InstancePtr->RequestedBytes);
- } else {
- (*(u32 *)InstancePtr->RecvBufferPtr) =
- XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- InstancePtr->RecvBufferPtr += 4;
- InstancePtr->RequestedBytes -= 4;
- if (InstancePtr->RequestedBytes < 0) {
- InstancePtr->RequestedBytes = 0;
- }
- }
- } else {
- Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- InstancePtr->RequestedBytes -= 4;
- }
- }
- RxCount = 0;
- }
-
- /*
- * If the Slave select lines are being manually controlled, disable
- * them because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- InstancePtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(InstancePtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Read the flash in Linear QSPI mode.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* @param Address is the starting address within the flash from
-* from where data needs to be read.
-* @param ByteCount contains the number of bytes to receive.
-*
-* @return
-* - XST_SUCCESS if read is performed
-* - XST_FAILURE if Linear mode is not set
-*
-* @note None.
-*
-*
-******************************************************************************/
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(RecvBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#endif
- /*
- * Enable the controller
- */
- XQspiPs_Enable(InstancePtr);
-
- if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
- XQSPIPS_LQSPI_CR_LINEAR_MASK) {
- memcpy((void*)RecvBufPtr,
- (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
- Address),
- (size_t)ByteCount);
- return XST_SUCCESS;
- } else {
- return XST_FAILURE;
- }
-
- /*
- * Disable the controller
- */
- XQspiPs_Disable(InstancePtr);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Selects the slave with which the master communicates.
-*
-* The user is not allowed to select the slave while a transfer is in progress.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - XST_SUCCESS if the slave is selected or deselected
-* successfully.
-* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
-* changed.
-*
-* @note
-*
-* This function only sets the slave which will be selected when a transfer
-* occurs. The slave is not selected when the QSPI is idle.
-*
-******************************************************************************/
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow the slave select to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Select the slave
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the status callback function, the status handler, which the driver
-* calls when it encounters conditions that should be reported to upper
-* layer software. The handler executes in an interrupt context, so it must
-* minimize the amount of processing performed. One of the following status
-* events is passed to the status handler.
-*
-* <pre>
-*
-* XST_SPI_TRANSFER_DONE The requested data transfer is done
-*
-* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
-* but there were none available in the transmit
-* register/FIFO. This typically means the slave
-* application did not issue a transfer request
-* fast enough, or the processor/driver could not
-* fill the transmit register/FIFO fast enough.
-*
-* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
-* but the receive data register/FIFO was full.
-*
-* </pre>
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note
-*
-* The handler is called within interrupt context, so it should do its work
-* quickly and queue potentially time-consuming work to a task-level thread.
-*
-******************************************************************************/
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = FuncPtr;
- InstancePtr->StatusRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param StatusEvent is the event that just occurred.
-* @param ByteCount is the number of bytes transferred up until the event
-* occurred.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount)
-{
- (void) CallBackRef;
- (void) StatusEvent;
- (void) ByteCount;
-
- Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-*
-* The interrupt handler for QSPI interrupts. This function must be connected
-* by the user to an interrupt controller.
-*
-* The interrupts that are handled are:
-*
-*
-* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
-* transmit register or FIFO is empty. The driver uses this interrupt during a
-* transmission to continually send/receive data until the transfer is done.
-*
-* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
-* the QSPI device, when configured as a slave, attempts to read an empty
-* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the
-* device data in a timely manner. No action is taken by the driver other than
-* to inform the upper layer software of the error.
-*
-* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
-* QSPI device attempts to write a received byte to an already full DRR/FIFO.
-* A full DRR/FIFO usually means software is not emptying the data in a timely
-* manner. No action is taken by the driver other than to inform the upper
-* layer software of the error.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note
-*
-* The slave select register is being set to deselect the slave when a transfer
-* is complete.
-*
-******************************************************************************/
-void XQspiPs_InterruptHandler(void *InstancePtr)
-{
- XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
- u32 IntrStatus;
- u32 ConfigReg;
- u32 Data;
- u32 TransCount;
- u32 Count = 0;
- unsigned BytesDone; /* Number of bytes done so far. */
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Immediately clear the interrupts in case the ISR causes another
- * interrupt to be generated. If we clear at the end of the ISR,
- * we may miss newly generated interrupts. This occurs because we
- * transmit from within the ISR, which could potentially cause another
- * TX_EMPTY interrupt.
- */
- IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
- (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
-
- if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
- (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
-
- /*
- * Rx FIFO has just reached threshold no. of entries.
- * Read threshold no. of entries from RX FIFO
- * Another possiblity of entering this loop is when
- * the last byte has been transmitted and TX FIFO is empty,
- * in which case, read all the data from RX FIFO.
- * Always get the received data, but only fill the
- * receive buffer if it is not null (it can be null when
- * the device does not care to receive data).
- */
- TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
- if (TransCount % 4) {
- TransCount = TransCount/4 + 1;
- } else {
- TransCount = TransCount/4;
- }
-
- while ((Count < TransCount) &&
- (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
-
- if (QspiPtr->RecvBufferPtr != NULL) {
- if (QspiPtr->RequestedBytes < 4) {
- Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- XQspiPs_GetReadData(QspiPtr, Data,
- QspiPtr->RequestedBytes);
- } else {
- (*(u32 *)QspiPtr->RecvBufferPtr) =
- XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- QspiPtr->RecvBufferPtr += 4;
- QspiPtr->RequestedBytes -= 4;
- if (QspiPtr->RequestedBytes < 0) {
- QspiPtr->RequestedBytes = 0;
- }
- }
- } else {
- XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- QspiPtr->RequestedBytes -= 4;
- if (QspiPtr->RequestedBytes < 0) {
- QspiPtr->RequestedBytes = 0;
- }
-
- }
- Count++;
- }
- Count = 0;
- /*
- * Interrupt asserted as TX_OW got asserted
- * See if there is more data to send.
- * Fill TX FIFO with RX threshold no. of entries or
- * remaining entries (in case that is less than threshold)
- */
- while ((QspiPtr->RemainingBytes > 0) &&
- (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- /*
- * Send more data.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)QspiPtr->SendBufferPtr));
- QspiPtr->SendBufferPtr += 4;
- QspiPtr->RemainingBytes -= 4;
- if (QspiPtr->RemainingBytes < 0) {
- QspiPtr->RemainingBytes = 0;
- }
-
- Count++;
- }
-
- if ((QspiPtr->RemainingBytes == 0) &&
- (QspiPtr->RequestedBytes == 0)) {
- /*
- * No more data to send. Disable the interrupt
- * and inform the upper layer software that the
- * transfer is done. The interrupt will be re-enabled
- * when another transfer is initiated.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK |
- XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
-
- /*
- * If the Slave select is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- QspiPtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_TRANSFER_DONE,
- QspiPtr->RequestedBytes);
- } else {
- /*
- * Enable the TXOW interrupt.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_IER_OFFSET,
- XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK |
- XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(QspiPtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- }
- }
-
- /*
- * Check for overflow and underflow errors.
- */
- if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
- BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
- QspiPtr->IsBusy = FALSE;
-
- /*
- * If the Slave select lines is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_RECEIVE_OVERRUN, BytesDone);
- }
-
- if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
- BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
-
- QspiPtr->IsBusy = FALSE;
- /*
- * If the Slave select lines is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Copies data from Data to the Receive buffer.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Data is the data which needs to be copied to the Rx buffer.
-* @param Size is the number of bytes to be copied to the Receive buffer.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
-{
- u8 DataByte3;
-
- if (InstancePtr->RecvBufferPtr) {
- switch (Size) {
- case 1:
- if (InstancePtr->ShiftReadData == 1) {
- *((u8 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0xFF000000) >> 24);
- } else {
- *((u8 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFF);
- }
- InstancePtr->RecvBufferPtr += 1;
- break;
- case 2:
- if (InstancePtr->ShiftReadData == 1) {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0xFFFF0000) >> 16);
- } else {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFFFF);
- }
- InstancePtr->RecvBufferPtr += 2;
- break;
- case 3:
- if (InstancePtr->ShiftReadData == 1) {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0x00FFFF00) >> 8);
- InstancePtr->RecvBufferPtr += 2;
- DataByte3 = ((Data & 0xFF000000) >> 24);
- *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
- } else {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFFFF);
- InstancePtr->RecvBufferPtr += 2;
- DataByte3 = ((Data & 0x00FF0000) >> 16);
- *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
- }
- InstancePtr->RecvBufferPtr += 1;
- break;
- default:
- /* This will never execute */
- break;
- }
- }
- InstancePtr->ShiftReadData = 0;
- InstancePtr->RequestedBytes -= Size;
- if (InstancePtr->RequestedBytes < 0) {
- InstancePtr->RequestedBytes = 0;
- }
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
deleted file mode 100644
index 139ce4d3801b49f191a9b96ba36fa8f84a89f290..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
+++ /dev/null
@@ -1,799 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_4
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* <b> Linear Mode </b>
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* <b>Multiple Masters</b>
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* <b>Modes of Operation</b>
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* <b>Interrupts</b>
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* <b>Polled Operation</b>
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* <b>Device Busy</b>
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* <b>Device Configuration</b>
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianess set to little-endian.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include <string.h>
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The <b>Active Low Clock option</b> configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The <b>Clock Phase option</b> configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The <b>Manual Start option</b> is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- RX FIFO full */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
deleted file mode 100644
index a7ced170816f9b4b020a55a46c0375c9ecbf2623..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
+++ /dev/null
@@ -1,57 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xqspips.h"
-
-/*
-* The configuration table for devices
-*/
-
-XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_QSPI_0_DEVICE_ID,
- XPAR_PS7_QSPI_0_BASEADDR,
- XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
- XPAR_PS7_QSPI_0_QSPI_MODE
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
deleted file mode 100644
index 1817b078069edce176d03884829b38f8da3d0c0c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.c
-* @addtogroup qspips_v3_4
-* @{
-*
-* Contains low level functions, primarily reset related.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 2.03a hk 09/17/13 First release
-* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips_hw.h"
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Pre-scaler value for divided by 4
- *
- * Pre-scaler value for divided by 4
- *
- * @{
- */
-#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Resets QSPI by disabling the device and bringing it to reset state through
-* register writes.
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_ResetHw(u32 BaseAddress)
-{
- u32 ConfigReg;
-
- /*
- * Disable interrupts
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_DISABLE_ALL);
-
- /*
- * Disable device
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
- 0);
-
- /*
- * De-assert slave select lines.
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Write default value to RX and TX threshold registers
- * RX threshold should be set to 1 here because the corresponding
- * status bit is used next to clear the RXFIFO
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
- (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
- (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
-
- /*
- * Clear RXFIFO
- */
- while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
- XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
- XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
- }
-
- /*
- * Clear status register by reading register and
- * writing 1 to clear the write to clear bits
- */
- XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
- XQSPIPS_IXR_WR_TO_CLR_MASK);
-
- /*
- * Write default value to configuration register
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
- ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * De-select linear mode
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
- 0x0);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Initializes QSPI to Linear mode with default QSPI boot settings.
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_LinearInit(u32 BaseAddress)
-{
- u32 BaudRateDiv;
- u32 LinearCfg;
- u32 ConfigReg;
-
- /*
- * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
- * should be set to 0x001; hence shift the value and use the mask.
- */
- BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
- XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
- /*
- * Write configuration register with default values, slave selected &
- * pre-scaler value for divide by 4
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
- ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Write linear configuration register with default value -
- * enable linear mode and use fast read.
- */
-
- if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
-
- }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
- XQSPIPS_CONNECTION_MODE_STACKED){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
-
- }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
- XQSPIPS_CONNECTION_MODE_PARALLEL){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
-
- }
-
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
- LinearCfg);
-
- /*
- * Enable device
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
- XQSPIPS_ER_ENABLE_MASK);
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
deleted file mode 100644
index 96c867ad3383fe4303731581d63f41db1ffb9231..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_4
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * <b>QSPI Status Register</b>
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * <b>QSPI Interrupt Enable Register</b>
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * <b>QSPI Interrupt Disable Register </b>
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * <b>QSPI Interrupt Mask Register</b>
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
deleted file mode 100644
index 1cd43f48c24d8ad0c3f8d9a58110eb01c74d1e32..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_options.c
-* @addtogroup qspips_v3_4
-* @{
-*
-* Contains functions for the configuration of the XQspiPs driver component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a kka 07/25/12 Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode. The driver doesnot support
-* Slave mode or the legacy mode.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
-*
-* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-*</pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} OptionsMap;
-
-static OptionsMap OptionsTable[] = {
- {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
- {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
- {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
- {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
- {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
-};
-
-#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the QSPI device driver. The options control
-* how the device behaves relative to the QSPI bus. The device must be idle
-* rather than busy transferring data before setting these device options.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Options contains the specified options to be set. This is a bit
-* mask where a 1 means to turn the option on, and a 0 means to
-* turn the option off. One or more bit values may be contained in
-* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
-* the file xqspips.h.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
-{
- u32 ConfigReg;
- unsigned int Index;
- u32 QspiOptions;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow to modify the Control Register while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
- Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
-
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- /*
- * Loop through the options table, turning the option on or off
- * depending on whether the bit is set in the incoming options flag.
- */
- for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
- if (Options & OptionsTable[Index].Option) {
- /* Turn it on */
- ConfigReg |= OptionsTable[Index].Mask;
- } else {
- /* Turn it off */
- ConfigReg &= ~(OptionsTable[Index].Mask);
- }
- }
-
- /*
- * Now write the control register. Leave it to the upper layers
- * to restart the device.
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
- ConfigReg);
-
- /*
- * Check for the LQSPI configuration options.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET);
-
-
- if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET,
- XQSPIPS_LQSPI_CR_RST_STATE);
- XQspiPs_SetSlaveSelect(InstancePtr);
- } else {
- ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the options for the QSPI device. The options control how
-* the device behaves relative to the QSPI bus.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-*
-* Options contains the specified options currently set. This is a bit value
-* where a 1 means the option is on, and a 0 means the option is off.
-* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
-{
- u32 OptionsFlag = 0;
- u32 ConfigReg;
- unsigned int Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the current options from QSPI configuration register.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- /*
- * Loop through the options table to grab options
- */
- for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
- if (ConfigReg & OptionsTable[Index].Mask) {
- OptionsFlag |= OptionsTable[Index].Option;
- }
- }
-
- /*
- * Check for the LQSPI configuration options.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET);
-
- if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
- OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
- }
-
- return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the clock prescaler for an QSPI device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Prescaler is the value that determine how much the clock should
-* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
-* in xqspips.h for this setting.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
-
- /*
- * Do not allow the slave select to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Read the configuration register, mask out the interesting bits, and set
- * them with the shifted value passed into the function. Write the
- * results back to the configuration register.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
- ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
- XQSPIPS_CR_PRESC_SHIFT;
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the clock prescaler of an QSPI device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return The prescaler value.
-*
-* @note None.
-*
-*
-******************************************************************************/
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- ConfigReg &= XQSPIPS_CR_PRESC_MASK;
-
- return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the delay register for the QSPI device driver.
-* The delay register controls the Delay Between Transfers, Delay After
-* Transfers, and the Delay Initially. The default value is 0x0. The range of
-* each delay value is 0-255.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param DelayNss is the delay to de-assert slave select between
-* two word transfers.
-* @param DelayBtwn is the delay between one Slave Select being
-* de-activated and the activation of another slave. The delay is
-* the number of master clock periods given by DelayBtwn + 2.
-* @param DelayAfter define the delay between the last bit of the current
-* byte transfer and the first bit of the next byte transfer.
-* The delay in number of master clock periods is given as:
-* CHPA=0:DelayInit+DelayAfter+3
-* CHPA=1:DelayAfter+1
-* @param DelayInit is the delay between asserting the slave select signal
-* and the first bit transfer. The delay int number of master clock
-* periods is DelayInit+1.
-*
-* @return
-* - XST_SUCCESS if delays are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit)
-{
- u32 DelayRegister;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow the delays to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /* Shift, Mask and OR the values to build the register settings */
- DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
- DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
- DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
- DelayRegister |= (u32) DelayInit;
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_DR_OFFSET, DelayRegister);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the delay settings for an QSPI device.
-* The delay register controls the Delay Between Transfers, Delay After
-* Transfers, and the Delay Initially. The default value is 0x0.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param DelayNss is a pointer to the Delay to de-assert slave select
-* between two word transfers.
-* @param DelayBtwn is a pointer to the Delay Between transfers value.
-* This is a return parameter.
-* @param DelayAfter is a pointer to the Delay After transfer value.
-* This is a return parameter.
-* @param DelayInit is a pointer to the Delay Initially value. This is
-* a return parameter.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit)
-{
- u32 DelayRegister;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_DR_OFFSET);
-
- *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
-
- *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
- XQSPIPS_DR_AFTER_SHIFT);
-
- *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
- XQSPIPS_DR_BTWN_SHIFT);
-
- *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
- XQSPIPS_DR_NSS_SHIFT);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
deleted file mode 100644
index 4c44cdff228c339490fde5308e2e63b7ee951cad..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_selftest.c
-* @addtogroup qspips_v3_4
-* @{
-*
-* This file contains the implementation of selftest function for the QSPI
-* device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter.
-* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are
-* reset in the previous step.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. The self-test is destructive in that
-* a reset of the device is performed in order to check the reset values of
-* the registers and to get the device into a known state.
-*
-* Upon successful return from the self-test, the device is reset.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - XST_SUCCESS if successful
-* - XST_REGISTER_ERROR indicates a register did not read or write
-* correctly.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_SelfTest(XQspiPs *InstancePtr)
-{
- int Status;
- u8 DelayTestNss;
- u8 DelayTestBtwn;
- u8 DelayTestAfter;
- u8 DelayTestInit;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Reset the QSPI device to leave it in a known good state
- */
- XQspiPs_Reset(InstancePtr);
-
- DelayTestNss = 0x5A;
- DelayTestBtwn = 0xA5;
- DelayTestAfter = 0xAA;
- DelayTestInit = 0x55;
-
- /*
- * Write and read the delay register, just to be sure there is some
- * hardware out there.
- */
- Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
- DelayTestAfter, DelayTestInit);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
- &DelayTestAfter, &DelayTestInit);
- if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
- (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
- return XST_REGISTER_ERROR;
- }
-
- Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- /*
- * Reset the QSPI device to leave it in a known good state
- */
- XQspiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
deleted file mode 100644
index 929ecd8328692a24509cb53e7f8d7f44835712b3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xqspips_sinit.c
-* @addtogroup qspips_v3_4
-* @{
-*
-* The implementation of the XQspiPs component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XQspiPs_Config XQspiPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xqspips.h for the definition of XQspiPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
-{
- XQspiPs_Config *CfgPtr = NULL;
- int Index;
-
- for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
- if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XQspiPs_ConfigTable[Index];
- break;
- }
- }
- return CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile
deleted file mode 100644
index 04867a48426ff72c6b489901e8c934d39ec68038..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner scugic_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling scugic"
-
-scugic_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: scugic_includes
-
-scugic_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
deleted file mode 100644
index f6afc0e5ac381a97a898c16ffbd302341dd0b155..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
+++ /dev/null
@@ -1,1020 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic.c
-* @addtogroup scugic_v3_8
-* @{
-*
-* Contains required functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
-* "Config" entry is now made as pointer in the XScuGic
-* structure, necessary changes are made.
-* The HandlerTable can now be populated through the low
-* level routine XScuGic_RegisterHandler added in this
-* release. Hence necessary checks are added not to
-* overwrite the HandlerTable entriesin function
-* XScuGic_CfgInitialize.
-* 1.03a srt 02/27/13 Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* Removed Offset calculation macros, defined in _hw.h
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-*
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
-* in function XScuGic_CfgInitialize is removed as it was
-* a bug.
-* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
-* target CPU mapping
-* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
-* the current cpu to interrupt processor targets registers
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
-* to interrupt target register to fix CR#951848
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
-* for single core zynq-7000s
-* 3.5 mus 10/05/16 Modified DistributorInit function to avoid re-initialization of
-* distributor,If it is already initialized by other CPU.
-* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
-* and properly mask interrupt target processor value to modify
-* interrupt target processor register for a given interrupt ID
-* and cpu ID
-* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
-* interrupts in case they are being used only by current cpu.
-* It also removes current cpu from interrupt target registers
-* for all interrupts.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU. It fixes CR#992490.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef);
-
-/*****************************************************************************/
-/**
-*
-* DoDistributorInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority and target CPU
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param CpuID is the Cpu ID to be initialized.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
-{
- u32 Int_Id;
- u32 LocalCpuID = CpuID;
-
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
-
- /*
- * Set the security domains in the int_security registers for
- * non-secure interrupts
- * All are secure, so leave at the default. Set to 1 for non-secure
- * interrupts.
- */
-
- /*
- * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
- */
-
- /*
- * 1. The trigger mode in the int_config register
- * Only write to the SPI interrupts, so start at 32
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
- /*
- * Each INT_ID uses two bits, or 16 INT_ID per register
- * Set them all to be level sensitive, active HIGH.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- 0U);
- }
-
-
-#define DEFAULT_PRIORITY 0xa0a0a0a0U
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
- /*
- * 2. The priority using int the priority_level register
- * The priority_level and spi_target registers use one byte per
- * INT_ID.
- * Write a default value that can be changed elsewhere.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- DEFAULT_PRIORITY);
- }
-
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
- /*
- * 3. The CPU interface in the spi_target register
- * Only write to the SPI interrupts, so start at 32
- */
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- LocalCpuID);
- }
-
- for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
- /*
- * 4. Enable the SPI using the enable_set register. Leave all
- * disabled for now.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
- 0xFFFFFFFFU);
-
- }
-
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
- XSCUGIC_EN_INT_MASK);
-}
-
-/*****************************************************************************/
-/**
-*
-* DistributorInit initializes the distributor of the GIC. It calls
-* DoDistributorInit to finish the initialization.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param CpuID is the Cpu ID to be initialized.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
-{
- u32 Int_Id;
- u32 LocalCpuID = CpuID;
- u32 RegValue;
-
-#if USE_AMP==1 && (defined (ARMA9) || defined(__aarch64__))
-#warning "Building GIC for AMP"
- /*
- * GIC initialization is taken care by master CPU in
- * openamp configuration, so do nothing and return.
- */
- return;
-#endif
-
- RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
- if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
- Xil_AssertVoid(InstancePtr != NULL);
- DoDistributorInit(InstancePtr, CpuID);
- return;
- }
-
- /*
- * The overall distributor should not be initialized in AMP case where
- * another CPU is taking care of it.
- */
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- RegValue |= LocalCpuID;
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
-*
-* - Set the priority of the CPU
-* - Enable the CPU interface
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void CPUInitialize(XScuGic *InstancePtr)
-{
- /*
- * Program the priority mask of the CPU using the Priority mask register
- */
- XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
-
-
- /*
- * If the CPU operates in both security domains, set parameters in the
- * control_s register.
- * 1. Set FIQen=1 to use FIQ for secure interrupts,
- * 2. Program the AckCtl bit
- * 3. Program the SBPR bit to select the binary pointer behavior
- * 4. Set EnableS = 1 to enable secure interrupts
- * 5. Set EnbleNS = 1 to enable non secure interrupts
- */
-
- /*
- * If the CPU operates only in the secure domain, setup the
- * control_s register.
- * 1. Set FIQen=1,
- * 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
- * Only enable the IRQ output unless secure interrupts are needed.
- */
- XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CfgInitialize a specific interrupt controller instance/driver. The
-* initialization entails:
-*
-* - Initialize fields of the XScuGic structure
-* - Initial vector table with stub function calls
-* - All interrupt sources are disabled
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param ConfigPtr is a pointer to a config table for the particular
-* device this driver is associated with.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
- XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- u32 Int_Id;
- u32 Cpu_Id = CpuId + (u32)1;
- (void) EffectiveAddr;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- /*
- * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
- * If it is single CPU cnfiguration then invoke assert for CPU ID=1
- */
-#ifdef ARMA9
- if ( XPAR_CPU_ID == 0x01 )
- {
- Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
- & EFUSE_STATUS_CPU_MASK ) == 0);
- }
-#endif
-
- if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
-
- InstancePtr->IsReady = 0U;
- InstancePtr->Config = ConfigPtr;
-
-
- for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id++) {
- /*
- * Initalize the handler to point to a stub to handle an
- * interrupt which has not been connected to a handler. Only
- * initialize it if the handler is 0 which means it was not
- * initialized statically by the tools/user. Set the callback
- * reference to this instance so that unhandled interrupts
- * can be tracked.
- */
- if ((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
- InstancePtr->Config->HandlerTable[Int_Id].Handler =
- StubHandler;
- }
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
- InstancePtr;
- }
- XScuGic_Stop(InstancePtr);
- DistributorInit(InstancePtr, Cpu_Id);
- CPUInitialize(InstancePtr);
-
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Int_Id of the interrupt source and the
-* associated handler that is to run when the interrupt is recognized. The
-* argument provided in this call as the Callbackref is used as the argument
-* for the handler when it is called.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-* @param Handler to the handler for that interrupt.
-* @param CallBackRef is the callback reference, usually the instance
-* pointer of the connecting driver.
-*
-* @return
-*
-* - XST_SUCCESS if the handler was connected correctly.
-*
-* @note
-*
-* WARNING: The handler provided as an argument will overwrite any handler
-* that was previously connected.
-*
-****************************************************************************/
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef)
-{
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertNonvoid(Handler != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The Int_Id is used as an index into the table to select the proper
- * handler
- */
- InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Updates the interrupt table with the Null Handler and NULL arguments at the
-* location pointed at by the Int_Id. This effectively disconnects that interrupt
-* source from any handler. The interrupt is disabled also.
-*
-* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
-* @param Int_Id contains the ID of the interrupt source and should
-* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = 0x00000001U << (Int_Id % 32U);
-
- /*
- * Disable the interrupt such that it won't occur while disconnecting
- * the handler, only disable the specified interrupt id without modifying
- * the other interrupt ids
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Disconnect the handler and connect a stub, the callback reference
- * must be set to this instance to allow unhandled interrupts to be
- * tracked
- */
- InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Int_Id. Any pending
-* interrupt condition for the specified Int_Id will occur after this function is
-* called.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = 0x00000001U << (Int_Id % 32U);
-
- /*
- * Enable the selected interrupt source by setting the
- * corresponding bit in the Enable Set register.
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Int_Id such that the
-* interrupt controller will not cause interrupts for the specified Int_Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Int_Id, but will not cause an interrupt.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = 0x00000001U << (Int_Id % 32U);
-
- /*
- * Disable the selected interrupt source by setting the
- * corresponding bit in the IDR.
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-}
-
-/*****************************************************************************/
-/**
-*
-* Allows software to simulate an interrupt in the interrupt controller. This
-* function will only be successful when the interrupt controller has been
-* started in simulation mode. A simulated interrupt allows the interrupt
-* controller to be tested without any device to drive an interrupt input
-* signal into it.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id is the software interrupt ID to simulate an interrupt.
-* @param Cpu_Id is the list of CPUs to send the interrupt.
-*
-* @return
-*
-* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
-* simulated
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Int_Id <= 15U) ;
- Xil_AssertNonvoid(Cpu_Id <= 255U) ;
-
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired interrupt. Int_Id currently limited to 0 - 15
- * Use the target list for the Cpu ID.
- */
- Mask = ((Cpu_Id << 16U) | Int_Id) &
- (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
-
- /*
- * Write to the Software interrupt trigger register. Use the appropriate
- * CPU Int_Id.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
-
- /* Indicate the interrupt was successfully simulated */
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* A stub for the asynchronous callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef) {
- /*
- * verify that the inputs are valid
- */
- Xil_AssertVoid(CallBackRef != NULL);
-
- /*
- * Indicate another unhandled interrupt for stats
- */
- ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is the new priority for the IRQ source. 0 is highest
-* priority, 0xF8 (248) is lowest. There are 32 priority levels
-* supported with a step of 8. Hence the supported priorities are
-* 0, 8, 16, 32, 40 ..., 248.
-* @param Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI Read Only b10 always
-* PPI Read Only depending on how the PPIs are configured.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive
-* SPI LSB is read only.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive/
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger)
-{
- u32 RegValue;
- u8 LocalPriority;
- LocalPriority = Priority;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
- Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * The priority bits are Bits 7 to 3 in GIC Priority Register. This
- * means the number of priority levels supported are 32 and they are
- * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
- * The lower order 3 bits are masked before putting it in the register.
- */
- LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
- RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
- RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is a pointer to the value of the priority of the IRQ
-* source. This is a return value.
-* @param Trigger is pointer to the value of the trigger of the IRQ
-* source. This is a return value.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger)
-{
- u32 RegValue;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Priority != NULL);
- Xil_AssertVoid(Trigger != NULL);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%4U)*8U);
- *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%16U)*2U);
-
- *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-/****************************************************************************/
-/**
-* Sets the target CPU for the interrupt of a peripheral
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Id is a CPU number for which the interrupt has to be targeted
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue, Offset;
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_Id = (0x1U << Cpu_Id);
-
- RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
- RegValue |= ((Cpu_Id) << (Offset*8U));
-
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
-}
-/****************************************************************************/
-/**
-* Unmaps specific SPI interrupt from the target CPU
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Id is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue;
- u8 BitPos;
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- /*
- * Identify bit position corresponding to Int_Id and Cpu_Id,
- * in interrupt target register and clear it
- */
- BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
- RegValue &= (~ ( 1U << BitPos ));
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
-}
-/****************************************************************************/
-/**
-* Unmaps all SPI interrupts from the target CPU
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Id is a CPU number from which the interrupts has to be
-* unmapped
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
-{
- u32 Int_Id;
- u32 Target_Cpu;
- u32 LocalCpuID = (1U << Cpu_Id);
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U)
- {
-
- Target_Cpu = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- /* Remove LocalCpuID from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-}
-/****************************************************************************/
-/**
-* It checks if the interrupt target register contains all interrupts to be
-* targeted for current CPU. If they are programmed to be forwarded to current
-* cpu, this API disable all interrupts and disable GIC distributor.
-* This API also removes current CPU from interrupt target registers for all
-* interrupt.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_Stop(XScuGic *InstancePtr)
-{
- u32 Int_Id;
- u32 RegValue;
- u32 Target_Cpu;
- u32 DistDisable = 1; /* To track if distributor need to be disabled or not */
- u32 LocalCpuID = ((u32)0x1 << CpuId);
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- /* If distributor is already disabled, no need to do anything */
- RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
- if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
- return;
- }
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- /*
- * Check if the interrupt are targeted to current cpu only or not.
- * Also remove current cpu from interrupt target register for all
- * interrupts.
- */
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
-
- Target_Cpu = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- if ((Target_Cpu != LocalCpuID) && (Target_Cpu!= 0)) {
- /*
- * If any other CPU is also programmed to target register, GIC
- * distributor can not be disabled.
- */
- DistDisable = 0;
- }
-
- /* Remove current CPU from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * If GIC distributor is safe to be disabled, disable all the interrupt
- * and then disable distributor.
- */
- if ( DistDisable == 1) {
- for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
- /*
- * Disable all the interrupts
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
- Int_Id),
- 0xFFFFFFFFU);
- }
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
- }
-}
-
-/****************************************************************************/
-/**
-* This updates the CpuId global variable.
-*
-* @param CpuCoreId is the CPU core number.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_SetCpuID(u32 CpuCoreId)
-{
- Xil_AssertVoid(CpuCoreId <= 1U);
-
- CpuId = CpuCoreId;
-}
-
-/****************************************************************************/
-/**
-* This function returns the CpuId variable.
-*
-* @param None.
-*
-* @return The CPU core number.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XScuGic_GetCpuID(void)
-{
- return CpuId;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.h
deleted file mode 100644
index e22ee5bc283595250258993723a4d1b8aa28077b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v3_8
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-* - specific individual interrupt enabling/disabling
-* - specific individual interrupt acknowledging
-* - attaching specific callback function to handle interrupt source
-* - assigning desired priority to interrupt source if default is not
-* acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <b>Interrupt Vector Tables</b>
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs. The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* <b>Nested Interrupts Processing</b>
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET 0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
- Xil_InterruptHandler Handler;
- void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
- u16 DeviceId; /**< Unique ID of device */
- u32 CpuBaseAddress; /**< CPU Interface Register base address */
- u32 DistBaseAddress; /**< Distributor Register base address */
- XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
- Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
- XScuGic_Config *Config; /**< Configuration table entry */
- u32 IsReady; /**< Device is initialized and ready */
- u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
- (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32 XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
deleted file mode 100644
index faad4ae4dd6879daf15ea7c3c90bc797e9812434..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
+++ /dev/null
@@ -1,57 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscugic.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SCUGIC_0_DEVICE_ID,
- XPAR_PS7_SCUGIC_0_BASEADDR,
- XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
- {{0}} /**< Initialize the HandlerTable to 0 */
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
deleted file mode 100644
index 6604e3a551d1baa7dfab473c5a6642b085aa6465..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
+++ /dev/null
@@ -1,649 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.c
-* @addtogroup scugic_v3_8
-* @{
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-* These routines are used when the user does not want to create an instance of
-* XScuGic structure but still wants to use the ScuGic device. Hence the
-* routines provided here take device id or scugic base address as arguments.
-* Separate static versions of DistInit and CPUInit are provided to implement
-* the low level driver routines.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.01a sdm 07/18/11 First release
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* Added support to direct interrupts to the appropriate CPU.
-* Earlier interrupts were directed to CPU1 (hard coded). Now
-* depending upon the CPU selected by the user (xparameters.h),
-* interrupts will be directed to the relevant CPU.
-* This fixes CR 699688.
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-*
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static void DistInit(XScuGic_Config *Config, u32 CpuID);
-static void CPUInit(XScuGic_Config *Config);
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
-extern u32 CpuId;
-
-/*****************************************************************************/
-/**
-*
-* DistInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority and target CPU
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param CpuID is the Cpu ID to be initialized.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DistInit(XScuGic_Config *Config, u32 CpuID)
-{
- u32 Int_Id;
- u32 LocalCpuID = CpuID;
-
-#if USE_AMP==1
- #warning "Building GIC for AMP"
-
- /*
- * The distrubutor should not be initialized by FreeRTOS in the case of
- * AMP -- it is assumed that Linux is the master of this device in that
- * case.
- */
- return;
-#endif
-
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
-
- /*
- * Set the security domains in the int_security registers for non-secure
- * interrupts. All are secure, so leave at the default. Set to 1 for
- * non-secure interrupts.
- */
-
-
- /*
- * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
- */
-
- /*
- * 1. The trigger mode in the int_config register
- * Only write to the SPI interrupts, so start at 32
- */
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+16U) {
- /*
- * Each INT_ID uses two bits, or 16 INT_ID per register
- * Set them all to be level sensitive, active HIGH.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
- }
-
-
-#define DEFAULT_PRIORITY 0xa0a0a0a0U
- for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
- /*
- * 2. The priority using int the priority_level register
- * The priority_level and spi_target registers use one byte per
- * INT_ID.
- * Write a default value that can be changed elsewhere.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- DEFAULT_PRIORITY);
- }
-
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
- /*
- * 3. The CPU interface in the spi_target register
- * Only write to the SPI interrupts, so start at 32
- */
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
- }
-
- for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
- /*
- * 4. Enable the SPI using the enable_set register. Leave all disabled
- * for now.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
- Int_Id),
- 0xFFFFFFFFU);
-
- }
-
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
- XSCUGIC_EN_INT_MASK);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
-*
-* - Set the priority of the CPU.
-* - Enable the CPU interface
-*
-* @param ConfigPtr is a pointer to a config table for the particular
-* device this driver is associated with.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void CPUInit(XScuGic_Config *Config)
-{
- /*
- * Program the priority mask of the CPU using the Priority mask
- * register
- */
- XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
- 0xF0U);
-
- /*
- * If the CPU operates in both security domains, set parameters in the
- * control_s register.
- * 1. Set FIQen=1 to use FIQ for secure interrupts,
- * 2. Program the AckCtl bit
- * 3. Program the SBPR bit to select the binary pointer behavior
- * 4. Set EnableS = 1 to enable secure interrupts
- * 5. Set EnbleNS = 1 to enable non secure interrupts
- */
-
- /*
- * If the CPU operates only in the secure domain, setup the
- * control_s register.
- * 1. Set FIQen=1,
- * 2. Set EnableS=1, to enable the CPU interface to signal secure .
- * interrupts Only enable the IRQ output unless secure interrupts
- * are needed.
- */
- XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* CfgInitialize a specific interrupt controller instance/driver. The
-* initialization entails:
-*
-* - Initialize fields of the XScuGic structure
-* - Initial vector table with stub function calls
-* - All interrupt sources are disabled
-*
-* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
-* @param ConfigPtr is a pointer to a config table for the particular device
-* this driver is associated with.
-* @param EffectiveAddr is the device base address in the virtual memory address
-* space. The caller is responsible for keeping the address mapping
-* from EffectiveAddr to the device physical base address unchanged
-* once this function is invoked. Unexpected errors may occur if the
-* address mapping changes after this function is called. If address
-* translation is not used, use Config->BaseAddress for this parameters,
-* passing the physical address instead.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-s32 XScuGic_DeviceInitialize(u32 DeviceId)
-{
- XScuGic_Config *Config;
- u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
-
- Config = &XScuGic_ConfigTable[(u32 )DeviceId];
-
- DistInit(Config, Cpu_Id);
-
- CPUInit(Config);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the
-* interrupt.Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-* @param DeviceId is the unique identifier for the ScuGic device.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuGic_DeviceInterruptHandler(void *DeviceId)
-{
-
- u32 InterruptID;
- u32 IntIDFull;
- XScuGic_VectorTableEntry *TablePtr;
- XScuGic_Config *CfgPtr;
-
- CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
-
- /*
- * Read the int_ack register to identify the highest priority
- * interrupt ID and make sure it is valid. Reading Int_Ack will
- * clear the interrupt in the GIC.
- */
- IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
- InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
- if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
- goto IntrExit;
- }
-
- /*
- * If the interrupt is shared, do some locking here if there are
- * multiple processors.
- */
- /*
- * If pre-eption is required:
- * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
- * interrupts or the F bit for secure interrupts
- */
-
- /*
- * If we need to change security domains, issue a SMC instruction here.
- */
-
- /*
- * Execute the ISR. Jump into the Interrupt service routine based on
- * the IRQSource. A software trigger is cleared by the ACK.
- */
- TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
- if(TablePtr != NULL) {
- TablePtr->Handler(TablePtr->CallBackRef);
- }
-
-IntrExit:
- /*
- * Write to the EOI register, we are all done here.
- * Let this function return, the boot code will restore the stack.
- */
- XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
-
- /*
- * Return from the interrupt. Change security domains could happen
- * here.
- */
-}
-
-/*****************************************************************************/
-/**
-*
-* Register a handler function for a specific interrupt ID. The vector table
-* of the interrupt controller is updated, overwriting any previous handler.
-* The handler function will be called when an interrupt occurs for the given
-* interrupt ID.
-*
-* @param BaseAddress is the CPU Interface Register base address of the
-* interrupt controller whose vector table will be modified.
-* @param InterruptId is the interrupt ID to be associated with the input
-* handler.
-* @param Handler is the function pointer that will be added to
-* the vector table for the given interrupt ID.
-* @param CallBackRef is the argument that will be passed to the new
-* handler function when it is called. This is user-specific.
-*
-* @return None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef)
-{
- XScuGic_Config *CfgPtr;
- CfgPtr = LookupConfigByBaseAddress(BaseAddress);
-
- if(CfgPtr != NULL) {
- if( IntrHandler != NULL) {
- CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
- }
- if( CallBackRef != NULL) {
- CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
- }
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the CPU interface base address of
-* the device. A table contains the configuration info for each device in the
-* system.
-*
-* @param CpuBaseAddress is the CPU Interface Register base address.
-*
-* @return A pointer to the configuration structure for the specified
-* device, or NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
-{
- XScuGic_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
- if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
- CpuBaseAddress) {
- CfgPtr = &XScuGic_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuGic_Config *)CfgPtr;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param BaseAddr is the device base address
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is the new priority for the IRQ source. 0 is highest
-* priority, 0xF8 (248) is lowest. There are 32 priority levels
-* supported with a step of 8. Hence the supported priorities are
-* 0, 8, 16, 32, 40 ..., 248.
-* @param Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI Read Only b10 always
-* PPI Read Only depending on how the PPIs are configured.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive
-* SPI LSB is read only.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive/
-*
-* @return None.
-*
-* @note This API has the similar functionality of XScuGic_SetPriority
-* TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger)
-{
- u32 RegValue;
- u8 LocalPriority = Priority;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
- Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * The priority bits are Bits 7 to 3 in GIC Priority Register. This
- * means the number of priority levels supported are 32 and they are
- * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
- * The lower order 3 bits are masked before putting it in the register.
- */
- LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
- RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
- RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- RegValue);
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param BaseAddr is the device base address
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is a pointer to the value of the priority of the IRQ
-* source. This is a return value.
-* @param Trigger is pointer to the value of the trigger of the IRQ
-* source. This is a return value.
-*
-* @return None.
-*
-* @note This API has the similar functionality of XScuGic_GetPriority
-* TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger)
-{
- u32 RegValue;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Priority != NULL);
- Xil_AssertVoid(Trigger != NULL);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%4U)*8U);
- *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%16U)*2U);
-
- *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-
-/****************************************************************************/
-/**
-* Unmaps specific SPI interrupt from the target CPU
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue;
- u8 BitPos;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- /*
- * Identify bit position corresponding to Int_Id and Cpu_Id,
- * in interrupt target register and clear it
- */
- BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
- RegValue &= (~ ( 1U << BitPos ));
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
-}
-
-/****************************************************************************/
-/**
-* Unmaps all SPI interrupts from the target CPU
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupts has to be
-* unmapped
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id)
-{
- u32 Int_Id;
- u32 Target_Cpu;
- u32 LocalCpuID = (1U << Cpu_Id);
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U)
- {
-
- Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- /* Remove LocalCpuID from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.h
deleted file mode 100644
index 08e65f456e41dcb0ea23b58e7bd3387a22cc6155..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.h
+++ /dev/null
@@ -1,650 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v3_8
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef __ARM_NEON__
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
-#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
- Register */
-#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
- Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
- Register */
-#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
- Register */
-#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
- Register */
-#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
- Register */
-#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
- Register */
-#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
- Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
- Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
- 0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
- Register */
-#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
- Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
-#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
-/* @} */
-
-/** @name Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
-/* @} */
-
-/** @name Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
- Shared Peripheral
- Interrupts*/
-#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080. A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
- INT_ID */
-#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
- actually the lowest priority*/
-/* @} */
-
-/** @name SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI Read Only b10 always
- * PPI Read Only depending on how the PPIs are configured.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive
- * SPI LSB is read only.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
-/* @} */
-
-/** @name PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
-/* @} */
-
-/** @name SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
- input */
-/* @} */
-
-/** @name AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianess
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
- 1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
- 1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name Software Triggered Interrupt Register
- * Controls issueing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
- b00-Use the target List
- b01-All CPUs except requester
- b10-To Requester
- b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
- signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
- Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
- Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
- Binary Point Register */
-
-/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
- 0=separate registers,
- 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
- interrupts,
- 0= use IRQ for both,
- 1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-/** @name Priority Mask Register
- * Priority Mask register definitions
- * The CPU interface does not send interrupt if the level of the interrupt is
- * lower than the level of the register.
- * @{
- */
-/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
-/* @} */
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
- Value Secure Non-secure
- b000 0xFE 0xFF
- b001 0xFC 0xFE
- b010 0xF8 0xFC
- b011 0xF0 0xF8
- b100 0xE0 0xF0
- b101 0xC0 0xE0
- b110 0x80 0xC0
- b111 0x00 0x80
- */
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
-/* @} */
-
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interupt
- */
-#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
-/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param Register is the register offset for the clear/enable bank.
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
- ((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/****************************************************************************/
-/**
-*
-* Enable specific interrupt(s) in the interrupt controller.
-*
-* @param DistBaseAddress is the Distributor Register base address of the
-* device
-* @param Int_Id is the ID of the interrupt source and should be in the
-* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
- XScuGic_WriteReg((DistBaseAddress), \
- XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
- (0x00000001U << ((Int_Id) % 32U)))
-
-/****************************************************************************/
-/**
-*
-* Disable specific interrupt(s) in the interrupt controller.
-*
-* @param DistBaseAddress is the Distributor Register base address of the
-* device
-* @param Int_Id is the ID of the interrupt source and should be in the
-* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
-*
-*****************************************************************************/
-#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
- XScuGic_WriteReg((DistBaseAddress), \
- XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
- (0x00000001U << ((Int_Id) % 32U)))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32 XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
deleted file mode 100644
index d82a60b9e0f3b1cabc70e099deb86751a56f06a2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_intr.c
-* @addtogroup scugic_v3_8
-* @{
-*
-* This file contains the interrupt processing for the driver for the Xilinx
-* Interrupt Controller. The interrupt processing is partitioned separately such
-* that users are not required to use the provided interrupt processing. This
-* file requires other files of the driver to be linked in also.
-*
-* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
-* is an instance pointer to an interrupt controller driver such that multiple
-* interrupt controllers can be supported. This handler requires the calling
-* function to pass it the appropriate argument, so another level of indirection
-* may be required.
-*
-* The interrupt processing may be used by connecting the interrupt handler to
-* the interrupt system. The handler does not save and restore the processor
-* context but only handles the processing of the Interrupt Controller. The user
-* is encouraged to supply their own interrupt handler when performance tuning is
-* deemed necessary.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
-* since the HandlerTable has now moved to XScuGic_Config.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-* @internal
-*
-* This driver assumes that the context of the processor has been saved prior to
-* the calling of the Interrupt Controller interrupt handler and then restored
-* after the handler returns. This requires either the running RTOS to save the
-* state of the machine or that a wrapper be used as the destination of the
-* interrupt vector to save the state of the processor and restore the state
-* after the interrupt handler returns.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the interrupt.
-* Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuGic_InterruptHandler(XScuGic *InstancePtr)
-{
-
- u32 InterruptID;
- u32 IntIDFull;
- XScuGic_VectorTableEntry *TablePtr;
-
- /* Assert that the pointer to the instance is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Read the int_ack register to identify the highest priority interrupt ID
- * and make sure it is valid. Reading Int_Ack will clear the interrupt
- * in the GIC.
- */
- IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
- InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-
- if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
- goto IntrExit;
- }
-
- /*
- * If the interrupt is shared, do some locking here if there are multiple
- * processors.
- */
- /*
- * If pre-eption is required:
- * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
- * interrupts or the F bit for secure interrupts
- */
-
- /*
- * If we need to change security domains, issue a SMC instruction here.
- */
-
- /*
- * Execute the ISR. Jump into the Interrupt service routine based on the
- * IRQSource. A software trigger is cleared by the ACK.
- */
- TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
- if(TablePtr != NULL) {
- TablePtr->Handler(TablePtr->CallBackRef);
- }
-
- IntrExit:
- /*
- * Write to the EOI register, we are all done here.
- * Let this function return, the boot code will restore the stack.
- */
- XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
-
- /*
- * Return from the interrupt. Change security domains could happen here.
- */
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
deleted file mode 100644
index 7b1028f9f5208c3a72e8bc682a622472a4f80deb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_selftest.c
-* @addtogroup scugic_v3_8
-* @{
-*
-* Contains diagnostic self-test functions for the XScuGic driver.
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XSCUGIC_PCELL_ID 0xB105F00DU
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. This test reads the ID registers and
-* compares them.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return
-*
-* - XST_SUCCESS if self-test is successful.
-* - XST_FAILURE if the self-test is not successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_SelfTest(XScuGic *InstancePtr)
-{
- u32 RegValue1 = 0U;
- u32 Index;
- s32 Status;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the ID registers.
- */
- for(Index=0U; Index<=3U; Index++) {
- RegValue1 |= XScuGic_DistReadReg(InstancePtr,
- ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
- }
-
- if(XSCUGIC_PCELL_ID != RegValue1){
- Status = XST_FAILURE;
- } else {
- Status = XST_SUCCESS;
- }
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
deleted file mode 100644
index 842f3181254b60ce05e2af821d73e801c6ab3e2a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscugic_sinit.c
-* @addtogroup scugic_v3_8
-* @{
-*
-* Contains static init functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique identifier for a device.
-*
-* @return A pointer to the XScuGic configuration structure for the
-* specified device, or NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
-{
- XScuGic_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
- if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XScuGic_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuGic_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
deleted file mode 100644
index 7c673d4b6e3ac3a30f3e0f580e2f15a54d3dc33e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner scutimer_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling scutimer"
-
-scutimer_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: scutimer_includes
-
-scutimer_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
deleted file mode 100644
index 9d477d971eac89fe821b93f90e85ca9565a44965..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer.c
-* @addtogroup scutimer_v2_1
-* @{
-*
-* Contains the implementation of interface functions of the SCU Timer driver.
-* See xscutimer.h for a description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize a specific timer instance/driver. This function must be called
-* before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param ConfigPtr points to the XScuTimer configuration structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
-{
- s32 Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
- /*
- * Copy configuration into the instance structure.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
-
- InstancePtr->IsStarted = (u32)0;
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- Status =(s32)XST_SUCCESS;
- }
- else {
- Status = (s32)XST_DEVICE_IS_STARTED;
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Start the timer.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuTimer_Start(XScuTimer *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
-
- /*
- * Set the 'timer enable' bit in the register.
- */
- Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
-
- /*
- * Update the Control register with the new value.
- */
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is started.
- */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-}
-
-/****************************************************************************/
-/**
-*
-* Stop the timer.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuTimer_Stop(XScuTimer *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
-
- /*
- * Clear the 'timer enable' bit in the register.
- */
- Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
-
- /*
- * Update the Control register with the new value.
- */
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is stopped.
- */
- InstancePtr->IsStarted = (u32)0;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the prescaler bits in the timer control register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
-{
- u32 ControlReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- /*
- * Read the Timer control register.
- */
- ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
-
- /*
- * Clear all of the prescaler control bits in the register.
- */
- ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
-
- /*
- * Set the prescaler value.
- */
- ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
-
- /*
- * Write the register with the new values.
- */
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, ControlReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current prescaler value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return The prescaler value.
-*
-* @note None.
-*
-****************************************************************************/
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
-{
- u32 ControlReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Timer control register.
- */
- ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
- ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
-
- return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
deleted file mode 100644
index ea4ba79de086a74eb57b0ab5c22fe3441ee3ce1e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_1
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* <b> Interrupts </b>
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
deleted file mode 100644
index 34b06867d26ef87262eebaa7981cbf6c18c32546..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscutimer.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SCUTIMER_0_DEVICE_ID,
- XPAR_PS7_SCUTIMER_0_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
deleted file mode 100644
index ac7b42934796aa41e49adfc510057e951e0b2e0d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_1
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
deleted file mode 100644
index 6e37fef3bb77005e3111e97a5b15830ce42d30e0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscutimer_selftest.c
-* @addtogroup scutimer_v2_1
-* @{
-*
-* Contains diagnostic self-test functions for the XScuTimer driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the timer. This test clears the timer enable bit in
-* the control register, writes to the timer load register and verifies the
-* value read back matches the value written and restores the control register
-* and the timer load register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if self test was not successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
-{
- u32 Register;
- u32 CtrlOrig;
- u32 LoadOrig;
- s32 Status;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Save the contents of the Control Register and stop the timer.
- */
- CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
- Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Save the contents of the Load Register.
- * Load a new test value in the Load Register, read it back and
- * compare it with the written value.
- */
- LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUTIMER_LOAD_OFFSET);
- XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
- Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUTIMER_LOAD_OFFSET);
-
- /*
- * Restore the contents of the Load Register and Control Register.
- */
- XScuTimer_LoadTimer(InstancePtr, LoadOrig);
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
-
- /*
- * Return a Failure if the contents of the Load Register do not
- * match with the value written to it.
- */
- if (Register != XSCUTIMER_SELFTEST_VALUE) {
- Status = (s32)XST_FAILURE;
- }
- else {
- Status = (s32)XST_SUCCESS;
- }
-
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
deleted file mode 100644
index 3bcc57ebde32600b754f7a01d71ece0fb0eecbdb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscutimer_sinit.c
-* @addtogroup scutimer_v2_1
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions ****************************/
-extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
-{
- XScuTimer_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
- if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XScuTimer_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuTimer_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
deleted file mode 100644
index 493ad9a4e8e87a236832a0e1875ad594931b2647..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner scuwdt_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling scuwdt"
-
-scuwdt_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: scuwdt_includes
-
-scuwdt_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
deleted file mode 100644
index cd9e15d2c1b68de39483e33b9654894cfbdc1718..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.c
-* @addtogroup scuwdt_v2_1
-* @{
-*
-* Contains the implementation of interface functions of the XScuWdt driver.
-* See xscuwdt.h for a description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize a specific watchdog timer instance/driver. This function
-* must be called before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ConfigPtr is the config structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note This function enables the watchdog mode.
-*
-******************************************************************************/
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
-{
- s32 CfgStatus;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- Xil_AssertNonvoid(EffectiveAddress != 0x00U);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- CfgStatus = (s32)XST_DEVICE_IS_STARTED;
- }
- else {
- /*
- * Copy configuration into instance.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
- InstancePtr->IsStarted = 0U;
-
- /*
- * Put the watchdog timer in Watchdog mode.
- */
- XScuWdt_SetWdMode(InstancePtr);
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- CfgStatus =(s32)XST_SUCCESS;
- }
- return CfgStatus;
-}
-
-/****************************************************************************/
-/**
-*
-* Start the watchdog counter of the device.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note User needs to select the appropriate mode (watchdog/timer)
-* before using this API.
-* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
-* xscuwdt.h.
-*
-******************************************************************************/
-void XScuWdt_Start(XScuWdt *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET);
-
- /*
- * Set the 'watchdog enable' bit in the register.
- */
- Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
-
- /*
- * Update the Control register with the new value.
- */
- XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is started.
- */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-}
-
-/****************************************************************************/
-/**
-*
-* Stop the watchdog timer.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuWdt_Stop(XScuWdt *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET);
-
- /*
- * Clear the 'watchdog enable' bit in the register.
- */
- Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
-
- /*
- * Update the Control register with the new value.
- */
- XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is stopped.
- */
- InstancePtr->IsStarted = 0U;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
deleted file mode 100644
index 372bbc3439aadbb94cf3fe04b97535757d4d1107..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_1
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* <b>Interrupts</b>
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b> Building the driver </b>
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <br><br>
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /* prevent circular inclusions */
-#define XSCUWDT_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
deleted file mode 100644
index ae52c194c68ab316223c512f8384f34b33f6a2b7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscuwdt.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SCUWDT_0_DEVICE_ID,
- XPAR_PS7_SCUWDT_0_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
deleted file mode 100644
index 2067d3a531870de0fe1851b65a2f653f58aa73f8..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_1
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
-#define XSCUWDT_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
deleted file mode 100644
index 95d50651030e1886a6bc176623c74ae986aeff68..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_selftest.c
-* @addtogroup scuwdt_v2_1
-* @{
-*
-* Contains diagnostic self-test functions for the XScuWdt driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the WDT. This test stops the watchdog, writes a value to
-* the watchdog load register, starts the watchdog and verifies that the value
-* read from the counter register is less that the value written to the load
-* register. It then restores the control register and the watchdog load
-* register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if the WDT is not decrementing.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
-{
- s32 SelfTestStatus;
- u32 Register;
- u32 CtrlOrig;
- u32 LoadOrig;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Stop the watchdog timer.
- */
- CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
- XScuWdt_SetControlReg(InstancePtr,
- CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
-
- LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUWDT_LOAD_OFFSET);
- XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
-
- /*
- * Start the watchdog timer and check if the watchdog counter is
- * decrementing.
- */
- XScuWdt_SetControlReg(InstancePtr,
- CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
-
- Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUWDT_COUNTER_OFFSET);
-
- XScuWdt_LoadWdt(InstancePtr, LoadOrig);
- XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
-
- if (Register == 0xFFFFFFFFU) {
- SelfTestStatus = (s32)XST_FAILURE;
- }
- else {
- SelfTestStatus = (s32)XST_SUCCESS;
- }
-
- return SelfTestStatus;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
deleted file mode 100644
index c63eb9af03395e6ab4294af62a380205bba1c58f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xscuwdt_sinit.c
-* @addtogroup scuwdt_v2_1
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
-{
- XScuWdt_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
- if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XScuWdt_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuWdt_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/Makefile
deleted file mode 100644
index f57081af62aab0d058d075fd27383824b280d42e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xsdps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling sdps"
-
-xsdps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xsdps_includes
-
-xsdps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
deleted file mode 100644
index 8b1f11382d0c470d6837b306a17c851725d875d0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
+++ /dev/null
@@ -1,1763 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps.c
-* @addtogroup sdps_v3_5
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
-* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 07/17/17 Add support for running SD at 200MHz
-* mn 07/26/17 Fixed compilation warnings
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Added CCI support for A53 and disabled data cache
-* operations when it is enabled.
-* mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
-* 3.4 mn 10/17/17 Use different commands for single and multi block
-* transfers
-* mn 03/02/18 Move UHS macro check to SD card initialization routine
-* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps.h"
-#include "sleep.h"
-
-/************************** Constant Definitions *****************************/
-#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
-#define XSDPS_RESPOCR_READY 0x80000000U
-#define XSDPS_ACMD41_HCS 0x40000000U
-#define XSDPS_ACMD41_3V3 0x00300000U
-#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
-#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
-#define HIGH_SPEED_SUPPORT 0x2U
-#define UHS_SDR50_SUPPORT 0x4U
-#define WIDTH_4_BIT_SUPPORT 0x4U
-#define SD_CLK_25_MHZ 25000000U
-#define SD_CLK_19_MHZ 19000000U
-#define SD_CLK_26_MHZ 26000000U
-#define EXT_CSD_DEVICE_TYPE_BYTE 196U
-#define EXT_CSD_SEC_COUNT_BYTE1 212U
-#define EXT_CSD_SEC_COUNT_BYTE2 213U
-#define EXT_CSD_SEC_COUNT_BYTE3 214U
-#define EXT_CSD_SEC_COUNT_BYTE4 215U
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
-#define CSD_SPEC_VER_3 0x3U
-#define SCR_SPEC_VER_3 0x80U
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
-static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
-
-u16 TransferMode;
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XSdPs instance such that the driver is ready to use.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific SD device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_DEVICE_IS_STARTED if the device is already started.
-* It must be stopped to re-initialize.
-*
-* @note This function initializes the host controller.
-* Initial clock of 400KHz is set.
-* Voltage of 3.3V is selected as that is supported by host.
-* Interrupts status is enabled and signal disabled by default.
-* Default data direction is card to host and
-* 32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
-*
-******************************************************************************/
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status;
- u8 PowerLevel;
- u8 ReadReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /* Set some default values. */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
- InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
- InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
- InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
- InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
- InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
- InstancePtr->SectorCount = 0;
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- InstancePtr->Config_TapDelay = NULL;
-
- /* Disable bus power and issue emmc hw reset */
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
- XSDPS_HC_SPEC_V3)
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
- else
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET, 0x0);
-
- /* Delay to poweroff card */
- (void)usleep(1000U);
-
- /* "Software reset for all" is initiated */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
- XSDPS_SWRST_ALL_MASK);
-
- /* Proceed with initialization only after reset is complete */
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- }
- /* Host Controller version is read. */
- InstancePtr->HC_Version =
- (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
-
- /*
- * Read capabilities register and update it in Instance pointer.
- * It is sufficient to read this once on power on.
- */
- InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_CAPS_OFFSET);
-
- /* Select voltage and enable bus power. */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
- ~XSDPS_PC_EMMC_HW_RST_MASK);
- else
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
-
- /* Delay before issuing the command after emmc reset */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
- if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
- XSDPS_CAPS_EMB_SLOT)
- usleep(200);
-
- /* Change the clock frequency to 400 KHz */
- Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
- } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
- } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
- } else {
- PowerLevel = 0U;
- }
-
- /* Select voltage based on capability and enable bus power. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- PowerLevel | XSDPS_PC_BUS_PWR_MASK);
-
-#ifdef __aarch64__
- /* Enable ADMA2 in 64bit mode. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- XSDPS_HC_DMA_ADMA2_64_MASK);
-#else
- /* Enable ADMA2 in 32bit mode. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- XSDPS_HC_DMA_ADMA2_32_MASK);
-#endif
-
- /* Enable all interrupt status except card interrupt initially */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_EN_OFFSET,
- XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_EN_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
-
- /* Disable all interrupt signals by default. */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
-
- /*
- * Transfer mode register - default value
- * DMA enabled, block count enabled, data direction card to host(read)
- */
- TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK;
-
- /* Set block size to 512 by default */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* SD initialization is done in this function
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) SD is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the
- initialization cycle failed
-*
-* @note This function initializes the SD card by following its
-* initialization and identification state diagram.
-* CMD0 is sent to reset card.
-* CMD8 and ACDM41 are sent to identify voltage and
-* high capacity support
-* CMD2 and CMD3 are sent to obtain Card ID and
-* Relative card address respectively.
-* CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
-{
- u32 PresentStateReg;
- s32 Status;
- u32 RespOCR;
- u32 CSD[4];
- u32 Arg;
- u8 ReadReg;
- u32 BlkLen, DeviceSize, Mult;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#ifndef UHS_MODE_ENABLE
- InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
-#endif
-
- if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT)) {
- if(InstancePtr->Config.CardDetect != 0U) {
- /*
- * Check the present state register to make sure
- * card is inserted and detected by host controller
- */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * CMD8; response expected
- * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
- */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
- XSDPS_CMD8_VOL_PATTERN, 0U);
- if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (Status == XSDPS_CT_ERROR) {
- /* "Software reset for all" is initiated */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
- XSDPS_SWRST_CMD_LINE_MASK);
-
- /* Proceed with initialization only after reset is complete */
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- }
- }
-
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
- InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
- }
- else {
- InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
- }
-
- RespOCR = 0U;
- /* Send ACMD41 while card is still busy with power up */
- while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
- /*
- * There is no support to switch to 1.8V and use UHS mode on
- * 1.0 silicon
- */
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
- (XGetPSVersion_Info() > XPS_VERSION_1) &&
-#endif
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
- Arg |= XSDPS_OCR_S18;
- }
-
- /* 0x40300000 - Host High Capacity support & 3.3V window */
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
- Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Response with card capacity */
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- }
-
- /* Update HCS support flag based on card capacity response */
- if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
- InstancePtr->HCS = 1U;
- }
-
- if ((RespOCR & XSDPS_OCR_S18) != 0U) {
- InstancePtr->Switch1v8 = 1U;
- Status = XSdPs_Switch_Voltage(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- /* CMD2 for Card ID */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->CardID[0] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- InstancePtr->CardID[1] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- InstancePtr->CardID[2] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- InstancePtr->CardID[3] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
- do {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Relative card address is stored as the upper 16 bits
- * This is to avoid shifting when sending commands
- */
- InstancePtr->RelCardAddr =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
- } while (InstancePtr->RelCardAddr == 0U);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Card specific data is read.
- * Currently not used for any operation.
- */
- CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
- BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
- Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
- DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
- DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
- DeviceSize = (DeviceSize + 1U) * Mult;
- DeviceSize = DeviceSize * BlkLen;
- InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
- } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
- InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
- 1U) * 1024U;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Initialize Card with Identification mode sequence
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) SD is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the
-* initialization cycle failed
-*
-*
-******************************************************************************/
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 ExtCsd[512];
- u8 SCR[8] = { 0U };
-#pragma data_alignment = 4
-#else
- static u8 ExtCsd[512] __attribute__ ((aligned(32)));
- u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
-#endif
- u8 ReadBuff[64] = { 0U };
- s32 Status;
- u32 Arg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Default settings */
- InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
- InstancePtr->CardType = XSDPS_CARD_SD;
- InstancePtr->Switch1v8 = 0U;
- InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- == XSDPS_CAPS_EMB_SLOT)) {
- InstancePtr->CardType = XSDPS_CHIP_EMMC;
- } else {
- Status = XSdPs_IdentifyCard(InstancePtr);
- if (Status == XST_FAILURE) {
- goto RETURN_PATH;
- }
- }
-
- if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
- (InstancePtr->CardType != XSDPS_CARD_MMC) &&
- (InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_SdCardInitialize(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Change clock to default clock 25MHz */
- /*
- * SD default speed mode timing should be closed at 19 MHz.
- * The reason for this is SD requires a voltage level shifter.
- * This limitation applies to ZynqMPSoC.
- */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
- InstancePtr->BusSpeed = SD_CLK_19_MHZ;
- else
- InstancePtr->BusSpeed = SD_CLK_25_MHZ;
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- } else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
- || (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
- Status = XSdPs_MmcCardInitialize(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- /* Change clock to default clock 26MHz */
- InstancePtr->BusSpeed = SD_CLK_26_MHZ;
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Select_Card(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- /* Pull-up disconnected during data transfer */
- Status = XSdPs_Pullup(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- /* Get speed supported by device */
- Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
- if (Status != XST_SUCCESS) {
- goto RETURN_PATH;
- }
-
- if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
- (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
- (XGetPSVersion_Info() > XPS_VERSION_1) &&
-#endif
- (InstancePtr->Switch1v8 == 0U)) {
- u16 CtrlReg, ClockReg;
-
- /* Stop the clock */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
- CtrlReg);
-
- /* Enabling 1.8V in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
- CtrlReg);
-
- /* Wait minimum 5mSec */
- (void)usleep(5000U);
-
- /* Check for 1.8V signal enable bit is cleared by Host */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for internal clock to stabilize */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET,
- ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- }
-
- /* Enable SD clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET,
- ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
-
- /* Wait for 1mSec */
- (void)usleep(1000U);
-
- InstancePtr->Switch1v8 = 1U;
- }
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- if (InstancePtr->Switch1v8 != 0U) {
-
- /* Identify the UHS mode supported by card */
- XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
-
- /* Set UHS-I SDR104 mode */
- Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
- if (Status != XST_SUCCESS) {
- goto RETURN_PATH;
- }
-
- } else {
-#endif
- /*
- * card supports CMD6 when SD_SPEC field in SCR register
- * indicates that the Physical Layer Specification Version
- * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
- */
- if (SCR[0] != 0U) {
- /* Check for high speed support */
- if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
-#endif
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- }
-#endif
-
- } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
- (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
- (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
-
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
-
- if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
- /* Change bus width to 8-bit */
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get Extended CSD */
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
-
- /* Check for card supported speed */
- if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
- EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HS200_MODE;
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
-#endif
- } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
- EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_DDR52_MODE;
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
-#endif
- } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
-#endif
- } else
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
-
- if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_HS200_MODE) {
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
- InstancePtr->Mode == XSDPS_DDR52_MODE) {
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
- }
-
- /* Enable Rst_n_Fun bit if it is disabled */
- if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
- Arg = XSDPS_MMC_RST_FUN_EN_ARG;
- Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
- if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
- (InstancePtr->CardType == XSDPS_CARD_SD)) {
- Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Identify type of card using CMD0 + CMD1 sequence
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
-{
- s32 Status;
- u8 ReadReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* 74 CLK delay after card is powered up, before the first command. */
- usleep(XSDPS_INIT_DELAY);
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Host High Capacity support & High voltage window */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
- XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
- if (Status != XST_SUCCESS) {
- InstancePtr->CardType = XSDPS_CARD_SD;
- } else {
- InstancePtr->CardType = XSDPS_CARD_MMC;
- }
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-
- /* "Software reset for all" is initiated */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
- XSDPS_SWRST_CMD_LINE_MASK);
-
- /* Proceed with initialization only after reset is complete */
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Switches the SD card voltage from 3v3 to 1v8
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 CtrlReg;
- u32 ReadReg, ClockReg;
-
- /* Send switch voltage command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- /* Wait for CMD and DATA line to go low */
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
- XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- }
-
- /* Stop the clock */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
- CtrlReg);
-
- /* Enabling 1.8V in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
- CtrlReg);
-
- /* Wait minimum 5mSec */
- (void)usleep(5000U);
-
- /* Check for 1.8V signal enable bit is cleared by Host */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for internal clock to stabilize */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET,
- ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- }
-
- /* Enable SD clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET,
- ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
-
- /* Wait for 1mSec */
- (void)usleep(1000U);
-
- /* Wait for CMD and DATA line to go high */
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
- != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-
-* This function does SD command generation.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the command to be sent.
-* @param Arg is the argument to be sent along with the command.
-* This could be address or any other information
-* @param BlkCnt - Block count passed by the user.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
-{
- u32 PresentStateReg;
- u32 CommandReg;
- u32 StatusReg;
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check the command inhibit to make sure no other
- * command transfer is in progress
- */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Write block count register */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
-
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
-
- /* Write argument register */
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSDPS_ARGMT_OFFSET, Arg);
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
- /* Command register is set to trigger transfer of command */
- CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
-
- /*
- * Mask to avoid writing to reserved bits 31-30
- * This is necessary because 0x80000000 is used by this software to
- * distinguish between ACMD and CMD of same number
- */
- CommandReg = CommandReg & 0x3FFFU;
-
- /*
- * Check for data inhibit in case of command using DAT lines.
- * For Tuning Commands DAT lines check can be ignored.
- */
- if ((Cmd != CMD21) && (Cmd != CMD19)) {
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
- XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
- ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
- (CommandReg << 16) | TransferMode);
-
- /* Polling for response for now */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((Cmd == CMD21) || (Cmd == CMD19)) {
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
- break;
- }
- }
-
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET);
- if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
- Status = XSDPS_CT_ERROR;
- }
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- goto RETURN_PATH;
- }
- } while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET,
- XSDPS_INTR_CC_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* This function frames the Command register for a particular command.
-* Note that this generates only the command register value i.e.
-* the upper 16 bits of the transfer mode and command register.
-* This value is already shifted to be upper 16 bits and can be directly
-* OR'ed with transfer mode register value.
-*
-* @param Command to be sent.
-*
-* @return Command register value complete with response type and
-* data, CRC and index related flags.
-*
-******************************************************************************/
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
-{
- u32 RetVal;
-
- RetVal = Cmd;
-
- switch(Cmd) {
- case CMD0:
- RetVal |= RESP_NONE;
- break;
- case CMD1:
- RetVal |= RESP_R3;
- break;
- case CMD2:
- RetVal |= RESP_R2;
- break;
- case CMD3:
- RetVal |= RESP_R6;
- break;
- case CMD4:
- RetVal |= RESP_NONE;
- break;
- case CMD5:
- RetVal |= RESP_R1B;
- break;
- case CMD6:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- } else {
- RetVal |= RESP_R1B;
- }
- break;
- case ACMD6:
- RetVal |= RESP_R1;
- break;
- case CMD7:
- RetVal |= RESP_R1;
- break;
- case CMD8:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R1;
- } else {
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- }
- break;
- case CMD9:
- RetVal |= RESP_R2;
- break;
- case CMD11:
- case CMD10:
- case CMD12:
- case ACMD13:
- case CMD16:
- RetVal |= RESP_R1;
- break;
- case CMD17:
- case CMD18:
- case CMD19:
- case CMD21:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD23:
- case ACMD23:
- case CMD24:
- case CMD25:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case ACMD41:
- RetVal |= RESP_R3;
- break;
- case ACMD42:
- RetVal |= RESP_R1;
- break;
- case ACMD51:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD52:
- case CMD55:
- RetVal |= RESP_R1;
- break;
- case CMD58:
- break;
- default :
- RetVal |= Cmd;
- break;
- }
-
- return RetVal;
-}
-
-/*****************************************************************************/
-/**
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
- u32 PresentStateReg;
- u32 StatusReg;
-
- if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT)) {
- if(InstancePtr->Config.CardDetect != 0U) {
- /* Check status to ensure card is initialized */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* Set block size to 512 if not already set */
- if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
- Status = XSdPs_SetBlkSize(InstancePtr,
- XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheInvalidateRange((INTPTR)Buff,
- BlkCnt * XSDPS_BLK_SIZE_512_MASK);
- }
-
- if (BlkCnt == 1U) {
- TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- /* Send single block read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
- XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
-
- /* Send multiple blocks read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- /* Check for transfer complete */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* This function performs SD write in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
-{
- s32 Status;
- u32 PresentStateReg;
- u32 StatusReg;
-
- if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT)) {
- if(InstancePtr->Config.CardDetect != 0U) {
- /* Check status to ensure card is initialized */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* Set block size to 512 if not already set */
- if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
- Status = XSdPs_SetBlkSize(InstancePtr,
- XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- }
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheFlushRange((INTPTR)Buff,
- BlkCnt * XSDPS_BLK_SIZE_512_MASK);
- }
-
- if (BlkCnt == 1U) {
- TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
-
- /* Send single block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- /* Send multiple blocks write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Selects card and sets default block size
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Select_Card (XSdPs *InstancePtr)
-{
- s32 Status = 0;
-
- /* Send CMD7 - Select card */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to setup ADMA2 descriptor table
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
- u32 TotalDescLines = 0U;
- u32 DescNum = 0U;
- u32 BlkSize = 0U;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET);
- BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
-
- TotalDescLines = 1U;
-
- }else {
-
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
-
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
-#ifdef __aarch64__
- InstancePtr->Adma2_DescrTbl[DescNum].Address =
- (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-#else
- InstancePtr->Adma2_DescrTbl[DescNum].Address =
- (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-#endif
- InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- /* This will write '0' to length field which indicates 65536 */
- InstancePtr->Adma2_DescrTbl[DescNum].Length =
- (u16)XSDPS_DESC_MAX_LENGTH;
- }
-
-#ifdef __aarch64__
- InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
- (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-#else
- InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
- (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-#endif
-
- InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
-
-#ifdef __aarch64__
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
- (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
-#endif
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
-
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor) * 32U);
- }
-}
-
-/*****************************************************************************/
-/**
-* Mmc initialization is done in this function
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) MMC is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the initialization
-* cycle failed
-* @note This function initializes the SD card by following its
-* initialization and identification state diagram.
-* CMD0 is sent to reset card.
-* CMD1 sent to identify voltage and high capacity support
-* CMD2 and CMD3 are sent to obtain Card ID and
-* Relative card address respectively.
-* CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
-{
- u32 PresentStateReg;
- s32 Status;
- u32 RespOCR;
- u32 CSD[4];
- u32 BlkLen, DeviceSize, Mult;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT)) {
- if(InstancePtr->Config.CardDetect != 0U) {
- /*
- * Check the present state register to make sure
- * card is inserted and detected by host controller
- */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- RespOCR = 0U;
- /* Send CMD1 while card is still busy with power up */
- while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
-
- /* Host High Capacity support & High volage window */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
- XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Response with card capacity */
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- }
-
- /* Update HCS support flag based on card capacity response */
- if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
- InstancePtr->HCS = 1U;
- }
-
- /* CMD2 for Card ID */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->CardID[0] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- InstancePtr->CardID[1] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- InstancePtr->CardID[2] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- InstancePtr->CardID[3] =
- XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- /* Set relative card address */
- InstancePtr->RelCardAddr = 0x12340000U;
- Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Card specific data is read.
- * Currently not used for any operation.
- */
- CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
-
- /* Calculating the memory capacity */
- BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
- Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
- DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
- DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
- DeviceSize = (DeviceSize + 1U) * Mult;
- DeviceSize = DeviceSize * BlkLen;
-
- InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
deleted file mode 100644
index b8d979d1d768214c5986d7899cbaa81ba5369c0d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_5
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Intialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in tranfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesytem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-*
-* </pre>
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include "xplatform_info.h"
-#include <string.h>
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
-#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
-
-/**************************** Type Definitions *******************************/
-
-typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u32 CardDetect; /**< Card Detect */
- u32 WriteProtect; /**< Write Protect */
- u32 BusWidth; /**< Bus Width */
- u32 BankNumber; /**< MIO Bank selection for SD */
- u32 HasEMIO; /**< If SD is connected to EMIO */
- u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
-} XSdPs_Config;
-
-/* ADMA2 descriptor table */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
-#ifdef __aarch64__
- u64 Address; /**< Address of current dma transfer */
-#else
- u32 Address; /**< Address of current dma transfer */
-#endif
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor;
-#pragma data_alignment = 4
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor;
-#endif
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XSdPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
- u32 Host_Caps; /**< Capabilities of host controller */
- u32 Host_CapsExt; /**< Extended Capabilities */
- u32 HCS; /**< High capacity support in card */
- u8 CardType; /**< Type of card - SD/MMC/eMMC */
- u8 Card_Version; /**< Card version */
- u8 HC_Version; /**< Host controller version */
- u8 BusWidth; /**< Current operating bus width */
- u32 BusSpeed; /**< Current operating bus speed */
- u8 Switch1v8; /**< 1.8V Switch support */
- u32 CardID[4]; /**< Card ID Register */
- u32 RelCardAddr; /**< Relative Card Address */
- u32 CardSpecData[4]; /**< Card Specific Data Register */
- u32 SectorCount; /**< Sector Count */
- u32 SdCardConfig; /**< Sd Card Configuration Register */
- u32 Mode; /**< Bus Speed Mode */
- XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
- /**< ADMA Descriptors */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
-#pragma data_alignment = 4
-#else
- XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Select_Card (XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
-void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
deleted file mode 100644
index e4456f8b19ccf0cbc73e2b5bb4d6044aa310906e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
+++ /dev/null
@@ -1,62 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xsdps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SD_0_DEVICE_ID,
- XPAR_PS7_SD_0_BASEADDR,
- XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
- XPAR_PS7_SD_0_HAS_CD,
- XPAR_PS7_SD_0_HAS_WP,
- XPAR_PS7_SD_0_BUS_WIDTH,
- XPAR_PS7_SD_0_MIO_BANK,
- XPAR_PS7_SD_0_HAS_EMIO,
- XPAR_PS7_SD_0_IS_CACHE_COHERENT
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
deleted file mode 100644
index c63d8f62afe518b28b3a3fadbeb820a323d9ee81..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
+++ /dev/null
@@ -1,1301 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_5
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/* @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/* @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
-#define XSDPS_CC_MAX_DIV_CNT 256U
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
-#define XSDPS_CC_EXT_DIV_SHIFT 6U
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U
-#define XSDPS_CC_DIV_SHIFT 8U
-
-/* @} */
-
-/** @name SD Interrupt Registers
- *
- * <b> Normal and Error Interrupt Status Register </b>
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * <b> Normal and Error Interrupt Status Enable Register </b>
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * <b> Normal and Error Interrupt Signal Enable Register </b>
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/* @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/* @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/* @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/* @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/* @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/* @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/* @} */
-
-/** @name Maximum Current Capablities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/* @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/* @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/* @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/* @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/* @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/* @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U
-#define XSDPS_HC_SPEC_V2 0x0001U
-#define XSDPS_HC_SPEC_V1 0x0000U
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U
-
-/* @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/* @} */
-
-/* Card Interface Conditions Definitions */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-
-/* Operation Conditions Register Definitions */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-
-/* SD Card Configuration Register Definitions */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-
-/* Card Status Register Definitions */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-
-/* Switch Function Definitions CMD6 */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-
-/* EXT_CSD field definitions */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/* @} */
-
-/* @400KHz, in usec */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
-#define XSDPS_CARD_DEF_ADDR 0x1234U
-
-#define XSDPS_CARD_SD 1U
-#define XSDPS_CARD_MMC 2U
-#define XSDPS_CARD_SDIO 3U
-#define XSDPS_CARD_SDCOMBO 4U
-#define XSDPS_CHIP_EMMC 5U
-
-
-/** @name ADMA2 Descriptor related definitions
- *
- * ADMA2 Descriptor related definitions
- * @{
- */
-
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/* @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U
-#define XSDPS_SCR_BLKSIZE 8U
-#define XSDPS_1_BIT_WIDTH 0x1U
-#define XSDPS_4_BIT_WIDTH 0x2U
-#define XSDPS_8_BIT_WIDTH 0x3U
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
-#define XSDPS_HIGH_SPEED_MODE 0x5U
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U
-#define XSDPS_HS200_MODE 0x7U
-#define XSDPS_DDR52_MODE 0x4U
-#define XSDPS_SWITCH_CMD_BLKCNT 1U
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
-#define XSDPS_TUNING_CMD_BLKCNT 1U
-#define XSDPS_TUNING_CMD_BLKSIZE 64U
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
-
-#define SD_DRIVER_TYPE_B 0x01U
-#define SD_DRIVER_TYPE_A 0x02U
-#define SD_DRIVER_TYPE_C 0x04U
-#define SD_DRIVER_TYPE_D 0x08U
-#define SD_SET_CURRENT_LIMIT_200 0U
-#define SD_SET_CURRENT_LIMIT_400 1U
-#define SD_SET_CURRENT_LIMIT_600 2U
-#define SD_SET_CURRENT_LIMIT_800 3U
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U
-/*
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U
-
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-
-#define XSDPS_SLOT_REM 0U
-#define XSDPS_SLOT_EMB 1U
-
-#define XSDPS_WIDTH_8 8U
-#define XSDPS_WIDTH_4 4U
-
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-
-#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD0_ITAPDLYSEL_SD50 0x00000014U
-#define SD0_OTAPDLYSEL_SD50 0x00000003U
-#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD0_ITAPDLYSEL_HSD 0x00000015U
-#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
-
-#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
-#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
-#define SD1_ITAPDLYSEL_SD50 0x00140000U
-#define SD1_OTAPDLYSEL_SD50 0x00030000U
-#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
-#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
-#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
-#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
-#define SD1_ITAPDLYSEL_HSD 0x00150000U
-#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
-#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
-
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64
-#define XSdPs_Out64 Xil_Out64
-
-#define XSdPs_In32 Xil_In32
-#define XSdPs_Out32 Xil_Out32
-
-#define XSdPs_In16 Xil_In16
-#define XSdPs_Out16 Xil_Out16
-
-#define XSdPs_In8 Xil_In8
-#define XSdPs_Out8 Xil_Out8
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
deleted file mode 100644
index 4894754ad9c829e47c411d85cf3050fce92d1e16..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
+++ /dev/null
@@ -1,1760 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_options.c
-* @addtogroup sdps_v3_5
-* @{
-*
-* Contains API's for changing the various options in host and card.
-* See xsdps.h for a detailed description of the device and driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* vns 03/13/17 Fixed MISRAC mandatory violation
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
-* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
-* settings
-* mn 08/17/17 Added CCI support for A53 and disabled data cache
-* operations when it is enabled.
-* mn 08/22/17 Updated for Word Access System support
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps.h"
-#include "sleep.h"
-#if defined (__aarch64__)
-#include "xil_smc.h"
-#endif
-/************************** Constant Definitions *****************************/
-#define UHS_SDR12_SUPPORT 0x1U
-#define UHS_SDR25_SUPPORT 0x2U
-#define UHS_SDR50_SUPPORT 0x4U
-#define UHS_SDR104_SUPPORT 0x8U
-#define UHS_DDR50_SUPPORT 0x10U
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
-void XSdPs_SetTapDelay(XSdPs *InstancePtr);
-static void XSdPs_DllReset(XSdPs *InstancePtr);
-#endif
-
-extern u16 TransferMode;
-/*****************************************************************************/
-/**
-* Update Block size for read/write operations.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkSize - Block size passed by the user.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
-{
- s32 Status;
- u32 PresentStateReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
-
- if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
- (u32)XSDPS_PSR_INHIBIT_DAT_MASK |
- (u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- /* Set block size to the value passed */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize & XSDPS_BLK_SIZE_MASK);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to get bus width support by card.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param SCR - buffer to store SCR register returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
-{
- s32 Status;
- u32 StatusReg;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
- SCR[LoopCnt] = 0U;
- }
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SCR_BLKCNT;
- BlkSize = XSDPS_SCR_BLKSIZE;
-
- /* Set block size to the value passed */
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
-
- TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set bus width to 4-bit in card and host
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 StatusReg;
- u32 Arg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- /*
- * check for bus width for 3.0 controller and return if
- * bus width is <4
- */
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
- 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
-
- Arg = ((u32)InstancePtr->BusWidth);
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
- && (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
- /* in case of eMMC data width 8-bit */
- InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
- } else {
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- }
-
- if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
- if (InstancePtr->Mode == XSDPS_DDR52_MODE)
- Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
- else
- Arg = XSDPS_MMC_8_BIT_BUS_ARG;
- } else {
- if (InstancePtr->Mode == XSDPS_DDR52_MODE)
- Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
- else
- Arg = XSDPS_MMC_4_BIT_BUS_ARG;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer complete */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
- }
-
- usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
- StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET);
-
- /* Width setting in controller */
- if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
- StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
- } else {
- StatusReg |= XSDPS_HC_WIDTH_MASK;
- }
-
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- (u8)StatusReg);
-
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
- StatusReg |= InstancePtr->Mode;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, StatusReg);
- }
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to get bus speed supported by card.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store function group support data
-* returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u32 StatusReg;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
- TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- Arg = XSDPS_SWITCH_CMD_HS_GET;
-
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set high speed in card and host. Changes clock in host accordingly.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 StatusReg;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- u8 ReadBuff[64] = {0U};
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
-
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
- }
-
- TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- Arg = XSDPS_SWITCH_CMD_HS_SET;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- /* Change the clock frequency to 50 MHz */
- InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- } else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
- Arg = XSDPS_MMC_HIGH_SPEED_ARG;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /*
- * Write to clear error bits
- */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /*
- * Write to clear bit
- */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- /* Change the clock frequency to 52 MHz */
- InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
- Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- if (InstancePtr->Mode == XSDPS_HS200_MODE) {
- Arg = XSDPS_MMC_HS200_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
- } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Arg = XSDPS_MMC_HIGH_SPEED_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
- } else {
- Arg = XSDPS_MMC_HIGH_SPEED_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /*
- * Write to clear error bits
- */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /*
- * Write to clear bit
- */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_HS200_MODE) {
- Status = XSdPs_Execute_Tuning(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
- StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET);
- StatusReg |= XSDPS_HC_SPEED_MASK;
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to change clock freq to given value.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param SelFreq - Clock frequency in Hz.
-*
-* @return None
-*
-* @note This API will change clock frequency to the value less than
-* or equal to the given value using the permissible dividors.
-*
-******************************************************************************/
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
-{
- u16 ClockReg;
- u16 DivCnt;
- u16 Divisor = 0U;
- u16 ExtDivisor;
- s32 Status;
- u16 ReadReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Disable clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
- (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
- /* Program the Tap delays */
- XSdPs_SetTapDelay(InstancePtr);
-#endif
- /* Calculate divisor */
- for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
- if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
- Divisor = DivCnt >> 1;
- break;
- }
- }
-
- if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
- /* No valid divisor found for given frequency */
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- /* Calculate divisor */
- DivCnt = 0x1U;
- while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
- if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
- Divisor = DivCnt / 2U;
- break;
- }
- DivCnt = DivCnt << 1U;
- }
-
- if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
- /* No valid divisor found for given frequency */
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- /* Set clock divisor */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
- XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
-
- ExtDivisor = Divisor >> 8;
- ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
- ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
-
- Divisor <<= XSDPS_CC_DIV_SHIFT;
- Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
- ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
- ClockReg);
- } else {
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
-
- Divisor <<= XSDPS_CC_DIV_SHIFT;
- Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
- ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
- ClockReg);
- }
-
- /* Wait for internal clock to stabilize */
- ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
- ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);;
- }
-
- /* Enable SD clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET,
- ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to send pullup command to card before using DAT line 3(using 4-bit bus)
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Pullup(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to get EXT_CSD register of eMMC.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store EXT_CSD
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u32 StatusReg;
- u32 Arg = 0U;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
- BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
- }
-
- TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- /* Send SEND_EXT_CSD command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* API to write EXT_CSD register of eMMC.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param Arg is the argument to be sent along with the command
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
-{
- s32 Status;
- u32 StatusReg;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /*
- * Write to clear error bits
- */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-/*****************************************************************************/
-/**
-*
-* API to Identify the supported UHS mode. This API will assign the
-* corresponding tap delay API to the Config_TapDelay pointer based on the
-* supported bus speed.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff contains the response for CMD6
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
-{
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
- InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
- }
- else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
- InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
- }
- else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
- InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
- }
- else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
- InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
- }
- else
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
-}
-
-/*****************************************************************************/
-/**
-*
-* API to UHS-I mode initialization
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param Mode UHS-I mode
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
-{
- s32 Status;
- u16 StatusReg;
- u16 CtrlReg;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- u8 ReadBuff[64] = {0U};
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Drive strength */
-
- /* Bus speed mode selection */
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize);
-
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
-
- if (InstancePtr->Config.IsCacheCoherent == 0) {
- Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
- }
-
- TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
-
- switch (Mode) {
- case 0U:
- Arg = XSDPS_SWITCH_CMD_SDR12_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
- break;
- case 1U:
- Arg = XSDPS_SWITCH_CMD_SDR25_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
- break;
- case 2U:
- Arg = XSDPS_SWITCH_CMD_SDR50_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
- break;
- case 3U:
- Arg = XSDPS_SWITCH_CMD_SDR104_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
- break;
- case 4U:
- Arg = XSDPS_SWITCH_CMD_DDR50_SET;
- InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
- break;
- default:
- Status = XST_FAILURE;
- goto RETURN_PATH;
- break;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
-
- /* Current limit */
-
- /* Set UHS mode in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
- CtrlReg |= Mode;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
-
- /* Change the clock frequency */
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
- (Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
- /* Send tuning pattern */
- Status = XSdPs_Execute_Tuning(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-}
-#endif
-
-static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 BlkSize;
- u16 CtrlReg;
- u8 TuningCount;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
- if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
- {
- BlkSize = BlkSize*2U;
- }
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize);
-
- TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
-
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
-
- /*
- * workaround which can work for 1.0/2.0 silicon for auto tuning.
- * This can be revisited for 3.0 silicon if necessary.
- */
- /* Wait for ~60 clock cycles to reset the tap values */
- (void)usleep(1U);
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- /* Issue DLL Reset to load new SDHC tuned tap values */
- XSdPs_DllReset(InstancePtr);
-#endif
-
- for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
- } else {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
- }
-
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
- break;
- }
-
- if (TuningCount == 31) {
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- /* Issue DLL Reset to load new SDHC tuned tap values */
- XSdPs_DllReset(InstancePtr);
-#endif
- }
- }
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for ~12 clock cycles to synchronize the new tap values */
- (void)usleep(1U);
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
- /* Issue DLL Reset to load new SDHC tuned tap values */
- XSdPs_DllReset(InstancePtr);
-#endif
-
- Status = XST_SUCCESS;
-
- RETURN_PATH: return Status;
-
-}
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-/*****************************************************************************/
-/**
-*
-* API to set Tap Delay for SDR104 and HS200 modes
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
-{
- u32 TapDelay;
- (void) CardType;
-
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- if (DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- if (Bank == 2)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
- (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
- (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
-#else
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- if (Bank == 2)
- TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
- else
- TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
- } else {
-#endif
- (void) DeviceId;
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- if (Bank == 2)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
- (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
- (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
-#else
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- if (Bank == 2)
- TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
- else
- TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- }
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set Tap Delay for SDR50 mode
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
-{
- u32 TapDelay;
- (void) Bank;
- (void) CardType;
-
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- if (DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
- 0, 0, 0, 0, 0);
-#else
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- TapDelay |= SD0_OTAPDLYSEL_SD50;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
- } else {
-#endif
- (void) DeviceId;
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
- 0, 0, 0, 0, 0);
-#else
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- TapDelay |= SD1_OTAPDLYSEL_SD50;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- }
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set Tap Delay for DDR50 mode
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
-{
- u32 TapDelay;
- (void) Bank;
-
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- if (DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
- 0, 0, 0, 0, 0);
- if (CardType== XSDPS_CARD_SD)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
- (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
- (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
- if (CardType == XSDPS_CARD_SD)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
- (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
- (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
-#else
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
- TapDelay |= SD0_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD0_ITAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- if (CardType== XSDPS_CARD_SD)
- TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
- else
- TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD0_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- if (CardType == XSDPS_CARD_SD)
- TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
- else
- TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
- } else {
-#endif
- (void) DeviceId;
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
- 0, 0, 0, 0, 0);
- if (CardType== XSDPS_CARD_SD)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
- (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
- (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
- (u64)0x0, 0, 0, 0, 0, 0);
- if (CardType == XSDPS_CARD_SD)
- Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
- (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
- (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
-#else
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
- TapDelay |= SD1_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD1_ITAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- if (CardType == XSDPS_CARD_SD)
- TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
- else
- TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD1_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- if (CardType == XSDPS_CARD_SD)
- TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
- else
- TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- }
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set Tap Delay for HSD and SDR25 mode
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
-{
- u32 TapDelay;
- (void) Bank;
-
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- if (DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
- if (CardType == XSDPS_CARD_SD)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
- (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
- (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
-#else
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
- TapDelay |= SD0_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD0_ITAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- TapDelay |= SD0_ITAPDLYSEL_HSD;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD0_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- if (CardType == XSDPS_CARD_SD)
- TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
- else
- TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
- } else {
-#endif
- (void) DeviceId;
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD,
- 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
- ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
- if (CardType == XSDPS_CARD_SD)
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
- (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
- else
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
- (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
-#else
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
- TapDelay |= SD1_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD1_ITAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- TapDelay |= SD1_ITAPDLYSEL_HSD;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD1_ITAPCHGWIN;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- if (CardType == XSDPS_CARD_SD)
- TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
- else
- TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
-#endif
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- }
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* API to set Tap Delay w.r.t speed modes
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetTapDelay(XSdPs *InstancePtr)
-{
- u32 DllCtrl, BankNum, DeviceId, CardType;
-
- BankNum = InstancePtr->Config.BankNumber;
- DeviceId = InstancePtr->Config.DeviceId ;
- CardType = InstancePtr->CardType ;
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- if (DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
- (u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
-#else
- DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
- DllCtrl |= SD0_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
- (u64)0x0, 0, 0, 0, 0, 0);
-#else
- DllCtrl &= ~SD0_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- } else {
-#endif
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
- (u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
-#else
- DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
- DllCtrl |= SD1_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
- (u64)0x0, 0, 0, 0, 0, 0);
-#else
- DllCtrl &= ~SD1_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
-#ifdef XPAR_PSU_SD_0_DEVICE_ID
- }
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* API to reset the DLL
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XSdPs_DllReset(XSdPs *InstancePtr)
-{
- u32 ClockReg, DllCtrl;
-
- /* Disable clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
- /* Issue DLL Reset to load zero tap values */
- DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
- if (InstancePtr->Config.DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
- (u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
-#else
- DllCtrl |= SD0_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- } else {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
- (u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
-#else
- DllCtrl |= SD1_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- }
-
- /* Wait for 2 micro seconds */
- (void)usleep(2U);
-
- /* Release the DLL out of reset */
- DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
- if (InstancePtr->Config.DeviceId == 0U) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
- (u64)0x0, 0, 0, 0, 0, 0);
-#else
- DllCtrl &= ~SD0_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- } else {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
- (u64)0x0, 0, 0, 0, 0, 0);
-#else
- DllCtrl &= ~SD1_DLL_RST;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-#endif
- }
-
- /* Wait for internal clock to stabilize */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- }
-
- /* Enable SD clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET,
- ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
-}
-#endif
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
deleted file mode 100644
index 62bbfc0dd970b829313ac73dc643376893e025a5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xsdps_sinit.c
-* @addtogroup sdps_v3_5
-* @{
-*
-* The implementation of the XSdPs component's static initialization
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xstatus.h"
-#include "xsdps.h"
-#include "xparameters.h"
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XSdPs_Config XSdPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xsdps.h for the definition of XSdPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
-{
- XSdPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
- if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XSdPs_ConfigTable[Index];
- break;
- }
- }
- return (XSdPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/Makefile
deleted file mode 100644
index 0f23775de3471f625d6512d03ed2d0aef0eb60fc..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/Makefile
+++ /dev/null
@@ -1,87 +0,0 @@
-###############################################################################
-#
-# Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# Use of the Software is limited solely to applications:
-# (a) running on a Xilinx device, or
-# (b) that interact with a Xilinx device through a bus or interconnect.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-#
-# Except as contained in this notice, the name of the Xilinx shall not be used
-# in advertising or otherwise to promote the sale, use or other dealings in
-# this Software without prior written authorization from Xilinx.
-#
-###############################################################################
-
-include config.make
-
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
-ECC_FLAGS += -nostartfiles\
- -march=armv7-a \
- -mfloat-abi=soft \
- -mfpu=neon
-endif
-
-ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
-ECC_FLAGS += -nostartfiles
-endif
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))
-INCLUDEFILES=*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(LIBSOURCES)
- echo "Compiling standalone"
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
- $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
-
-profile_libs:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
-
-.PHONY: include
-include: standalone_includes profile_includes
-
-standalone_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-profile_includes:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
deleted file mode 100644
index cf598882be91ac2d785f8bd8d3dc757b308ac775..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <unistd.h>
-#include "xil_types.h"
-
-/* _exit - Simple implementation. Does not return.
-*/
-__attribute__((weak)) void _exit (sint32 status)
-{
- (void)status;
- while (1) {
- ;
- }
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
deleted file mode 100644
index a108b771620def28d60cda4cd26204429a2a9a18..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#ifndef UNDEFINE_FILE_OPS
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
-}
-#endif
-
-/*
- * _open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
deleted file mode 100644
index 967bdfc5b0cca4d2143f41a804cdc5a716e75edd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <sys/types.h>
-#include "xil_types.h"
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) caddr_t _sbrk ( s32 incr );
-}
-#endif
-
-__attribute__((weak)) caddr_t _sbrk ( s32 incr )
-{
- static u8 *heap = NULL;
- u8 *prev_heap;
- static u8 *HeapEndPtr = (u8 *)&_heap_end;
- caddr_t Status;
-
- if (heap == NULL) {
- heap = (u8 *)&_heap_start;
- }
- prev_heap = heap;
-
- if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
- heap += incr;
- Status = (caddr_t) ((void *)prev_heap);
- } else {
- Status = (caddr_t) -1;
- }
-
- return Status;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
deleted file mode 100644
index e8988c04818685c56287b2de514e6c96cc2d6cb4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <stdlib.h>
-#include <unistd.h>
-
-/*
- * abort -- go out via exit...
- */
-__attribute__((weak)) void abort(void)
-{
- _exit(1);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S
deleted file mode 100644
index 1752548d73bcd9ba920579f417180fd06bf8ea7e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S
+++ /dev/null
@@ -1,198 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.s
-*
-* This file contains the initial vector table for the Cortex A9 processor
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Save lr when profiling is enabled
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.00a pkp 22/01/14 Modified return addresses for interrupt
-* handlers (DataAbortHandler and SVCHandler)
-* to fix CR#767251
-* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-* abort and prefetch abort into DataAbortAddr and
-* PrefetchAbortAddr for further use to fix CR#854523
-* 5.4 pkp 12/03/15 Added handler for undefined exception
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xil_errata.h"
-
-#define __ARM_NEON__ 1
-
-.org 0
-.text
-
-.globl _vector_table
-
-.section .vectors
-_vector_table:
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler: /* IRQ vector handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
-#ifdef __ARM_NEON__
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-#ifdef PROFILING
- ldr r2, =prof_pc
- subs r3, lr, #0
- str r3, [r2]
-#endif
-
- bl IRQInterrupt /* IRQ vector */
-
-#ifdef __ARM_NEON__
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
-
- subs pc, lr, #4 /* adjust return */
-
-
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-#ifdef __ARM_NEON__
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
-
-#ifdef __ARM_NEON__
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
-
- bl SWInterrupt /* SWInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr /*return to the next instruction after the SWI instruction */
-
-
-DataAbortHandler: /* Data Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
-
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
-
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
-
-.end
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S
deleted file mode 100644
index 5dfe5c2e74410aa368f16a6a053523a5e390a4d5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S
+++ /dev/null
@@ -1,496 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
-* @{
-* <h2> boot.S </h2>
-* The boot code performs minimum configuration which is required for an
-* application to run starting from processor's reset state. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 5. Enable data cache, instruction cache and MMU
-* 6. Enable Floating point unit
-* 7. Transfer control to _start which clears BSS sections, initializes
-* global timer and runs global constructor before jumping to main
-* application
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-* register settings.
-* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-* register settings.
-* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
-* performance. Changed the property of the ".boot"
-* section.
-* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
-* Register settings
-* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
-* value of 0x00020202. Fix for CR 697094 (SI#687034).
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
-* MMU is enabled
-* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-* caches and TLB, enable MMU and caches, then enable SMP
-* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-* is done later.
-* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
-* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-* attempt to enable dual core behavior on single cpu zynq-7000s
-* devices is prevented from corrupting system behavior.
-* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
-* zynq-7000s devices
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
-.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
-.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
-.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
-.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
-.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
-.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
-.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
-
-.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
-.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
-
-/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
-.if SIM_MODE == 1
-.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
-.else
-.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
-.endif
-
-.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
-
-.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
- Event monitor bus enable and Way Size (64 KB) */
-.set L2CCControl, 0x01 /* Enable L2CC */
-.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
-.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
-
-.set SLCRlockKey, 0x767B /* SLCR lock key */
-.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
-.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-#if XPAR_CPU_ID==0
- /* only allow cpu0 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
- EndlessLoop0:
- wfe
- b EndlessLoop0
-
-CheckEFUSE:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
-
- /* single core device, reset cpu1 */
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] /* Read CPU Software Reset Control register */
- orr r1,r1,#0x22
- str r1,[r0] /* Reset CPU1 */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
-#elif XPAR_CPU_ID==1
- /* only allow cpu1 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
- EndlessLoop1:
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /*invalidate scu*/
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-#ifdef SHAREABLE_DDR
- /* Mark the entire DDR memory as shareable */
- ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
- ldr r0, =TblBase /* MMU Table address in memory */
- ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-shareable_loop:
- str r2, [r0] /* write the entry to MMU table */
- add r0, r0, #0x4 /* next entry in the table */
- add r2, r2, #0x100000 /* next section */
- subs r3, r3, #1
- bge shareable_loop /* loop till 1G is covered */
-#endif
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /*set scu enable bit in scu*/
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- /* enable MMU and cache */
-
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
-
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- ldr r0,=CRValMmuCac
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- dsb /* dsb allow the MMU to start up */
- isb /* isb flush prefetch buffer */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- orr r0, r0, #(0x01 << 6) /* set SMP bit */
- orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Invalidate L2 Cache and enable L2 Cache*/
-/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- mov r1, #0 /* force the disable bit */
- str r1, [r0] /* disable the L2 Caches */
-
- ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
- ldr r1,[r0] /* read the register */
- ldr r2,=L2CCAuxControl /* set the default bits */
- orr r1,r1,r2
- str r1, [r0] /* store the Aux Control Register */
-
- ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
- ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
- str r1, [r0] /* store the TAG Latency register Register */
-
- ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
- ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
- str r1, [r0] /* store the Data Latency register Register */
-
- ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
- ldr r2, =0xFFFF
- str r2, [r0] /* force invalidate */
-
- ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
- /* Load L2CC base address base + sync register*/
- /* poll for completion */
-Sync: ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw /* clear pending interrupts */
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
- ldr r1,=SLCRL2cRamConfig /* set the configuration value */
- str r1, [r0] /* store the L2c Ram Control Register */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- ldr r1,[r0] /* read the register */
- mov r2, #L2CCControl /* set the enable bit */
- orr r1,r1,r2
- str r1, [r0] /* enable the L2 Caches */
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- fmrx r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- fmxr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _start /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A9, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* swith back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
deleted file mode 100644
index 7859b0eef626654613361272366cfb818a2a0bab..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
+++ /dev/null
@@ -1,45 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H /* prevent circular inclusions */
-#define BSPCONFIG_H /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-#endif /*end of __BSPCONFIG_H_*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
deleted file mode 100644
index 0dab3e943010e6772ebd9511da2c5988a4b81dcf..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
+++ /dev/null
@@ -1,549 +0,0 @@
-/*****************************************************************************
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ---------------------------------------------------
- * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
- * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
- * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
- * cacheable regions
- * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
- * generated by the cpu driver, for enabling caches
- * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
- * write-thru caches
- * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
- * Updated the MMU table to mark OCM in high address space
- * as inner cacheable and reserved space as Invalid
- * 3.03a sdm 08/20/11 Changes to support FreeRTOS
- * Updated the MMU table to mark upper half of the DDR as
- * non-cacheable
- * Setup supervisor and abort mode stacks
- * Do not initialize/enable L2CC in case of AMP
- * Initialize UART1 for 9600bps in case of AMP
- * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
- * in case of AMP
- * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
- * counters
- * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
- * xparameters.h file for CR630532 - Xil_DCacheFlush()/
- * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
- * for MicroBlaze will invalidate data in the cache instead
- * of flushing it for writeback caches
- * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
- * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
- * Remove redundant dsb/dmb instructions in cache maintenance
- * APIs
- * Remove redundant dsb in mcr instruction
- * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
- * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
- * driver tcl in xparameters.h. Update the gcc/translationtable.s
- * for the QSPI complete address range - DT644567
- * Removed profile directory for armcc compiler and changed
- * profiling setting to false in standalone_v2_1_0.tcl file
- * Deleting boot.S file after preprocessing for armcc compiler
- * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
- * invalidate the caches before enabling back the MMU and
- * D cache.
- * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
- * xil_mmu.c. Now we invalidate UTLB, Branch predictor
- * array, flush the D-cache before changing the attributes
- * in translation table. The user need not call Xil_DisableMMU
- * before calling Xil_SetTlbAttributes.
- * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
- * sgd initialization is present. Changes for this were done in
- * uart.c and xil-crt0.s.
- * Made changes in xil_io.c to use volatile pointers.
- * Made changes in xil_mmu.c to correct the function
- * Xil_SetTlbAttributes.
- * Changes are made xil-crt0.s to initialize the static
- * C++ constructors.
- * Changes are made in boot.s, to fix the TTBR settings,
- * correct the L2 Cache Auxiliary register settings, L2 cache
- * latency settings.
- * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
- * sgd usleep.c to use global timer intstead of CP15.
- * Made changes in cortexa9/gcc/translation_table.s to map
- * the peripheral devices as shareable device memory.
- * Made changes in cortexa9/gcc/xil-crt0.s to initialize
- * the global timer.
- * Made changes in cortexa9/armcc/boot.S to initialize
- * the global timer.
- * Made changes in cortexa9/armcc/translation_table.s to
- * map the peripheral devices as shareable device memory.
- * Made changes in cortexa9/gcc/boot.S to optimize the
- * L2 cache settings. Changes the section properties for
- * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
- * and cortexa9/gcc/translation_table.S.
- * Made changes in cortexa9/xil_cache.c to change the
- * cache invalidation order.
- * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
- * compilation/linking issues for C++ compiler.
- * Made changes in mb_interface.h to remove compilation/
- * linking issues for C++ compiler.
- * Added macros for swapb and swaph microblaze instructions
- * mb_interface.h
- * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
- * for CortexA9.
- * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
- * 3.07a asa 08/31/12 Added xil_printf.h include
- * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
- * Corrected L2 cache sequence disable sequence
- * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
- * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
- * irq/fiq handling.
- * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
- * fixes the CR #692094.
- * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
- * 3.10a srt 04/18/13 Implemented ARM Erratas.
- * Cortex A9 Errata - 742230, 743622, 775420, 794073
- * L2Cache PL310 Errata - 588369, 727915, 759370
- * Please refer to file 'xil_errata.h' for errata
- * description.
- * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
- * cache APIs were corresponding to only Layer 1 cache
- * memories. New APIs were now added and the existing cache
- * related APIs were changed to provide a uniform interface
- * to flush/invalidate/enable/disable the complete cache
- * system which includes both L1 and L2 caches. The changes
- * for these were done in:
- * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
- * files.
- * Four new files were added for supporting L2 cache. They are:
- * microblaze_flush_cache_ext.S-> Flushes L2 cache
- * microblaze_flush_cache_ext_range.S -> Flushes a range of
- * memory in L2 cache.
- * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
- * microblaze_invalidate_cache_ext_range -> Invalidates a
- * range of memory in L2 cache.
- * These changes are done to implement PR #697214.
- * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
- * fix the CR #706464. L2 cache disabling happens independent
- * of L1 data cache disable operation. Changes are done in the
- * same file in cache handling APIs to do a L2 cache sync
- * (poll reg7_?cache_?sync). This fixes CR #700542.
- * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
- * interrupts for ARM. These are done to fix the CR#699680.
- * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
- * sync operation. This fixes the CR# 716781.
- * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
- * for armcc toolchain.
- * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
- * fix issues related to NEON context saving. The assembly
- * routines for IRQ and FIQ handling are modified.
- * Deprecated the older BSP (3.10a).
- * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
- * various potential issues. Made changes in the function
- * Xil_SetAttributes in file xil_mmu.c.
- * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
- * in src\cortexa9 and src\microblaze folders.
- * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
- * L2 cache sync operation and to fix issues around complete
- * L2 cache flush/invalidation by ways.
- * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
- * to fix linking issues with armcc/DS-5. Modified the armcc
- * makefile to fix issues.
- * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
- * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
- * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
- * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
- * src\cortexa9\armcc\) to fix CR#767251
- * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
- * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
- * Few cache lines were missed to invalidate when unaligned address
- * invalidation was accommodated in Xil_DCacheInvalidateRange.
- * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
- * stack memory (which contains return address) was invalidated. So
- * stack memory is flushed first and then L1D cache is invalidated.
- * This is done to fix CR #763829
- * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
- * mblaze_nt_types.h file and replace uint32_t with u32 in the
- * profile_hist.c to fix the above CR.
- * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
- * instead of libxil.a and added prototypes for
- * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
- * mb_interface.h
- * 4.1 hk 04/18/14 Add sleep function.
- * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
- * some of the *.s files inMB BSP source to *.S.
- * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
- * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
- * CR#794205
- * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
- * common/xil_testcache.c
- * Fix for CR#764881.
- * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
- * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
- * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
- * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
- * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
- * cortexa9/armcc/boot.s. Added default exception handlers for data
- * abort and prefetch abort using handlers called
- * DataAbortHandler and PrefetchAbortHandler respectively in
- * cortexa9/xil_exception.c to fix CR#802862.
- * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
- * issue of improper linking of translation_table.s
- * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
- * in tool chain to avoid conflicts into some special cases
- * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
- * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
- * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
- * containing type def u32 defined in xil_types.g to resolve issue of
- * CR#805869
- * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
- * it is not possible to generate timer in nanosecond due to limited
- * cpu frequency
- * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
- * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
- * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
- * removed function definition of XSmc_NorInit and XSmc_NorInit from
- * cortexa9/smc.h
- * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
- * cache_ext_range declarations in mb_interface.h CR#783821.
- * Modified profile_mcount_mb.S to fix CR#808412.
- * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
- * cortexa9/iccarm to fix CR#816701
- * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
- * armcc/translation_table.s and iccarm/translation_table.s
- * to properly defined reserved entries according to address map for
- * fixing CR#820146
- * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
- * and cortexa9/armcc/translation_table.s to resolve compilation
- * error for solving CR#822897
- * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
- * MISRA-C:2012 compliance.
- * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
- * adding src/common/xplatform_info.*s
- * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
- * removed incorrect initialization of TLB lockdown register to fix
- * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
- * and iccarm/boot.s
- * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
- * for iccarm and armcc compiler of cortexA9
- * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
- * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
- * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
- * of L2Cache is done later.
- * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
- * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
- * taking long time to fix CR#853097. L2CacheSync is added into
- * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
- * Xil_L2CacheInvalidate APIs are modified to flush the complete stack
- * instead of just System Stack
- * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
- * to update ECC_FLAGS and also take the compiler and archiver as specified
- * in settings instead of hardcoding it.
- * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
- * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
- * accordingly generate the translation table
- * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
- * to update ECC_FLAGS to fix a bug introduced during new version creation
- * of BSP.
- * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
- * functionalities are avoided for the OpenAMP slave application(when
- * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
- * cache for its operation. Also file operations such as read, write,
- * close, open are also avoided for OpenAMP support(when USE_AMP flag is
- * defined for BSP) because XilOpenAMP library contains own file operation.
- * The xil-crt0.S file is modified for not initializing global timer for
- * OpenAMP application as it might be already in use by master CPU
- * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
- * definition for dsb, isb and dmb to fix the compilation error when used
- * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
- * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
- * R5 deadlock for errata 780125
- * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
- * 32 bit BSP in the initialization
- * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
- * for XOcm_Remap function
- * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
- * for XOcm_Remap function
- * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
- * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
- * required for MISRA-C:2012 Compliance.
- * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
- * in cortexa9/xil_mmu.h
- * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
- * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
- * checking the current executing platform
- * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
- * to initialize global constructor for C++ applications
- * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
- * C++ applications
- * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
- * translation_table.S to update the translation table according to proper
- * address map
- * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
- * address map
- * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
- * equivalent to vector table base address
- * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
- * as per the toolchain update
- * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
- * for Cortex-A53 32bit mode
- * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
- * and usleep.c to correct routines to avoid hardcoding the timer frequency,
- * instead take it from xparameters.h to properly configure the timestamp
- * clock frequency
- * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
- * new instructions for MB address extension feature
- * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
- * system monitor.
- * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
- * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
- * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
- * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
- * use set of assembly instructions to provide required delay to fix
- * CR#913249.
- * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
- * _exit with exit. We should not be directly calling _exit and should
- * always use the library exit. This fixes the CR#937036.
- * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
- * registers, banked registers for various modes and enabled
- * the cache ECC check before enabling the fault log for lock step mode
- * Also modified the cortexr5/gcc/Makefile to support floating point
- * registers initialization in boot code.
- * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
- * logic in case of lock-step mode when fault log is enabled to fix
- * CR#938281
- * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
- * header file instrinsics.h which contains assembly instructions
- * definitions which can be used by C
- * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
- * proto for all print.c across the BSPs. This patch fixes CR#938738.
- * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
- * interrupts when sleep/usleep is being executed using assembly
- * instructions to fix CR#913249.
- * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
- * instead modified cortexr5/sleep.c and usleep.c to poll the counter
- * value and compare it with previous value to detect the overflow
- * to fix CR#940209.
- * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
- * the fault log to avoid intervention for lock-step mode and cortexr5/
- * _exit.c to enable the dbg_lpd_reset once the fault log is disabled
- * to fix CR#947335
- * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
- * in lock-step to avoid resetting the debug logic which restricts the
- * access for debugger and removed enabling back of debug modules in
- * cortexr5/_exit.c
- * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
- * read buffer is filled and removed the redundant NULL checking for
- * buffer to simplify the code
- * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
- * to return correct number of bytes when read buffer is filled and
- * removed the redundant NULL checking for buffer to simplify the code
- * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
- * read buffer is filled and removed the redundant NULL checking for
- * buffer to simplify the code
- * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
- * instruction macros to disable certain optimizations which may move
- * code out of loops if optimizers believe that the code will always
- * return the same result or discard asm statements if optimizers
- * determine there is no need for the output variables
- * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
- * starts the timer if it is disabled and modified XTime_GetTime to
- * enable the timer if it is not enabled. Also modified cortexa53/64bit/
- * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
- * disabled and read the counter value directly from register instead
- * of using XTime_GetTime for optimization
- * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
- * starts the timer if it is disabled and modified XTime_GetTime to
- * enable the timer if it is not enabled. Also modified cortexa53/32bit/
- * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
- * disabled and read the counter value directly from register instead
- * of using XTime_GetTime for optimization
- * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
- * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
- * Xil_DCacheInvalidateRange functions description for proper
- * explaination to fix CR#949801
- * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
- * file mb_interface.h. This fixes the CR#949503.
- * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
- * memory is not included for MicroBlaze.
- * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
- * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
- * the issue of lr being corrupted to resolve CR#950468
- * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
- * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
- * the issue of lr being corrupted to resolve CR#950468
- * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
- * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
- * section since it is part of boot process to fix CR#949555
- * hk 07/12/16 Correct masks for IOU SLCR GEM registers
- * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
- * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
- * the accuracy of MB sleep functionality. This fixes the CR#954191.
- * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
- * Source code directories specific to ARM processor's are moved to src/arm
- * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
- * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
- * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
- * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
- * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
- * into common file each and consolidated files are kept at src/arm/common directory.
- * GCC source files related to file operations are consolidated and kept
- * at src/arm/common/gcc directory.
- * All io interfacing functions (i.e. All variants of xil_out, xil_in )
- * are made as static inline and implementation is kept in consolidated common/xil_io.h,
- * xil_io.h must be included as a header file to access io interfacing functions.
- * Added undefined exception handler for A53 32 bit and R5 processor
- * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
- * TTC counter value register is read only.
- * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
- * the CR#956899.
- * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
- * in cortexr5/xparameters_ps.h
- * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
- * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
- * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
- * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
- * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
- * these APIs and modifications are done on top of it to handle stdout/stdin
- * parameters for design which doesnt have UART.It fixes CR#953681
- * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy
- * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
- * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
- * and rest of the memory in that 32GB region is marked as reserved to avoid
- * any speculative access
- * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified
- * asm_vectors.S to implement lazy floating point context saving i.e. floating point
- * access is enabled if there is any floating point operation, it is disabled by
- * default. Also FPU is initally disabled for IRQ and none of the floating point
- * registers are saved during normal context saving. If IRQ handler does not require
- * floating point operation, the floating point registers are untouched and no need
- * for saving/restoring. If IRQ handler uses any floating point operation, then floating
- * point registers are saved and FPU is enabled for IRQ handler. Then floating point
- * registers are restored back after servicing IRQ during normal context restoring.
- * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
- * target.It fixes the CR#966900
- * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
- * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
- * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
- * as false i.e. default bsp is EL3.
- * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
- * contains initial status of FPU i.e. disabled. In case of a warm restart execution
- * when bss sections are not cleared, it may contain previously updated value which
- * does not hold true once processor resumes. This fixes CR#966826.
- * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
- * D caches and then disables it. The problem with that is,
- * potentially there will be a small window after the cache
- * flush operation and before the we disable D caches where
- * we might have valid data in cache lines. In such a
- * scenario disabling the D cache can lead to unknown behavior.
- * The ideal solution to this is to use assembly code for
- * the complete API and avoid any memory accesses. But with
- * that we will end up having a huge amount on assembly code
- * which is not maintainable. Changes are done to use a mix
- * of assembly and C code. All local variables are put in
- * registers. Also function calls are avoided in the API to
- * avoid using stack memory.
- * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
- * scenarios when an invalidated cache line can get pre fetched to cache.
- * If that happens, the coherency between cache and memory is lost
- * resulting in lost data. To avoid this kind of issue either
- * user has to use dsb() or disable pre-fetching for L1 cache
- * or else reduce maximum number of outstanding data prefetches allowed.
- * Using dsb() while comparing data costing more performance compared to
- * disabling pre-fetching/reducing maximum number of outstanding data
- * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
- * to disable pre-fetching/configure maximum number of outstanding data
- * prefetches allowed in L1 cache system.This fixes CR#967864.
- * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
- * used by cortex-A53 64bit EL1 Non-secure application.
- * 6.2 kvn 03/03/17 Added support thumb mode
- * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
- * It fixes CR#970543
- * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
- * profiling we see a crash. That is because the the tcl uses invalid
- * HSI command. This change fixes it.
- * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
- * any FPD peripheral is configured to use CCI.It fixes CR#972638
- * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
- * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
- * the HW coherency enablement. It fixes the CR#973287
- * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
- * L2CTLR_EL1 register. It fixes the CR#974698
- * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
- * of ARM 32 bit processor's.
- * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
- * snippet, which checks for the FPEN bit of CPACR_EL1 register.
- * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
- * XGetPSVersion_Info function for PMUFW.
- * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
- * function for PMUFW.
- * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
- * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
- * operations.Now,VFP is being enabled in FPEXC register, through boot code
- * and FPU registers are being saved/restored when irq/fiq vector is invoked.
- * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
- * if h/w design configured with HPC port.
- * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
- * EL1 NS execution. This change has been done to support CCI enabled IP's.
- * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
- * CR#982209.
- * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
- * make RPU MPU handling user-friendly. This also fixes the CR-981028.
- * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
- * version register through SMC call, over EL1 NS mode. This change has been done to
- * support these APIs over EL1 NS mode.
- * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
- * it fixes CR#987464.
- * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
- * It fixes CR#989132.
- * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
- * will use the timer specified by the user to provide delay. A9 and A53 can use
- * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
- * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
- * to support the sleep configuration Added new API's for the Axi timer in
- * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
- * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
- * xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
- * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
- * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
- * or L2 cache only when the respective caches are enabled. This fixes CR-922023.
- * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
- * after writing to cpacr_el1/cptr_el3 registers. It would ensure
- * disabling/enabling of floating-point unit, before any subsequent
- * instruction.
- * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
- * support. Now, xil_printf would use PV console instead of UART in case of
- * hypervisor enabled BSP.
- * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
- * configured with smart interconnect.It fixes CR#990318.
- * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
- * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
- * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
- * CR#995014.
- * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
-* non-JTAG boot mode, when processor is in lockstep configuration.
-* This behavior is restricting application debugging in non-JTAG boot
-* mode. To get rid of this restriction, added new mld parameter
-* "lockstep_mode_debug", to enable/disable debug logic from BSP
-* settings. Now, debug logic can be enabled through BSP settings,
-* by modifying value of parameter "lockstep_mode_debug" as "true".
-* It fixes CR#993896.
- * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
-* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
-* in handling upper DDR addresses.It fixes CR#995581.
-* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
-* in the list of include paths. This change allows applications/BSP
-* files to include .h files in include_ps directory.
-* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
-* results into abort if accessed from EL1 non secure privilege
-* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
-* to avoid CPUACTLR_EL1 access from privile levels other than EL3.
-* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
-* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
-* use UART console, PV console can be enabled by appending
- "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
- *
-* 6.7 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
-* floating point register would be done through newly introduced flag
-* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
-* the -mfpu-abi option in extra compiler flags.. This change has
-* been done to avoid saving/restoring of HW floating point registers,
-* when BSP is not compiled with HW floating point configuration.
-* 6.7 asa 04/26/18 Added API Xil_GetExceptionRegisterHandler for obtaining information
-* on an already registered exception vector.
-* 6.7 asa 05/18/18 Fixed bugss in the API Xil_GetExceptionRegisterHandler.
-*
- *****************************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
deleted file mode 100644
index dbbe0d4fd06f59e1cdd29e8bfa7f6d87db119537..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _close(s32 fd);
-}
-#endif
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-
-__attribute__((weak)) s32 _close(s32 fd)
-{
- (void)fd;
- return (0);
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/config.make b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/config.make
deleted file mode 100644
index 2668199bfdf5ebf427fd279c95c8ece05f0e450f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/config.make
+++ /dev/null
@@ -1,3 +0,0 @@
-LIBSOURCES = *.c *.S
-PROFILE_ARCH_OBJS = profile_mcount_arm.o
-LIBS = standalone_libs
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S
deleted file mode 100644
index 2b4048f3b3c89234397b7bb51bd539007cccb537..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.s
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
-* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
-* register to fix CR#830580
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
- .text
- .global __cpu_init
- .align 2
-__cpu_init:
-
-/* Clear cp15 regs with unknown reset values */
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 /* DFSR */
- mcr p15, 0, r0, c5, c0, 1 /* IFSR */
- mcr p15, 0, r0, c6, c0, 0 /* DFAR */
- mcr p15, 0, r0, c6, c0, 2 /* IFAR */
- mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
- mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
- mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
-
-/* Reset and start Cycle Counter */
- mov r2, #0x80000000 /* clear overflow */
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd /* D, C, E */
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 /* enable cycle counter */
- mcr p15, 0, r2, c9, c12, 1
-
- bx lr
-
-.end
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
deleted file mode 100644
index df0218e865194a13e2fec8e1bca030fb2d8574ad..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/* The errno variable is stored in the reentrancy structure. This
- function returns its address for use by the macro errno defined in
- errno.h. */
-
-#include <errno.h>
-#include <reent.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 * __errno (void);
-}
-#endif
-
-__attribute__((weak)) sint32 *
-__errno (void)
-{
- return &_REENT->_errno;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
deleted file mode 100644
index e58221a14039f3333e6512081f8e69b9f0e7ab6d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <stdio.h>
-#include "xil_types.h"
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
-{
- (void)fd;
- (void)cmd;
- (void)arg;
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
deleted file mode 100644
index c5a31f31ba16956a039eb9f88817541bf55d76a1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <sys/stat.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
-}
-#endif
-/*
- * fstat -- Since we have no file system, we just return an error.
- */
-__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
-{
- (void)fd;
- buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
-
- return (0);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
deleted file mode 100644
index d02df5ce2eaaf24db17fc25ec219bb53ec1cc625..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "xil_types.h"
-/*
- * getpid -- only one process, so just return 1.
- */
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _getpid(void);
-}
-#endif
-
-__attribute__((weak)) s32 getpid(void)
-{
- return 1;
-}
-
-__attribute__((weak)) s32 _getpid(void)
-{
- return 1;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
deleted file mode 100644
index 0036459e40288e21e8d2017d9d8aee0e43a40a76..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
+++ /dev/null
@@ -1,14 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-char inbyte(void);
-#ifdef __cplusplus
-}
-#endif
-
-char inbyte(void) {
- return XUartPs_RecvByte(STDIN_BASEADDRESS);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
deleted file mode 100644
index f142515110adffb71ef1c92aa10925066ce61ef5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#include <unistd.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _isatty(sint32 fd);
-}
-#endif
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- * returns 0 if not. Since we're hooked up to a
- * serial port, we'll say yes _AND return a 1.
- */
-__attribute__((weak)) sint32 isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
-
-__attribute__((weak)) sint32 _isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
deleted file mode 100644
index fc2f89d6cc6c9f6194a1a950f7f9e30219c1ea9c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#include <signal.h>
-#include <unistd.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) int _kill(pid_t pid, int sig);
-}
-#endif
-
-/*
- * kill -- go out via exit...
- */
-
-__attribute__((weak)) int kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
-
-__attribute__((weak)) int _kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
deleted file mode 100644
index 106c45c891d86912e4c527e4a735773c0a829a08..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <sys/types.h>
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
-}
-#endif
-/*
- * lseek -- Since a serial port is non-seekable, we return an error.
- */
-__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
-{
- (void)fd;
- (void)offset;
- (void)whence;
- errno = ESPIPE;
- return ((off_t)-1);
-}
-
-__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
-{
- (void)fd;
- (void)offset;
- (void)whence;
- errno = ESPIPE;
- return ((off_t)-1);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
deleted file mode 100644
index 85e9ce4022c5e8dff64f391e7c2a3cadc6d4515e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#ifndef UNDEFINE_FILE_OPS
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
-}
-#endif
-/*
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
deleted file mode 100644
index 8b56036b7677518b290df22d590cdad568fbdad4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
+++ /dev/null
@@ -1,15 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-void outbyte(char c);
-
-#ifdef __cplusplus
-}
-#endif
-
-void outbyte(char c) {
- XUartPs_SendByte(STDOUT_BASEADDRESS, c);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
deleted file mode 100644
index da7e768d0667a158de947e22a46333fa3e146c4f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* print.c -- print a string on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- *
- */
-
-/*
- * print -- do a raw print of a string
- */
-#include "xil_printf.h"
-
-void print(const char8 *ptr)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- XPVXenConsole_Write(ptr);
-#else
-#ifdef STDOUT_BASEADDRESS
- while (*ptr != (char8)0) {
- outbyte (*ptr);
- ptr++;
- }
-#else
-(void)ptr;
-#endif
-#endif
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/Makefile
deleted file mode 100644
index 891fdf64304026ff2b06af604514161fe9f3b2b0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/Makefile
+++ /dev/null
@@ -1,78 +0,0 @@
-###############################################################################
-#
-# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# Use of the Software is limited solely to applications:
-# (a) running on a Xilinx device, or
-# (b) that interact with a Xilinx device through a bus or interconnect.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-#
-# Except as contained in this notice, the name of the Xilinx shall not be used
-# in advertising or otherwise to promote the sale, use or other dealings in
-# this Software without prior written authorization from Xilinx.
-#
-###############################################################################
-#
-# Makefile for profiler
-#
-#######################################################################
-
-# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
-include ../config.make
-
-AS=mb-as
-COMPILER = mb-gcc
-ARCHIVER = mb-ar
-CP = cp
-COMPILER_FLAGS=-O2
-EXTRA_COMPILER_FLAGS=
-LIB = libxil.a
-DUMMYLIB = libxilprofile.a
-
-CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
-
-RELEASEDIR = ../../../../lib
-INCLUDEDIR = ../../../../include
-INCLUDES = -I./. -I${INCLUDEDIR}
-
-OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
-DUMMYOBJ = dummy.o
-INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
-
-libs : reallibs dummylibs
-
-reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
- $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
-
-dummylibs : $(DUMMYOBJ)
- $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
-
-%.o:%.c
- $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
-
-%.o:%.S
- $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
-
-include:
- $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
deleted file mode 100644
index 1d8aada04d7e1eec3fd97fe7cbfc1d23772a39b2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#include "xil_exception.h"
-
-void _profile_clean( void );
-
-/*
- * This function is the exit routine and is called by the crtinit, when the
- * program terminates. The name needs to be changed later..
- */
-void _profile_clean( void )
-{
- Xil_ExceptionDisable();
- disable_timer();
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
deleted file mode 100644
index 0ac51b1750e1149011f0c50c6372ab707bbbbb9d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_init.c:
-* Initialize the Profiling Structures.
-*
-******************************************************************************/
-
-#include "profile.h"
-
-/* XMD Initializes the following Global Variables Value during Program
- * Download with appropriate values. */
-
-#ifdef PROC_MICROBLAZE
-
-extern s32 microblaze_init(void);
-
-#elif defined PROC_PPC
-
-extern s32 powerpc405_init(void);
-
-#else
-
-extern s32 cortexa9_init(void);
-
-#endif
-
-s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
-
-u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
-u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
-u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
-u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
-
-/* Structure for Storing the Profiling Data */
-struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
-s32 n_gmon_sections = 1;
-
-/* This is the initialization code, which is called from the crtinit. */
-
-void _profile_init( void )
-{
-/* print("Gmon Init called....\r\n") */
-/* putnum(n_gmon_sections) , print("\r\n") */
-/* if( _gmonparam == 0xffffffff ) */
-/* printf("Gmonparam is NULL !!\r\n") */
-/* for( i = 0, i < n_gmon_sections, i++ )[ */
-/* putnum( _gmonparam[i].lowpc) , print("\t") */
-/* putnum( _gmonparam[i].highpc) , print("\r\n") */
-/* putnum( _gmonparam[i].textsize ), print("\r\n") */
-/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
-/* ] */
-
-#ifdef PROC_MICROBLAZE
- (void)microblaze_init();
-#elif defined PROC_PPC
- powerpc405_init();
-#else
- (void)cortexa9_init();
-#endif
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
deleted file mode 100644
index e85fb5c2d3cea521c419b5600530173448694702..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_timer_hw.c:
-* Timer related functions
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-
-#include "xil_exception.h"
-
-#ifdef PROC_PPC
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-/* #ifndef PPC_PIT_INTERRUPT */
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-/* extern u32 timer_clk_ticks, */
-
-#ifdef PROC_PPC405
-#ifdef PPC_PIT_INTERRUPT
-s32 ppc_pit_init( void );
-#endif
-s32 powerpc405_init()
-#endif /* PROC_CORTEXA9 */
-
-#ifdef PROC_PPC440
-#ifdef PPC_PIT_INTERRUPT
-s32 ppc_dec_init( void );
-#endif
-s32 powerpc405_init(void);
-#endif /* PROC_PPC440 */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-s32 opb_timer_init( void );
-#endif
-
-#ifdef PROC_MICROBLAZE
-s32 microblaze_init(void);
-#endif /* PROC_MICROBLAZE */
-
-#ifdef PROC_CORTEXA9
-s32 scu_timer_init( void );
-s32 cortexa9_init(void);
-#endif /* PROC_CORTEXA9 */
-
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC405
-
-
-/*--------------------------------------------------------------------
-* PowerPC PIT Timer Init.
-* Defined only if PIT Timer is used for Profiling
-*
-*-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-int ppc_pit_init( void )
-{
- /* 1. Register Profile_intr_handler as Interrupt handler */
- /* 2. Set PIT Timer Interrupt and Enable it. */
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
- XTime_PITSetInterval( timer_clk_ticks ) ;
- XTime_PITEnableAutoReload() ;
- return 0;
-}
-#endif
-
-
-/* --------------------------------------------------------------------
-* PowerPC Timer Initialization functions.
-* For PowerPC, PIT and opb_timer can be used for Profiling. This
-* is selected by the user in standalone BSP
-*
-*-------------------------------------------------------------------- */
-s32 powerpc405_init()
-{
- Xil_ExceptionInit() ;
- Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-
- /* Initialize the Timer.
- * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
- * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
-#ifdef PPC_PIT_INTERRUPT
- ppc_pit_init();
-#else
-#ifdef TIMER_CONNECT_INTC
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,NULL);
-#else
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
-#endif
- /* Initialize the timer with Timer Ticks */
- opb_timer_init() ;
-#endif
-
- /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
- * in the System. */
-#ifdef ENABLE_SYS_INTR
-#ifdef PPC_PIT_INTERRUPT
- XTime_PITEnableInterrupt() ;
-#elif TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
-#endif
- Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-#endif
- return 0;
-}
-
-#endif /* PROC_PPC */
-
-
-
-/*--------------------------------------------------------------------
- * PowerPC440 Target - Timer related functions
- * -------------------------------------------------------------------- */
-#ifdef PROC_PPC440
-
-
-/*--------------------------------------------------------------------
- * PowerPC DEC Timer Init.
- * Defined only if DEC Timer is used for Profiling
- *
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-s32 ppc_dec_init( void )
-{
- /* 1. Register Profile_intr_handler as Interrupt handler */
- /* 2. Set DEC Timer Interrupt and Enable it. */
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
- XTime_DECSetInterval( timer_clk_ticks ) ;
- XTime_DECEnableAutoReload() ;
- return 0;
-}
-#endif
-
-
-/*--------------------------------------------------------------------
- * PowerPC Timer Initialization functions.
- * For PowerPC, DEC and opb_timer can be used for Profiling. This
- * is selected by the user in standalone BSP
- *
- *-------------------------------------------------------------------- */
-s32 powerpc405_init(void)
-{
- Xil_ExceptionInit();
- Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-
- /* Initialize the Timer.
- * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
- * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
-#ifdef PPC_PIT_INTERRUPT
- ppc_dec_init();
-#else
-#ifdef TIMER_CONNECT_INTC
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
-
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,NULL);
-#else
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
-#endif
- /* Initialize the timer with Timer Ticks */
- opb_timer_init() ;
-#endif
-
- /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
- * in the System. */
-#ifdef ENABLE_SYS_INTR
-#ifdef PPC_PIT_INTERRUPT
- XTime_DECEnableInterrupt() ;
-#elif TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
-#endif
- Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
-#endif
- return 0;
-}
-
-#endif /* PROC_PPC440 */
-
-/* --------------------------------------------------------------------
- * opb_timer Initialization for PowerPC and MicroBlaze. This function
- * is not needed if DEC timer is used in PowerPC
- *
- *-------------------------------------------------------------------- */
-/* #ifndef PPC_PIT_INTERRUPT */
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-s32 opb_timer_init( void )
-{
- /* set the number of cycles the timer counts before interrupting */
- XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
-
- /* reset the timers, and clear interrupts */
- XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
- (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
-
- /* start the timers */
- XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
- | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
- return 0;
-}
-#endif
-
-
-/*--------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Initialize the Profile Timer for MicroBlaze Target.
- * For MicroBlaze, opb_timer is used. The opb_timer can be directly
- * connected to MicroBlaze or connected through Interrupt Controller.
- *
- *-------------------------------------------------------------------- */
-s32 microblaze_init(void)
-{
- /* Register profile_intr_handler
- * 1. If timer is connected to Interrupt Controller, register the handler
- * to Interrupt Controllers vector table.
- * 2. If timer is directly connected to MicroBlaze, register the handler
- * as Interrupt handler */
- Xil_ExceptionInit();
-
-#ifdef TIMER_CONNECT_INTC
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,NULL);
-#else
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)profile_intr_handler,
- NULL) ;
-#endif
-
- /* Initialize the timer with Timer Ticks */
- (void)opb_timer_init() ;
-
- /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
- * in the System. */
-#ifdef ENABLE_SYS_INTR
-#ifdef TIMER_CONNECT_INTC
- XIntc_MasterEnable((u32)INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
-#endif
-
-#endif
-
- Xil_ExceptionEnable();
-
- return 0;
-
-}
-
-#endif /* PROC_MICROBLAZE */
-
-
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Initialize the Profile Timer for Cortex A9 Target.
- * The scu private timer is connected to the Scu GIC controller.
- *
- *-------------------------------------------------------------------- */
-s32 scu_timer_init( void )
-{
- /* set the number of cycles the timer counts before interrupting
- * scu timer runs at half the cpu clock */
- XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
-
- /* clear any pending interrupts */
- XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
-
- /* enable interrupts, auto-reload mode and start the timer */
- XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
-
- return 0;
-}
-
-s32 cortexa9_init(void)
-{
-
- Xil_ExceptionInit();
-
- XScuGic_DeviceInitialize(0);
-
- /*
- * Connect the interrupt controller interrupt handler to the hardware
- * interrupt handling logic in the processor.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
- (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
- NULL);
-
- /*
- * Connect the device driver handler that will be called when an
- * interrupt for the device occurs, the handler defined above performs
- * the specific interrupt processing for the device.
- */
- XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
- PROFILE_TIMER_INTR_ID,
- (Xil_ExceptionHandler)profile_intr_handler,
- NULL);
-
- /*
- * Enable the interrupt for scu timer.
- */
- XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
-
- /*
- * Enable interrupts in the Processor.
- */
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
-
- /*
- * Initialize the timer with Timer Ticks
- */
- (void)scu_timer_init() ;
-
- Xil_ExceptionEnable();
-
- return 0;
-}
-
-#endif /* PROC_CORTEXA9 */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
deleted file mode 100644
index 2cee66b09ec02849f667a2e6731e44e6ab6163e4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_timer_hw.h:
-* Timer related functions
-*
-******************************************************************************/
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S
deleted file mode 100644
index d28646d6dd63c9171888d94fadfd2d219d6b8c48..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
- .globl dummy_f
-
-#ifdef PROC_MICROBLAZE
- .text
- .align 2
- .ent dummy_f
-
-dummy_f:
- nop
-
- .end dummy_f
-#endif
-
-#ifdef PROC_PPC
- .section .text
- .align 2
- .type dummy_f@function
-
-dummy_f:
- b dummy_f
-
-#endif
-
-#ifdef PROC_CORTEXA9
- .section .text
- .align 2
- .type dummy_f, %function
-
-dummy_f:
- b dummy_f
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
deleted file mode 100644
index 7096a92d804e8cbd2a660b78a32d5ea3a7256862..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
deleted file mode 100644
index 4cb07a7d3e230e647f9e6c5dbcb1447be4bfed5a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef PROFILE_H
-#define PROFILE_H 1
-
-#include <stdio.h>
-#include "xil_types.h"
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(u32 frompc, u32 selfpc);
-void profile_intr_handler( void ) ;
-void _profile_init( void );
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define HISTCOUNTER u16
-
-struct tostruct {
- u32 selfpc;
- s32 count;
- s16 link;
- u16 pad;
-};
-
-struct fromstruct {
- u32 frompc ;
- s16 link ;
- u16 pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y) (((x)/(y))*(y))
-#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
- s32 state;
-
- /* Histogram Information */
- u16 *kcount; /* No. of bins in histogram */
- u32 kcountsize; /* Histogram samples */
-
- /* Call-graph Information */
- struct fromstruct *froms;
- u32 fromssize;
- struct tostruct *tos;
- u32 tossize;
-
- /* Initialization I/Ps */
- u32 lowpc;
- u32 highpc;
- u32 textsize;
- /* u32 cg_froms, */
- /* u32 cg_tos, */
-};
-extern struct gmonparam *_gmonparam;
-extern s32 n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define GMON_PROF_ON 0
-#define GMON_PROF_BUSY 1
-#define GMON_PROF_ERROR 2
-#define GMON_PROF_OFF 3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define GPROF_STATE 0 /* int: profiling enabling variable */
-#define GPROF_COUNT 1 /* struct: profile tick count buffer */
-#define GPROF_FROMS 2 /* struct: from location hash bucket */
-#define GPROF_TOS 3 /* struct: destination/count structure */
-#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PROFILE_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
deleted file mode 100644
index 2539ce61aa9c4aac388d3cbf0c6dea0621752add..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-/*
- * The mcount fucntion is excluded from the library, if the user defines
- * PROFILE_NO_GRAPH.
- */
-#ifndef PROFILE_NO_GRAPH
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#ifdef PROFILE_NO_FUNCPTR
-s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
-#else
-s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
-#endif
-
-/*extern struct gmonparam *_gmonparam, */
-
-#ifdef PROFILE_NO_FUNCPTR
-s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
-{
- s32 index = 0 ;
-
- while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
- index++ ;
- }
- if( index == cgtable_size ) {
- return -1 ;
- } else {
- return index ;
- }
-}
-#else
-s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
-{
- s32 index = 0 ;
- s32 Status;
-
- while( (index < fromssize) && (froms[index].frompc != frompc) ){
- index++ ;
- }
- if( index == fromssize ) {
- Status = -1 ;
- } else {
- Status = index ;
- }
- return Status;
-}
-#endif /* PROFILE_NO_FUNCPTR */
-
-
-void mcount( u32 frompc, u32 selfpc )
-{
- register struct gmonparam *p = NULL;
- register s32 toindex, fromindex;
- s32 j;
-
- disable_timer();
-
- /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
- * check that frompcindex is a reasonable pc value.
- * for example: signal catchers get called from the stack,
- * not from text space. too bad.
- */
- for(j = 0; j < n_gmon_sections; j++ ){
- if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
- p = &_gmonparam[j];
- break;
- }
- }
- if( j == n_gmon_sections ) {
- goto done;
- }
-
-#ifdef PROFILE_NO_FUNCPTR
- fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
- if( fromindex == -1 ) {
- fromindex = p->cgtable_size ;
- p->cgtable_size++ ;
- p->cgtable[fromindex].frompc = frompc ;
- p->cgtable[fromindex].selfpc = selfpc ;
- p->cgtable[fromindex].count = 1 ;
- goto done ;
- }
- p->cgtable[fromindex].count++ ;
-#else
- fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
- if( fromindex == -1 ) {
- fromindex = (s32)p->fromssize ;
- p->fromssize++ ;
- /*if( fromindex >= N_FROMS ) {
- * print("Error : From PC table overflow\r\n")
- * goto overflow
- *}*/
- p->froms[fromindex].frompc = frompc ;
- p->froms[fromindex].link = -1 ;
- }else {
- toindex = ((s32)(p->froms[fromindex].link));
- while(toindex != -1) {
- toindex = (((s32)p->tossize) - toindex)-1 ;
- if( p->tos[toindex].selfpc == selfpc ) {
- p->tos[toindex].count++ ;
- goto done ;
- }
- toindex = ((s32)(p->tos[toindex].link)) ;
- }
- }
-
- /*if( toindex == -1 ) { */
- p->tos-- ;
- p->tossize++ ;
- /* if( toindex >= N_TOS ) {
- * print("Error : To PC table overflow\r\n")
- * goto overflow
- *} */
- p->tos[0].selfpc = selfpc ;
- p->tos[0].count = 1 ;
- p->tos[0].link = p->froms[fromindex].link ;
- p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
-#endif
-
- done:
- p->state = GMON_PROF_ON;
- goto enable_timer_label ;
- /* overflow: */
- /*p->state = GMON_PROF_ERROR */
- enable_timer_label:
- enable_timer();
- return ;
-}
-
-
-#endif /* PROFILE_NO_GRAPH */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
deleted file mode 100644
index 550c60b449b990de20009d14b095b2331274547e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-
-#ifndef _PROFILE_CONFIG_H
-#define _PROFILE_CONFIG_H
-
-#define BINSIZE 4U
-#define SAMPLE_FREQ_HZ 100000U
-#define TIMER_CLK_TICKS 1000U
-
-#define PROFILE_NO_FUNCPTR_FLAG 0
-
-#define PROFILE_TIMER_BASEADDR 0x00608000U
-#define PROFILE_TIMER_INTR_ID 0U
-
-#define TIMER_CONNECT_INTC
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
deleted file mode 100644
index c8ee9cef91928d58505b1bc1d22b54bedd2694f3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef PROC_PPC
-#include "xpseudo_asm.h"
-#define SPR_SRR0 0x01A
-#endif
-
-#include "xil_types.h"
-
-extern u32 binsize ;
-u32 prof_pc ;
-
-void profile_intr_handler( void )
-{
-
- s32 j;
-
-#ifdef PROC_MICROBLAZE
- asm( "swi r14, r0, prof_pc" ) ;
-#elif defined PROC_PPC
- prof_pc = mfspr(SPR_SRR0);
-#else
- /* for cortexa9, lr is saved in asm interrupt handler */
-#endif
- /* print("PC: "), putnum(prof_pc), print("\r\n"), */
- for(j = 0; j < n_gmon_sections; j++ ){
- if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
- _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
- break;
- }
- }
- /* Ack the Timer Interrupt */
- timer_ack();
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S
deleted file mode 100644
index e62cec0bd54f5d28e04b8950f563745565f3be93..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
-
-.globl __gnu_mcount_nc
-.type __gnu_mcount_nc, %function
-
-__gnu_mcount_nc:
- push {r0, r1, r2, r3, lr}
- subs r1, lr, #0 /* callee - current lr */
- ldr r0, [sp, #20] /* caller - at the top of the stack */
- bl mcount /* when __gnu_mcount_nc is called */
- pop {r0, r1, r2, r3, ip, lr}
- bx ip
-
- .end __gnu_mcount_nc
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S
deleted file mode 100644
index bea2726b66d847c6b19cc262a9f83177062a74d0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
- .globl _mcount
- .text
- .align 2
- .ent _mcount
-
- #ifndef PROFILE_NO_GRAPH
-
-_mcount:
- addi r1, r1, -48
- swi r11, r1, 44
- swi r12, r1, 40
- swi r5, r1, 36
- swi r6, r1, 32
- swi r7, r1, 28
- swi r8, r1, 24
- swi r9, r1, 20
- swi r10, r1, 16
- swi r15, r1, 12
- add r5, r0, r15
- brlid r15, mcount
- add r6, r0, r16
-
- lwi r11, r1, 44
- lwi r12, r1, 40
- lwi r5, r1, 36
- lwi r6, r1, 32
- lwi r7, r1, 28
- lwi r8, r1, 24
- lwi r9, r1, 20
- lwi r10, r1, 16
- lwi r15, r1, 12
- rtsd r15, 4
- addi r1, r1, 48
-
- #endif /* PROFILE_NO_GRAPH */
-
- .end _mcount
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S
deleted file mode 100644
index 39bb92f774a18c45dcbfe972b2bd6bde0f9305ac..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S
+++ /dev/null
@@ -1,71 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
- .globl _mcount
-
- #define _MCOUNT_STACK_FRAME 48
- .section .text
- .align 2
- .type _mcount@function
-
-
-_mcount:
- stwu 1, -_MCOUNT_STACK_FRAME(1)
- stw 3, 8(1)
- stw 4, 12(1)
- stw 5, 16(1)
- stw 6, 20(1)
- stw 7, 24(1)
- stw 8, 28(1)
- stw 9, 32(1)
- stw 10, 36(1)
- stw 11, 40(1)
- stw 12, 44(1)
- mflr 4
- stw 4, (_MCOUNT_STACK_FRAME+4)(1)
- lwz 3, (_MCOUNT_STACK_FRAME)(1)
- lwz 3, 4(3)
- bl mcount
- lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
- mtlr 4
- lwz 12, 44(1)
- lwz 11, 40(1)
- lwz 10, 36(1)
- lwz 9, 32(1)
- lwz 8, 28(1)
- lwz 7, 24(1)
- lwz 6, 20(1)
- lwz 5, 16(1)
- lwz 4, 12(1)
- lwz 3, 8(1)
- addi 1,1, _MCOUNT_STACK_FRAME
- blr
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
deleted file mode 100644
index aaf9edee7e1d66620949e3d97c75e989eaced499..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* putnum.c -- put a hex number on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Function Prototypes ******************************/
-extern void print (const char8 *ptr);
-void putnum(u32 num);
-
-void putnum(u32 num)
-{
- char8 buf[9];
- s32 cnt;
- s32 i;
- char8 *ptr;
- u32 digit;
- for(i = 0; i<9; i++) {
- buf[i] = '0';
- }
-
- ptr = buf;
- for (cnt = 7 ; cnt >= 0 ; cnt--) {
- digit = (num >> (cnt * 4U)) & 0x0000000fU;
-
- if ((digit <= 9U) && (ptr != NULL)) {
- digit += (u32)'0';
- *ptr = ((char8) digit);
- ptr += 1;
- } else if (ptr != NULL) {
- digit += ((u32)'a' - (u32)10);
- *ptr = ((char8)digit);
- ptr += 1;
- } else {
- /*Made for MisraC Compliance*/;
- }
- }
-
- if(ptr != NULL) {
- *ptr = (char8) 0;
- }
- print (buf);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
deleted file mode 100644
index 7f7b7d26152c6f8eab88ea49ec886e949580d9e6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/* read.c -- read bytes from a input device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
-}
-#endif
-
-/*
- * read -- read bytes from the serial port. Ignore fd, since
- * we only have stdin.
- */
-__attribute__((weak)) s32
-read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) s32
-_read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
deleted file mode 100644
index 87a753d4906486b9ce256e2c03341d0743cbed50..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <errno.h>
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) char8 *sbrk (s32 nbytes);
-}
-#endif
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-extern char8 HeapBase[];
-extern char8 HeapLimit[];
-
-
-
-__attribute__((weak)) char8 *sbrk (s32 nbytes)
-{
- char8 *base;
- static char8 *heap_ptr = HeapBase;
-
- base = heap_ptr;
- if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
- heap_ptr += nbytes;
- return base;
- } else {
- errno = ENOMEM;
- return ((char8 *)-1);
- }
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
deleted file mode 100644
index f85743b47d858386f68dd48822c7fd8af9fe3fe0..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated sleep function to make use Global
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-* </pre>
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A9(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
deleted file mode 100644
index f53b2d8c8e2c4c3d68702d7780654fc60e1950ea..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep rountines
-* function prototypes.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
deleted file mode 100644
index 5a4d33608256f53d59b1c6470b9627803ea20b55..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-* </pre>
-*
-* @note None.
-*
-******************************************************************************/
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET 0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S
deleted file mode 100644
index ade44de2bfadf6adb25ba416aafb4a05a261d552..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S
+++ /dev/null
@@ -1,223 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.s
-*
-* @addtogroup a9_boot_code
-* @{
-* <h2> translation_table.S </h2>
-* translation_table.S contains a static page table required by MMU for
-* cortex-A9. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq architecture. It
-* utilizes short descriptor translation table format with each section defining
-* 1MB of memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-------------------------|-----------------------------------|
-*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
-*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
-*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
-*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
-*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
-*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
-*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
-*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
-*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
-*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
-*
-* @note
-*
-* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
-* region after DDR and before PL is marked as undefined/reserved in translation
-* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
-* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
-* of 1MB, it is not possible to define separate regions for them. For region
-* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
-* granual size, it is not possible to define separate region for it
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
-* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
-* instead of strongly-ordered.
-* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
-* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
-* and 0xe0000000 - 0xe1ffffff is broken down into
-* 0xe0000000 - 0xe02fffff (memory mapped devides)
-* 0xe0300000 - 0xe0ffffff (reserved) and
-* 0xe1000000 - 0xe1ffffff (NAND)
-* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
-* if DDR is present or not and accordingly generate the
-* translation table
-* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
-* </pre>
-*
-*
-******************************************************************************/
-#include "xparameters.h"
- .globl MMUTable
-
- .section .mmu_tbl,"a"
-
-MMUTable:
- /* Each table entry occupies one 32-bit word and there are
- * 4096 entries, so the entire table takes up 16KB.
- * Each entry covers a 1MB section.
- */
-.set SECT, 0
-
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
-.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
-.set DDR_SIZE, (DDR_END - DDR_START)+1
-.set DDR_REG, DDR_SIZE/0x100000
-#else
-.set DDR_REG, 0
-#endif
-
-.set UNDEF_REG, 0x3FF - DDR_REG
-
- /*0x00000000 - 0x00100000 (cacheable )*/
-.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-
-.rept DDR_REG /* (DDR Cacheable) */
-.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept UNDEF_REG /* (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-
-.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
-.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
-.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
- * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
-.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
- 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
- 1MB, it is not possible to define separate regions for them */
-
-.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
-
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
-.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
- 1MB, it is not possible to define separate region for it
-
- 0xfff00000 - 0xffffffff
- 256K OCM when mapped to high address space
- inner-cacheable */
-.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
-.set SECT, SECT+0x100000
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
deleted file mode 100644
index d0cc6807ba9061e8a1fa85e632587d23880980fe..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <errno.h>
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 unlink(char8 *path);
-}
-#endif
-/*
- * unlink -- since we have no file system,
- * we just return an error.
- */
-__attribute__((weak)) sint32 unlink(char8 *path)
-{
- (void) path;
- errno = EIO;
- return (-1);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
deleted file mode 100644
index 65eea28cfacfd1aa76d1dded45c9f0f98743ee98..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Upadted micro sleep function to make use Global Timer
-* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
-* possible to generate timer in nanosecond due to
-* limited cpu frequency
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-* </pre>
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa9.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A9(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
deleted file mode 100644
index 0a3616328f7dee51d1eceb7a780938a8a8e18dd6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file vectors.c
-*
-* This file contains the C level vectors for the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
-* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
-* and added UndefinedException for a53 32 bit and r5
-* processor
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_exception.h"
-#include "vectors.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XExc_VectorTableEntry XExc_VectorTable[];
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the FIQ interrupt called from the vectors.s
-* file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void FIQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_FIQ_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the IRQ interrupt called from the vectors.s
-* file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void IRQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_IRQ_INT].Data);
-}
-
-#if !defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Undefined exception called from the
-* vectors.s file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void UndefinedException(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SW Interrupt called from the vectors.s
-* file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void SWInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SWI_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the DataAbort Interrupt called from the
-* vectors.s file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void DataAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the PrefetchAbort Interrupt called from the
-* vectors.s file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void PrefetchAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
-}
-#else
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
-* file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void SynchronousInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SYNC_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SError Interrupt called from the
-* vectors.s file.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void SErrorInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
-}
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
deleted file mode 100644
index bb599b5602601d799de56541046a0530075fedff..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-#if !defined (__aarch64__)
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-void UndefinedException(void);
-#else
-void SynchronousInterrupt(void);
-void SErrorInterrupt(void);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
deleted file mode 100644
index 9389f610a8db20c8a8cf5bffafc1995f826b23af..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/* write.c -- write bytes to an output device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
-}
-#endif
-
-/*
- * write -- write bytes to the serial port. Ignore fd, since
- * stdout and stderr are the same. Since we have no filesystem,
- * open will only return an error.
- */
-__attribute__((weak)) sint32
-write (sint32 fd, char8* buf, sint32 nbytes)
-
-{
-#ifdef STDOUT_BASEADDRESS
- s32 i;
- char8* LocalBuf = buf;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte ('\r');
- }
- outbyte (*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) sint32
-_write (sint32 fd, char8* buf, sint32 nbytes)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- sint32 length;
-
- (void)fd;
- (void)nbytes;
- length = XPVXenConsole_Write(buf);
- return length;
-#else
-#ifdef STDOUT_BASEADDRESS
- s32 i;
- char8* LocalBuf = buf;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte ('\r');
- }
- outbyte (*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-#endif
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
deleted file mode 100644
index 787212ca75ff368e405799266b103f095b0b22a1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef unsigned char Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef unsigned short Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef unsigned long Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include <linux/types.h>
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
deleted file mode 100644
index 650946bd01f4555daaeaf12db9919130e4aecf7d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef XDEBUG /* prevent circular inclusions */
-#define XDEBUG /* by using protection macros */
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL)
-
-#define xdbg_stmnt(x) x
-
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-#define xdbg_printf(...)
-
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#endif /* XDEBUG */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
deleted file mode 100644
index 3d97bebd450eda76d8221c8a9b012bb723c9b6ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
deleted file mode 100644
index f18601874bb5b8a84f10954730b4aca1bc988598..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include <string.h>
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implemention MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- * <br><br>
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S
deleted file mode 100644
index 6beb6fd1570b5739ce62fe2d2adb90f4d6814f78..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S
+++ /dev/null
@@ -1,159 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Added code for profiling
-* 3.06a sgd 05/16/12 Added global constructors and cleanup code
-* Uart initialization based on compiler flag
-* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-* initialization of uart smc nor and sram
-* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
-* timer when USE_AMP flag is defined
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "bspconfig.h"
-
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start
-
-.Lbss_end:
- .long __bss_end
-
-.Lstack:
- .long __stack
-
-
- .globl _start
-_start:
- bl __cpu_init /* Initialize the CPU first (BSP provides this) */
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
-
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* Reset and start Global Timer */
- mov r0, #0x0
- mov r1, #0x0
-
- /* Reset and start Triple Timer Counter */
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#if USE_AMP != 1
- bl XTime_SetTime
-#endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- /* Let her rip */
- bl main
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
-#ifdef PROFILING
- /* Cleanup profiling stuff */
- bl _profile_clean
-#endif /* PROFILING */
-
- /* All done */
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _start,.Lstart-_start
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
deleted file mode 100644
index 59b3c1c98be72a13c998fb13b2ea66892d4dbc88..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.c
-*
-* This file contains basic assert related functions for Xilinx software IP.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 Initial release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-u32 Xil_AssertStatus;
-
-/**
- * This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-s32 Xil_AssertWait = 1;
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief Implement assert. Currently, it calls a user-defined callback
-* function if one has been set. Then, it potentially enters an
-* infinite loop depending on the value of the Xil_AssertWait
-* variable.
-*
-* @param file: filename of the source
-* @param line: linenumber within File
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Assert(const char8 *File, s32 Line)
-{
- /* if the callback has been set then invoke it */
- if (Xil_AssertCallbackRoutine != 0) {
- (*Xil_AssertCallbackRoutine)(File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (Xil_AssertWait != 0) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Set up a callback function to be invoked when an assert occurs.
-* If a callback is already installed, then it will be replaced.
-*
-* @param routine: callback to be invoked when an assert is taken
-*
-* @return None.
-*
-* @note This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
- Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Null handler function. This follows the XInterruptHandler
-* signature for interrupt handlers. It can be used to assign a null
-* handler (a stub) to an interrupt controller vector table.
-*
-* @param NullParameter: arbitrary void pointer and not used.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void) NullParameter;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
deleted file mode 100644
index add4124e2c0c48a8844dfb3aad307c8ec5ae6e38..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accomodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accomodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
deleted file mode 100644
index 259c3b1f104987f101ae74450cae7474d0918ba2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
+++ /dev/null
@@ -1,1641 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
-* to xil_cache_mach.h to give access to sophisticated users
-* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
-* L1 and L2 caches in a single loop and used dsb, L2 sync
-* at the end of the loop.
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
-* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
-* operation was being done with L1 Data cache disabled. This is
-* fixed so that L2 cache disable operation happens independent of
-* L1 cache disable operation. This fixes CR #706464.
-* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
-* This is done to fix the CR #700542.
-* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
-* relevant cache APIs to disable and enable back the interrupts.
-* This fixes CR #663885.
-* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
-* out that for L2 cache flush/clean/invalidation by cache lines
-* does not need a cache sync as these are atomic nature. Similarly
-* figured out that for complete L2 cache flush/invalidation by way
-* we need to wait for some more time in a loop till the status
-* shows that the cache operation is completed.
-* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
-* cache lines were missed to invalidate when unaligned address
-* invalidation was accommodated. That fixes CR #766768.
-* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
-* stack memory which contains return address was invalidated. So
-* stack memory was flushed first and then L1D cache is invalidated.
-* This is done to fix CR #763829
-* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
-* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
-* explanation of CR#785243
-* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
-* has stack memory which has return address. Before invalidating
-* cache, stack memory was flushed first and L2 Cache is invalidated.
-* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
-* to remove unnecessary dsb in the APIs. Instead of using dsb
-* for L2 Cache, L2CacheSync has been used for each L2 cache line
-* and single dsb has been used for L1 cache. Also L2CacheSync is
-* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
-* and Xil_L2CacheInvalidate APIs are modified to flush the complete
-* stack instead of just System Stack
-* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
-* application(when USE_AMP flag is defined for BSP) as master CPU
-* would be utilizing L2 cache for its operation
-* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
-* version r0p2, which is present in zynq. So,removed the handling
-* related to same.It fixes CR#989132.
-* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
-* routines to ensure the stack data flushed only when the respective
-* caches are enabled. This fixes CR-992023.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_cache_l.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa9.h"
-#include "xl2cc.h"
-#include "xil_errata.h"
-#include "xil_exception.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-#ifdef __GNUC__
- extern s32 _stack_end;
- extern s32 __undef_stack;
-#endif
-
-#ifndef USE_AMP
-/****************************************************************************
-*
-* Access L2 Debug Control Register.
-*
-* @param Value, value to be written to Debug Control Register.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2WriteDebugCtrl(u32 Value)
-#else
-static void Xil_L2WriteDebugCtrl(u32 Value)
-#endif
-{
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
-#else
- (void)(Value);
-#endif
-}
-
-/****************************************************************************
-*
-* Perform L2 Cache Sync Operation.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2CacheSync(void)
-#else
-static void Xil_L2CacheSync(void)
-#endif
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
-}
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- Xil_L1DCacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1DCacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* modified contents are lost and are NOT written to the system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1DCacheInvalidateLine(adr);
-
- mtcpsr(currmask);
-}
-
-
-/*****************************************************************************/
-/**
-* @brief Invalidate the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If
-* the cachelines are modified (dirty), the modified contents are lost
-* and NOT written to the system memory before the lines are
-* invalidated.
-*
-* In this function, if start address or end address is not aligned to
-* cache-line, particular cache-line containing unaligned start or end
-* address is flush first and then invalidated the others as
-* invalidating the same unaligned cache line may result into loss of
-* data. This issue raises few possibilities.
-*
-* If the address to be invalidated is not cache-line aligned, the
-* following choices are available:
-* 1. Invalidate the cache line when required and do not bother much
-* for the side effects. Though it sounds good, it can result in
-* hard-to-debug issues. The problem is, if some other variable are
-* allocated in the same cache line and had been recently updated
-* (in cache), the invalidation would result in loss of data.
-* 2. Flush the cache line first. This will ensure that if any other
-* variable present in the same cache line and updated recently are
-* flushed out to memory. Then it can safely be invalidated. Again it
-* sounds good, but this can result in issues. For example, when the
-* invalidation happens in a typical ISR (after a DMA transfer has
-* updated the memory), then flushing the cache line means, loosing
-* data that were updated recently before the ISR got invoked.
-*
-* Linux prefers the second one. To have uniform implementation
-* (across standalone and Linux), the second option is implemented.
-* This being the case, follwoing needs to be taken care of:
-* 1. Whenever possible, the addresses must be cache line aligned.
-* Please nore that, not just start address, even the end address must
-* be cache line aligned. If that is taken care of, this will always
-* work.
-* 2. Avoid situations where invalidation has to be done after the
-* data is updated by peripheral/DMA directly into the memory. It is
-* not tough to achieve (may be a bit risky). The common use case to
-* do invalidation is when a DMA happens. Generally for such use
-* cases, buffers can be allocated first and then start the DMA. The
-* practice that needs to be followed here is, immediately after
-* buffer allocation and before starting the DMA, do the invalidation.
-* With this approach, invalidation need not to be done after the DMA
-* transfer is over.
-*
-* This is going to always work if done carefully.
-* However, the concern is, there is no guarantee that invalidate has
-* not needed to be done after DMA is complete. For example, because
-* of some reasons if the first cache line or last cache line
-* (assuming the buffer in question comprises of multiple cache lines)
-* are brought into cache (between the time it is invalidated and DMA
-* completes) because of some speculative prefetching or reading data
-* for a variable present in the same cache line, then we will have to
-* invalidate the cache after DMA is complete.
-*
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempadr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempadr);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempend);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempend);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- }
-
- while (tempadr < tempend) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = tempadr;
- Xil_L2CacheSync();
-#endif
-
- /* Invalidate L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(tempadr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = tempadr; }
-#endif
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlush();
-#ifndef USE_AMP
- Xil_L2CacheFlush();
-#endif
- mtcpsr(currmask);
-}
-
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlushLine(adr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_L2CacheFlushLine(adr);
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the
-* data cache, the cachelines containing those bytes are invalidated.
-* If the cachelines are modified (dirty), they are written to the
-* system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-
- while (LocalAddr < end) {
-
- /* Flush L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
-#ifndef USE_AMP
- /* Flush L2 cache line */
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
-#endif
- LocalAddr += cacheline;
- }
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache and the cacheline is modified (dirty),
-* the entire contents of the cacheline are written to system memory.
-* After the store completes, the cacheline is marked as unmodified
-* (not dirty).
-*
-* @param adr: 32bit address of the data to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- Xil_L1DCacheStoreLine(adr);
-#ifndef USE_AMP
- Xil_L2CacheStoreLine(adr);
-#endif
- mtcpsr(currmask);
-}
-
-/***************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- Xil_L1ICacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1ICacheDisable();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1ICacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line. If the instruction specified
-* by the address is cached by the instruction cache, the cacheline
-* containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1ICacheInvalidateLine(adr);
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the instructions specified by the address range are cached by
-* the instrunction cache, the cachelines containing those
-* instructions are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = LocalAddr;
- dsb();
-#endif
-
- /* Invalidate L1 I-cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 and L2 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- return;
- }
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the level 1 Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheFlush();
-
-#ifdef __GNUC__
- /* disable the Data cache */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for invalidating
-* the whole D-cache. This function invalidates each line by
-* set/way.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidate(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
-#ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 CtrlReg;
-#endif
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#ifdef __GNUC__
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * dont flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- * */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-#endif
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
- /* Determine Cache Size */
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
-
- /* Invalidate by Set/Way */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_sw(C7Reg);
-#else
- /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 Data cache line. If the byte specified by the
-* address (Addr) is cached by the Data cache, the cacheline
-* containing that byte is invalidated. If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written to
-* system memory before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* NOT written to the system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for flushing
-* the whole D-cache. Need to flush each line.
-*
-****************************************************************************/
-void Xil_L1DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way;
- u32 WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
-
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_sw(C7Reg);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 flush to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache and the cacheline is
-* modified (dirty), the entire contents of the cacheline are written
-* to system memory. After the store completes, the cacheline is
-* marked as unmodified (not dirty).
-*
-* @param Address to be stored.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheStoreLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 store to complete */
- dsb();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
- return;
- }
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Disable level 1 the instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* disable the instruction cache */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire level 1 instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidate(void)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 instruction cache line. If the instruction
-* specified by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 instruction cache for the given address
-* range. If the instrucions specified by the address range are cached
-* by the instruction cache, the cacheline containing those bytes are
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-#ifndef USE_AMP
-/****************************************************************************/
-/**
-* @brief Enable the L2 cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L2CacheEnable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- /* only enable if L2CC is currently disabled */
- if ((L2CCReg & 0x01U) == 0U) {
- /* set up the way size and latencies */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_AUX_CNTRL_OFFSET);
- L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
- L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
- L2CCReg);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
- XPS_L2CC_TAG_RAM_DEFAULT_MASK);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
- XPS_L2CC_DATA_RAM_DEFAULT_MASK);
-
- /* Clear the pending interrupts */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_ISR_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
-
- Xil_L2CacheInvalidate();
- /* Enable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg | (0x01U)));
-
- Xil_L2CacheSync();
- /* synchronize the processor */
- dsb();
-
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the L2 cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L2CacheDisable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- if((L2CCReg & 0x1U) != 0U) {
-
- /* Clean and Invalidate L2 Cache */
- Xil_L2CacheFlush();
-
- /* Disable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg & (~0x01U)));
- /* Wait for the cache operations to complete */
-
- dsb();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate the entire level 2 cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidate(void)
-{
- #ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 L2CCReg;
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * dont flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- if ((L2CCReg & 0x01U) != 0U) {
- /*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-
- #endif
- u32 ResultDCache;
- /* Invalidate the caches */
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
- 0x0000FFFFU);
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- while(ResultDCache != (u32)0U) {
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- /* Wait for the invalidate to complete */
- Xil_L2CacheSync();
-
- /* synchronize the processor */
- dsb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a level 2 cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty),
-* the modified contents are lost and are NOT written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* are NOT written to system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
-
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire level 2 cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L2CacheFlush(void)
-{
- u32 ResultL2Cache;
-
- /* Flush the caches */
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
- 0x0000FFFFU);
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
-
- while(ResultL2Cache != (u32)0U) {
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- Xil_L2CacheSync();
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheFlushLine(u32 adr)
-{
-#ifdef CONFIG_PL310_ERRATA_588369
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
-#else
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
-#endif
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to the system
-* memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_L2CacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory. After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data/instruction to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheStoreLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- /* synchronize the processor */
- dsb();
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
deleted file mode 100644
index b6614d5f992709379ce97da6e8be0cfb9eb80d8b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __GNUC__
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#elif defined (__ICCARM__)
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#endif
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
deleted file mode 100644
index fa92c6b1c4087b05b80e256770a5c0d023d99fe2..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
deleted file mode 100644
index 6e8cfa75fbfaa26744b0f9f9bf3114753dc9b5f8..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
deleted file mode 100644
index 490aebeabe7f0d17ed05105a8bfe9433f74515fd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note
-* The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-* </pre>
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
deleted file mode 100644
index d34fd2199c5aff7e3295d8df847b01338262d086..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xil_exception.c
-*
-* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
-* Handler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
-* processors and added Xil_UndefinedExceptionHandler
-* for a53 32 bit and r5 as well.
-* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
-* fix the warnings.
-* 6.7 mna 26/04/18 Add an API to obtain a corresponding
-* Xil_ExceptionHandler entry from XExc_VectorTable.
-* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xpseudo_asm.h"
-#include "xdebug.h"
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-static void Xil_ExceptionNullHandler(void *Data);
-/************************** Variable Definitions *****************************/
-/*
- * Exception vector table to store handlers for each exception vector.
- */
-#if defined (__aarch64__)
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SyncAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SErrorAbortHandler, NULL},
-
-};
-#else
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_UndefinedExceptionHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_PrefetchAbortHandler, NULL},
- {Xil_DataAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
-};
-#endif
-#if !defined (__aarch64__)
-u32 DataAbortAddr; /* Address of instruction causing data abort */
-u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
-u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
- exception */
-#endif
-
-/*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function is a stub Handler that is the default Handler that gets called
-* if the application has not setup a Handler for a specific exception. The
-* function interface has to match the interface specified for a Handler even
-* though none of the arguments are used.
-*
-* @param Data is unused by this function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-DieLoop: goto DieLoop;
-}
-
-/****************************************************************************/
-/**
-* @brief The function is a common API used to initialize exception handlers
-* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
-* and Cortex-A9, the exception handlers are being initialized
-* statically and this function does not do anything.
-* However, it is still present to take care of backward compatibility
-* issues (in earlier versions of BSPs, this API was being used to
-* initialize exception handlers).
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- return;
-}
-
-/*****************************************************************************/
-/**
-* @brief Register a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data)
-{
- XExc_VectorTable[Exception_id].Handler = Handler;
- XExc_VectorTable[Exception_id].Data = Data;
-}
-
-/*****************************************************************************/
-/**
-* @brief Get a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler,
- void **Data)
-{
- *Handler = XExc_VectorTable[Exception_id].Handler;
- *Data = XExc_VectorTable[Exception_id].Data;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Removes the Handler for a specific exception Id. The stub Handler
-* is then registered for this exception Id.
-*
-* @param exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Exception_id)
-{
- Xil_ExceptionRegisterHandler(Exception_id,
- Xil_ExceptionNullHandler,
- NULL);
-}
-
-#if defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* Default Synchronous abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-
-void Xil_SyncAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default SError abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_SErrorAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-#else
-/*****************************************************************************/
-/*
-*
-* Default Data abort handler which prints data fault status register through
-* which information about data fault can be acquired
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-
-void Xil_DataAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/*
-*
-* Default Prefetch abort handler which prints prefetch fault status register through
-* which information about instruction prefetch fault can be acquired
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_PrefetchAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-/*****************************************************************************/
-/*
-*
-* Default undefined exception handler which prints address of the undefined
-* instruction if debug prints are enabled
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void Xil_UndefinedExceptionHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
- while(1) {
- ;
- }
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
deleted file mode 100644
index 83303875d43a0de16324293bade2e2050e7d1370..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if !defined (__aarch64__) && !defined (ARMA53_32)
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
deleted file mode 100644
index d4434d07fa748457f2f476ebf82f9f8b20c93c91..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
deleted file mode 100644
index 90bfc81dc190a506078fa5ec12c27db7c466a0a1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.c
-*
-* Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures.
-*
-* @note
-*
-* This file contains architecture-dependent code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* </pre>
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian converion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianess
-*
-******************************************************************************/
-u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian converion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianess
-*
-******************************************************************************/
-u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
deleted file mode 100644
index 9c5aa43c7ecbc506145d0aaf5f409992bb08036e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* </pre>
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-u16 Xil_EndianSwap16(u16 Data);
-u32 Xil_EndianSwap32(u32 Data);
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
deleted file mode 100644
index ebafde87d7ff8a38bd28724a08ecca7701ea4f58..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*********************************************************************/
-/**
- * @file xil_macroback.h
- *
- * This header file is meant to bring back the removed _m macros.
- * This header file must be included last.
- * The following macros are not defined here due to the driver change:
- * XGpio_mSetDataDirection
- * XGpio_mGetDataReg
- * XGpio_mSetDataReg
- * XIIC_RESET
- * XIIC_CLEAR_STATS
- * XSpi_mReset
- * XSysAce_mSetCfgAddr
- * XSysAce_mIsCfgDone
- * XTft_mSetPixel
- * XTft_mGetPixel
- * XWdtTb_mEnableWdt
- * XWdtTb_mDisbleWdt
- * XWdtTb_mRestartWdt
- * XWdtTb_mGetTimebaseReg
- * XWdtTb_mHasReset
- *
- * Please refer the corresonding driver document for replacement.
- *
- *********************************************************************/
-
-#ifndef XIL_MACROBACK_H
-#define XIL_MACROBACK_H
-
-/*********************************************************************/
-/**
- * Macros for Driver XCan
- *
- *********************************************************************/
-#ifndef XCan_mReadReg
-#define XCan_mReadReg XCan_ReadReg
-#endif
-
-#ifndef XCan_mWriteReg
-#define XCan_mWriteReg XCan_WriteReg
-#endif
-
-#ifndef XCan_mIsTxDone
-#define XCan_mIsTxDone XCan_IsTxDone
-#endif
-
-#ifndef XCan_mIsTxFifoFull
-#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
-#endif
-
-#ifndef XCan_mIsHighPriorityBufFull
-#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
-#endif
-
-#ifndef XCan_mIsRxEmpty
-#define XCan_mIsRxEmpty XCan_IsRxEmpty
-#endif
-
-#ifndef XCan_mIsAcceptFilterBusy
-#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
-#endif
-
-#ifndef XCan_mCreateIdValue
-#define XCan_mCreateIdValue XCan_CreateIdValue
-#endif
-
-#ifndef XCan_mCreateDlcValue
-#define XCan_mCreateDlcValue XCan_CreateDlcValue
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDmaCentral
- *
- *********************************************************************/
-#ifndef XDmaCentral_mWriteReg
-#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
-#endif
-
-#ifndef XDmaCentral_mReadReg
-#define XDmaCentral_mReadReg XDmaCentral_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsAdc
- *
- *********************************************************************/
-#ifndef XDsAdc_mWriteReg
-#define XDsAdc_mWriteReg XDsAdc_WriteReg
-#endif
-
-#ifndef XDsAdc_mReadReg
-#define XDsAdc_mReadReg XDsAdc_ReadReg
-#endif
-
-#ifndef XDsAdc_mIsEmpty
-#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
-#endif
-
-#ifndef XDsAdc_mSetFstmReg
-#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
-#endif
-
-#ifndef XDsAdc_mGetFstmReg
-#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
-#endif
-
-#ifndef XDsAdc_mEnableConversion
-#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
-#endif
-
-#ifndef XDsAdc_mDisableConversion
-#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
-#endif
-
-#ifndef XDsAdc_mGetFifoOccyReg
-#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsDac
- *
- *********************************************************************/
-#ifndef XDsDac_mWriteReg
-#define XDsDac_mWriteReg XDsDac_WriteReg
-#endif
-
-#ifndef XDsDac_mReadReg
-#define XDsDac_mReadReg XDsDac_ReadReg
-#endif
-
-#ifndef XDsDac_mIsEmpty
-#define XDsDac_mIsEmpty XDsDac_IsEmpty
-#endif
-
-#ifndef XDsDac_mFifoIsFull
-#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
-#endif
-
-#ifndef XDsDac_mGetVacancy
-#define XDsDac_mGetVacancy XDsDac_GetVacancy
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XEmacLite
- *
- *********************************************************************/
-#ifndef XEmacLite_mReadReg
-#define XEmacLite_mReadReg XEmacLite_ReadReg
-#endif
-
-#ifndef XEmacLite_mWriteReg
-#define XEmacLite_mWriteReg XEmacLite_WriteReg
-#endif
-
-#ifndef XEmacLite_mGetTxStatus
-#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
-#endif
-
-#ifndef XEmacLite_mSetTxStatus
-#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
-#endif
-
-#ifndef XEmacLite_mGetRxStatus
-#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
-#endif
-
-#ifndef XEmacLite_mSetRxStatus
-#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
-#endif
-
-#ifndef XEmacLite_mIsTxDone
-#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
-#endif
-
-#ifndef XEmacLite_mIsRxEmpty
-#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
-#endif
-
-#ifndef XEmacLite_mNextTransmitAddr
-#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
-#endif
-
-#ifndef XEmacLite_mNextReceiveAddr
-#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
-#endif
-
-#ifndef XEmacLite_mIsMdioConfigured
-#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
-#endif
-
-#ifndef XEmacLite_mIsLoopbackConfigured
-#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
-#endif
-
-#ifndef XEmacLite_mGetReceiveDataLength
-#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
-#endif
-
-#ifndef XEmacLite_mGetTxActive
-#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
-#endif
-
-#ifndef XEmacLite_mSetTxActive
-#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XGpio
- *
- *********************************************************************/
-#ifndef XGpio_mWriteReg
-#define XGpio_mWriteReg XGpio_WriteReg
-#endif
-
-#ifndef XGpio_mReadReg
-#define XGpio_mReadReg XGpio_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XHwIcap
- *
- *********************************************************************/
-#ifndef XHwIcap_mFifoWrite
-#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
-#endif
-
-#ifndef XHwIcap_mFifoRead
-#define XHwIcap_mFifoRead XHwIcap_FifoRead
-#endif
-
-#ifndef XHwIcap_mSetSizeReg
-#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
-#endif
-
-#ifndef XHwIcap_mGetControlReg
-#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
-#endif
-
-#ifndef XHwIcap_mStartConfig
-#define XHwIcap_mStartConfig XHwIcap_StartConfig
-#endif
-
-#ifndef XHwIcap_mStartReadBack
-#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
-#endif
-
-#ifndef XHwIcap_mGetStatusReg
-#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
-#endif
-
-#ifndef XHwIcap_mIsTransferDone
-#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
-#endif
-
-#ifndef XHwIcap_mIsDeviceBusy
-#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
-#endif
-
-#ifndef XHwIcap_mIntrGlobalEnable
-#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
-#endif
-
-#ifndef XHwIcap_mIntrGlobalDisable
-#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
-#endif
-
-#ifndef XHwIcap_mIntrGetStatus
-#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
-#endif
-
-#ifndef XHwIcap_mIntrDisable
-#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
-#endif
-
-#ifndef XHwIcap_mIntrEnable
-#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
-#endif
-
-#ifndef XHwIcap_mIntrGetEnabled
-#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
-#endif
-
-#ifndef XHwIcap_mIntrClear
-#define XHwIcap_mIntrClear XHwIcap_IntrClear
-#endif
-
-#ifndef XHwIcap_mGetWrFifoVacancy
-#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
-#endif
-
-#ifndef XHwIcap_mGetRdFifoOccupancy
-#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
-#endif
-
-#ifndef XHwIcap_mSliceX2Col
-#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
-#endif
-
-#ifndef XHwIcap_mSliceY2Row
-#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
-#endif
-
-#ifndef XHwIcap_mSliceXY2Slice
-#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
-#endif
-
-#ifndef XHwIcap_mReadReg
-#define XHwIcap_mReadReg XHwIcap_ReadReg
-#endif
-
-#ifndef XHwIcap_mWriteReg
-#define XHwIcap_mWriteReg XHwIcap_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIic
- *
- *********************************************************************/
-#ifndef XIic_mReadReg
-#define XIic_mReadReg XIic_ReadReg
-#endif
-
-#ifndef XIic_mWriteReg
-#define XIic_mWriteReg XIic_WriteReg
-#endif
-
-#ifndef XIic_mEnterCriticalRegion
-#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIic_mExitCriticalRegion
-#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_GINTR_DISABLE
-#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIIC_GINTR_ENABLE
-#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_IS_GINTR_ENABLED
-#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
-#endif
-
-#ifndef XIIC_WRITE_IISR
-#define XIIC_WRITE_IISR XIic_WriteIisr
-#endif
-
-#ifndef XIIC_READ_IISR
-#define XIIC_READ_IISR XIic_ReadIisr
-#endif
-
-#ifndef XIIC_WRITE_IIER
-#define XIIC_WRITE_IIER XIic_WriteIier
-#endif
-
-#ifndef XIic_mClearIisr
-#define XIic_mClearIisr XIic_ClearIisr
-#endif
-
-#ifndef XIic_mSend7BitAddress
-#define XIic_mSend7BitAddress XIic_Send7BitAddress
-#endif
-
-#ifndef XIic_mDynSend7BitAddress
-#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
-#endif
-
-#ifndef XIic_mDynSendStartStopAddress
-#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
-#endif
-
-#ifndef XIic_mDynSendStop
-#define XIic_mDynSendStop XIic_DynSendStop
-#endif
-
-#ifndef XIic_mSend10BitAddrByte1
-#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
-#endif
-
-#ifndef XIic_mSend10BitAddrByte2
-#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
-#endif
-
-#ifndef XIic_mSend7BitAddr
-#define XIic_mSend7BitAddr XIic_Send7BitAddr
-#endif
-
-#ifndef XIic_mDisableIntr
-#define XIic_mDisableIntr XIic_DisableIntr
-#endif
-
-#ifndef XIic_mEnableIntr
-#define XIic_mEnableIntr XIic_EnableIntr
-#endif
-
-#ifndef XIic_mClearIntr
-#define XIic_mClearIntr XIic_ClearIntr
-#endif
-
-#ifndef XIic_mClearEnableIntr
-#define XIic_mClearEnableIntr XIic_ClearEnableIntr
-#endif
-
-#ifndef XIic_mFlushRxFifo
-#define XIic_mFlushRxFifo XIic_FlushRxFifo
-#endif
-
-#ifndef XIic_mFlushTxFifo
-#define XIic_mFlushTxFifo XIic_FlushTxFifo
-#endif
-
-#ifndef XIic_mReadRecvByte
-#define XIic_mReadRecvByte XIic_ReadRecvByte
-#endif
-
-#ifndef XIic_mWriteSendByte
-#define XIic_mWriteSendByte XIic_WriteSendByte
-#endif
-
-#ifndef XIic_mSetControlRegister
-#define XIic_mSetControlRegister XIic_SetControlRegister
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIntc
- *
- *********************************************************************/
-#ifndef XIntc_mMasterEnable
-#define XIntc_mMasterEnable XIntc_MasterEnable
-#endif
-
-#ifndef XIntc_mMasterDisable
-#define XIntc_mMasterDisable XIntc_MasterDisable
-#endif
-
-#ifndef XIntc_mEnableIntr
-#define XIntc_mEnableIntr XIntc_EnableIntr
-#endif
-
-#ifndef XIntc_mDisableIntr
-#define XIntc_mDisableIntr XIntc_DisableIntr
-#endif
-
-#ifndef XIntc_mAckIntr
-#define XIntc_mAckIntr XIntc_AckIntr
-#endif
-
-#ifndef XIntc_mGetIntrStatus
-#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XLlDma
- *
- *********************************************************************/
-#ifndef XLlDma_mBdRead
-#define XLlDma_mBdRead XLlDma_BdRead
-#endif
-
-#ifndef XLlDma_mBdWrite
-#define XLlDma_mBdWrite XLlDma_BdWrite
-#endif
-
-#ifndef XLlDma_mWriteReg
-#define XLlDma_mWriteReg XLlDma_WriteReg
-#endif
-
-#ifndef XLlDma_mReadReg
-#define XLlDma_mReadReg XLlDma_ReadReg
-#endif
-
-#ifndef XLlDma_mBdClear
-#define XLlDma_mBdClear XLlDma_BdClear
-#endif
-
-#ifndef XLlDma_mBdSetStsCtrl
-#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdGetStsCtrl
-#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdSetLength
-#define XLlDma_mBdSetLength XLlDma_BdSetLength
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mBdSetId
-#define XLlDma_mBdSetId XLlDma_BdSetId
-#endif
-
-#ifndef XLlDma_mBdGetId
-#define XLlDma_mBdGetId XLlDma_BdGetId
-#endif
-
-#ifndef XLlDma_mBdSetBufAddr
-#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetBufAddr
-#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mGetTxRing
-#define XLlDma_mGetTxRing XLlDma_GetTxRing
-#endif
-
-#ifndef XLlDma_mGetRxRing
-#define XLlDma_mGetRxRing XLlDma_GetRxRing
-#endif
-
-#ifndef XLlDma_mGetCr
-#define XLlDma_mGetCr XLlDma_GetCr
-#endif
-
-#ifndef XLlDma_mSetCr
-#define XLlDma_mSetCr XLlDma_SetCr
-#endif
-
-#ifndef XLlDma_mBdRingCntCalc
-#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
-#endif
-
-#ifndef XLlDma_mBdRingMemCalc
-#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
-#endif
-
-#ifndef XLlDma_mBdRingGetCnt
-#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
-#endif
-
-#ifndef XLlDma_mBdRingGetFreeCnt
-#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
-#endif
-
-#ifndef XLlDma_mBdRingSnapShotCurrBd
-#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
-#endif
-
-#ifndef XLlDma_mBdRingNext
-#define XLlDma_mBdRingNext XLlDma_BdRingNext
-#endif
-
-#ifndef XLlDma_mBdRingPrev
-#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
-#endif
-
-#ifndef XLlDma_mBdRingGetSr
-#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
-#endif
-
-#ifndef XLlDma_mBdRingSetSr
-#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
-#endif
-
-#ifndef XLlDma_mBdRingGetCr
-#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
-#endif
-
-#ifndef XLlDma_mBdRingSetCr
-#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
-#endif
-
-#ifndef XLlDma_mBdRingBusy
-#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
-#endif
-
-#ifndef XLlDma_mBdRingIntEnable
-#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
-#endif
-
-#ifndef XLlDma_mBdRingIntDisable
-#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
-#endif
-
-#ifndef XLlDma_mBdRingIntGetEnabled
-#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
-#endif
-
-#ifndef XLlDma_mBdRingGetIrq
-#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
-#endif
-
-#ifndef XLlDma_mBdRingAckIrq
-#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMbox
- *
- *********************************************************************/
-#ifndef XMbox_mWriteReg
-#define XMbox_mWriteReg XMbox_WriteReg
-#endif
-
-#ifndef XMbox_mReadReg
-#define XMbox_mReadReg XMbox_ReadReg
-#endif
-
-#ifndef XMbox_mWriteMBox
-#define XMbox_mWriteMBox XMbox_WriteMBox
-#endif
-
-#ifndef XMbox_mReadMBox
-#define XMbox_mReadMBox XMbox_ReadMBox
-#endif
-
-#ifndef XMbox_mFSLReadMBox
-#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
-#endif
-
-#ifndef XMbox_mFSLWriteMBox
-#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
-#endif
-
-#ifndef XMbox_mFSLIsEmpty
-#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
-#endif
-
-#ifndef XMbox_mFSLIsFull
-#define XMbox_mFSLIsFull XMbox_FSLIsFull
-#endif
-
-#ifndef XMbox_mIsEmpty
-#define XMbox_mIsEmpty XMbox_IsEmptyHw
-#endif
-
-#ifndef XMbox_mIsFull
-#define XMbox_mIsFull XMbox_IsFullHw
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMpmc
- *
- *********************************************************************/
-#ifndef XMpmc_mReadReg
-#define XMpmc_mReadReg XMpmc_ReadReg
-#endif
-
-#ifndef XMpmc_mWriteReg
-#define XMpmc_mWriteReg XMpmc_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMutex
- *
- *********************************************************************/
-#ifndef XMutex_mWriteReg
-#define XMutex_mWriteReg XMutex_WriteReg
-#endif
-
-#ifndef XMutex_mReadReg
-#define XMutex_mReadReg XMutex_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XPcie
- *
- *********************************************************************/
-#ifndef XPcie_mReadReg
-#define XPcie_mReadReg XPcie_ReadReg
-#endif
-
-#ifndef XPcie_mWriteReg
-#define XPcie_mWriteReg XPcie_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSpi
- *
- *********************************************************************/
-#ifndef XSpi_mIntrGlobalEnable
-#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
-#endif
-
-#ifndef XSpi_mIntrGlobalDisable
-#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
-#endif
-
-#ifndef XSpi_mIsIntrGlobalEnabled
-#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
-#endif
-
-#ifndef XSpi_mIntrGetStatus
-#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
-#endif
-
-#ifndef XSpi_mIntrClear
-#define XSpi_mIntrClear XSpi_IntrClear
-#endif
-
-#ifndef XSpi_mIntrEnable
-#define XSpi_mIntrEnable XSpi_IntrEnable
-#endif
-
-#ifndef XSpi_mIntrDisable
-#define XSpi_mIntrDisable XSpi_IntrDisable
-#endif
-
-#ifndef XSpi_mIntrGetEnabled
-#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
-#endif
-
-#ifndef XSpi_mSetControlReg
-#define XSpi_mSetControlReg XSpi_SetControlReg
-#endif
-
-#ifndef XSpi_mGetControlReg
-#define XSpi_mGetControlReg XSpi_GetControlReg
-#endif
-
-#ifndef XSpi_mGetStatusReg
-#define XSpi_mGetStatusReg XSpi_GetStatusReg
-#endif
-
-#ifndef XSpi_mSetSlaveSelectReg
-#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mGetSlaveSelectReg
-#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mEnable
-#define XSpi_mEnable XSpi_Enable
-#endif
-
-#ifndef XSpi_mDisable
-#define XSpi_mDisable XSpi_Disable
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysAce
- *
- *********************************************************************/
-#ifndef XSysAce_mGetControlReg
-#define XSysAce_mGetControlReg XSysAce_GetControlReg
-#endif
-
-#ifndef XSysAce_mSetControlReg
-#define XSysAce_mSetControlReg XSysAce_SetControlReg
-#endif
-
-#ifndef XSysAce_mOrControlReg
-#define XSysAce_mOrControlReg XSysAce_OrControlReg
-#endif
-
-#ifndef XSysAce_mAndControlReg
-#define XSysAce_mAndControlReg XSysAce_AndControlReg
-#endif
-
-#ifndef XSysAce_mGetErrorReg
-#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
-#endif
-
-#ifndef XSysAce_mGetStatusReg
-#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
-#endif
-
-#ifndef XSysAce_mWaitForLock
-#define XSysAce_mWaitForLock XSysAce_WaitForLock
-#endif
-
-#ifndef XSysAce_mEnableIntr
-#define XSysAce_mEnableIntr XSysAce_EnableIntr
-#endif
-
-#ifndef XSysAce_mDisableIntr
-#define XSysAce_mDisableIntr XSysAce_DisableIntr
-#endif
-
-#ifndef XSysAce_mIsReadyForCmd
-#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
-#endif
-
-#ifndef XSysAce_mIsMpuLocked
-#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
-#endif
-
-#ifndef XSysAce_mIsIntrEnabled
-#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysMon
- *
- *********************************************************************/
-#ifndef XSysMon_mIsEventSamplingModeSet
-#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
-#endif
-
-#ifndef XSysMon_mIsDrpBusy
-#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
-#endif
-
-#ifndef XSysMon_mIsDrpLocked
-#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
-#endif
-
-#ifndef XSysMon_mRawToTemperature
-#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
-#endif
-
-#ifndef XSysMon_mRawToVoltage
-#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
-#endif
-
-#ifndef XSysMon_mTemperatureToRaw
-#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
-#endif
-
-#ifndef XSysMon_mVoltageToRaw
-#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
-#endif
-
-#ifndef XSysMon_mReadReg
-#define XSysMon_mReadReg XSysMon_ReadReg
-#endif
-
-#ifndef XSysMon_mWriteReg
-#define XSysMon_mWriteReg XSysMon_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XTmrCtr
- *
- *********************************************************************/
-#ifndef XTimerCtr_mReadReg
-#define XTimerCtr_mReadReg XTimerCtr_ReadReg
-#endif
-
-#ifndef XTmrCtr_mWriteReg
-#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
-#endif
-
-#ifndef XTmrCtr_mSetControlStatusReg
-#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetControlStatusReg
-#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetTimerCounterReg
-#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mSetLoadReg
-#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
-#endif
-
-#ifndef XTmrCtr_mGetLoadReg
-#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
-#endif
-
-#ifndef XTmrCtr_mEnable
-#define XTmrCtr_mEnable XTmrCtr_Enable
-#endif
-
-#ifndef XTmrCtr_mDisable
-#define XTmrCtr_mDisable XTmrCtr_Disable
-#endif
-
-#ifndef XTmrCtr_mEnableIntr
-#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
-#endif
-
-#ifndef XTmrCtr_mDisableIntr
-#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
-#endif
-
-#ifndef XTmrCtr_mLoadTimerCounterReg
-#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mHasEventOccurred
-#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartLite
- *
- *********************************************************************/
-#ifndef XUartLite_mUpdateStats
-#define XUartLite_mUpdateStats XUartLite_UpdateStats
-#endif
-
-#ifndef XUartLite_mWriteReg
-#define XUartLite_mWriteReg XUartLite_WriteReg
-#endif
-
-#ifndef XUartLite_mReadReg
-#define XUartLite_mReadReg XUartLite_ReadReg
-#endif
-
-#ifndef XUartLite_mClearStats
-#define XUartLite_mClearStats XUartLite_ClearStats
-#endif
-
-#ifndef XUartLite_mSetControlReg
-#define XUartLite_mSetControlReg XUartLite_SetControlReg
-#endif
-
-#ifndef XUartLite_mGetStatusReg
-#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
-#endif
-
-#ifndef XUartLite_mIsReceiveEmpty
-#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
-#endif
-
-#ifndef XUartLite_mIsTransmitFull
-#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
-#endif
-
-#ifndef XUartLite_mIsIntrEnabled
-#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
-#endif
-
-#ifndef XUartLite_mEnableIntr
-#define XUartLite_mEnableIntr XUartLite_EnableIntr
-#endif
-
-#ifndef XUartLite_mDisableIntr
-#define XUartLite_mDisableIntr XUartLite_DisableIntr
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartNs550
- *
- *********************************************************************/
-#ifndef XUartNs550_mUpdateStats
-#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
-#endif
-
-#ifndef XUartNs550_mReadReg
-#define XUartNs550_mReadReg XUartNs550_ReadReg
-#endif
-
-#ifndef XUartNs550_mWriteReg
-#define XUartNs550_mWriteReg XUartNs550_WriteReg
-#endif
-
-#ifndef XUartNs550_mClearStats
-#define XUartNs550_mClearStats XUartNs550_ClearStats
-#endif
-
-#ifndef XUartNs550_mGetLineStatusReg
-#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
-#endif
-
-#ifndef XUartNs550_mGetLineControlReg
-#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
-#endif
-
-#ifndef XUartNs550_mSetLineControlReg
-#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
-#endif
-
-#ifndef XUartNs550_mEnableIntr
-#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
-#endif
-
-#ifndef XUartNs550_mDisableIntr
-#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
-#endif
-
-#ifndef XUartNs550_mIsReceiveData
-#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
-#endif
-
-#ifndef XUartNs550_mIsTransmitEmpty
-#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUsb
- *
- *********************************************************************/
-#ifndef XUsb_mReadReg
-#define XUsb_mReadReg XUsb_ReadReg
-#endif
-
-#ifndef XUsb_mWriteReg
-#define XUsb_mWriteReg XUsb_WriteReg
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
deleted file mode 100644
index 0929a6878ff746123ebbd285804913712a1ba879..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* @file xil_mem.c
-*
-* This file contains xil mem copy function to use in case of word aligned
-* data copies.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-/***************** Inline Functions Definitions ********************/
-/*****************************************************************************/
-/**
-* @brief This function copies memory from once location to other.
-*
-* @param dst: pointer pointing to destination memory
-*
-* @param src: pointer pointing to source memory
-*
-* @param cnt: 32 bit length of bytes to be copied
-*
-*****************************************************************************/
-void Xil_MemCpy(void* dst, const void* src, u32 cnt)
-{
- char *d = (char*)(void *)dst;
- const char *s = src;
-
- while (cnt >= sizeof (int)) {
- *(int*)d = *(int*)s;
- d += sizeof (int);
- s += sizeof (int);
- cnt -= sizeof (int);
- }
- while ((cnt) > 0U){
- *d = *s;
- d += 1U;
- s += 1U;
- cnt -= 1U;
- }
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
deleted file mode 100644
index a2d5e6681d9b82f40e81baa106789d512da27f6b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-* </pre>
-*
-*****************************************************************************/
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
deleted file mode 100644
index e114d142d2a9c1bfafa4060fea861721afc2fce7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_misc_reset.c
-*
-* This file contains the implementation of the reset sequence for various
-* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
-* sequence provided to the interfaces is based on the provision in
-* slcr reset functional blcok.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
deleted file mode 100644
index c228c988eb3035912db6e0d906d41609afac4b38..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register defintions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
deleted file mode 100644
index 1f58d906b88a3de11364214191ffe89be161486e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
-* before enabling back.
-* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
-* translation table and branch predictor arrays are
-* invalidated, D-cache flushed before the attribute
-* change is applied. This is done so that the user
-* need not call Xil_DisableMMU before calling
-* Xil_SetTlbAttributes.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
-* D cache after the translation table update. Removed the
-* redundant TLB invalidation in the same API at the beginning.
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "xil_errata.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region. xil_mmu.h contains
-* definitions of commonly used memory attributes which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for cortex A9 processor. This function invalidates the
-* instruction and data caches, and then enables MMU.
-*
-* @param None.
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A9 processors. This function invalidates
-* the TLBs, Branch Predictor Array and flushed the D Caches before
-* disabling the MMU.
-*
-* @param None.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg &= (u32)(~0x05U);
-#ifdef CONFIG_ARM_ERRATA_794073
- /* Disable Branch Prediction */
- Reg &= (u32)(~0x800U);
-#endif
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
deleted file mode 100644
index dd14b63b7057e38c5df9eadbab636379d684e30e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02 /* Strongly ordered */
-#define DEVICE_MEMORY 0xC06 /* Device memory */
-#define RESERVED 0x0 /* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE (~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a9_mmu_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
deleted file mode 100644
index dc0897f0d3c65b253cd018bd96766ddf08d4863c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
+++ /dev/null
@@ -1,443 +0,0 @@
-/*---------------------------------------------------*/
-/* Modified from : */
-/* Public Domain version of printf */
-/* Rud Merriam, Compsult, Inc. Houston, Tx. */
-/* For Embedded Systems Programming, 1991 */
-/* */
-/*---------------------------------------------------*/
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include <ctype.h>
-#include <string.h>
-#include <stdarg.h>
-
-static void padding( const s32 l_flag,const struct params_s *par);
-static void outs(const charptr lp, struct params_s *par);
-static s32 getnum( charptr* linep);
-
-typedef struct params_s {
- s32 len;
- s32 num1;
- s32 num2;
- char8 pad_character;
- s32 do_padding;
- s32 left_flag;
- s32 unsigned_flag;
-} params_t;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-/* */
-/* This routine puts pad characters into the output */
-/* buffer. */
-/* */
-static void padding( const s32 l_flag, const struct params_s *par)
-{
- s32 i;
-
- if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
- i=(par->len);
- for (; i<(par->num1); i++) {
-#ifdef STDOUT_BASEADDRESS
- outbyte( par->pad_character);
-#endif
- }
- }
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a string to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-static void outs(const charptr lp, struct params_s *par)
-{
- charptr LocalPtr;
- LocalPtr = lp;
- /* pad on left if needed */
- if(LocalPtr != NULL) {
- par->len = (s32)strlen( LocalPtr);
- }
- padding( !(par->left_flag), par);
-
- /* Move string to the buffer */
- while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
- (par->num2)--;
-#ifdef STDOUT_BASEADDRESS
- outbyte(*LocalPtr);
-#endif
- LocalPtr += 1;
-}
-
- /* Pad on right if needed */
- /* CR 439175 - elided next stmt. Seemed bogus. */
- /* par->len = strlen( lp) */
- padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a number to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-
-static void outnum( const s32 n, const s32 base, struct params_s *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[32];
- const char8 digits[] = "0123456789ABCDEF";
- u32 num;
- for(i = 0; i<32; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = n;
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = 0;
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
-#ifdef STDOUT_BASEADDRESS
- outbyte( outbuf[i] );
-#endif
- i--;
-}
- padding( par->left_flag, par);
-}
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a 64-bit number to the output */
-/* buffer as directed by the padding and positioning */
-/* flags. */
-/* */
-#if defined (__aarch64__)
-static void outnum1( const s64 n, const s32 base, params_t *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[64];
- const char8 digits[] = "0123456789ABCDEF";
- u64 num;
- for(i = 0; i<64; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = (n);
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = 0;
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
- outbyte( outbuf[i] );
- i--;
-}
- padding( par->left_flag, par);
-}
-#endif
-/*---------------------------------------------------*/
-/* */
-/* This routine gets a number from the format */
-/* string. */
-/* */
-static s32 getnum( charptr* linep)
-{
- s32 n;
- s32 ResultIsDigit = 0;
- charptr cptr;
- n = 0;
- cptr = *linep;
- if(cptr != NULL){
- ResultIsDigit = isdigit(((s32)*cptr));
- }
- while (ResultIsDigit != 0) {
- if(cptr != NULL){
- n = ((n*10) + (((s32)*cptr) - (s32)'0'));
- cptr += 1;
- if(cptr != NULL){
- ResultIsDigit = isdigit(((s32)*cptr));
- }
- }
- ResultIsDigit = isdigit(((s32)*cptr));
- }
- *linep = ((charptr )(cptr));
- return(n);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine operates just like a printf/sprintf */
-/* routine. It outputs a set of data under the */
-/* control of a formatting string. Not all of the */
-/* standard C format control are supported. The ones */
-/* provided are primarily those needed for embedded */
-/* systems work. Primarily the floating point */
-/* routines are omitted. Other formats could be */
-/* added easily by following the examples shown for */
-/* the supported formats. */
-/* */
-
-/* void esp_printf( const func_ptr f_ptr,
- const charptr ctrl1, ...) */
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-void xil_printf( const char8 *ctrl1, ...){
- XPVXenConsole_Printf(ctrl1);
-}
-#else
-void xil_printf( const char8 *ctrl1, ...)
-{
- s32 Check;
-#if defined (__aarch64__)
- s32 long_flag;
-#endif
- s32 dot_flag;
-
- params_t par;
-
- char8 ch;
- va_list argp;
- char8 *ctrl = (char8 *)ctrl1;
-
- va_start( argp, ctrl1);
-
- while ((ctrl != NULL) && (*ctrl != (char8)0)) {
-
- /* move format string chars to buffer until a */
- /* format control is found. */
- if (*ctrl != '%') {
-#ifdef STDOUT_BASEADDRESS
- outbyte(*ctrl);
-#endif
- ctrl += 1;
- continue;
- }
-
- /* initialize all the flags for this format. */
- dot_flag = 0;
-#if defined (__aarch64__)
- long_flag = 0;
-#endif
- par.unsigned_flag = 0;
- par.left_flag = 0;
- par.do_padding = 0;
- par.pad_character = ' ';
- par.num2=32767;
- par.num1=0;
- par.len=0;
-
- try_next:
- if(ctrl != NULL) {
- ctrl += 1;
- }
- if(ctrl != NULL) {
- ch = *ctrl;
- }
- else {
- ch = *ctrl;
- }
-
- if (isdigit((s32)ch) != 0) {
- if (dot_flag != 0) {
- par.num2 = getnum(&ctrl);
- }
- else {
- if (ch == '0') {
- par.pad_character = '0';
- }
- if(ctrl != NULL) {
- par.num1 = getnum(&ctrl);
- }
- par.do_padding = 1;
- }
- if(ctrl != NULL) {
- ctrl -= 1;
- }
- goto try_next;
- }
-
- switch (tolower((s32)ch)) {
- case '%':
-#ifdef STDOUT_BASEADDRESS
- outbyte( '%');
-#endif
- Check = 1;
- break;
-
- case '-':
- par.left_flag = 1;
- Check = 0;
- break;
-
- case '.':
- dot_flag = 1;
- Check = 0;
- break;
-
- case 'l':
- #if defined (__aarch64__)
- long_flag = 1;
- #endif
- Check = 0;
- break;
-
- case 'u':
- par.unsigned_flag = 1;
- /* fall through */
- case 'i':
- case 'd':
- #if defined (__aarch64__)
- if (long_flag != 0){
- outnum1((s64)va_arg(argp, s64), 10L, &par);
- }
- else {
- outnum( va_arg(argp, s32), 10L, &par);
- }
- #else
- outnum( va_arg(argp, s32), 10L, &par);
- #endif
- Check = 1;
- break;
- case 'p':
- #if defined (__aarch64__)
- par.unsigned_flag = 1;
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- Check = 1;
- break;
- #endif
- case 'X':
- case 'x':
- par.unsigned_flag = 1;
- #if defined (__aarch64__)
- if (long_flag != 0) {
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- }
- else {
- outnum((s32)va_arg(argp, s32), 16L, &par);
- }
- #else
- outnum((s32)va_arg(argp, s32), 16L, &par);
- #endif
- Check = 1;
- break;
-
- case 's':
- outs( va_arg( argp, char *), &par);
- Check = 1;
- break;
-
- case 'c':
-#ifdef STDOUT_BASEADDRESS
- outbyte( va_arg( argp, s32));
-#endif
- Check = 1;
- break;
-
- case '\\':
- switch (*ctrl) {
- case 'a':
-#ifdef STDOUT_BASEADDRESS
- outbyte( ((char8)0x07));
-#endif
- break;
- case 'h':
-#ifdef STDOUT_BASEADDRESS
- outbyte( ((char8)0x08));
-#endif
- break;
- case 'r':
-#ifdef STDOUT_BASEADDRESS
- outbyte( ((char8)0x0D));
-#endif
- break;
- case 'n':
-#ifdef STDOUT_BASEADDRESS
- outbyte( ((char8)0x0D));
- outbyte( ((char8)0x0A));
-#endif
- break;
- default:
-#ifdef STDOUT_BASEADDRESS
- outbyte( *ctrl);
-#endif
- break;
- }
- ctrl += 1;
- Check = 0;
- break;
-
- default:
- Check = 1;
- break;
- }
- if(Check == 1) {
- if(ctrl != NULL) {
- ctrl += 1;
- }
- continue;
- }
- goto try_next;
- }
- va_end( argp);
-}
-#endif
-/*---------------------------------------------------*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
deleted file mode 100644
index 016ae3b2f6b40423b9efe6063e2282dc1d9ffb74..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
+++ /dev/null
@@ -1,48 +0,0 @@
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <ctype.h>
-#include <string.h>
-#include <stdarg.h>
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
deleted file mode 100644
index 972a310a8d2cc3c3e586e549ae321eeaff4639f4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-*@file xil_sleepcommon.c
-*
-* This file contains the sleep API's
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.6 srm 11/02/17 First release
-* </pre>
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "sleep.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This API gives delay in sec
-*
-* @param seconds - delay time in seconds
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
- void sleep(unsigned int seconds)
- {
-#if defined (ARMR5)
- sleep_R5(seconds);
-#elif defined (__aarch64__) || defined (ARMA53_32)
- sleep_A53(seconds);
-#elif defined (__MICROBLAZE__)
- sleep_MB(seconds);
-#else
- sleep_A9(seconds);
-#endif
-
- }
-
-/****************************************************************************/
-/**
-*
-* This API gives delay in usec
-*
-* @param useconds - delay time in useconds
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
- void usleep(unsigned long useconds)
- {
-#if defined (ARMR5)
- usleep_R5(useconds);
-#elif defined (__aarch64__) || defined (ARMA53_32)
- usleep_A53(useconds);
-#elif defined (__MICROBLAZE__)
- usleep_MB(useconds);
-#else
- usleep_A9(useconds);
-#endif
-
- }
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
deleted file mode 100644
index 5bf30ccb4537843d0c04fc19d1b9d436db9125cf..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.c
-*
-* This file provides the common helper routines for the sleep API's
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
-*
-* </pre>
-*****************************************************************************/
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xil_sleeptimer.h"
-#include "xtime_l.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/* Function definitions are applicable only when TTC3 is present*/
-#if defined (SLEEP_TIMER_BASEADDR)
-/****************************************************************************/
-/**
-*
-* This is a helper function used by sleep/usleep APIs to
-* have delay in sec/usec
-*
-* @param delay - delay time in seconds/micro seconds
-*
-* @param frequency - Number of counts per second/micro second
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void Xil_SleepTTCCommon(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- XCntrVal TimeHighVal = 0U;
- XCntrVal TimeLowVal1 = 0U;
- XCntrVal TimeLowVal2 = 0U;
-
- TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do
- {
- TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
- (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This API starts the Triple Timer Counter
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void XTime_StartTTCTimer()
-{
- u32 TimerPrescalar;
- u32 TimerCntrl;
-
-#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
- u32 LpdRst;
-
- LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
-
- /* check if the timer is reset */
- if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
- XSLEEP_TTC_INSTANCE)) != 0 )) {
- LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
- XSLEEP_TTC_INSTANCE));
- Xil_Out32(RST_LPD_IOU2, LpdRst);
- } else {
-#endif
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- /* check if Timer is disabled */
- if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- /* check if Timer is configured with proper functionalty for sleep */
- if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
- return;
- }
-#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
- }
-#endif
- /* Disable the timer to configure */
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
- /* Disable the prescalar */
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
- TimerPrescalar);
- /* Enable the Timer */
- TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
deleted file mode 100644
index 4bfac0ac46f7d9516516cb2c0dbc6c85977e2cac..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-* <pre>
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-*
-* </pre>
-*****************************************************************************/
-
-#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H /* by using protection macros */
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT 32U
-#define XSleep_ReadCounterVal Xil_In32
-#define XCntrVal u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT 16U
-#define XSleep_ReadCounterVal Xil_In16
-#define XCntrVal u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#define RST_LPD_IOU2 0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
- /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
- /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
- /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
- /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
- /**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
- /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-#endif /* XIL_SLEEPTIMER_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
deleted file mode 100644
index 157ad08369f66a3a1d68212c5204e77713d4dfd3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.c
-*
-* Contains utility functions to test cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
-* cache line.
-* </pre>
-*
-* @note
-* This file contain functions that all operate on HAL.
-*
-******************************************************************************/
-#ifdef __ARM__
-#include "xil_cache.h"
-#include "xil_testcache.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#ifdef __aarch64__
-#include "xreg_cortexa53.h"
-#else
-#include "xreg_cortexr5.h"
-#endif
-
-#include "xil_types.h"
-
-extern void xil_printf(const char8 *ctrl1, ...);
-
-#define DATA_LENGTH 128
-
-#ifdef __aarch64__
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
-#else
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#endif
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
-* and Xil_DCacheInvalidateRange. This test function writes a constant
-* value to the Data array, flushes the range, writes a new value, then
-* invalidates the corresponding range.
-* @param None
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestDCacheRange(void)
-{
- s32 Index;
- s32 Status = 0;
- u32 CtrlReg;
- INTPTR Value;
-
- xil_printf("-- Cache Range Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A00505;
-
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" flush range done\r\n");
-
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A00505) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush worked\r\n");
- }
- else {
- xil_printf("Error: flush dcache range not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0C505;
-
-
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" invalidate dcache range done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0A05;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A0A05) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
-
- if (!Status) {
- xil_printf(" Invalidate worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache range not working\r\n");
- }
- xil_printf("-- Cache Range Test Complete --\r\n");
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value,
-* then invalidates the DCache.
-*
-* @return
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*****************************************************************************/
-s32 Xil_TestDCacheAll(void)
-{
- s32 Index;
- s32 Status;
- INTPTR Value;
- u32 CtrlReg;
-
- xil_printf("-- Cache All Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50500A0A;
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlush();
- xil_printf(" flush all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
-
- if (Value != 0x50500A0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush all worked\r\n");
- }
- else {
- xil_printf("Error: Flush dcache all not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x505FFA0A;
-
- Xil_DCacheFlush();
-
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidate();
-
- xil_printf(" invalidate all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50CFA0A;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0x50CFA0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Invalidate all worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache all not working\r\n");
- }
-
- xil_printf("-- DCache all Test Complete --\n\r");
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-* @note
-* The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheRange(void)
-{
-
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
-
- xil_printf("-- Invalidate icache range done --\r\n");
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-* @note
-* The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheAll(void)
-{
- Xil_ICacheInvalidate();
- xil_printf("-- Invalidate icache all done --\r\n");
- return 0;
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
deleted file mode 100644
index c35e9a463f05d7fa7e176b96369f5af1493d3127..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* @addtogroup common_test_utils
-* <h2>Cache test </h2>
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-* <pre>
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
deleted file mode 100644
index e6a36807b3795050909953e93beffd87b0e4c1d3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.c
-*
-* Contains the memory test utility functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param Data is the 16-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u16 Swap16(u16 Data)
-{
- return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param Data is the 32-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u32 Swap32(u32 Data)
-{
- u16 Lo16;
- u16 Hi16;
-
- u16 Swap16Lo;
- u16 Swap16Hi;
-
- Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
- Lo16 = (u16)(Data & 0x0000FFFFU);
-
- Swap16Lo = Swap16(Lo16);
- Swap16Hi = Swap16(Hi16);
-
- return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide register IO test where the
-* register is accessed using Xil_Out8 and Xil_In8, and comparing
-* the written values by reading them back.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writting the memory.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
-{
- u8 ValueIn;
- s32 Index;
- s32 Status = 0;
-
- for (Index = 0; Index < Length; Index++) {
- Xil_Out8((INTPTR)Addr, Value);
-
- ValueIn = Xil_In8((INTPTR)Addr);
-
- if ((Value != ValueIn) && (Status == 0)) {
- Status = -1;
- break;
- }
- }
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide register IO test. Each location
-* is tested by sequentially writing a 16-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register
-* IO, and big-endian register IO. When testing little/big-endian IO,
-* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
-* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
-* Compare In-Out values. Whether to swap the read-in value before
-* comparing is controlled by the 5th argument.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writting the memory.
-* @param Kind: Type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
-{
- u16 *TempAddr16;
- u16 ValueIn = 0U;
- s32 Index;
- TempAddr16 = Addr;
- Xil_AssertNonvoid(TempAddr16 != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out16LE((INTPTR)TempAddr16, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out16BE((INTPTR)TempAddr16, Value);
- break;
- default:
- Xil_Out16((INTPTR)TempAddr16, Value);
- break;
- }
-
- ValueIn = Xil_In16((INTPTR)TempAddr16);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out16((INTPTR)TempAddr16, Value);
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In16LE((INTPTR)TempAddr16);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In16BE((INTPTR)TempAddr16);
- break;
- default:
- ValueIn = Xil_In16((INTPTR)TempAddr16);
- break;
- }
-
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr16 += sizeof(u16);
- }
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide register IO test. Each location
-* is tested by sequentially writing a 32-bit wide regsiter, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register IO,
-* and big-endian register IO. When testing little/big-endian IO,
-* the function perform the following sequence, Xil_Out32LE/
-* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
-* Whether to swap the read-in value *before comparing is controlled
-* by the 5th argument.
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writting the memory.
-* @param Kind: type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
-{
- u32 *TempAddr;
- u32 ValueIn = 0U;
- s32 Index;
- TempAddr = Addr;
- Xil_AssertNonvoid(TempAddr != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out32LE((INTPTR)TempAddr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out32BE((INTPTR)TempAddr, Value);
- break;
- default:
- Xil_Out32((INTPTR)TempAddr, Value);
- break;
- }
-
- ValueIn = Xil_In32((INTPTR)TempAddr);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out32((INTPTR)TempAddr, Value);
-
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In32LE((INTPTR)TempAddr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In32BE((INTPTR)TempAddr);
- break;
- default:
- ValueIn = Xil_In32((INTPTR)TempAddr);
- break;
- }
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr += sizeof(u32);
- }
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
deleted file mode 100644
index ad68ead6430fef3b1a961165119aca5b8c557652..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities
-* <h2>I/O test </h2>
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTIO_H /* prevent circular inclusions */
-#define XIL_TESTIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 0
-#define XIL_TESTIO_LE 1
-#define XIL_TESTIO_BE 2
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
deleted file mode 100644
index 87426d17aa6312ce77ec592ad582e56f17d68d84..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.c
-*
-* Contains the memory test utility functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 FirtVal;
- u32 WordMem32;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
- Xil_AssertNonvoid(Addr != NULL);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- *(Addr+I) = Val;
- Val++;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)32; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u32) RotateLeft(Val, 32U);
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
-
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, 32U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)32; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* Read the location */
- WordMem32 = *(Addr+I);
- Val = (u32) (~((INTPTR) (&Addr[I])));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
-
- /* read memory location */
-
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 FirtVal;
- u16 WordMem16;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
- Xil_AssertNonvoid(Addr != NULL);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u16)RotateLeft(Val, 16U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, 16U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u16) (~((INTPTR)(&Addr[I])));
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- Val = (u16) (~((INTPTR) (&Addr[I])));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 FirtVal;
- u8 WordMem8;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
- Xil_AssertNonvoid(Addr != NULL);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, 8U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- Val = (u8) (~((INTPTR) (&Addr[I])));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the left one bit position
-*
-* @param Input is value to be rotated to the left
-* @param Width is the number of bits in the input data
-*
-* @return
-* The resulting unsigned long value of the rotate left
-*
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
- u32 Msb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << (u32)1) - (u32)1;
-
- /*
- * set the Width of the Input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- Msb = LocalInput & MsbMask;
-
- ReturnVal = LocalInput << 1U;
-
- if (Msb != 0x00000000U) {
- ReturnVal = ReturnVal | (u32)0x00000001;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the right one bit position
-*
-* @param Input: value to be rotated to the right
-* @param Width: number of bits in the input data
-*
-* @return
-* The resulting u32 value of the rotate right
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
- u32 Lsb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << 1U) - 1U;
-
- /*
- * set the width of the input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- ReturnVal = LocalInput >> 1U;
-
- Lsb = LocalInput & 0x00000001U;
-
- if (Lsb != 0x00000000U) {
- ReturnVal = ReturnVal | MsbMask;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
deleted file mode 100644
index c204728223b2c15e57d4e9f8afc944ad02a40c76..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils
-*
-* <h2>Memory test</h2>
-*
-* The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
-#define XIL_TESTMEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE 1U
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS 0x00U
-#define XIL_TESTMEM_INCREMENT 0x01U
-#define XIL_TESTMEM_WALKONES 0x02U
-#define XIL_TESTMEM_WALKZEROS 0x03U
-#define XIL_TESTMEM_INVERSEADDR 0x04U
-#define XIL_TESTMEM_FIXEDPATTERN 0x05U
-#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-
-extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
deleted file mode 100644
index 8143aff1ea4481ade21acf41eba4c361096081a9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#include <stdint.h>
-#include <stddef.h>
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include <linux/types.h>
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
deleted file mode 100644
index 735e26dd4df8663a93b4f22ce5eb5cd712bc6653..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
deleted file mode 100644
index d6b88cb3960871015e280d99552a83aedb857522..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.c
-*
-* This file contains APIs for configuring and controlling the event counters
-* in PL310 L2 cache controller. For more information about the event counters,
-* see xl2cc_counter.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include <stdint.h>
-#include "xparameters_ps.h"
-#include "xl2cc_counter.h"
-#include "xl2cc.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XL2cc_EventCtrReset(void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function initializes the event counters in L2 Cache controller
-* with a set of event codes specified by the user.
-*
-* @param Event0: Event code for counter 0.
-* @param Event1: Event code for counter 1.
-*
-* @return None.
-*
-* @note The definitions for event codes XL2CC_* can be found in
-* xl2cc_counter.h.
-*
-*****************************************************************************/
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
-{
-
- /* Write event code into cnt1 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
-
- /* Write event code into cnt0 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
-
- /* Reset counters */
- XL2cc_EventCtrReset();
-}
-
-
-/****************************************************************************/
-/**
-*
-* @brief This function starts the event counters in L2 Cache controller.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStart(void)
-{
- u32 *LocalPtr;
- LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
- XL2cc_EventCtrReset();
-
- /* Enable counter */
- /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
- *LocalPtr = (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters in L2 Cache controller,
-* saves the counter values and resets the counters.
-*
-* @param EveCtr0: Output parameter which is used to return the value
-* in event counter 0.
-* EveCtr1: Output parameter which is used to return the value
-* in event counter 1.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
-{
- /* Disable counter */
- *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
-
- /* Save counter values */
- *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
- *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
-
- XL2cc_EventCtrReset();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the event counters in L2 Cache controller.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrReset(void)
-{
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
deleted file mode 100644
index 8d0a61f07d193f41dc887b73052a3be9b1b5b78f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* </pre>
-*
-******************************************************************************/
-
-#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
-#define L2CCCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants define the event codes for the event counters.
- */
-#define XL2CC_CO 0x1
-#define XL2CC_DRHIT 0x2
-#define XL2CC_DRREQ 0x3
-#define XL2CC_DWHIT 0x4
-#define XL2CC_DWREQ 0x5
-#define XL2CC_DWTREQ 0x6
-#define XL2CC_IRHIT 0x7
-#define XL2CC_IRREQ 0x8
-#define XL2CC_WA 0x9
-#define XL2CC_IPFALLOC 0xa
-#define XL2CC_EPFHIT 0xb
-#define XL2CC_EPFALLOC 0xc
-#define XL2CC_SRRCVD 0xd
-#define XL2CC_SRCONF 0xe
-#define XL2CC_EPFRCVD 0xf
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
-void XL2cc_EventCtrStart(void);
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* L2CCCOUNTER_H */
-/**
-* @} End of "addtogroup l2_event_counter_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
deleted file mode 100644
index 0fa77710d14ea0476deb274aaa458285bfb8cf84..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XPARAMETERS_PS_H_
-#define _XPARAMETERS_PS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************** Include Files *******************************/
-
-
-/************************** Constant Definitions *****************************/
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock
- */
-
-/* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR 0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
-
-/* Canonical definitions for Interrupts */
-#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
-#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
-#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
-#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
-#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
-
-
-#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
-#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
-
-
-
-/* Canonical definitions for DMAC */
-
-
-/* Canonical definitions for WDT */
-
-/* Canonical definitions for SLCR */
-#define XPAR_XSLCR_NUM_INSTANCES 1U
-#define XPAR_XSLCR_0_DEVICE_ID 0U
-#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
-
-/* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES 1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
-#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
-#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_ACK_BEFORE 0U
-
-/* Canonical definitions for Global Timer */
-#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
-#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
-#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
-#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
-
-
-/* Xilinx Parallel Flash Library (XilFlash) User Settings */
-#define XPAR_AXI_EMC
-
-
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock. These have been put for bacwards compatibilty
- */
-
-#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
-#define XPS_UART0_BASEADDR 0xE0000000U
-#define XPS_UART1_BASEADDR 0xE0001000U
-#define XPS_USB0_BASEADDR 0xE0002000U
-#define XPS_USB1_BASEADDR 0xE0003000U
-#define XPS_I2C0_BASEADDR 0xE0004000U
-#define XPS_I2C1_BASEADDR 0xE0005000U
-#define XPS_SPI0_BASEADDR 0xE0006000U
-#define XPS_SPI1_BASEADDR 0xE0007000U
-#define XPS_CAN0_BASEADDR 0xE0008000U
-#define XPS_CAN1_BASEADDR 0xE0009000U
-#define XPS_GPIO_BASEADDR 0xE000A000U
-#define XPS_GEM0_BASEADDR 0xE000B000U
-#define XPS_GEM1_BASEADDR 0xE000C000U
-#define XPS_QSPI_BASEADDR 0xE000D000U
-#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
-#define XPS_SDIO0_BASEADDR 0xE0100000U
-#define XPS_SDIO1_BASEADDR 0xE0101000U
-#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
-#define XPS_NAND_BASEADDR 0xE1000000U
-#define XPS_PARPORT0_BASEADDR 0xE2000000U
-#define XPS_PARPORT1_BASEADDR 0xE4000000U
-#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
-#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
-#define XPS_TTC0_BASEADDR 0xF8001000U
-#define XPS_TTC1_BASEADDR 0xF8002000U
-#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
-#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
-#define XPS_WDT_BASEADDR 0xF8005000U
-#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
-#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
-#define XPS_AFI0_BASEADDR 0xF8008000U
-#define XPS_AFI1_BASEADDR 0xF8009000U
-#define XPS_AFI2_BASEADDR 0xF800A000U
-#define XPS_AFI3_BASEADDR 0xF800B000U
-#define XPS_OCM_BASEADDR 0xF800C000U
-#define XPS_EFUSE_BASEADDR 0xF800D000U
-#define XPS_CORESIGHT_BASEADDR 0xF8800000U
-#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
-#define XPS_SCU_PERIPH_BASE 0xF8F00000U
-#define XPS_L2CC_BASEADDR 0xF8F02000U
-#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
-#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
-#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
-#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
-#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
-
-/* Shared Peripheral Interrupts (SPI) */
-#define XPS_CORE_PARITY0_INT_ID 32U
-#define XPS_CORE_PARITY1_INT_ID 33U
-#define XPS_L2CC_INT_ID 34U
-#define XPS_OCMINTR_INT_ID 35U
-#define XPS_ECC_INT_ID 36U
-#define XPS_PMU0_INT_ID 37U
-#define XPS_PMU1_INT_ID 38U
-#define XPS_SYSMON_INT_ID 39U
-#define XPS_DVC_INT_ID 40U
-#define XPS_WDT_INT_ID 41U
-#define XPS_TTC0_0_INT_ID 42U
-#define XPS_TTC0_1_INT_ID 43U
-#define XPS_TTC0_2_INT_ID 44U
-#define XPS_DMA0_ABORT_INT_ID 45U
-#define XPS_DMA0_INT_ID 46U
-#define XPS_DMA1_INT_ID 47U
-#define XPS_DMA2_INT_ID 48U
-#define XPS_DMA3_INT_ID 49U
-#define XPS_SMC_INT_ID 50U
-#define XPS_QSPI_INT_ID 51U
-#define XPS_GPIO_INT_ID 52U
-#define XPS_USB0_INT_ID 53U
-#define XPS_GEM0_INT_ID 54U
-#define XPS_GEM0_WAKE_INT_ID 55U
-#define XPS_SDIO0_INT_ID 56U
-#define XPS_I2C0_INT_ID 57U
-#define XPS_SPI0_INT_ID 58U
-#define XPS_UART0_INT_ID 59U
-#define XPS_CAN0_INT_ID 60U
-#define XPS_FPGA0_INT_ID 61U
-#define XPS_FPGA1_INT_ID 62U
-#define XPS_FPGA2_INT_ID 63U
-#define XPS_FPGA3_INT_ID 64U
-#define XPS_FPGA4_INT_ID 65U
-#define XPS_FPGA5_INT_ID 66U
-#define XPS_FPGA6_INT_ID 67U
-#define XPS_FPGA7_INT_ID 68U
-#define XPS_TTC1_0_INT_ID 69U
-#define XPS_TTC1_1_INT_ID 70U
-#define XPS_TTC1_2_INT_ID 71U
-#define XPS_DMA4_INT_ID 72U
-#define XPS_DMA5_INT_ID 73U
-#define XPS_DMA6_INT_ID 74U
-#define XPS_DMA7_INT_ID 75U
-#define XPS_USB1_INT_ID 76U
-#define XPS_GEM1_INT_ID 77U
-#define XPS_GEM1_WAKE_INT_ID 78U
-#define XPS_SDIO1_INT_ID 79U
-#define XPS_I2C1_INT_ID 80U
-#define XPS_SPI1_INT_ID 81U
-#define XPS_UART1_INT_ID 82U
-#define XPS_CAN1_INT_ID 83U
-#define XPS_FPGA8_INT_ID 84U
-#define XPS_FPGA9_INT_ID 85U
-#define XPS_FPGA10_INT_ID 86U
-#define XPS_FPGA11_INT_ID 87U
-#define XPS_FPGA12_INT_ID 88U
-#define XPS_FPGA13_INT_ID 89U
-#define XPS_FPGA14_INT_ID 90U
-#define XPS_FPGA15_INT_ID 91U
-
-/* Private Peripheral Interrupts (PPI) */
-#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
-#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
-#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
-#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
-#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
-
-
-/* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
-#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
-
-#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
-
-/* For backwards compatibilty */
-#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
-
-#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
-
-#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
-#endif
-
-#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
-#endif
-
-#define XPAR_SCUTIMER_DEVICE_ID 0U
-#define XPAR_SCUWDT_DEVICE_ID 0U
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
deleted file mode 100644
index 2c08e5f2eacdaed8f0a9eeaf2f9e7e2c81408a79..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.c
-*
-* This file contains information about hardware for which the code is built
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00 pkp 12/15/14 Initial release
-* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
-* mode
-* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* ms 06/13/17 Added PSU_PMU macro to provide support of
-* XGetPlatform_Info function for PMUFW.
-* mus 08/17/17 Add EL1 NS mode support for
-* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
-* APIs.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xplatform_info.h"
-#if defined (__aarch64__)
-#include "bspconfig.h"
-#include "xil_smc.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about platform
-*
-* @param None.
-*
-* @return The information about platform defined in xplatform_info.h
-*
-******************************************************************************/
-u32 XGetPlatform_Info()
-{
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
- return XPLAT_ZYNQ_ULTRA_MP;
-#elif (__microblaze__)
- return XPLAT_MICROBLAZE;
-#else
- return XPLAT_ZYNQ;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about zynq ultrascale MP platform
-*
-* @param None.
-*
-* @return The information about zynq ultrascale MP platform defined in
-* xplatform_info.h
-*
-******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info()
-{
-#if EL1_NONSECURE
- XSmc_OutVar reg;
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
-#else
- u32 reg;
- reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
- return reg;
-#endif
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about PS Silicon version
-*
-* @param None.
-*
-* @return The information about PS Silicon version.
-*
-******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
-u32 XGetPSVersion_Info()
-{
-#if EL1_NONSECURE
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- XSmc_OutVar reg;
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)(reg.Arg1 & XPS_VERSION_INFO_MASK);
-#else
- u32 reg;
- reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
- & XPS_VERSION_INFO_MASK);
- return reg;
-#endif
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
deleted file mode 100644
index 0582222bc9d6b07a08f87199fc8f7622c6c3f6cb..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
-#define XPLATFORM_INFO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define XPAR_CSU_VER_OFFSET 0x00000044U
-
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-
-#define XPLAT_INFO_MASK (0xF)
-#define XPLAT_INFO_SHIFT (0xC)
-#define XPS_VERSION_INFO_MASK (0xF)
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info();
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
-u32 XGetPSVersion_Info();
-#endif
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info();
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
deleted file mode 100644
index d0765b60076862a675c91d72797f82b86783d86f..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-A9
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
-* Xpm_ResetEventCounters to fix CR#796275
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the Cortex A9 event counters.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
- /* Disable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function enables the Cortex A9 event counters.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
- /* Enable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the Cortex A9 event counters.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
- u32 Reg;
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
- Reg = C15Reg; }
-#endif
- Reg |= (1U << 1U); /* reset event counters */
- mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-
-}
-
-/****************************************************************************/
-/**
-* @brief This function configures the Cortex A9 event counters controller,
-* with the event codes, in a configuration selected by the user and
-* enables the counters.
-*
-* @param PmcrCfg: Configuration value based on which the event counters
-* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
-* be utilized for setting configuration.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
- u32 Counter;
- static PmcrEventCfg32 PmcrEvents[] = {
- {
- XPM_EVENT_SOFTINCR,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- {
- XPM_EVENT_DATA_READS,
- XPM_EVENT_DATA_WRITE,
- XPM_EVENT_EXCEPTION,
- XPM_EVENT_EXCEPRETURN,
- XPM_EVENT_CHANGECONTEXT,
- XPM_EVENT_SW_CHANGEPC
- },
- {
- XPM_EVENT_IMMEDBRANCH,
- XPM_EVENT_UNALIGNEDACCESS,
- XPM_EVENT_BRANCHMISS,
- XPM_EVENT_CLOCKCYCLES,
- XPM_EVENT_BRANCHPREDICT,
- XPM_EVENT_JAVABYTECODE
- },
- {
- XPM_EVENT_SWJAVABYTECODE,
- XPM_EVENT_JAVABACKBRANCH,
- XPM_EVENT_COHERLINEMISS,
- XPM_EVENT_COHERLINEHIT,
- XPM_EVENT_INSTRSTALL,
- XPM_EVENT_DATASTALL
- },
- {
- XPM_EVENT_MAINTLBSTALL,
- XPM_EVENT_STREXPASS,
- XPM_EVENT_STREXFAIL,
- XPM_EVENT_DATAEVICT,
- XPM_EVENT_NODISPATCH,
- XPM_EVENT_ISSUEEMPTY
- },
- {
- XPM_EVENT_INSTRRENAME,
- XPM_EVENT_PREDICTFUNCRET,
- XPM_EVENT_MAINEXEC,
- XPM_EVENT_SECEXEC,
- XPM_EVENT_LDRSTR,
- XPM_EVENT_FLOATRENAME
- },
- {
- XPM_EVENT_NEONRENAME,
- XPM_EVENT_PLDSTALL,
- XPM_EVENT_WRITESTALL,
- XPM_EVENT_INSTRTLBSTALL,
- XPM_EVENT_DATATLBSTALL,
- XPM_EVENT_INSTR_uTLBSTALL
- },
- {
- XPM_EVENT_DATA_uTLBSTALL,
- XPM_EVENT_DMB_STALL,
- XPM_EVENT_INT_CLKEN,
- XPM_EVENT_DE_CLKEN,
- XPM_EVENT_INSTRISB,
- XPM_EVENT_INSTRDSB
- },
- {
- XPM_EVENT_INSTRDMB,
- XPM_EVENT_EXTINT,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_PLE_OVFL,
- XPM_EVENT_PLE_PROG,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_DATASTALL,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- };
- const u32 *ptr = PmcrEvents[PmcrCfg];
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- /* Selecet event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
- }
-
- Xpm_ResetEventCounters();
- Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters and returns the counter
-* values.
-*
-* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
-* It is an output parameter which is used to return the PM
-* counter values.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
- u32 Counter;
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
- PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
-#else
- { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- PmCtrValue[Counter] = Cp15Reg; }
-#endif
- }
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
deleted file mode 100644
index 45f091982497d96d757ce80559712dbd227905e6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include <stdint.h>
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface fuctions to access perfromance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
deleted file mode 100644
index 4ad9e5d73cf6aa041462b24325df210f40a23bd4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* </pre>
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
deleted file mode 100644
index 37971bc59d96983f89152b26e5bb97bdb58e62a5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
-#define XPSEUDO_ASM_GCC_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/* necessary for pre-processor */
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-#if defined (__aarch64__)
-/* pseudo assembler instructions */
-#define mfcpsr() ({u32 rval = 0U; \
- asm volatile("mrs %0, DAIF" : "=r" (rval));\
- rval;\
- })
-
-#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
-
-#define cpsiei() //__asm__ __volatile__("cpsie i\n")
-#define cpsidi() //__asm__ __volatile__("cpsid i\n")
-
-#define cpsief() //__asm__ __volatile__("cpsie f\n")
-#define cpsidf() //__asm__ __volatile__("cpsid f\n")
-
-
-
-#define mtgpr(rn, v) /*__asm__ __volatile__(\
- "mov r" stringify(rn) ", %0 \n"\
- : : "r" (v)\
- )*/
-
-#define mfgpr(rn) /*({u32 rval; \
- __asm__ __volatile__(\
- "mov %0,r" stringify(rn) "\n"\
- : "=r" (rval)\
- );\
- rval;\
- })*/
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb sy")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__("dsb sy")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__("dmb sy")
-
-
-/* Memory Operations */
-#define ldr(adr) ({u64 rval; \
- __asm__ __volatile__(\
- "ldr %0,[%1]"\
- : "=r" (rval) : "r" (adr)\
- );\
- rval;\
- })
-
-#define mfelrel3() ({u64 rval = 0U; \
- asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
- rval;\
- })
-
-#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
-
-#else
-
-/* pseudo assembler instructions */
-#define mfcpsr() ({u32 rval = 0U; \
- __asm__ __volatile__(\
- "mrs %0, cpsr\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
-
-#define mtcpsr(v) __asm__ __volatile__(\
- "msr cpsr,%0\n"\
- : : "r" (v)\
- )
-
-#define cpsiei() __asm__ __volatile__("cpsie i\n")
-#define cpsidi() __asm__ __volatile__("cpsid i\n")
-
-#define cpsief() __asm__ __volatile__("cpsie f\n")
-#define cpsidf() __asm__ __volatile__("cpsid f\n")
-
-
-
-#define mtgpr(rn, v) __asm__ __volatile__(\
- "mov r" stringify(rn) ", %0 \n"\
- : : "r" (v)\
- )
-
-#define mfgpr(rn) ({u32 rval; \
- __asm__ __volatile__(\
- "mov %0,r" stringify(rn) "\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-
-/* Data Synchronization Barrier */
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-
-/* Data Memory Barrier */
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
-
-
-/* Memory Operations */
-#define ldr(adr) ({u32 rval; \
- __asm__ __volatile__(\
- "ldr %0,[%1]"\
- : "=r" (rval) : "r" (adr)\
- );\
- rval;\
- })
-
-#endif
-
-#define ldrb(adr) ({u8 rval; \
- __asm__ __volatile__(\
- "ldrb %0,[%1]"\
- : "=r" (rval) : "r" (adr)\
- );\
- rval;\
- })
-
-#define str(adr, val) __asm__ __volatile__(\
- "str %0,[%1]\n"\
- : : "r" (val), "r" (adr)\
- )
-
-#define strb(adr, val) __asm__ __volatile__(\
- "strb %0,[%1]\n"\
- : : "r" (val), "r" (adr)\
- )
-
-/* Count leading zeroes (clz) */
-#define clz(arg) ({u8 rval; \
- __asm__ __volatile__(\
- "clz %0,%1"\
- : "=r" (rval) : "r" (arg)\
- );\
- rval;\
- })
-
-#if defined (__aarch64__)
-#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
-#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
-
-#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
-#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
-#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
-/* CP15 operations */
-#define mfcp(reg) ({u64 rval = 0U;\
- __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
- rval;\
- })
-
-#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
-
-#else
-/* CP15 operations */
-#define mtcp(rn, v) __asm__ __volatile__(\
- "mcr " rn "\n"\
- : : "r" (v)\
- );
-
-#define mfcp(rn) ({u32 rval = 0U; \
- __asm__ __volatile__(\
- "mrc " rn "\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
-#endif
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
deleted file mode 100644
index dc9a4ebd2c36ac3f03ad6816b05610129a6a7943..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XREG_CORTEXA9_H
-#define XREG_CORTEXA9_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* GPRs */
-#define XREG_GPR0 r0
-#define XREG_GPR1 r1
-#define XREG_GPR2 r2
-#define XREG_GPR3 r3
-#define XREG_GPR4 r4
-#define XREG_GPR5 r5
-#define XREG_GPR6 r6
-#define XREG_GPR7 r7
-#define XREG_GPR8 r8
-#define XREG_GPR9 r9
-#define XREG_GPR10 r10
-#define XREG_GPR11 r11
-#define XREG_GPR12 r12
-#define XREG_GPR13 r13
-#define XREG_GPR14 r14
-#define XREG_GPR15 r15
-#define XREG_CPSR cpsr
-
-/* Coprocessor number defines */
-#define XREG_CP0 0
-#define XREG_CP1 1
-#define XREG_CP2 2
-#define XREG_CP3 3
-#define XREG_CP4 4
-#define XREG_CP5 5
-#define XREG_CP6 6
-#define XREG_CP7 7
-#define XREG_CP8 8
-#define XREG_CP9 9
-#define XREG_CP10 10
-#define XREG_CP11 11
-#define XREG_CP12 12
-#define XREG_CP13 13
-#define XREG_CP14 14
-#define XREG_CP15 15
-
-/* Coprocessor control register defines */
-#define XREG_CR0 cr0
-#define XREG_CR1 cr1
-#define XREG_CR2 cr2
-#define XREG_CR3 cr3
-#define XREG_CR4 cr4
-#define XREG_CR5 cr5
-#define XREG_CR6 cr6
-#define XREG_CR7 cr7
-#define XREG_CR8 cr8
-#define XREG_CR9 cr9
-#define XREG_CR10 cr10
-#define XREG_CR11 cr11
-#define XREG_CR12 cr12
-#define XREG_CR13 cr13
-#define XREG_CR14 cr14
-#define XREG_CR15 cr15
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE 0x20
-#define XREG_CPSR_MODE_BITS 0x1F
-#define XREG_CPSR_SYSTEM_MODE 0x1F
-#define XREG_CPSR_UNDEFINED_MODE 0x1B
-#define XREG_CPSR_DATA_ABORT_MODE 0x17
-#define XREG_CPSR_SVC_MODE 0x13
-#define XREG_CPSR_IRQ_MODE 0x12
-#define XREG_CPSR_FIQ_MODE 0x11
-#define XREG_CPSR_USER_MODE 0x10
-
-#define XREG_CPSR_IRQ_ENABLE 0x80
-#define XREG_CPSR_FIQ_ENABLE 0x40
-
-#define XREG_CPSR_N_BIT 0x80000000
-#define XREG_CPSR_Z_BIT 0x40000000
-#define XREG_CPSR_C_BIT 0x20000000
-#define XREG_CPSR_V_BIT 0x10000000
-
-
-/* CP15 defines */
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
-#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
-#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
-
-#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
-#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
-
-#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
-#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
-#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
-#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
-#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
-
-#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
-#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
-#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
-
-#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
-#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
-#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
-
-#else /* RVCT */
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
-#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
-#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
-#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
-
-#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
-#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
-#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
-#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
-#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
-#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
-#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
-
-#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
-#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
-#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
-#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
-#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
-
-#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
-#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
-#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
-#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
-#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
-
-#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
-#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
-#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
-#endif
-
-/* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
-#define XREG_CP15_CONTROL_V_BIT 0x00002000U
-#define XREG_CP15_CONTROL_I_BIT 0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
-#define XREG_CP15_CONTROL_B_BIT 0x00000080U
-#define XREG_CP15_CONTROL_C_BIT 0x00000004U
-#define XREG_CP15_CONTROL_A_BIT 0x00000002U
-#define XREG_CP15_CONTROL_M_BIT 0x00000001U
-
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
-#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
-#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
-
-#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
-
-#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
-
-#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
-#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
-#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
-#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
-#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
-#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
-#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
-#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
-
-#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
-
-#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
-#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
-
-#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
-#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
-#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
-#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
-#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
-#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
-
-#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
-#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
-
-#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
-
-#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
-
-#else
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
-#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
-#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
-#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
-#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "cp15:0:c7:c0:4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
-
-#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
-
-#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
-#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
-
-#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
-#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
-#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
-#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
-#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
-#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
-#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
-#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
-#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
-#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
-#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
-#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
-#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
-#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
-
-#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
-#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
-#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
-
-#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
-#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
-
-#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
-#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
-#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
-#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
-#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
-#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
-
-#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
-#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
-
-#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
-
-#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
-#endif
-
-
-/* MPE register definitions */
-#define XREG_FPSID c0
-#define XREG_FPSCR c1
-#define XREG_MVFR1 c6
-#define XREG_MVFR0 c7
-#define XREG_FPEXC c8
-#define XREG_FPINST c9
-#define XREG_FPINST2 c10
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT (24)
-#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE (1<<23)
-#define XREG_FPSID_ARCH_BIT (16)
-#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT (8)
-#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT (4)
-#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT (0)
-#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT (1 << 31)
-#define XREG_FPSCR_Z_BIT (1 << 30)
-#define XREG_FPSCR_C_BIT (1 << 29)
-#define XREG_FPSCR_V_BIT (1 << 28)
-#define XREG_FPSCR_QC (1 << 27)
-#define XREG_FPSCR_AHP (1 << 26)
-#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
-#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
-#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
-#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
-#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
-#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
-#define XREG_FPSCR_RMODE_BIT (22)
-#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT (20)
-#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT (16)
-#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC (1 << 7)
-#define XREG_FPSCR_IXC (1 << 4)
-#define XREG_FPSCR_UFC (1 << 3)
-#define XREG_FPSCR_OFC (1 << 2)
-#define XREG_FPSCR_DZC (1 << 1)
-#define XREG_FPSCR_IOC (1 << 0)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT (28)
-#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT (24)
-#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT (20)
-#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT (16)
-#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT (12)
-#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT (8)
-#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT (4)
-#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT (0)
-#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX (1 << 31)
-#define XREG_FPEXC_EN (1 << 30)
-#define XREG_FPEXC_DEX (1 << 29)
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXA9_H */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
deleted file mode 100644
index 993747588d94aa9364dfacd1f14cd5970331d66a..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
+++ /dev/null
@@ -1,535 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx® software status codes
-*
-* The xstatus.h file contains the Xilinx® software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
deleted file mode 100644
index e81643f90b96461dbffec7b7a27dfdd234bd7dc5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A9 MP core.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
-* </pre>
-*
-* @note None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************/
-/**
-* @brief Set the time in the Global Timer Counter Register.
-*
-* @param Xtime_Global: 64-bit Value to be written to the Global Timer
-* Counter Register.
-*
-* @return None.
-*
-* @note When this function is called by any one processor in a multi-
-* processor environment, reference time will reset/lost for all
-* processors.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- /* Disable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
-
- /* Updating Global Timer Counter Register */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
- (u32)((u32)(Xtime_Global>>32U)));
-
- /* Enable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the Global Timer Counter Register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location which will be
-* updated with the current timer value.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- u32 low;
- u32 high;
-
- /* Reading Global Timer Counter Register */
- do
- {
- high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
- low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
- } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
-
- *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
-}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
deleted file mode 100644
index 9b872b6cb696a54594707facec1b228bd9facc42..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
-#define GTIMER_CONTROL_OFFSET 0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/Makefile
deleted file mode 100644
index c3076709321a06b349467ec65fdbf2f48dbfb12e..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-LIBSOURCES=*.c
-INCLUDEFILES=*.h
-
-libs:
- echo "Compiling tmrctr"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OBJECTS}
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr.c
deleted file mode 100644
index ef31207d6471dc859e3d9260e52978b5a34748f4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* Contains required functions for the XTmrCtr driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.05a adk 15/05/13 Fixed the CR:693066
-* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-* XTmrCtr instance structure.
-* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-* the XTmrCtr_Start function.
-* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-* There will be no Initialization done in the
-* XTmrCtr_Initialize if both the timers have already started and
-* the XST_DEVICE_IS_STARTED Status is returned.
-* Removed the logic in the XTmrCtr_Initialize function
-* which was checking the Register Value to know whether
-* a timer has started or not.
-* 4.0 als 09/30/15 Updated initialization API.
-* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
-* Changed the prototype of XTmrCtr_CfgInitialize API.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xtmrctr.h"
-#include "xtmrctr_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-static void XTmrCtr_StubCallback(void *CallBackRef, u8 TmrCtrNumber);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function populates the timer counter's configuration structure and sets
-* some configurations defaults.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param ConfigPtr is a pointer to the configuration structure that will
-* be used to copy the settings from.
-* @param EffectiveAddr is the device base address in the virtual memory
-* space. If the address translation is not used, then the physical
-* address is passed.
-*
-* @return None.
-*
-* @note Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-******************************************************************************/
-void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
- UINTPTR EffectiveAddr)
-{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(ConfigPtr != NULL);
- Xil_AssertVoid(EffectiveAddr != 0x0);
-
- InstancePtr->IsReady = 0;
- InstancePtr->Config = *ConfigPtr;
-
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->BaseAddress = EffectiveAddr;
-
- InstancePtr->Handler = XTmrCtr_StubCallback;
- InstancePtr->CallBackRef = InstancePtr;
- InstancePtr->Stats.Interrupts = 0;
-
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-}
-
-/*****************************************************************************/
-/**
-* (Re-)initialzes all timer counters which aren't started already.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-*
-* @return
-* - XST_SUCCESS if at least one timer counter is stopped.
-* - XST_DEVICE_IS_STARTED otherwise.
-*
-* @note None.
-*
-******************************************************************************/
-int XTmrCtr_InitHw(XTmrCtr *InstancePtr)
-{
- int Status = XST_DEVICE_IS_STARTED;
- u8 TmrIndex;
- u32 TmrCtrStarted[XTC_DEVICE_TIMER_COUNT];
-
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- TmrCtrStarted[0] = InstancePtr->IsStartedTmrCtr0;
- TmrCtrStarted[1] = InstancePtr->IsStartedTmrCtr1;
-
- for (TmrIndex = 0; TmrIndex < XTC_DEVICE_TIMER_COUNT; TmrIndex++) {
- /* Only initialize timers counters which aren't started. */
- if (TmrCtrStarted[TmrIndex] == XIL_COMPONENT_IS_STARTED) {
- continue;
- }
-
- /* Set the compare register to 0. */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrIndex,
- XTC_TLR_OFFSET, 0);
- /* Reset the timer and the interrupt. */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrIndex,
- XTC_TCSR_OFFSET,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
- /* Release the reset. */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrIndex,
- XTC_TCSR_OFFSET, 0);
-
- /* Indicate that at least one timer is not running and has been
- * initialized. */
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* Initializes a specific timer/counter instance/driver. Initialize fields of
-* the XTmrCtr structure, then reset the timer/counter.If a timer is already
-* running then it is not initialized.
-*
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param DeviceId is the unique id of the device controlled by this
-* XTmrCtr component. Passing in a device id associates the
-* generic XTmrCtr component to a specific device, as chosen by
-* the caller or application developer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_DEVICE_IS_STARTED if the device has already been started
-* - XST_DEVICE_NOT_FOUND if the device doesn't exist
-*
-* @note None.
-*
-******************************************************************************/
-int XTmrCtr_Initialize(XTmrCtr *InstancePtr, u16 DeviceId)
-{
- XTmrCtr_Config *ConfigPtr;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* In case all timer counters are already started, don't proceed with
- * re-initialization. */
- if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED) &&
- (InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /* Retrieve configuration of timer counter core with matching ID. */
- ConfigPtr = XTmrCtr_LookupConfig(DeviceId);
- if (!ConfigPtr) {
- return XST_DEVICE_NOT_FOUND;
- }
-
- XTmrCtr_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddress);
-
- return XTmrCtr_InitHw(InstancePtr);
-}
-
-/*****************************************************************************/
-/**
-*
-* Starts the specified timer counter of the device such that it starts running.
-* The timer counter is reset before it is started and the reset value is
-* loaded into the timer counter.
-*
-* If interrupt mode is specified in the options, it is necessary for the caller
-* to connect the interrupt handler of the timer/counter to the interrupt source,
-* typically an interrupt controller, and enable the interrupt within the
-* interrupt controller.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 ControlStatusReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the current register contents such that only the necessary bits
- * of the register are modified in the following operations
- */
- ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Reset the timer counter such that it reloads from the compare
- * register and the interrupt is cleared simultaneously, the interrupt
- * can only be cleared after reset such that the interrupt condition is
- * cleared
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_LOAD_MASK);
-
-
-
- /*
- * Indicate that the timer is started before enabling it
- */
- if (TmrCtrNumber == 0) {
- InstancePtr->IsStartedTmrCtr0 = XIL_COMPONENT_IS_STARTED;
- } else {
- InstancePtr->IsStartedTmrCtr1 = XIL_COMPONENT_IS_STARTED;
- }
-
-
- /*
- * Remove the reset condition such that the timer counter starts running
- * with the value loaded from the compare register
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg | XTC_CSR_ENABLE_TMR_MASK);
-}
-
-/*****************************************************************************/
-/**
-*
-* Stops the timer counter by disabling it.
-*
-* It is the callers' responsibility to disconnect the interrupt handler of the
-* timer_counter from the interrupt source, typically an interrupt controller,
-* and disable the interrupt within the interrupt controller.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 ControlStatusReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the current register contents
- */
- ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Disable the timer counter such that it's not running
- */
- ControlStatusReg &= ~(XTC_CSR_ENABLE_TMR_MASK);
-
- /*
- * Write out the updated value to the actual register.
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, ControlStatusReg);
-
- /*
- * Indicate that the timer is stopped
- */
- if (TmrCtrNumber == 0) {
- InstancePtr->IsStartedTmrCtr0 = 0;
- } else {
- InstancePtr->IsStartedTmrCtr1 = 0;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the current value of the specified timer counter. The timer counter
-* may be either incrementing or decrementing based upon the current mode of
-* operation.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The current value for the timer counter.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCR_OFFSET);
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the reset value for the specified timer counter. This is the value
-* that is loaded into the timer counter when it is reset. This value is also
-* loaded when the timer counter is started.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param ResetValue contains the value to be used to reset the timer
-* counter.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
- u32 ResetValue)
-{
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TLR_OFFSET, ResetValue);
-}
-
-/*****************************************************************************/
-/**
-*
-* Returns the timer counter value that was captured the last time the external
-* capture input was asserted.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The current capture value for the indicated timer counter.
-*
-* @note None.
-*
-*******************************************************************************/
-u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TLR_OFFSET);
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the specified timer counter of the device. A reset causes the timer
-* counter to set it's value to the reset value.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 CounterControlReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read current contents of the register so it won't be destroyed
- */
- CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Reset the timer by toggling the reset bit in the register
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- CounterControlReg | XTC_CSR_LOAD_MASK);
-
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, CounterControlReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Checks if the specified timer counter of the device has expired. In capture
-* mode, expired is defined as a capture occurred. In compare mode, expired is
-* defined as the timer counter rolled over/under for up/down counting.
-*
-* When interrupts are enabled, the expiration causes an interrupt. This function
-* is typically used to poll a timer counter to determine when it has expired.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return TRUE if the timer has expired, and FALSE otherwise.
-*
-* @note None.
-*
-******************************************************************************/
-int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 CounterControlReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check if timer is expired
- */
- CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
-
- return ((CounterControlReg & XTC_CSR_INT_OCCURED_MASK) ==
- XTC_CSR_INT_OCCURED_MASK);
-}
-
-/*****************************************************************************/
-/**
-* Default callback for the driver does nothing. It matches the signature of the
-* XTmrCtr_Handler type.
-*
-* @param CallBackRef is a pointer to the callback's data.
-* @param TmrCtrNumber is the ID of the timer counter which a user-defined
-* callback would normally operate on.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void XTmrCtr_StubCallback(void *CallBackRef, u8 TmrCtrNumber)
-{
- Xil_AssertVoid(CallBackRef != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
-}
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr.h
deleted file mode 100644
index f30de60bc2a553deedbbf8ed5b1bbc0827125070..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr.h
-* @addtogroup tmrctr_v4_4
-* @{
-* @details
-*
-* The Xilinx timer/counter component. This component supports the Xilinx
-* timer/counter. More detailed description of the driver operation can
-* be found in the xtmrctr.c file.
-*
-* The Xilinx timer/counter supports the following features:
-* - Polled mode.
-* - Interrupt driven mode
-* - enabling and disabling specific timers
-* - PWM operation
-* - Cascade Operation (This is to be used for getting a 64 bit timer and this
-* feature is present in the latest versions of the axi_timer IP)
-*
-* The driver does not currently support the PWM operation of the device.
-*
-* The timer counter operates in 2 primary modes, compare and capture. In
-* either mode, the timer counter may count up or down, with up being the
-* default.
-*
-* Compare mode is typically used for creating a single time period or multiple
-* repeating time periods in the auto reload mode, such as a periodic interrupt.
-* When started, the timer counter loads an initial value, referred to as the
-* compare value, into the timer counter and starts counting down or up. The
-* timer counter expires when it rolls over/under depending upon the mode of
-* counting. An external compare output signal may be configured such that a
-* pulse is generated with this signal when it hits the compare value.
-*
-* Capture mode is typically used for measuring the time period between
-* external events. This mode uses an external capture input signal to cause
-* the value of the timer counter to be captured. When started, the timer
-* counter loads an initial value, referred to as the compare value,
-
-* The timer can be configured to either cause an interrupt when the count
-* reaches the compare value in compare mode or latch the current count
-* value in the capture register when an external input is asserted
-* in capture mode. The external capture input can be enabled/disabled using the
-* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
-* drive an external output when the compare value is reached in the count
-* register The external compare output can be enabled/disabled using the
-* XTmrCtr_SetOptions function.
-*
-* <b>Interrupts</b>
-*
-* It is the responsibility of the application to connect the interrupt
-* handler of the timer/counter to the interrupt source. The interrupt
-* handler function, XTmrCtr_InterruptHandler, is visible such that the user
-* can connect it to the interrupt source. Note that this interrupt handler
-* does not provide interrupt context save and restore processing, the user
-* must perform this processing.
-*
-* The driver services interrupts and passes timeouts to the upper layer
-* software through callback functions. The upper layer software must register
-* its callback functions during initialization. The driver requires callback
-* functions for timers.
-*
-* @note
-* The default settings for the timers are:
-* - Interrupt generation disabled
-* - Count up mode
-* - Compare mode
-* - Hold counter (will not reload the timer)
-* - External compare output disabled
-* - External capture input disabled
-* - Pulse width modulation disabled
-* - Timer disabled, waits for Start function to be called
-* <br><br>
-* A timer counter device may contain multiple timer counters. The symbol
-* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
-* The device currently contains 2 timer counters.
-* <br><br>
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta 03/21/07 Updated to new coding style.
-* 1.11a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-* for naming consistency (CR 559142).
-* 2.02a sdm 09/28/10 Updated the driver tcl to generate the xparameters
-* for the timer clock frequency (CR 572679).
-* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further
-* processing for CR 584557.
-* 2.04a sdm 07/12/11 Added support for cascade mode operation.
-* The cascade mode of operation is present in the latest
-* versions of the axi_timer IP. Please check the HW
-* Datasheet to see whether this feature is present in the
-* version of the IP that you are using.
-* 2.05a adk 15/05/13 Fixed the CR:693066
-* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-* XTmrCtr instance structure.
-* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-* the XTmrCtr_Start function.
-* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-* There will be no Initialization done in the
-* XTmrCtr_Initialize if both the timers have already started and
-* the XST_DEVICE_IS_STARTED Status is returned.
-* Removed the logic in the XTmrCtr_Initialize function
-* which was checking the Register Value to know whether
-* a timer has started or not.
-* 3.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.0 als 09/30/15 Updated initialization API.
-* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
-* Changed the prototype of XTmrCtr_CfgInitialize API.
-* 4.2 nsk 15/09/16 Updated tcl, to get correct device id for canonical defines,
-* when there exist more than one timer perepheral
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of tmrctr in xparameters.h
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_H /* prevent circular inclusions */
-#define XTMRCTR_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xtmrctr_l.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name Configuration options
- * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
- * @{
- */
-/**
- * Used to configure the timer counter device.
- * <pre>
- * XTC_CASCADE_MODE_OPTION Enables the Cascade Mode only valid for TCSRO.
- * XTC_ENABLE_ALL_OPTION Enables all timer counters at once.
- * XTC_DOWN_COUNT_OPTION Configures the timer counter to count down from
- * start value, the default is to count up.
- * XTC_CAPTURE_MODE_OPTION Configures the timer to capture the timer
- * counter value when the external capture line is
- * asserted. The default mode is compare mode.
- * XTC_INT_MODE_OPTION Enables the timer counter interrupt output.
- * XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer counter to
- * reload from the compare value. The default mode
- * causes the timer counter to hold when the
- * compare value is hit.
- * In capture mode, configures the timer counter to
- * not hold the previous capture value if a new
- * event occurs. The default mode cause the timer
- * counter to hold the capture value until
- * recognized.
- * XTC_EXT_COMPARE_OPTION Enables the external compare output signal.
- * </pre>
- */
-#define XTC_CASCADE_MODE_OPTION 0x00000080UL
-#define XTC_ENABLE_ALL_OPTION 0x00000040UL
-#define XTC_DOWN_COUNT_OPTION 0x00000020UL
-#define XTC_CAPTURE_MODE_OPTION 0x00000010UL
-#define XTC_INT_MODE_OPTION 0x00000008UL
-#define XTC_AUTO_RELOAD_OPTION 0x00000004UL
-#define XTC_EXT_COMPARE_OPTION 0x00000002UL
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Register base address */
- u32 SysClockFreqHz; /**< The AXI bus clock frequency */
-} XTmrCtr_Config;
-
-/**
- * Signature for the callback function.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the
- * upper layer when the callback is invoked. Its type is
- * unimportant to the driver, so it is a void pointer.
- * @param TmrCtrNumber is the number of the timer/counter within the
- * device. The device typically contains at least two
- * timer/counters. The timer number is a zero based number with a
- * range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
- */
-typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
-
-
-/**
- * Timer/Counter statistics
- */
-typedef struct {
- u32 Interrupts; /**< The number of interrupts that have occurred */
-} XTmrCtrStats;
-
-/**
- * The XTmrCtr driver instance data. The user is required to allocate a
- * variable of this type for every timer/counter device in the system. A
- * pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XTmrCtr_Config Config; /**< Core configuration. */
- XTmrCtrStats Stats; /**< Component Statistics */
- UINTPTR BaseAddress; /**< Base address of registers */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */
- u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */
-
- XTmrCtr_Handler Handler; /**< Callback function */
- void *CallBackRef; /**< Callback reference for handler */
-} XTmrCtr;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* Required functions, in file xtmrctr.c */
-void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
- UINTPTR EffectiveAddr);
-int XTmrCtr_InitHw(XTmrCtr *InstancePtr);
-int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
-void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
- u32 ResetValue);
-u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/* Lookup configuration in xtmrctr_sinit.c */
-XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
-
-/* Functions for options, in file xtmrctr_options.c */
-void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
-u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/* Functions for statistics, in file xtmrctr_stats.c */
-void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
-void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
-
-/* Functions for self-test, in file xtmrctr_selftest.c */
-int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/* Functions for interrupts, in file xtmrctr_intr.c */
-void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
- void *CallBackRef);
-void XTmrCtr_InterruptHandler(void *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c
deleted file mode 100644
index 1857fbc41aceb851b414d9ab56f861a8c419f0ff..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c
+++ /dev/null
@@ -1,56 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xtmrctr.h"
-
-/*
-* The configuration table for devices
-*/
-
-XTmrCtr_Config XTmrCtr_ConfigTable[XPAR_XTMRCTR_NUM_INSTANCES] =
-{
- {
- XPAR_AXI_TIMER_0_DEVICE_ID,
- XPAR_AXI_TIMER_0_BASEADDR,
- XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_i.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_i.h
deleted file mode 100644
index b806f81f5693130465f7005a65d5a91380fa94ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_i.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_i.h
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* This file contains data which is shared between files internal to the
-* XTmrCtr component. It is intended for internal use only.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 _m is removed from all the macro definitions.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_I_H /* prevent circular inclusions */
-#define XTMRCTR_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-extern u8 XTmrCtr_Offsets[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_intr.c
deleted file mode 100644
index f48cd68c526f1b688095be27e9e1a53f7ec3ca76..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_intr.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_intr.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* Contains interrupt-related functions for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further
-* processing for CR 584557.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr.h"
-
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Sets the timer callback function, which the driver calls when the specified
-* timer times out.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance .
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note
-*
-* The handler is called within interrupt context so the function that is
-* called should either be short or pass the more extensive processing off
-* to another task to allow the interrupt to return and normal processing
-* to continue.
-*
-******************************************************************************/
-void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
- void *CallBackRef)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = FuncPtr;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* Interrupt Service Routine (ISR) for the driver. This function only performs
-* processing for the device and does not save and restore the interrupt context.
-*
-* @param InstancePtr contains a pointer to the timer/counter instance for
-* the interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_InterruptHandler(void *InstancePtr)
-{
- XTmrCtr *TmrCtrPtr = NULL;
- u8 TmrCtrNumber;
- u32 ControlStatusReg;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Convert the non-typed pointer to an timer/counter instance pointer
- * such that there is access to the timer/counter
- */
- TmrCtrPtr = (XTmrCtr *) InstancePtr;
-
- /*
- * Loop thru each timer counter in the device and call the callback
- * function for each timer which has caused an interrupt
- */
- for (TmrCtrNumber = 0;
- TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) {
-
- ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET);
- /*
- * Check if interrupt is enabled
- */
- if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) {
-
- /*
- * Check if timer expired and interrupt occured
- */
- if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) {
- /*
- * Increment statistics for the number of
- * interrupts and call the callback to handle
- * any application specific processing
- */
- TmrCtrPtr->Stats.Interrupts++;
- TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef,
- TmrCtrNumber);
- /*
- * Read the new Control/Status Register content.
- */
- ControlStatusReg =
- XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET);
- /*
- * If in compare mode and a single shot rather
- * than auto reload mode then disable the timer
- * and reset it such so that the interrupt can
- * be acknowledged, this should be only temporary
- * till the hardware is fixed
- */
- if (((ControlStatusReg &
- XTC_CSR_AUTO_RELOAD_MASK) == 0) &&
- ((ControlStatusReg &
- XTC_CSR_CAPTURE_MODE_MASK)== 0)) {
- /*
- * Disable the timer counter and
- * reset it such that the timer
- * counter is loaded with the
- * reset value allowing the
- * interrupt to be acknowledged
- */
- ControlStatusReg &=
- ~XTC_CSR_ENABLE_TMR_MASK;
-
- XTmrCtr_WriteReg(
- TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg |
- XTC_CSR_LOAD_MASK);
-
- /*
- * Clear the reset condition,
- * the reset bit must be
- * manually cleared by a 2nd write
- * to the register
- */
- XTmrCtr_WriteReg(
- TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg);
- }
-
- /*
- * Acknowledge the interrupt by clearing the
- * interrupt bit in the timer control status
- * register, this is done after calling the
- * handler so the application could call
- * IsExpired, the interrupt is cleared by
- * writing a 1 to the interrupt bit of the
- * register without changing any of the other
- * bits
- */
- XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg |
- XTC_CSR_INT_OCCURED_MASK);
- }
- }
- }
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_l.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_l.c
deleted file mode 100644
index a6f59563601ed0414a2ae5ba1520bb44a3127cdc..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_l.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_l.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr_l.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/* The following table contains the offset from the base address of a timer
- * counter device for each timer counter. A single device may contain multiple
- * timer counters and the functions specify which one to operate on.
- */
-u8 XTmrCtr_Offsets[] = { 0, XTC_TIMER_COUNTER_OFFSET };
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_l.h
deleted file mode 100644
index 5842f5e9422617d01fa092a395d46bfed26e5fd5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_l.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_l.h
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* High-level driver functions are defined in xtmrctr.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-* for naming consistency (CR 559142).
-* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the
-* cascade mode operation.
-* The cascade mode of operation is present in the latest
-* versions of the axi_timer IP. Please check the HW
-* Datasheet to see whether this feature is present in the
-* version of the IP that you are using.
-* 4.4 mus 07/21/17 Updated XTmrCtr_DisableIntr macro to not to clear
-* T0INT flag
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_L_H /* prevent circular inclusions */
-#define XTMRCTR_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * Defines the number of timer counters within a single hardware device. This
- * number is not currently parameterized in the hardware but may be in the
- * future.
- */
-#define XTC_DEVICE_TIMER_COUNT 2
-
-/* Each timer counter consumes 16 bytes of address space */
-
-#define XTC_TIMER_COUNTER_OFFSET 16
-
-/** @name Register Offset Definitions
- * Register offsets within a timer counter, there are multiple
- * timer counters within a single device
- * @{
- */
-
-#define XTC_TCSR_OFFSET 0 /**< Control/Status register */
-#define XTC_TLR_OFFSET 4 /**< Load register */
-#define XTC_TCR_OFFSET 8 /**< Timer counter register */
-
-/* @} */
-
-/** @name Control Status Register Bit Definitions
- * Control Status Register bit masks
- * Used to configure the timer counter device.
- * @{
- */
-
-#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */
-#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer
- counters */
-#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width
- Modulation */
-#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an
- interrupt has occured.
- If set and '1' is
- written to this bit
- position, bit is
- cleared. */
-#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the
- specific timer */
-#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt
- output. */
-#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using
- the load value provided
- earlier in the Load
- Register,
- XTC_TLR_OFFSET. */
-#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode,
- configures
- the timer counter to
- reload from the
- Load Register. The
- default mode
- causes the timer counter
- to hold when the compare
- value is hit. In capture
- mode, configures the
- timer counter to not
- hold the previous
- capture value if a new
- event occurs. The
- default mode cause the
- timer counter to hold
- the capture value until
- recognized. */
-#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the
- external input
- to the timer counter. */
-#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the
- external generate output
- for the timer. */
-#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer
- counter to count down
- from start value, the
- default is to count
- up.*/
-#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to
- capture the timer
- counter value when the
- external capture line is
- asserted. The default
- mode is compare mode.*/
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-extern u8 XTmrCtr_Offsets[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Read one of the timer counter registers.
-*
-* @param BaseAddress contains the base address of the timer counter
-* device.
-* @param TmrCtrNumber contains the specific timer counter within the
-* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegOffset contains the offset from the 1st register of the timer
-* counter to select the specific register of the timer counter.
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
- unsigned RegOffset);
-******************************************************************************/
-#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset))
-
-#ifndef XTimerCtr_ReadReg
-#define XTimerCtr_ReadReg XTmrCtr_ReadReg
-#endif
-
-/*****************************************************************************/
-/**
-* Write a specified value to a register of a timer counter.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegOffset contain the offset from the 1st register of the timer
-* counter to select the specific register of the timer counter.
-* @param ValueToWrite is the 32 bit value to be written to the register.
-*
-* @note C-Style signature:
-* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
-* unsigned RegOffset, u32 ValueToWrite);
-******************************************************************************/
-#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset)), (ValueToWrite))
-
-/****************************************************************************/
-/**
-*
-* Set the Control Status Register of a timer counter to the specified value.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegisterValue is the 32 bit value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
-* u8 TmrCtrNumber,u32 RegisterValue);
-*****************************************************************************/
-#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the Control Status Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
-* u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Get the Timer Counter Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
-* u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
-
-/****************************************************************************/
-/**
-*
-* Set the Load Register of a timer counter to the specified value.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegisterValue is the 32 bit value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
-* u32 RegisterValue);
-*****************************************************************************/
-#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the Load Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \
-XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable a timer counter such that it starts running.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
- XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable a timer counter such that it stops running.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
- XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
-
-/****************************************************************************/
-/**
-*
-* Enable the interrupt for a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the interrupt for a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) & ~ (XTC_CSR_ENABLE_INT_MASK \
- | XTC_CSR_INT_OCCURED_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Cause the timer counter to load it's Timer Counter Register with the value
-* in the Load Register.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
- u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
- XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Determine if a timer counter event has occurred. Events are defined to be
-* when a capture has occurred or the counter has roller over.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @note C-Style signature:
-* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \
- ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \
- XTC_CSR_INT_OCCURED_MASK)
-
-/************************** Function Prototypes ******************************/
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_options.c
deleted file mode 100644
index fa05efa99277ce49573ff1c2a7311b4603be3837..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_options.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_options.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* Contains configuration options functions for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.04a sdm 07/12/11 Added support for the cascade mode operation.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr.h"
-#include "xtmrctr_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/*
- * The following data type maps an option to a register mask such that getting
- * and setting the options may be table driven.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} Mapping;
-
-/*
- * Create the table which contains options which are to be processed to get/set
- * the options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-static Mapping OptionsTable[] = {
- {XTC_CASCADE_MODE_OPTION, XTC_CSR_CASC_MASK},
- {XTC_ENABLE_ALL_OPTION, XTC_CSR_ENABLE_ALL_MASK},
- {XTC_DOWN_COUNT_OPTION, XTC_CSR_DOWN_COUNT_MASK},
- {XTC_CAPTURE_MODE_OPTION, XTC_CSR_CAPTURE_MODE_MASK |
- XTC_CSR_EXT_CAPTURE_MASK},
- {XTC_INT_MODE_OPTION, XTC_CSR_ENABLE_INT_MASK},
- {XTC_AUTO_RELOAD_OPTION, XTC_CSR_AUTO_RELOAD_MASK},
- {XTC_EXT_COMPARE_OPTION, XTC_CSR_EXT_GENERATE_MASK}
-};
-
-/* Create a constant for the number of entries in the table */
-
-#define XTC_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
-
-/*****************************************************************************/
-/**
-*
-* Enables the specified options for the specified timer counter. This function
-* sets the options without regard to the current options of the driver. To
-* prevent a loss of the current options, the user should call
-* XTmrCtr_GetOptions() prior to this function and modify the retrieved options
-* to pass into this function to prevent loss of the current options.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param Options contains the desired options to be set or cleared.
-* Setting the option to '1' enables the option, clearing the to
-* '0' disables the option. The options are bit masks such that
-* multiple options may be set or cleared. The options are
-* described in xtmrctr.h.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options)
-{
- u32 CounterControlReg = 0;
- u32 Index;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop through the Options table, turning the enable on or off
- * depending on whether the bit is set in the incoming Options flag.
- */
-
- for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
- if (Options & OptionsTable[Index].Option) {
-
- /*
- * Turn the option on
- */
- CounterControlReg |= OptionsTable[Index].Mask;
- }
- else {
- /*
- * Turn the option off
- */
- CounterControlReg &= ~OptionsTable[Index].Mask;
- }
- }
-
- /*
- * Write out the updated value to the actual register
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, CounterControlReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the options for the specified timer counter.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return
-*
-* The currently set options. An option which is set to a '1' is enabled and
-* set to a '0' is disabled. The options are bit masks such that multiple
-* options may be set or cleared. The options are described in xtmrctr.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
-
- u32 Options = 0;
- u32 CounterControlReg;
- u32 Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the current contents of the control status register to allow
- * the current options to be determined
- */
- CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Loop through the Options table, turning the enable on or off
- * depending on whether the bit is set in the current register settings.
- */
- for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
- if (CounterControlReg & OptionsTable[Index].Mask) {
- Options |= OptionsTable[Index].Option; /* turn it on */
- }
- else {
- Options &= ~OptionsTable[Index].Option; /* turn it off */
- }
- }
-
- return Options;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_selftest.c
deleted file mode 100644
index 09cbaba52ef99ae0819da2a7b4cfae31fd6ab809..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_selftest.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_selftest.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* Contains diagnostic/self-test functions for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "xtmrctr.h"
-#include "xtmrctr_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. This test verifies that the specified
-* timer counter of the device can be enabled and increments.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return
-* - XST_SUCCESS if self-test was successful
-* - XST_FAILURE if the timer is not incrementing.
-*
-* @note
-*
-* This is a destructive test using the provided timer. The current settings
-* of the timer are returned to the initialized values and all settings at the
-* time this function is called are overwritten.
-*
-******************************************************************************/
-int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 TimerCount1 = 0;
- u32 TimerCount2 = 0;
- u16 Count = 0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Set the Capture register to 0
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TLR_OFFSET, 0);
-
- /*
- * Reset the timer and the interrupt
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
-
- /*
- * Set the control/status register to enable timer
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, XTC_CSR_ENABLE_TMR_MASK);
-
- /*
- * Read the timer
- */
- TimerCount1 = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCR_OFFSET);
- /*
- * Make sure timer is incrementing if the Count rolls over to zero
- * and the timer still has not incremented an error is returned
- */
-
- do {
- TimerCount2 = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCR_OFFSET);
- Count++;
- }
- while ((TimerCount1 == TimerCount2) && (Count != 0));
-
- /*
- * Reset the timer and the interrupt
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
-
- /*
- * Set the control/status register to 0 to complete initialization
- * this disables the timer completely and allows it to be used again
- */
-
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, 0);
-
- if (TimerCount1 == TimerCount2) {
- return XST_FAILURE;
- }
- else {
- return XST_SUCCESS;
- }
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_sinit.c
deleted file mode 100644
index c1e2fdf03609bc2735b9749167b2f91bf561f82d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_sinit.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_sinit.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* This file contains static initialization methods for the XTmrCtr driver.
-*
-* @note None.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 4.0 als 09/30/15 Creation of this file. Moved LookupConfig from xtmrctr.c.
-* 4.4 mn 07/31/17 Resolve Compilation warning
-* </pre>
-*
-******************************************************************************/
-
-/******************************* Include Files *******************************/
-
-#include "xparameters.h"
-#include "xtmrctr.h"
-
-/************************** Constant Definitions *****************************/
-
-#ifndef XPAR_XTMRCTR_NUM_INSTANCES
-#define XPAR_XTMRCTR_NUM_INSTANCES 0
-#endif
-
-/*************************** Variable Declarations ***************************/
-
-/* A table of configuration structures containing the configuration information
- * for each timer core in the system. */
-extern XTmrCtr_Config XTmrCtr_ConfigTable[XPAR_XTMRCTR_NUM_INSTANCES];
-
-/**************************** Function Definitions ***************************/
-
-/*****************************************************************************/
-/**
-* Looks up the device configuration based on the unique device ID. The table
-* TmrCtr_ConfigTable contains the configuration info for each device in the
-* system.
-*
-* @param DeviceId is the unique device ID to search for in the config
-* table.
-*
-* @return A pointer to the configuration that matches the given device
-* ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId)
-{
- XTmrCtr_Config *CfgPtr = NULL;
- u16 Index;
-
- for (Index = 0; Index < XPAR_XTMRCTR_NUM_INSTANCES; Index++) {
- if (XTmrCtr_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XTmrCtr_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_stats.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_stats.c
deleted file mode 100644
index a157eea5e3a88f118beaee871081d5c0478cf032..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_stats.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_stats.c
-* @addtogroup tmrctr_v4_4
-* @{
-*
-* Contains function to get and clear statistics for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release.
-* 1.10b mta 03/21/07 Updated for new coding style.
-* 2.00a ktn 10/30/09 Updated to use HAL API's.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Get a copy of the XTmrCtrStats structure, which contains the current
-* statistics for this driver.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param StatsPtr is a pointer to a XTmrCtrStats structure which will get
-* a copy of current statistics.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(StatsPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- StatsPtr->Interrupts = InstancePtr->Stats.Interrupts;
-}
-
-/*****************************************************************************/
-/**
-*
-* Clear the XTmrCtrStats structure for this driver.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_ClearStats(XTmrCtr * InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Stats.Interrupts = 0;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile
deleted file mode 100644
index 88b1e625cc135e2c0a0a0ebd6a3a5aca68ce7639..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xuartps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling uartps"
-
-xuartps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xuartps_includes
-
-xuartps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
deleted file mode 100644
index c33ec5481ebb744b1384eb4881ef7a76d98dbb9b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
+++ /dev/null
@@ -1,645 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps.c
-* @addtogroup uartps_v3_5
-* @{
-*
-* This file contains the implementation of the interface functions for XUartPs
-* driver. Refer to the header file xuartps.h for more detailed information.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-/* The following constant defines the amount of error that is allowed for
- * a specified baud rate. This error is the difference between the actual
- * baud rate that will be generated using the specified clock and the
- * desired baud rate.
- */
-#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
- u32 ByteCount);
-
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* Initializes a specific XUartPs instance such that it is ready to be used.
-* The data format of the device is setup for 8 data bits, 1 stop bit, and no
-* parity by default. The baud rate is set to a default value specified by
-* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
-* receive FIFO threshold is set for 8 bytes. The default operating mode of the
-* driver is polled mode.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param Config is a reference to a structure containing information
-* about a specific XUartPs driver.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, pass in the physical
-* address instead.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-* - XST_UART_BAUD_ERROR if the baud rate is not possible because
-* the inputclock frequency is not divisible with an acceptable
-* amount of error
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* All interrupts are disabled.
-*
-*****************************************************************************/
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr)
-{
- s32 Status;
- u32 ModeRegister;
- u32 BaudRate;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Config != NULL);
-
- /* Setup the driver instance using passed in parameters */
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = Config->InputClockHz;
- InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
-
- /* Initialize other instance data to default values */
- InstancePtr->Handler = XUartPs_StubHandler;
-
- InstancePtr->SendBuffer.NextBytePtr = NULL;
- InstancePtr->SendBuffer.RemainingBytes = 0U;
- InstancePtr->SendBuffer.RequestedBytes = 0U;
-
- InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
- InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
- InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
-
- /* Initialize the platform data */
- InstancePtr->Platform = XGetPlatform_Info();
-
- InstancePtr->is_rxbs_error = 0U;
-
- /* Flag that the driver instance is ready to use */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- /*
- * Set the default baud rate here, can be changed prior to
- * starting the device
- */
- BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
- Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
- if (Status != (s32)XST_SUCCESS) {
- InstancePtr->IsReady = 0U;
- } else {
-
- /*
- * Set up the default data format: 8 bit data, 1 stop bit, no
- * parity
- */
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Mask off what's already there */
- ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
- (u32)XUARTPS_MR_STOPMODE_MASK |
- (u32)XUARTPS_MR_PARITY_MASK));
-
- /* Set the register value to the desired data format */
- ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
- (u32)XUARTPS_MR_STOPMODE_1_BIT |
- (u32)XUARTPS_MR_PARITY_NONE);
-
- /* Write the mode register out */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- /* Set the RX FIFO trigger at 8 data bytes. */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET, 0x08U);
-
- /* Set the RX timeout to 1, which will be 4 character time */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET, 0x01U);
-
- /* Disable all interrupts, polled mode is the default */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- Status = XST_SUCCESS;
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sends the specified buffer using the device in either
-* polled or interrupt driven mode. This function is non-blocking, if the device
-* is busy sending data, it will return and indicate zero bytes were sent.
-* Otherwise, it fills the TX FIFO as much as it can, and return the number of
-* bytes sent.
-*
-* In a polled mode, this function will only send as much data as TX FIFO can
-* buffer. The application may need to call it repeatedly to send the entire
-* buffer.
-*
-* In interrupt mode, this function will start sending the specified buffer,
-* then the interrupt handler will continue sending data until the entire
-* buffer has been sent. A callback function, as specified by the application,
-* will be called to indicate the completion of sending.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param BufferPtr is pointer to a buffer of data to be sent.
-* @param NumBytes contains the number of bytes to be sent. A value of
-* zero will stop a previous send operation that is in progress
-* in interrupt mode. Any data that was already put into the
-* transmit FIFO will be sent.
-*
-* @return The number of bytes actually sent.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called with
-* a value of zero to stop an operation that is already in progress.
-* <br><br>
-*
-*****************************************************************************/
-u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
- u32 NumBytes)
-{
- u32 BytesSent;
-
- /* Asserts validate the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the UART transmit interrupts to allow this call to stop a
- * previous operation that may be interrupt driven.
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
-
- /* Setup the buffer parameters */
- InstancePtr->SendBuffer.RequestedBytes = NumBytes;
- InstancePtr->SendBuffer.RemainingBytes = NumBytes;
- InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
-
- /*
- * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
- * filling the TX FIFO.
- */
- BytesSent = XUartPs_SendBuffer(InstancePtr);
-
- return BytesSent;
-}
-
-/****************************************************************************/
-/**
-*
-* This function attempts to receive a specified number of bytes of data
-* from the device and store it into the specified buffer. This function works
-* for both polled or interrupt driven modes. It is non-blocking.
-*
-* In a polled mode, this function will only receive the data already in the
-* RX FIFO. The application may need to call it repeatedly to receive the
-* entire buffer. Polled mode is the default mode of operation for the device.
-*
-* In interrupt mode, this function will start the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue receiving data
-* until the entire buffer has been received. A callback function, as specified
-* by the application, will be called to indicate the completion of the
-* receiving or error conditions.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param BufferPtr is pointer to buffer for data to be received into
-* @param NumBytes is the number of bytes to be received. A value of zero
-* will stop a previous receive operation that is in progress in
-* interrupt mode.
-*
-* @return The number of bytes received.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called
-* with a value of zero to stop an operation that is already in progress.
-*
-*****************************************************************************/
-u32 XUartPs_Recv(XUartPs *InstancePtr,
- u8 *BufferPtr, u32 NumBytes)
-{
- u32 ReceivedCount;
- u32 ImrRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable all the interrupts.
- * This stops a previous operation that may be interrupt driven
- */
- ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- /* Setup the buffer parameters */
- InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
- InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
- InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
-
- /* Receive the data from the device */
- ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
-
- /* Restore the interrupt state */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
- ImrRegister);
-
- return ReceivedCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function sends a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function for the XUartPs driver such that it may be called from a shell
-* function that sets up the buffer or from an interrupt handler.
-*
-* This function sends the specified buffer in either polled or interrupt
-* driven modes. This function is non-blocking.
-*
-* In a polled mode, this function only sends as much data as the TX FIFO
-* can buffer. The application may need to call it repeatedly to send the
-* entire buffer.
-*
-* In interrupt mode, this function starts the sending of the buffer, if not
-* the entire buffer has been sent, then the interrupt handler continues the
-* sending until the entire buffer has been sent. A callback function, as
-* specified by the application, will be called to indicate the completion of
-* sending.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return The number of bytes actually sent
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
-{
- u32 SentCount = 0U;
- u32 ImrRegister;
-
- /*
- * If the TX FIFO is full, send nothing.
- * Otherwise put bytes into the TX FIFO unil it is full, or all of the
- * data has been put into the FIFO.
- */
- while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
- (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
-
- /* Fill the FIFO from the buffer */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FIFO_OFFSET,
- ((u32)InstancePtr->SendBuffer.
- NextBytePtr[SentCount]));
-
- /* Increment the send count. */
- SentCount++;
- }
-
- /* Update the buffer to reflect the bytes that were sent from it */
- InstancePtr->SendBuffer.NextBytePtr += SentCount;
- InstancePtr->SendBuffer.RemainingBytes -= SentCount;
-
- /*
- * If interrupts are enabled as indicated by the receive interrupt, then
- * enable the TX FIFO empty interrupt, so further action can be taken
- * for this sending.
- */
- ImrRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
- ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
- ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IER_OFFSET,
- ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
- }
-
- return SentCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function receives a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function, and it may be called from a shell function that sets up the buffer
-* or from an interrupt handler.
-*
-* This function attempts to receive a specified number of bytes from the
-* device and store it into the specified buffer. This function works for
-* either polled or interrupt driven modes. It is non-blocking.
-*
-* In polled mode, this function only receives as much data as in the RX FIFO.
-* The application may need to call it repeatedly to receive the entire buffer.
-* Polled mode is the default mode for the driver.
-*
-* In interrupt mode, this function starts the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue until the
-* entire buffer has been received. A callback function, as specified by the
-* application, will be called to indicate the completion of the receiving or
-* error conditions.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return The number of bytes received.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
-{
- u32 CsrRegister;
- u32 ReceivedCount = 0U;
- u32 ByteStatusValue, EventData;
- u32 Event;
-
- /*
- * Read the Channel Status Register to determine if there is any data in
- * the RX FIFO
- */
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- /*
- * Loop until there is no more data in RX FIFO or the specified
- * number of bytes has been received
- */
- while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
- (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
-
- if (InstancePtr->is_rxbs_error) {
- ByteStatusValue = XUartPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XUARTPS_RXBS_OFFSET);
- if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
- EventData = ByteStatusValue;
- Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
- /*
- * Call the application handler to indicate that there is a receive
- * error or a break interrupt, if the application cares about the
- * error it call a function to get the last errors.
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- Event, EventData);
- }
- }
-
- InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
- XUartPs_ReadReg(InstancePtr->Config.
- BaseAddress,
- XUARTPS_FIFO_OFFSET);
-
- ReceivedCount++;
-
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
- }
- InstancePtr->is_rxbs_error = 0;
- /*
- * Update the receive buffer to reflect the number of bytes just
- * received
- */
- if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
- InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
- }
- InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
-
- return ReceivedCount;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the baud rate for the device. Checks the input value for
-* validity and also verifies that the requested rate can be configured to
-* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
-* If the provided rate is not possible, the current setting is unchanged.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param BaudRate to be set
-*
-* @return
-* - XST_SUCCESS if everything configured as expected
-* - XST_UART_BAUD_ERROR if the requested rate is not available
-* because there was too much error
-*
-* @note None.
-*
-*****************************************************************************/
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
-{
- u32 IterBAUDDIV; /* Iterator for available baud divisor values */
- u32 BRGR_Value; /* Calculated value for baud rate generator */
- u32 CalcBaudRate; /* Calculated baud rate */
- u32 BaudError; /* Diff between calculated and requested baud rate */
- u32 Best_BRGR = 0U; /* Best value for baud rate generator */
- u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
- u32 Best_Error = 0xFFFFFFFFU;
- u32 PercentError;
- u32 ModeReg;
- u32 InputClk;
-
- /* Asserts validate the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
- Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
-
- /*
- * Make sure the baud rate is not impossilby large.
- * Fastest possible baud rate is Input Clock / 2.
- */
- if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
- return XST_UART_BAUD_ERROR;
- }
- /* Check whether the input clock is divided by 8 */
- ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- InputClk = InstancePtr->Config.InputClockHz;
- if(ModeReg & XUARTPS_MR_CLKSEL) {
- InputClk = InstancePtr->Config.InputClockHz / 8;
- }
-
- /*
- * Determine the Baud divider. It can be 4to 254.
- * Loop through all possible combinations
- */
- for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
-
- /* Calculate the value for BRGR register */
- BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
-
- /* Calculate the baud rate from the BRGR value */
- CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
-
- /* Avoid unsigned integer underflow */
- if (BaudRate > CalcBaudRate) {
- BaudError = BaudRate - CalcBaudRate;
- }
- else {
- BaudError = CalcBaudRate - BaudRate;
- }
-
- /* Find the calculated baud rate closest to requested baud rate. */
- if (Best_Error > BaudError) {
-
- Best_BRGR = BRGR_Value;
- Best_BAUDDIV = IterBAUDDIV;
- Best_Error = BaudError;
- }
- }
-
- /* Make sure the best error is not too large. */
- PercentError = (Best_Error * 100) / BaudRate;
- if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
- return XST_UART_BAUD_ERROR;
- }
-
- /* Disable TX and RX to avoid glitches when setting the baud rate. */
- XUartPs_DisableUart(InstancePtr);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
-
- /* RX and TX SW reset */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
- XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
-
- /* Enable device */
- XUartPs_EnableUart(InstancePtr);
-
- InstancePtr->BaudRate = BaudRate;
-
- return XST_SUCCESS;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is a stub handler that is the default handler such that if the
-* application has not set the handler when interrupts are enabled, this
-* function will be called.
-*
-* @param CallBackRef is unused by this function.
-* @param Event is unused by this function.
-* @param ByteCount is unused by this function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
- u32 ByteCount)
-{
- (void) CallBackRef;
- (void) Event;
- (void) ByteCount;
- /* Assert occurs always since this is a stub and should never be called */
- Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
deleted file mode 100644
index 33758c23b3733d2ffce9e1b8a27bfbdc22e0f4d1..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_5
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* <b>Initialization & Configuration</b>
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the parameter EffectiveAddr should be the
-* virtual address.
-*
-* <b>Baud Rate</b>
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. Ther input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-* <pre>
-* baud_rate = input_clock / (bgen * (bdiv + 1)
-* </pre>
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* <b>Interrupts</b>
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* <b>Data Transfer</b>
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-*
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 921600U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
deleted file mode 100644
index 6ea3eb7688466ccec2d0c67260a53ec5ea942f8d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
+++ /dev/null
@@ -1,63 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xuartps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_UART_0_DEVICE_ID,
- XPAR_PS7_UART_0_BASEADDR,
- XPAR_PS7_UART_0_UART_CLK_FREQ_HZ,
- XPAR_PS7_UART_0_HAS_MODEM
- },
- {
- XPAR_PS7_UART_1_DEVICE_ID,
- XPAR_PS7_UART_1_BASEADDR,
- XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
- XPAR_PS7_UART_1_HAS_MODEM
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
deleted file mode 100644
index 724c3cb40ece5f6cdea32bb885f3d15f2992ed4b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_hw.c
-* @addtogroup uartps_v3_5
-* @{
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.05a hk 08/22/13 Added reset function
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xuartps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function sends one byte using the device. This function operates in
-* polled mode and blocks until the data has been put into the TX FIFO register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param Data contains the byte to be sent.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SendByte(u32 BaseAddress, u8 Data)
-{
- /* Wait until there is space in TX FIFO */
- while (XUartPs_IsTransmitFull(BaseAddress)) {
- ;
- }
-
- /* Write the byte into the TX FIFO */
- XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
-}
-
-/****************************************************************************/
-/**
-*
-* This function receives a byte from the device. It operates in polled mode
-* and blocks until a byte has received.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return The data byte received.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_RecvByte(u32 BaseAddress)
-{
- u32 RecievedByte;
- /* Wait until there is data */
- while (!XUartPs_IsReceiveData(BaseAddress)) {
- ;
- }
- RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
- /* Return the byte received */
- return (u8)RecievedByte;
-}
-
-/****************************************************************************/
-/**
-*
-* This function resets UART
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_ResetHw(u32 BaseAddress)
-{
-
- /* Disable interrupts */
- XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
-
- /* Disable receive and transmit */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
-
- /*
- * Software reset of receive and transmit
- * This clears the FIFO.
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
-
- /* Clear status flags - SW reset wont clear sticky flags. */
- XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
-
- /*
- * Mode register reset value : All zeroes
- * Normal mode, even parity, 1 stop bit
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
- XUARTPS_MR_CHMODE_NORM);
-
- /* Rx and TX trigger register reset values */
- XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
- XUARTPS_RXWM_RESET_VAL);
- XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
- XUARTPS_TXWM_RESET_VAL);
-
- /* Rx timeout disabled by default */
- XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
- XUARTPS_RXTOUT_DISABLE);
-
- /* Baud rate generator and dividor reset values */
- XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
- XUARTPS_BAUDGEN_RESET_VAL);
- XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
- XUARTPS_BAUDDIV_RESET_VAL);
-
- /*
- * Control register reset value -
- * RX and TX are disable by default
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
- (u32)XUARTPS_CR_STOPBRK));
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
deleted file mode 100644
index 9a2bc430544035bcbde490106a1b9b1f2c4c09cd..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
+++ /dev/null
@@ -1,451 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_5
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-* </pre>
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H /* prevent circular inclusions */
-#define XUARTPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
-#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
-#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
-#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
-#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
-#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatabilty, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
-#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress) \
- !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress) \
- ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
deleted file mode 100644
index dff02fd6307c53fb6784df2c60814a4e6c300336..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_intr.c
-* @addtogroup uartps_v3_5
-* @{
-*
-* This file contains the functions for interrupt handling
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-static void ReceiveDataHandler(XUartPs *InstancePtr);
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
-static void ModemHandler(XUartPs *InstancePtr);
-
-
-/* Internal function prototypes implemented in xuartps.c */
-extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-typedef void (*Handler)(XUartPs *InstancePtr);
-
-/****************************************************************************/
-/**
-*
-* This function gets the interrupt mask
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* The current interrupt mask. The mask indicates which interupts
-* are enabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
-{
- /* Assert validates the input argument */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Read the Interrupt Mask register */
- return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the interrupt mask.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param Mask contains the interrupts to be enabled or disabled.
-* A '1' enables an interupt, and a '0' disables.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
-{
- u32 TempMask = Mask;
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
-
- TempMask &= (u32)XUARTPS_IXR_MASK;
-
- /* Write the mask to the IER Register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IER_OFFSET, TempMask);
-
- /* Write the inverse of the Mask to the IDR register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IDR_OFFSET, (~TempMask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param FuncPtr is the pointer to the callback function.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-*
-* @return None.
-*
-* @note
-*
-* There is no assert on the CallBackRef since the driver doesn't know what it
-* is (nor should it)
-*
-*****************************************************************************/
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef)
-{
- /*
- * Asserts validate the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = FuncPtr;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is the interrupt handler for the driver.
-* It must be connected to an interrupt system by the application such that it
-* can be called when an interrupt occurs.
-*
-* @param InstancePtr contains a pointer to the driver instance
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUartPs_InterruptHandler(XUartPs *InstancePtr)
-{
- u32 IsrStatus;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the interrupt ID register to determine which
- * interrupt is active
- */
- IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
-
- IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_ISR_OFFSET);
-
- /* Dispatch an appropriate handler. */
- if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
- (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
- /* Received data interrupt */
- ReceiveDataHandler(InstancePtr);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
- != (u32)0) {
- /* Transmit data interrupt */
- SendDataHandler(InstancePtr, IsrStatus);
- }
-
- /* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
- if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
- (u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
- /* Received Error Status interrupt */
- ReceiveErrorHandler(InstancePtr, IsrStatus);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
- /* Received Timeout interrupt */
- ReceiveTimeoutHandler(InstancePtr);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
- /* Modem status interrupt */
- ModemHandler(InstancePtr);
- }
-
- /* Clear the interrupt status. */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
- IsrStatus);
-
-}
-
-/****************************************************************************/
-/*
-*
-* This function handles interrupts for receive errors which include
-* overrun errors, framing errors, parity errors, and the break interrupt.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
- u32 EventData;
- u32 Event;
-
- InstancePtr->is_rxbs_error = 0;
-
- if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
- (IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
- | (u32)XUARTPS_IXR_FRAMING))) {
- InstancePtr->is_rxbs_error = 1;
- }
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
-
- (void)XUartPs_ReceiveBuffer(InstancePtr);
-
- if (!(InstancePtr->is_rxbs_error)) {
- Event = XUARTPS_EVENT_RECV_ERROR;
- EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes;
-
- /*
- * Call the application handler to indicate that there is a receive
- * error or a break interrupt, if the application cares about the
- * error it call a function to get the last errors.
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- Event,
- EventData);
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the receive timeout interrupt. This interrupt occurs
-* whenever a number of bytes have been present in the RX FIFO and the receive
-* data line has been idle for at lease 4 or more character times, (the timeout
-* is set using XUartPs_SetrecvTimeout() function).
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
-{
- u32 Event;
-
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- (void)XUartPs_ReceiveBuffer(InstancePtr);
- }
-
- /*
- * If there are no more bytes to receive then indicate that this is
- * not a receive timeout but the end of the buffer reached, a timeout
- * normally occurs if # of bytes is not divisible by FIFO threshold,
- * don't rely on previous test of remaining bytes since receive
- * function updates it
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- Event = XUARTPS_EVENT_RECV_TOUT;
- } else {
- Event = XUARTPS_EVENT_RECV_DATA;
- }
-
- /*
- * Call the application handler to indicate that there is a receive
- * timeout or data event
- */
- InstancePtr->Handler(InstancePtr->CallBackRef, Event,
- InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes);
-
-}
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data is in RX FIFO.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveDataHandler(XUartPs *InstancePtr)
-{
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- (void)XUartPs_ReceiveBuffer(InstancePtr);
- }
-
- /* If the last byte of a message was received then call the application
- * handler, this code should not use an else from the previous check of
- * the number of bytes to receive because the call to receive the buffer
- * updates the bytes ramained
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_RECV_DATA,
- (InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes));
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data has been sent, the transmit
-* FIFO is empty (transmitter holding register).
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param IsrStatus is the register value for channel status register
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
-
- /*
- * If there are not bytes to be sent from the specified buffer then disable
- * the transmit interrupt so it will stop interrupting as it interrupts
- * any time the FIFO is empty
- */
- if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IDR_OFFSET,
- ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
-
- /* Call the application handler to indicate the sending is done */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_SENT_DATA,
- InstancePtr->SendBuffer.RequestedBytes -
- InstancePtr->SendBuffer.RemainingBytes);
- }
-
- /* If TX FIFO is empty, send more. */
- else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
- (void)XUartPs_SendBuffer(InstancePtr);
- }
- else {
- /* Else with dummy entry for MISRA-C Compliance.*/
- ;
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles modem interrupts. It does not do any processing
-* except to call the application handler to indicate a modem event.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ModemHandler(XUartPs *InstancePtr)
-{
- u32 MsrRegister;
-
- /*
- * Read the modem status register so that the interrupt is acknowledged
- * and it can be passed to the callback handler with the event
- */
- MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MODEMSR_OFFSET);
-
- /*
- * Call the application handler to indicate the modem status changed,
- * passing the modem status and the event data in the call
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_MODEM,
- MsrRegister);
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
deleted file mode 100644
index 5d8d3017cbf5e34ca05af51d0216d2f542b977d5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
+++ /dev/null
@@ -1,764 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_options.c
-* @addtogroup uartps_v3_5
-* @{
-*
-* The implementation of the options functions for the XUartPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
-* value was not being written to the register.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-/*
- * The following data type is a map from an option to the offset in the
- * register to which it belongs as well as its bit mask in that register.
- */
-typedef struct {
- u16 Option;
- u16 RegisterOffset;
- u32 Mask;
-} Mapping;
-
-/*
- * Create the table which contains options which are to be processed to get/set
- * the options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-
-static Mapping OptionsTable[] = {
- {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
- {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
- {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
- {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
- {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
- {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
- XUARTPS_MODEMCR_RTS},
- {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
- XUARTPS_MODEMCR_DTR},
- {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
-};
-
-/* Create a constant for the number of entries in the table */
-
-#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Gets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simulataneously.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The current options for the UART. The optionss are bit masks that are
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XUartPs_GetOptions(XUartPs *InstancePtr)
-{
- u16 Options = 0U;
- u32 Register;
- u32 Index;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop thru the options table to map the physical options in the
- * registers of the UART to the logical options to be returned
- */
- for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
- Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].
- RegisterOffset);
-
- /*
- * If the bit in the register which correlates to the option
- * is set, then set the corresponding bit in the options,
- * ignoring any bits which are zero since the options variable
- * is initialized to zero
- */
- if ((Register & OptionsTable[Index].Mask) != (u32)0) {
- Options |= OptionsTable[Index].Option;
- }
- }
-
- return Options;
-}
-
-/****************************************************************************/
-/**
-*
-* Sets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simultaneously.
-*
-* The GetOptions function may be called to retrieve the currently enabled
-* options. The result is ORed in the desired new settings to be enabled and
-* ANDed with the inverse to clear the settings to be disabled. The resulting
-* value is then used as the options for the SetOption function call.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param Options contains the options to be set which are bit masks
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
-{
- u32 Index;
- u32 Register;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop thru the options table to map the logical options to the
- * physical options in the registers of the UART.
- */
- for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
-
- /*
- * Read the register which contains option so that the register
- * can be changed without destoying any other bits of the
- * register.
- */
- Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].
- RegisterOffset);
-
- /*
- * If the option is set in the input, then set the corresponding
- * bit in the specified register, otherwise clear the bit in
- * the register.
- */
- if ((Options & OptionsTable[Index].Option) != (u16)0) {
- if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
- Register &= ~XUARTPS_CR_STOPBRK;
- Register |= OptionsTable[Index].Mask;
- }
- else {
- Register &= ~OptionsTable[Index].Mask;
- }
-
- /* Write the new value to the register to set the option */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].RegisterOffset,
- Register);
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the receive FIFO trigger level. The receive trigger
-* level indicates the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The current receive FIFO trigger level. This is a value
-* from 0-31.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
-{
- u8 RtrigRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the value of the FIFO control register so that the threshold
- * can be retrieved, this read takes special register processing
- */
- RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET);
-
- /* Return only the trigger level from the register value */
-
- RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
- return RtrigRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the receive FIFO trigger level. The receive trigger
-* level specifies the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param TriggerLevel contains the trigger level to set.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
-{
- u32 RtrigRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
-
- /*
- * Write the new value for the FIFO control register to it such that the
- * threshold is changed
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET, RtrigRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the modem status from the specified UART. The modem
-* status indicates any changes of the modem signals. This function allows
-* the modem status to be read in a polled mode. The modem status is updated
-* whenever it is read such that reading it twice may not yield the same
-* results.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The modem status which are bit masks that are contained in the file
-* xuartps.h and named XUARTPS_MODEM_*.
-*
-* @note
-*
-* The bit masks used for the modem status are the exact bits of the modem
-* status register with no abstraction.
-*
-*****************************************************************************/
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
-{
- u32 ModemStatusRegister;
- u16 TmpRegister;
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the modem status register to return
- */
- ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MODEMSR_OFFSET);
- TmpRegister = (u16)ModemStatusRegister;
- return TmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function determines if the specified UART is sending data.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if the UART is sending data
-* - FALSE if UART is not sending data
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_IsSending(XUartPs *InstancePtr)
-{
- u32 ChanStatRegister;
- u32 ChanTmpSRegister;
- u32 ActiveResult;
- u32 EmptyResult;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel status register to determine if the transmitter is
- * active
- */
- ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- /*
- * If the transmitter is active, or the TX FIFO is not empty, then indicate
- * that the UART is still sending some data
- */
- ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
- EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
- ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
- (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
-
- return ChanTmpSRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The operational mode is specified by constants defined in xuartps.h. The
-* constants are named XUARTPS_OPER_MODE_*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
-{
- u32 ModeRegister;
- u8 OperMode;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Mode register. */
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
- /* Return the constant */
- switch (ModeRegister) {
- case XUARTPS_MR_CHMODE_NORM:
- OperMode = XUARTPS_OPER_MODE_NORMAL;
- break;
- case XUARTPS_MR_CHMODE_ECHO:
- OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
- break;
- case XUARTPS_MR_CHMODE_L_LOOP:
- OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
- break;
- case XUARTPS_MR_CHMODE_R_LOOP:
- OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
- break;
- default:
- OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
- XUARTPS_MR_CHMODE_SHIFT);
- break;
- }
-
- return OperMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param OperationMode is the mode of the UART.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
-{
- u32 ModeRegister;
-
- /* Assert validates the input arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
-
- /* Read the Mode register. */
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Set the correct value by masking the bits, then ORing the const. */
- ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
-
- switch (OperationMode) {
- case XUARTPS_OPER_MODE_NORMAL:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
- break;
- case XUARTPS_OPER_MODE_AUTO_ECHO:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
- break;
- case XUARTPS_OPER_MODE_LOCAL_LOOP:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
- break;
- case XUARTPS_OPER_MODE_REMOTE_LOOP:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
- break;
- default:
- /* Default case made for MISRA-C Compliance. */
- break;
- }
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The Flow Delay is specified by constants defined in xuartps_hw.h. The
-* constants are named XUARTPS_FLOWDEL*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
-{
- u32 FdelTmpRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Mode register. */
- FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FLOWDEL_OFFSET);
-
- /* Return the contents of the flow delay register */
- FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
- return FdelTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FlowDelayValue is the Setting for the flow delay.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
-{
- u32 FdelRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Set the correct value by shifting the input constant, then masking
- * the bits
- */
- FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FLOWDEL_OFFSET, FdelRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Receive Timeout of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The current setting for receive time out.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
-{
- u32 RtoRegister;
- u8 RtoRTmpRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Receive Timeout register. */
- RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET);
-
- /* Return the contents of the mode register shifted appropriately */
- RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
- return RtoRTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Receive Timeout of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RecvTimeout setting allows the UART to detect an idle connection
-* on the reciever data line.
-* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
-* timeout function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
-{
- u32 RtoRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Set the correct value by masking the bits */
- RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET, RtoRegister);
-
- /* Configure CR to restart the receiver timeout counter */
- RtoRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_CR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
- (RtoRegister | XUARTPS_CR_TORST));
-
-}
-/****************************************************************************/
-/**
-*
-* Sets the data format for the device. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity. It is the
-* caller's responsibility to ensure that the UART is not sending or receiving
-* data when this function is called.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FormatPtr is a pointer to a format structure containing the data
-* format to be set.
-*
-* @return
-* - XST_SUCCESS if the data format was successfully set.
-* - XST_UART_BAUD_ERROR indicates the baud rate could not be
-* set because of the amount of error with the baud rate and
-* the input clock frequency.
-* - XST_INVALID_PARAM if one of the parameters was not valid.
-*
-* @note
-*
-* The data types in the format type, data bits and parity, are 32 bit fields
-* to prevent a compiler warning.
-* The asserts in this function will cause a warning if these fields are
-* bytes.
-* <br><br>
-*
-*****************************************************************************/
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
- XUartPsFormat * FormatPtr)
-{
- s32 Status;
- u32 ModeRegister;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(FormatPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Verify the inputs specified are valid */
- if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
- (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
- (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
- Status = XST_INVALID_PARAM;
- } else {
-
- /*
- * Try to set the baud rate and if it's not successful then don't
- * continue altering the data format, this is done first to avoid the
- * format from being altered when an error occurs
- */
- Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
- if (Status != (s32)XST_SUCCESS) {
- ;
- } else {
-
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /*
- * Set the length of data (8,7,6) by first clearing out the bits
- * that control it in the register, then set the length in the register
- */
- ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
- ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
-
- /*
- * Set the number of stop bits in the mode register by first clearing
- * out the bits that control it in the register, then set the number
- * of stop bits in the register.
- */
- ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
- ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
-
- /*
- * Set the parity by first clearing out the bits that control it in the
- * register, then set the bits in the register, the default is no parity
- * after clearing the register bits
- */
- ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
- ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
-
- /* Update the mode register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- Status = XST_SUCCESS;
- }
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Gets the data format for the specified UART. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FormatPtr is a pointer to a format structure that will contain
-* the data format after this call completes.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
-{
- u32 ModeRegister;
-
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FormatPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the baud rate from the instance, this is not retrieved from the
- * hardware because it is only kept as a divisor such that it is more
- * difficult to get back to the baud rate
- */
- FormatPtr->BaudRate = InstancePtr->BaudRate;
-
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Get the length of data (8,7,6,5) */
- FormatPtr->DataBits =
- ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
- XUARTPS_MR_CHARLEN_SHIFT);
-
- /* Get the number of stop bits */
- FormatPtr->StopBits =
- (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
- XUARTPS_MR_STOPMODE_SHIFT);
-
- /* Determine what parity is */
- FormatPtr->Parity =
- (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
- XUARTPS_MR_PARITY_SHIFT);
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
deleted file mode 100644
index de58201a10defbbfdf435648be1c0aaa9f4ef924..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_selftest.c
-* @addtogroup uartps_v3_5
-* @{
-*
-* This file contains the self-test functions for the XUartPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XUARTPS_TOTAL_BYTES (u8)32
-
-/************************** Variable Definitions *****************************/
-
-static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
-static u8 ReturnString[XUARTPS_TOTAL_BYTES];
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return
-* - XST_SUCCESS if the test was successful
-* - XST_UART_TEST_FAIL if the test failed looping back the data
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-s32 XUartPs_SelfTest(XUartPs *InstancePtr)
-{
- s32 Status = XST_SUCCESS;
- u32 IntrRegister;
- u32 ModeRegister;
- u8 Index;
- u32 ReceiveDataResult;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Disable all interrupts in the interrupt disable register */
- IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- /* Setup for local loopback */
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
- (u32)XUARTPS_MR_CHMODE_L_LOOP));
-
- /* Send a number of bytes and receive them, one at a time. */
- for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
- /*
- * Send out the byte and if it was not sent then the failure
- * will be caught in the comparison at the end
- */
- (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
-
- /*
- * Wait until the byte is received. This can hang if the HW
- * is broken. Watch for the FIFO empty flag to be false.
- */
- ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
- XUARTPS_SR_RXEMPTY;
- while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
- ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
- XUARTPS_SR_RXEMPTY;
- }
-
- /* Receive the byte */
- (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
- }
-
- /*
- * Compare the bytes received to the bytes sent to verify the exact data
- * was received
- */
- for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
- if (TestString[Index] != ReturnString[Index]) {
- Status = XST_UART_TEST_FAIL;
- }
- }
-
- /*
- * Restore the registers which were altered to put into polling and
- * loopback modes so that this test is not destructive
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
- IntrRegister);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
deleted file mode 100644
index 22e2f7a83c0ee9f82e0659b6e4f6e4f2628a87c7..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartps_sinit.c
-* @addtogroup uartps_v3_5
-* @{
-*
-* The implementation of the XUartPs driver's static initialzation
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device
-*
-* @return A pointer to the configuration structure or NULL if the
-* specified device is not in the system.
-*
-* @note None.
-*
-******************************************************************************/
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
-{
- XUartPs_Config *CfgPtr = NULL;
-
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
- if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XUartPs_ConfigTable[Index];
- break;
- }
- }
-
- return (XUartPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
deleted file mode 100644
index 7cf97e2f02131dc8dcc848251f88cf637781f852..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
+++ /dev/null
@@ -1,41 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xusbps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling usbps"
-
-xusbps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xusbps_includes
-
-xusbps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
deleted file mode 100644
index b76c94a464535c5a1037e5452386357b7b613006..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/******************************************************************************/
-/**
- * @file xusbps.c
-* @addtogroup usbps_v2_4
-* @{
- *
- * The XUsbPs driver. Functions in this file are the minimum required
- * functions for this driver. See xusbps.h for a detailed description of the
- * driver.
- *
- * @note None.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 2.1 kpc 04/28/14 Removed ununsed functions
- * </pre>
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-#include <stdio.h>
-#include "xusbps.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/***************** Macros (Inline Functions) Definitions **********************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes *******************************/
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a XUsbPs instance/driver.
-*
-* The initialization entails:
-* - Initialize all members of the XUsbPs structure.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param ConfigPtr is a pointer to a XUsbPs_Config configuration
-* structure. This structure will contain the requested
-* configuration for the device. Typically, this is a local
-* structure and the content of which will be copied into the
-* configuration structure within XUsbPs.
-* @param VirtBaseAddress is the base address of the device. For systems
-* with virtual memory, this address must be the virtual address
-* of the device.
-* For systems that do not support virtual memory this address
-* should be the physical address of the device. For backwards
-* compatibilty NULL may be passed in systems that do not support
-* virtual memory (deprecated).
-*
-* @return
-* - XST_SUCCESS no errors occured.
-* - XST_FAILURE an error occured during initialization.
-*
-* @note
-* After calling XUsbPs_CfgInitialize() the controller
-* IS NOT READY for use. Before the controller can be used its
-* DEVICE parameters must be configured. See xusbps.h
-* for details.
-*
-******************************************************************************/
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /* Copy the config structure. */
- InstancePtr->Config = *ConfigPtr;
-
- /* Check if the user provided a non-NULL base address. If so, we have
- * to overwrite the base address in the configuration structure.
- */
- if (0 != VirtBaseAddress) {
- InstancePtr->Config.BaseAddress = VirtBaseAddress;
- }
-
- /* Initialize the XUsbPs structure to default values. */
- InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING;
-
- InstancePtr->HandlerFunc = NULL;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function performs device reset, device is stopped at the end.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
-{
- int Timeout;
-
- /* Clear all setup token semaphores by reading the
- * XUSBPS_EPSTAT_OFFSET register and writing its value back to
- * itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET));
-
- /* Clear all the endpoint complete status bits by reading the
- * XUSBPS_EPCOMPL_OFFSET register and writings its value back
- * to itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET));
-
- /* Cancel all endpoint prime status by waiting until all bits
- * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
- * to XUSBPS_EPFLUSH_OFFSET.
- *
- * Avoid hanging here by using a Timeout counter...
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET) &
- XUSBPS_EP_ALL_MASK) && --Timeout) {
- /* NOP */
- }
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
-
- XUsbPs_Stop(InstancePtr);
-
- /* Write to CR register for controller reset */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
-
- /* Wait for reset to finish, hardware clears the reset bit once done */
- Timeout = 1000000;
- while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_RST_MASK) && --Timeout) {
- /* NOP */
- }
-}
-/*****************************************************************************/
-/**
-*
-* This function resets the USB device. All the configuration registers are
-* reset to their default values. The function waits until the reset operation
-* is complete or for a certain duration within which the reset operation is
-* expected to be completed.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS Reset operation completed successfully.
-* - XST_FAILURE Reset operation timed out.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_Reset(XUsbPs *InstancePtr)
-{
- int Timeout;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
- * RESET is complete.
- *
- * We are going to wait for the RESET bit to clear before we return
- * from this function. Unfortunately we do not have timers available at
- * this point to determine when we should report a Timeout.
- *
- * However, by using a large number for the poll loop we can assume
- * that the polling operation will take longer than the expected time
- * the HW needs to RESET. If the poll loop expires we can assume a
- * Timeout. The drawback is that on a slow system (and even on a fast
- * system) this can lead to _very_ long Timeout periods.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
-
-
- /* Wait for the RESET bit to be cleared by HW. */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_RST_MASK) && --Timeout) {
- /* NOP */
- }
-
- if (0 == Timeout) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * USB Suspend
- *
- * In order to conserve power, USB devices automatically enter the suspended
- * state when the device has observed no bus traffic for a specified period.
- * When suspended, the USB device maintains any internal status, including its
- * address and configuration. Attached devices must be prepared to suspend at
- * any time they are powered, regardless of if they have been assigned a
- * non-default address, are configured, or neither. Bus activity may cease due
- * to the host entering a suspend mode of its own. In addition, a USB device
- * shall also enter the suspended state when the hub port it is attached to is
- * disabled.
- *
- * A USB device exits suspend mode when there is bus activity. A USB device may
- * also request the host to exit suspend mode or selective suspend by using
- * electrical signaling to indicate remote wakeup. The ability of a device to
- * signal remote wakeup is optional. If the USB device is capable of remote
- * wakeup signaling, the device must support the ability of the host to enable
- * and disable this capability. When the device is reset, remote wakeup
- * signaling must be disabled.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- *
- * @return
- * - XST_SUCCESS if the USB device has entered Suspend mode
- * successfully
- * - XST_FAILURE on any error
- *
- * @note None.
- *
- ******************************************************************************/
-int XUsbPs_Suspend(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* USB Resume
-*
- If the USB controller is suspended, its operation is resumed when any
-* non-idle signaling is received on its upstream facing port.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS if the USB device has Resumed successfully
-* - XST_FAILURE on any error
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_Resume(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* USB Assert Resume
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS if the USB device has Resumed successfully
-* - XST_FAILURE on any error
-*
-* @note None.
-*
-******************************************************************************/
-
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* This functions sets the controller's DEVICE address. It also sets the
-* advance bit so the controller will wait for the next IN-ACK before the new
-* address takes effect.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Address is the Address of the device.
-*
-* @return
-* - XST_SUCCESS: Address set successfully.
-* - XST_FAILURE: An error occured.
-* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address
-* value too big.
-*
-* @note None.
-*
-*****************************************************************************/
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Check address range validity. */
- if (Address > XUSBPS_DEVICEADDR_MAX) {
- return XST_INVALID_PARAM;
- }
-
- /* Set the address register with the Address value provided. Also set
- * the Address Advance Bit. This will cause the address to be set only
- * after an IN occured and has been ACKed on the endpoint.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_DEVICEADDR_OFFSET,
- (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
- XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
-
- return XST_SUCCESS;
-}
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
deleted file mode 100644
index b5c472ef9e3d912141993ac47da134013c9d3d06..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
+++ /dev/null
@@ -1,1098 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xusbps.h
-* @addtogroup usbps_v2_4
-* @{
-* @details
- *
- * This file contains the implementation of the XUsbPs driver. It is the
- * driver for an USB controller in DEVICE or HOST mode.
- *
- * <h2>Introduction</h2>
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- * <h2>USB Controller Features</h2>
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- * <h2>Initialization & Configuration</h2>
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- * <h2>USB Device Endpoints</h2>
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- * <h2>Interrupt Handling</h2>
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler fucntions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- * <h2>Data buffer handling</h2>
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- * <h3>Zero copy</h3>
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- * <h2>DMA</h2>
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * </pre>
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
-
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the enpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occured on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
deleted file mode 100644
index 7b16d22b507e52a1edee897bf86bae92a5fcd775..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
+++ /dev/null
@@ -1,1454 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/******************************************************************************/
-/**
- * @file xusbps_endpoint.c
-* @addtogroup usbps_v2_4
-* @{
- *
- * Endpoint specific function implementations.
- *
- * @note None.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names
- * 2.1 kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
- * code to XUsbPs_EpQueueRequest.
- * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
- * (moving of dTD Head/Tail Pointers)and CR#873974(invalidate
- * Caches After Buffer Receive in Endpoint Buffer Handler...)
- * </pre>
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-
-#include <string.h> /* for bzero() */
-#include <stdio.h>
-
-#include "xusbps.h"
-#include "xusbps_endpoint.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes ******************************/
-
-static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
-static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
-static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
-static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
- const u8 *BufferPtr, u32 BufferLen);
-
-static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
-
-/* Functions to reconfigure endpoint upon host's set alternate interface
- * request.
- */
-static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
- int EpNum, unsigned short NewDirection);
-static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
- int EpNum, unsigned short NewDirection);
-static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
-
-/******************************* Functions ************************************/
-
-/*****************************************************************************/
-/**
- *
- * This function configures the DEVICE side of the controller. The caller needs
- * to pass in the desired configuration (e.g. number of endpoints) and a
- * DMAable buffer that will hold the Queue Head List and the Transfer
- * Descriptors. The required size for this buffer can be obtained by the caller
- * using the: XUsbPs_DeviceMemRequired() macro.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param CfgPtr is a pointer to the configuration structure that contains
- * the desired DEVICE side configuration.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occured.
- *
- * @note
- * The caller may configure the controller for both, DEVICE and
- * HOST side.
- *
- ******************************************************************************/
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr)
-{
- int Status;
- u32 ModeValue = 0x0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- /* Copy the configuration data over into the local instance structure */
- InstancePtr->DeviceConfig = *CfgPtr;
-
-
- /* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
- InstancePtr->DeviceConfig.PhysAligned =
- (InstancePtr->DeviceConfig.DMAMemPhys +
- XUSBPS_dQH_BASE_ALIGN) &
- ~(XUSBPS_dQH_BASE_ALIGN -1);
-
- /* Initialize the endpoint pointer list data structure. */
- XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
-
-
- /* Initialize the Queue Head structures in DMA memory. */
- XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
-
-
- /* Initialize the Transfer Descriptors in DMA memory.*/
- Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
- if (XST_SUCCESS != Status) {
- return XST_FAILURE;
- }
-
- /* Changing the DEVICE mode requires a controller RESET. */
- if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
- return XST_FAILURE;
- }
-
- /* Set the Queue Head List address. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPLISTADDR_OFFSET,
- InstancePtr->DeviceConfig.PhysAligned);
-
- /* Set the USB mode register to configure DEVICE mode.
- *
- * XUSBPS_MODE_SLOM_MASK note:
- * Disable Setup Lockout. Setup Lockout is not required as we
- * will be using the tripwire mechanism when handling setup
- * packets.
- */
- ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
-
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_MODE_OFFSET, ModeValue);
-
- XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
- XUSBPS_OTGSC_OT_MASK);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function sends a given data buffer.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param BufferPtr is a pointer to the buffer to send.
-* @param BufferLen is the Buffer length.
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occured.
-* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
-* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
-*
-******************************************************************************/
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
- BufferLen, FALSE);
-}
-
-/*****************************************************************************/
-/**
-* This function sends a given data buffer and also zero length packet if the
-* Bufferlen is in multiples of endpoint max packet size.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param BufferPtr is a pointer to the buffer to send.
-* @param BufferLen is the Buffer length.
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occured.
-* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
-* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
-*
-******************************************************************************/
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen)
-{
- u8 ReqZero = FALSE;
- XUsbPs_EpSetup *Ep;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
-
- if ((BufferLen >= Ep->MaxPacketSize) &&
- (BufferLen % Ep->MaxPacketSize == 0)) {
- ReqZero = TRUE;
- }
-
- return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
- BufferLen, ReqZero);
-}
-
-/*****************************************************************************/
-/**
-* This function sends a given data buffer and also sends ZLT packet if it is
-* requested.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param BufferPtr is a pointer to the buffer to send.
-* @param BufferLen is the Buffer length.
-* @param ReqZero is the
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occured.
-* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
-* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
-*
-******************************************************************************/
-static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
-{
- int Status;
- u32 Token;
- XUsbPs_EpIn *Ep;
- XUsbPs_dTD *DescPtr;
- u32 Length;
- u32 PipeEmpty = 1;
- u32 Mask = 0x00010000;
- u32 BitMask = Mask << EpNum;
- u32 RegValue;
- u32 Temp;
- u32 exit = 1;
-
-
- /* Locate the next available buffer in the ring. A buffer is available
- * if its descriptor is not active.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
-
- Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
-
- if(Ep->dTDTail != Ep->dTDHead) {
- PipeEmpty = 0;
- }
- XUsbPs_dTDInvalidateCache(Ep->dTDHead);
-
- /* Tell the caller if we do not have any descriptors available. */
- if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
- return XST_USB_NO_DESC_AVAILABLE;
- }
-
- /* Remember the current head. */
- DescPtr = Ep->dTDHead;
-
- do {
-
- /* Tell the caller if we do not have any descriptors available. */
- if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
- return XST_USB_NO_DESC_AVAILABLE;
- }
-
- Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
- /* Attach the provided buffer to the current descriptor.*/
- Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
- if (XST_SUCCESS != Status) {
- return XST_FAILURE;
- }
- BufferLen -= Length;
- BufferPtr += Length;
-
- XUsbPs_dTDSetActive(Ep->dTDHead);
- if (BufferLen == 0 && (ReqZero == FALSE)) {
- XUsbPs_dTDSetIOC(Ep->dTDHead);
- exit = 0;
- }
- XUsbPs_dTDClrTerminate(Ep->dTDHead);
- XUsbPs_dTDFlushCache(Ep->dTDHead);
-
- /* Advance the head descriptor pointer to the next descriptor. */
- Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
- /* Terminate the next descriptor and flush the cache.*/
- XUsbPs_dTDInvalidateCache(Ep->dTDHead);
-
- if (ReqZero && BufferLen == 0) {
- ReqZero = FALSE;
- }
-
- } while(BufferLen || exit);
-
- XUsbPs_dTDSetTerminate(Ep->dTDHead);
- XUsbPs_dTDFlushCache(Ep->dTDHead);
-
- if(!PipeEmpty) {
- /* Read the endpoint prime register. */
- RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
- if(RegValue & BitMask) {
- return XST_SUCCESS;
- }
-
- do {
- RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- RegValue | XUSBPS_CMD_ATDTW_MASK);
- Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
- & BitMask;
- } while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_ATDTW_MASK));
-
- RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- RegValue & ~XUSBPS_CMD_ATDTW_MASK);
-
- if(Temp) {
- return XST_SUCCESS;
- }
- }
-
- /* Check, if the DMA engine is still running. If it is running, we do
- * not clear Queue Head fields.
- *
- * Same cache rule as for the Transfer Descriptor applies for the Queue
- * Head.
- */
- XUsbPs_dQHInvalidateCache(Ep->dQH);
- /* Add the dTD to the dQH */
- XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
- Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
- Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
- XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
-
- XUsbPs_dQHFlushCache(Ep->dQH);
-
- Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * This function receives a data buffer from the endpoint of the given endpoint
- * number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param BufferPtr (OUT param) is a pointer to the buffer pointer to hold
- * the reference of the data buffer.
- * @param BufferLenPtr (OUT param) is a pointer to the integer that will
- * hold the buffer length.
- * @param Handle is the opaque handle to be used when the buffer is
- * released.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occured.
- * - XST_USB_NO_BUF: No buffer available.
- *
- * @note
- * After handling the data in the buffer, the user MUST release
- * the buffer using the Handle by calling the
- * XUsbPs_EpBufferRelease() function.
- *
- ******************************************************************************/
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
-{
- XUsbPs_EpOut *Ep;
- XUsbPs_EpSetup *EpSetup;
- u32 length = 0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(BufferLenPtr != NULL);
- Xil_AssertNonvoid(Handle != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- /* Locate the next available buffer in the ring. A buffer is available
- * if its descriptor is not active.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
-
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
- return XST_USB_NO_BUF;
- }
-
- /* The buffer is not active which means that it has been processed by
- * the DMA engine and contains valid data.
- */
- EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
-
-
- /* Use the buffer pointer stored in the "user data" field of the
- * Transfer Descriptor.
- */
- *BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
- XUSBPS_dTDUSERDATA);
-
- length = EpSetup->BufSize -
- XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
-
- if(length > 0) {
- *BufferLenPtr = length;
- }else {
- *BufferLenPtr = 0;
- }
-
- *Handle = (u32) Ep->dTDCurr;
-
-
- /* Reset the descriptor's BufferPointer0 and Transfer Length fields to
- * their original value. Note that we can not yet re-activate the
- * descriptor as the caller will be using the attached buffer. Once the
- * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
- * can re-activate the descriptor.
- */
- XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
- XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
-
- XUsbPs_dTDFlushCache(Ep->dTDCurr);
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function returns a previously received data buffer to the driver.
-*
-* @param Handle is a pointer to the buffer that is returned.
-*
-* @return None.
-*
-******************************************************************************/
-void XUsbPs_EpBufferRelease(u32 Handle)
-{
- XUsbPs_dTD *dTDPtr;
-
- /* Perform sanity check on Handle.*/
- Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
-
- /* Activate the descriptor and clear the Terminate bit. Make sure to do
- * the proper cache handling.
- */
- dTDPtr = (XUsbPs_dTD *) Handle;
-
- XUsbPs_dTDInvalidateCache(dTDPtr);
-
- XUsbPs_dTDClrTerminate(dTDPtr);
- XUsbPs_dTDSetActive(dTDPtr);
- XUsbPs_dTDSetIOC(dTDPtr);
-
- XUsbPs_dTDFlushCache(dTDPtr);
-
-}
-
-
-/*****************************************************************************/
-/**
- * This function sets the handler for endpoint events.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param Direction is the direction of the endpoint (bitfield):
- * - XUSBPS_EP_DIRECTION_OUT
- * - XUSBPS_EP_DIRECTION_IN
- * @param CallBackFunc is the Handler callback function.
- * Can be NULL if the user wants to disable the handler entry.
- * @param CallBackRef is the user definable data pointer that will be
- * passed back if the handler is called. May be NULL.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occured.
- * - XST_INVALID_PARAM: Invalid parameter passed.
- *
- * @note
- * The user can disable a handler by setting the callback function
- * pointer to NULL.
- *
- ******************************************************************************/
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef)
-{
- XUsbPs_Endpoint *Ep;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CallBackFunc != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
-
- if(Direction & XUSBPS_EP_DIRECTION_OUT) {
- Ep->Out.HandlerFunc = CallBackFunc;
- Ep->Out.HandlerRef = CallBackRef;
- }
-
- if(Direction & XUSBPS_EP_DIRECTION_IN) {
- Ep->In.HandlerFunc = CallBackFunc;
- Ep->In.HandlerRef = CallBackRef;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function primes an endpoint.
-*
-* @param InstancePtr is pointer to the XUsbPs instance.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param Direction is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occured.
-* - XST_INVALID_PARAM: Invalid parameter passed.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
-{
- u32 Mask;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- /* Get the right bit mask for the endpoint direction. */
- switch (Direction) {
-
- case XUSBPS_EP_DIRECTION_OUT:
- Mask = 0x00000001;
- break;
-
- case XUSBPS_EP_DIRECTION_IN:
- Mask = 0x00010000;
- break;
-
- default:
- return XST_INVALID_PARAM;
- }
-
- /* Write the endpoint prime register. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function extracts the Setup Data from a given endpoint.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param SetupDataPtr is a pointer to the setup data structure to be
-* filled.
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occured.
-*
-* @note None.
-******************************************************************************/
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr)
-{
- XUsbPs_EpOut *Ep;
-
- u32 Data[2];
- u8 *p;
-
- int Timeout;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SetupDataPtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
-
-
- /* Get the data from the Queue Heads Setup buffer into local variables
- * so we can extract the setup data values.
- */
- do {
- /* Arm the tripwire. The tripwire will tell us if a new setup
- * packet arrived (in which case the tripwire bit will be
- * cleared) while we were reading the buffer. If a new setup
- * packet arrived the buffer is corrupted and we continue
- * reading.
- */
- XUsbPs_SetSetupTripwire(InstancePtr);
-
- XUsbPs_dQHInvalidateCache(Ep->dQH);
-
- Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
- Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
- } while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
-
- /* Clear the pending endpoint setup stat bit.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
-
- /* Clear the Tripwire bit and continue.
- */
- XUsbPs_ClrSetupTripwire(InstancePtr);
-
-
- /* Data in the setup buffer is being converted by the core to big
- * endian format. We have to take care of proper byte swapping when
- * reading the setup data values.
- *
- * Need to check if there is a smarter way to do this and take the
- * processor/memory-controller endianess into account?
- */
- p = (u8 *) Data;
-
- SetupDataPtr->bmRequestType = p[0];
- SetupDataPtr->bRequest = p[1];
- SetupDataPtr->wValue = (p[3] << 8) | p[2];
- SetupDataPtr->wIndex = (p[5] << 8) | p[4];
- SetupDataPtr->wLength = (p[7] << 8) | p[6];
-
- /* Before we leave we need to make sure that the endpoint setup bit has
- * cleared. It needs to be 0 before the endpoint can be re-primed.
- *
- * Note: According to the documentation this endpoint setup bit should
- * clear within 1-2us after it has been written above. This means that
- * we should never catch it being 1 here. However, we still need to
- * poll it to make sure. Just in case, we use a counter 'Timeout' so we
- * won't hang here if the bit is stuck for some reason.
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET) &
- (1 << EpNum)) && --Timeout) {
- /* NOP */
- }
- if (0 == Timeout) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes the endpoint pointer data structure.
-*
-* The function sets up the local data structure with the aligned addresses for
-* the Queue Head and Transfer Descriptors.
-*
-* @param DevCfgPtr is pointer to the XUsbPs DEVICE configuration
-* structure.
-*
-* @return none
-*
-* @note
-* Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
-* system. Therefore no memory is reserved for them.
-*
-******************************************************************************/
-static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
-{
- int EpNum;
- u8 *p;
-
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Set up the XUsbPs_Endpoint array. This array is used to define the
- * location of the Queue Head list and the Transfer Descriptors in the
- * block of DMA memory that has been passed into the driver.
- *
- * 'p' is used to set the pointers in the local data structure.
- * Initially 'p' is pointed to the beginning of the DMAable memory
- * block. As pointers are assigned, 'p' is incremented by the size of
- * the respective object.
- */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
- /* Start off with 'p' pointing to the (aligned) beginning of the DMA
- * buffer.
- */
- p = (u8 *) DevCfgPtr->PhysAligned;
-
-
- /* Initialize the Queue Head pointer list.
- *
- * Each endpoint has two Queue Heads. One for the OUT direction and one
- * for the IN direction. An OUT Queue Head is always followed by an IN
- * Queue Head.
- *
- * Queue Head alignment is XUSBPS_dQH_ALIGN.
- *
- * Note that we have to reserve space here for unused endpoints.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- /* OUT Queue Head */
- Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
- p += XUSBPS_dQH_ALIGN;
-
- /* IN Queue Head */
- Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
- p += XUSBPS_dQH_ALIGN;
- }
-
-
- /* 'p' now points to the first address after the Queue Head list. The
- * Transfer Descriptors start here.
- *
- * Each endpoint has a variable number of Transfer Descriptors
- * depending on user configuration.
- *
- * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- /* OUT Descriptors.
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- Ep[EpNum].Out.dTDs = (XUsbPs_dTD *) p;
- Ep[EpNum].Out.dTDCurr = (XUsbPs_dTD *) p;
- p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
- }
-
- /* IN Descriptors.
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
- Ep[EpNum].In.dTDs = (XUsbPs_dTD *) p;
- Ep[EpNum].In.dTDHead = (XUsbPs_dTD *) p;
- Ep[EpNum].In.dTDTail = (XUsbPs_dTD *) p;
- p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
- }
- }
-
-
- /* 'p' now points to the first address after the Transfer Descriptors.
- * The data buffers for the OUT Transfer Desciptors start here.
- *
- * Note that IN (TX) Transfer Descriptors are not assigned buffers at
- * this point. Buffers will be assigned when the user calls the send()
- * function.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
-
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- /* If BufSize for this endpoint is set to 0 it means
- * that we do not need to attach a buffer to this
- * descriptor. We also initialize it's buffer pointer
- * to NULL.
- */
- if (0 == EpCfg[EpNum].Out.BufSize) {
- Ep[EpNum].Out.dTDBufs = NULL;
- continue;
- }
-
- Ep[EpNum].Out.dTDBufs = p;
- p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
- }
- }
-
-
- /* Initialize the endpoint event handlers to NULL.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- Ep[EpNum].Out.HandlerFunc = NULL;
- Ep[EpNum].In.HandlerFunc = NULL;
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes the Queue Head List in memory.
-*
-* @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
-* structure.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
-{
- int EpNum;
-
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Setup pointers for simpler access. */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- /* Go through the list of Queue Head entries and:
- *
- * - Set Transfer Descriptor addresses
- * - Set Maximum Packet Size
- * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
- * - Enable Interrupt On Setup (IOS)
- *
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
-
- /* OUT Queue Heads.*/
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
-
- /* For isochronous, ep max packet size translates to different
- * values in queue head than other types.
- * Also enable ZLT for isochronous.
- */
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
- }
-
- /* Only control OUT needs this */
- if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
- XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
- }
-
- /* Set up the overlay next dTD pointer. */
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
-
- XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
- }
-
-
- /* IN Queue Heads. */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
- XUsbPs_WritedQH(Ep[EpNum].In.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
-
-
- /* Isochronous ep packet size can be larger than 1024.*/
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
- }
-
- XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
- }
- }
-}
-
-
-/*****************************************************************************/
-/**
- *
- * This function initializes the Transfer Descriptors lists in memory.
- *
- * @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
- * structure.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occured.
- *
- ******************************************************************************/
-static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
-{
- int EpNum;
-
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Setup pointers for simpler access. */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- /* Walk through the list of endpoints and initialize their Transfer
- * Descriptors.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- int Td;
- int NumdTD;
-
- XUsbPs_EpOut *Out = &Ep[EpNum].Out;
- XUsbPs_EpIn *In = &Ep[EpNum].In;
-
-
- /* OUT Descriptors
- * ===============
- *
- * + Set the next link pointer
- * + Set the interrupt complete and the active bit
- * + Attach the buffer to the dTD
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- NumdTD = EpCfg[EpNum].Out.NumBufs;
- }
- else {
- NumdTD = 0;
- }
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int Status;
-
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
-
- /* Set NEXT link pointer. */
- XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
- &Out->dTDs[NextTd]);
-
- /* Set the OUT descriptor ACTIVE and enable the
- * interrupt on complete.
- */
- XUsbPs_dTDSetActive(&Out->dTDs[Td]);
- XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
-
-
- /* Set up the data buffer with the descriptor. If the
- * buffer pointer is NULL it means that we do not need
- * to attach a buffer to this descriptor.
- */
- if (NULL == Out->dTDBufs) {
- XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
- continue;
- }
-
- Status = XUsbPs_dTDAttachBuffer(
- &Out->dTDs[Td],
- Out->dTDBufs +
- (Td * EpCfg[EpNum].Out.BufSize),
- EpCfg[EpNum].Out.BufSize);
- if (XST_SUCCESS != Status) {
- return XST_FAILURE;
- }
-
- XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
- }
-
-
- /* IN Descriptors
- * ==============
- *
- * + Set the next link pointer
- * + Set the Terminate bit to mark it available
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
- NumdTD = EpCfg[EpNum].In.NumBufs;
- }
- else {
- NumdTD = 0;
- }
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
-
- /* Set NEXT link pointer. */
- XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
- In->dTDs[NextTd]);
-
- /* Set the IN descriptor's TERMINATE bits. */
- XUsbPs_dTDSetTerminate(In->dTDs[Td]);
-
- XUsbPs_dTDFlushCache(&In->dTDs[Td]);
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- *
- * This function associates a buffer with a Transfer Descriptor. The function
- * will take care of splitting the buffer into multiple 4kB aligned segments if
- * the buffer happens to span one or more 4kB pages.
- *
- * @param dTDIndex is a pointer to the Transfer Descriptor
- * @param BufferPtr is pointer to the buffer to link to the descriptor.
- * @param BufferLen is the length of the buffer.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occured.
- * - XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
- * maximum allowed buffer size (16k).
- *
- * @note
- * Cache invalidation and flushing needs to be handler by the
- * caller of this function.
- *
- ******************************************************************************/
-static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
- const u8 *BufferPtr, u32 BufferLen)
-{
- u32 BufAddr;
- u32 BufEnd;
- u32 PtrNum;
-
- Xil_AssertNonvoid(dTDPtr != NULL);
-
- /* Check if the buffer is smaller than 16kB. */
- if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
- return XST_USB_BUF_TOO_BIG;
- }
-
- /* Get a u32 of the buffer pointer to avoid casting in the following
- * logic operations.
- */
- BufAddr = (u32) BufferPtr;
-
-
- /* Set the buffer pointer 0. Buffer pointer 0 can point to any location
- * in memory. It does not need to be 4kB aligned. However, if the
- * provided buffer spans one or more 4kB boundaries, we need to set up
- * the subsequent buffer pointers which must be 4kB aligned.
- */
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
-
- /* Check if the buffer spans a 4kB boundary.
- *
- * Only do this check, if we are not sending a 0-length buffer.
- */
- if (BufferLen > 0) {
- BufEnd = BufAddr + BufferLen -1;
- PtrNum = 1;
-
- while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
- /* The buffer spans at least one boundary, let's set
- * the next buffer pointer and repeat the procedure
- * until the end of the buffer and the pointer written
- * are in the same 4kB page.
- */
- BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
- BufAddr);
- PtrNum++;
- }
- }
-
- /* Set the length of the buffer. */
- XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
-
-
- /* We remember the buffer pointer in the user data field (reserved
- * field in the dTD). This makes it easier to reset the buffer pointer
- * after a buffer has been received on the endpoint. The buffer pointer
- * needs to be reset because the DMA engine modifies the buffer pointer
- * while receiving.
- */
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- * This function set the Max PacketLen for the queue head for isochronous EP.
- *
- * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
- * Mult bits are set to reflect that.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the Length to be set.
- *
- ******************************************************************************/
-static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
-{
- u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
- u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
-
- if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
- return;
- }
-
- if (Mult > 3) {
- return;
- }
-
- /* Set Max packet size */
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
- ~XUSBPS_dQHCFG_MPL_MASK) |
- (MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
-
- /* Set Mult to tell hardware how many transactions in each microframe */
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
- ~XUSBPS_dQHCFG_MULT_MASK) |
- (Mult << XUSBPS_dQHCFG_MULT_SHIFT));
-
-}
-
-/*****************************************************************************/
-/**
-* This function reconfigures one Ep corresponding to host's request of setting
-* alternate interface. The endpoint has been disabled before this call.
-*
-* Both QH and dTDs are updated for the new configuration.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param CfgPtr
-* Pointer to the updated XUsbPs DEVICE configuration structure.
-*
-* @param EpNum
-* The endpoint to be reconfigured.
-*
-* @param NewDirection
-* The new transfer direction the endpoint.
-*
-* @param DirectionChanged
-* A boolean value indicate whether the transfer direction has changed.
-*
-* @return
-* XST_SUCCESS upon success, XST_FAILURE otherwise.
-*
-******************************************************************************/
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection,
- int DirectionChanged) {
-
- int Status = XST_SUCCESS;
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- Ep = CfgPtr->Ep;
- EpCfg = CfgPtr->EpCfg;
-
- /* If transfer direction changes, dTDs has to be reset
- * Number of buffers are preset and should not to be changed.
- */
- if(DirectionChanged) {
- if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- u8 *p;
-
- /* Swap the pointer to the dTDs.
- */
- Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
- p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
-
- /* Set the OUT buffer if buffer size is not zero
- */
- if(EpCfg[EpNum].Out.BufSize > 0) {
- Ep[EpNum].Out.dTDBufs = p;
- }
- } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
- Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
- }
- }
-
- /* Reset dTD progress tracking pointers
- */
- if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
- Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
- } else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
- }
-
- /* Reinitialize information in QH
- */
- XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
-
- /* Reinitialize the dTD linked list, and flush the cache
- */
- Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
- if(Status != XST_SUCCESS) {
- return Status;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- * This function re-initializes the Queue Head List in memory.
- * The endpoint 1 has been disabled before this call.
- *
- * @param DevCfgPtr
- * Pointer to the updated XUsbPs DEVICE configuration structure.
- *
- * @param EpNum
- * The endpoint to be reconfigured.
- *
- * @param NewDirection
- * The new transfer direction of endpoint 1
- *
- * @return none
- *
- ******************************************************************************/
-static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
-int EpNum, unsigned short NewDirection)
-{
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Setup pointers for simpler access.
- */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- /* Go through the list of Queue Head entries and:
- *
- * - Set Transfer Descriptor addresses
- * - Set Maximum Packet Size
- * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
- * - Enable Interrupt On Setup (IOS)
- *
- */
- if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- /* OUT Queue Heads.
- */
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
-
- /* For isochronous, ep max packet size translates to different
- * values in queue head than other types.
- * Also enable ZLT for isochronous.
- */
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
- }
-
- XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
-
- /* Set up the overlay next dTD pointer.
- */
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
-
- XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
-
- } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
-
- /* IN Queue Heads.
- */
- XUsbPs_WritedQH(Ep[EpNum].In.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
-
- /* Isochronous ep packet size can be larger than 1024. */
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
- }
-
- XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
-
- XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
- }
-
-}
-
-/*****************************************************************************/
-/**
- *
- * This function re-initializes the Transfer Descriptors lists in memory.
- * The endpoint has been disabled before the call. The transfer descriptors
- * list pointer has been initialized too.
- *
- * @param DevCfgPtr
- * Pointer to the XUsbPs DEVICE configuration structure.
- *
- * @param EpNum
- * The endpoint to be reconfigured.
- *
- * @param NewDirection
- * The new transfer direction of endpoint 1
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occured.
- *
- ******************************************************************************/
-static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
-int EpNum, unsigned short NewDirection)
-{
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
- int Td;
- int NumdTD;
-
-
- /* Setup pointers for simpler access.
- */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- XUsbPs_EpOut *Out = &Ep[EpNum].Out;
-
- /* OUT Descriptors
- * ===============
- *
- * + Set the next link pointer
- * + Set the interrupt complete and the active bit
- * + Attach the buffer to the dTD
- */
- NumdTD = EpCfg[EpNum].Out.NumBufs;
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int Status;
-
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
-
- /* Set NEXT link pointer.
- */
- XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
- &Out->dTDs[NextTd]);
-
- /* Set the OUT descriptor ACTIVE and enable the
- * interrupt on complete.
- */
- XUsbPs_dTDSetActive(&Out->dTDs[Td]);
- XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
-
- /* Set up the data buffer with the descriptor. If the
- * buffer pointer is NULL it means that we do not need
- * to attach a buffer to this descriptor.
- */
- if (Out->dTDBufs != NULL) {
-
- Status = XUsbPs_dTDAttachBuffer(
- &Out->dTDs[Td],
- Out->dTDBufs +
- (Td * EpCfg[EpNum].Out.BufSize),
- EpCfg[EpNum].Out.BufSize);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
- XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
- }
- } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
- XUsbPs_EpIn *In = &Ep[EpNum].In;
-
- /* IN Descriptors
- * ==============
- *
- * + Set the next link pointer
- * + Set the Terminate bit to mark it available
- */
- NumdTD = EpCfg[EpNum].In.NumBufs;
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
-
- /* Set NEXT link pointer.
- */
- XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
- &In->dTDs[NextTd]);
-
- /* Set the IN descriptor's TERMINATE bits.
- */
- XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
-
- XUsbPs_dTDFlushCache(&In->dTDs[Td]);
- }
- }
-
- return XST_SUCCESS;
-}
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
deleted file mode 100644
index 1cb0cfcd3e755d485abb3837c546125ee65b4418..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xusbps_endpoint.h
-* @addtogroup usbps_v2_4
-* @{
- *
- * This is an internal file containung the definitions for endpoints. It is
- * included by the xusbps_endpoint.c which is implementing the endpoint
- * functions and by xusbps_intr.c.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * </pre>
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
deleted file mode 100644
index bb6cff341a3a4491eb488591c2d18011b3eb79a4..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xusbps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_USB_0_DEVICE_ID,
- XPAR_PS7_USB_0_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
deleted file mode 100644
index 04963b28874195ffb6fcba1c6fd8885059edcec5..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
- *
- * @file xusbps_hw.c
-* @addtogroup usbps_v2_4
-* @{
- *
- * The implementation of the XUsbPs interface reset functionality
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.05a kpc 10/10/10 first version
- * </pre>
- *
- *****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xusbps.h"
-#include "xparameters.h"
-
-
-/************************** Constant Definitions ****************************/
-#define XUSBPS_RESET_TIMEOUT 0xFFFFF
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given usbps interface by
-* configuring the appropriate control bits in the usbps specifc registers.
-* the usbps reset sequence involves the below steps
-* Disbale the interrupts
-* Clear the status registers
-* Apply the reset command and wait for reset complete status
-* Update the relevant control registers with reset values
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XUsbPs_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
- u32 Timeout = 0;
-
- /* Host and device mode */
- /* Disable the interrupts */
- XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
- /* Clear the interuupt status */
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
- XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
-
- /* Perform the reset operation using USB CMD register */
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
- RegVal = RegVal | XUSBPS_CMD_RST_MASK;
- XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
- /* Wait till the reset operation returns success */
- /*
- * FIX ME: right now no indication to the caller or user about
- * timeout overflow
- */
- while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
- {
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
- Timeout++;
- }
- /* Update periodic list base address register with reset value */
- XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);
- /* Update async/endpoint list base address register with reset value */
- XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);
-
-}
-
-
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
deleted file mode 100644
index 69f3ebffb4fef5b1f9ff7ad459509df87b94882c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * @file xusbps_hw.h
-* @addtogroup usbps_v2_4
-* @{
- *
- * This header file contains identifiers and low-level driver functions (or
- * macros) that can be used to access the device. High-level driver functions
- * are defined in xusbps.h.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * </pre>
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Regsiter offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
deleted file mode 100644
index 83463bdfeb840a618b197a5ba7cb2ba06658cd9b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
+++ /dev/null
@@ -1,472 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/******************************************************************************/
-/**
- * @file xusbps_intr.c
-* @addtogroup usbps_v2_4
-* @{
- *
- * This file contains the functions that are related to interrupt processing
- * for the EPB USB driver.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
- * (moving of dTD Head/Tail Pointers properly).
- * </pre>
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-
-#include "xusbps.h"
-#include "xusbps_endpoint.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/***************** Macros (Inline Functions) Definitions **********************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes *******************************/
-
-static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
-static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
-static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
-static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
-
-/*****************************************************************************/
-/**
-* This function is the first-level interrupt handler for the USB core. All USB
-* interrupts will be handled here. Depending on the type of the interrupt,
-* second level interrupt handler may be called. Second level interrupt
-* handlers will be registered by the user using the:
-* XUsbPs_IntrSetHandler()
-* and/or
-* XUsbPs_EpSetHandler()
-* functions.
-*
-*
-* @param HandlerRef is a Reference passed to the interrupt register
-* function. In our case this will be a pointer to the XUsbPs
-* instance.
-*
-* @return None
-*
-* @note None
-*
-******************************************************************************/
-void XUsbPs_IntrHandler(void *HandlerRef)
-{
- XUsbPs *InstancePtr;
-
- u32 IrqSts;
-
- Xil_AssertVoid(HandlerRef != NULL);
-
- InstancePtr = (XUsbPs *) HandlerRef;
-
- /* Handle controller (non-endpoint) related interrupts. */
- IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_ISR_OFFSET);
-
- /* Clear the interrupt status register. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_ISR_OFFSET, IrqSts);
-
- /* Nak interrupt, used to respond to host's IN request */
- if(IrqSts & XUSBPS_IXR_NAK_MASK) {
- /* Ack the hardware */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPNAKISR_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPNAKISR_OFFSET));
- }
-
-
- /***************************************************************
- *
- * Handle general interrupts. Endpoint interrupts will be handler
- * later.
- *
- */
-
- /* RESET interrupt.*/
- if (IrqSts & XUSBPS_IXR_UR_MASK) {
- XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
- return;
- }
-
- /* Check if we have a user handler that needs to be called. Note that
- * this is the handler for general interrupts. Endpoint interrupts will
- * be handled below.
- */
- if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
- }
-
-
- /***************************************************************
- *
- * Handle Endpoint interrupts.
- *
- */
- if (IrqSts & XUSBPS_IXR_UI_MASK) {
- u32 EpStat;
- u32 EpCompl;
-
- /* ENDPOINT 0 SETUP PACKET HANDLING
- *
- * Check if we got a setup packet on endpoint 0. Currently we
- * only check for setup packets on endpoint 0 as we would not
- * expect setup packets on any other endpoint (even though it
- * is possible to send setup packets on other endpoints).
- */
- EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET);
- if (EpStat & 0x0001) {
- /* Handle the setup packet */
- XUsbPs_IntrHandleEp0Setup(InstancePtr);
-
- /* Re-Prime the endpoint.
- * Endpoint is de-primed if a setup packet comes in.
- */
- XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
- }
-
- /* Check for RX and TX complete interrupts. */
- EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET);
-
-
- /* ACK the complete interrupts. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET, EpCompl);
-
- /* Check OUT (RX) endpoints. */
- if (EpCompl & XUSBPS_EP_OUT_MASK) {
- XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
- }
-
- /* Check IN (TX) endpoints. */
- if (EpCompl & XUSBPS_EP_IN_MASK) {
- XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
- }
- }
-}
-
-
-/*****************************************************************************/
-/**
-* This function registers the user callback handler for controller
-* (non-endpoint) interrupts.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param CallBackFunc is the Callback function to register.
-* CallBackFunc may be NULL to clear the entry.
-* @param CallBackRef is the user data reference passed to the
-* callback function. CallBackRef may be NULL.
-* @param Mask is the User interrupt mask. Defines which interrupts
-* will cause the callback to be called.
-*
-* @return
-* - XST_SUCCESS: Callback registered successfully.
-* - XST_FAILURE: Callback could not be registered.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- InstancePtr->HandlerFunc = CallBackFunc;
- InstancePtr->HandlerRef = CallBackRef;
- InstancePtr->HandlerMask = Mask;
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles TX buffer interrupts. It is called by the interrupt
-* when a transmit complete interrupt occurs. It returns buffers of completed
-* descriptors to the caller.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpCompl is the Bit mask of endpoints that caused a transmit
-* complete interrupt.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
-{
- int Index;
- u32 Mask;
- int NumEp;
-
- /* Check all endpoints for TX complete bits.
- */
- Mask = 0x00010000;
- NumEp = InstancePtr->DeviceConfig.NumEndpoints;
-
- /* Check for every endpoint if its TX complete bit is
- * set.
- */
- for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
- XUsbPs_EpIn *Ep;
-
- if (!(EpCompl & Mask)) {
- continue;
- }
- /* The TX complete bit for this endpoint is
- * set. Walk the list of descriptors to see
- * which ones are completed.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
- do {
-
- XUsbPs_dTDInvalidateCache(Ep->dTDTail);
-
- /* If the descriptor is not active then the buffer has
- * not been sent yet.
- */
- if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
- break;
- }
-
- if (Ep->HandlerFunc) {
- void *BufPtr;
-
- BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
- XUSBPS_dTDUSERDATA);
-
- Ep->HandlerFunc(Ep->HandlerRef, Index,
- XUSBPS_EP_EVENT_DATA_TX,
- BufPtr);
- }
-
- Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
- } while(Ep->dTDTail != Ep->dTDHead);
- }
-}
-
-
-/*****************************************************************************/
-/**
- * This function handles RX buffer interrupts. It is called by the interrupt
- * when a receive complete interrupt occurs. It notifies the callback functions
- * that have been registered with the individual endpoints that data has been
- * received.
- *
- * @param InstancePtr
- * Pointer to the XUsbPs instance of the controller.
- *
- * @param EpCompl
- * Bit mask of endpoints that caused a receive complete interrupt.
- * @return
- * none
- *
- ******************************************************************************/
-static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
-{
- XUsbPs_EpOut *Ep;
- int Index;
- u32 Mask;
- int NumEp;
-
- /* Check all endpoints for RX complete bits. */
- Mask = 0x00000001;
- NumEp = InstancePtr->DeviceConfig.NumEndpoints;
-
-
- /* Check for every endpoint if its RX complete bit is set.*/
- for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
- int numP = 0;
-
- if (!(EpCompl & Mask)) {
- continue;
- }
- Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
-
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- /* Handle all finished dTDs */
- while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
- numP += 1;
- if (Ep->HandlerFunc) {
- Ep->HandlerFunc(Ep->HandlerRef, Index,
- XUSBPS_EP_EVENT_DATA_RX, NULL);
- }
-
- Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
- }
- /* Re-Prime the endpoint.*/
- XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
- }
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles a RESET interrupt. It will notify the interrupt
-* handler callback of the RESET condition.
-*
-* @param InstancePtr is pointer to the XUsbPs instance of the controller
-* @param IrqSts is the Interrupt status register content.
-* To be passed on to the user.
-*
-* @return None
-*
-* @Note None.
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
-{
- int Timeout;
-
- /* Clear all setup token semaphores by reading the
- * XUSBPS_EPSTAT_OFFSET register and writing its value back to
- * itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET));
-
- /* Clear all the endpoint complete status bits by reading the
- * XUSBPS_EPCOMPL_OFFSET register and writings its value back
- * to itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET));
-
- /* Cancel all endpoint prime status by waiting until all bits
- * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
- * to XUSBPS_EPFLUSH_OFFSET.
- *
- * Avoid hanging here by using a Timeout counter...
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET) &
- XUSBPS_EP_ALL_MASK) && --Timeout) {
- /* NOP */
- }
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
-
- /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
- * still set at this point. If the code gets to this point and
- * the reset bit has already been cleared we are in trouble and
- * hardware reset is necessary.
- */
- if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_PORTSCR1_OFFSET) &
- XUSBPS_PORTSCR_PR_MASK)) {
- /* Send a notification to the user that a hardware
- * RESET is required. At this point we can only hope
- * that the user registered an interrupt handler and
- * will issue a hardware RESET.
- */
- if (InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
- IrqSts);
- }
- else {
- for (;;);
- }
-
- /* If we get here there is nothing more to do. The user
- * should have reset the core.
- */
- return;
- }
-
- /* Check if we have a user handler that needs to be called.
- */
- if (InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
- }
-
- /* We are done. After RESET we don't proceed in the interrupt
- * handler.
- */
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles a Setup Packet interrupt. It will notify the interrupt
-* handler callback of the RESET condition.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-*
-* @return None
-*
-* @Note None
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
-{
-
- XUsbPs_EpOut *Ep;
-
- /* Notifiy the user. */
- Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
-
- if (Ep->HandlerFunc) {
- Ep->HandlerFunc(Ep->HandlerRef, 0,
- XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
- }
-}
-
-
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
deleted file mode 100644
index a2070a76e69b73bcb9e553f4f2b4ce1e8e51817d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
- *
- * @file xusbps_sinit.c
-* @addtogroup usbps_v2_4
-* @{
- *
- * The implementation of the XUsbPs driver's static initialzation
- * functionality.
- *
- * <pre>
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * </pre>
- *
- *****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xusbps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-extern XUsbPs_Config XUsbPs_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the controller configuration based on the unique controller ID. A
-* table contains the configuration info for each controller in the system.
-*
-* @param DeviceID is the ID of the controller to look up the
-* configuration for.
-*
-* @return
-* A pointer to the configuration found or NULL if the specified
-* controller ID was not found.
-*
-******************************************************************************/
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
-{
- XUsbPs_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
- if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
- CfgPtr = &XUsbPs_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
deleted file mode 100644
index 837ca13624ab228e150dee23b0b07180f6f4de13..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner xadcps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling xadcps"
-
-xadcps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: xadcps_includes
-
-xadcps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
deleted file mode 100644
index 92a86560bfe169b7172c2be80b5512f777f7f0a9..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
+++ /dev/null
@@ -1,1831 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps.c
-* @addtogroup xadcps_v2_2
-* @{
-*
-* This file contains the driver API functions that can be used to access
-* the XADC device.
-*
-* Refer to the xadcps.h header file for more information about this driver.
-*
-* @note None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* to fix CR #693371
-* 2.1 bss 08/05/14 Modified Assert for XAdcPs_SetSingleChParams to fix
-* CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address
-* (CR#854437).
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
-u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
-
-
-/************************** Variable Definitions ****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a specific XAdcPs device/instance. This function
-* must be called prior to using the XADC device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param ConfigPtr points to the XAdcPs device configuration structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address is passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return
-* - XST_SUCCESS if successful.
-*
-* @note The user needs to first call the XAdcPs_LookupConfig() API
-* which returns the Configuration structure pointer which is
-* passed as a parameter to the XAdcPs_CfgInitialize() API.
-*
-******************************************************************************/
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
-
- u32 RegValue;
- /*
- * Assert the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
-
- /*
- * Set the values read from the device config and the base address.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
-
- /* Write Unlock value to Device Config Unlock register */
- XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
- XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
-
- /* Enable the PS access of xadc and set FIFO thresholds */
-
- RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET);
-
- RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
- XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET, RegValue);
-
- /* Release xadc from reset */
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x00);
-
- /*
- * Indicate the instance is now ready to use and
- * initialized without error.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions sets the contents of the Config Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET, Data);
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Config Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Config Register.
-* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Config Register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Miscellaneous Status Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Miscellaneous
-* Status Register. Use the XADCPS_MSTS_*_MASK constants defined
-* in xadcps_hw.h to interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous Status Register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MSTS_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions sets the contents of the Miscellaneous Control register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write to the Miscellaneous control register Register.
- */
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, Data);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Miscellaneous control register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Config Register.
-* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous control register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function resets the XADC Hard Macro in the device.
-*
-* @param InstancePtr is a pointer to the Xxadc instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XAdcPs_Reset(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Generate the reset by Control
- * register and release from reset
- */
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x10);
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x00);
-}
-
-
-/****************************************************************************/
-/**
-*
-* Get the ADC converted data for the specified channel.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Channel is the channel number. Use the XADCPS_CH_* defined in
-* the file xadcps.h.
-* The valid channels are
-* - 0 to 6
-* - 13 to 31
-*
-* @return A 16-bit value representing the ADC converted data for the
-* specified channel. The XADC Monitor/ADC device guarantees
-* a 10 bit resolution for the ADC converted data and data is the
-* 10 MSB bits of the 16 data read from the device.
-*
-* @note The channels 7,8,9 are used for calibration of the device and
-* hence there is no associated data with this channel.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
-{
-
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
- ((Channel >= XADCPS_CH_VCCPINT) &&
- (Channel <= XADCPS_CH_AUX_MAX)));
-
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_TEMP_OFFSET +
- Channel));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the calibration coefficient data for the specified
-* parameter.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param CoeffType specifies the calibration coefficient
-* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
-* specify the calibration coefficient to be read.
-*
-* @return A 16-bit value representing the calibration coefficient.
-* The XADC device guarantees a 10 bit resolution for
-* the ADC converted data and data is the 10 MSB bits of the 16
-* data read from the device.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
-
- /*
- * Read the selected calibration coefficient.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
- CoeffType));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the Minimum/Maximum measurement for one of the
-* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
-* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
-* VccPInt, VccPAux and VccPDro).
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param MeasurementType specifies the parameter for which the
-* Minimum/Maximum measurement has to be read.
-* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
-* specify the data to be read.
-*
-* @return A 16-bit value representing the maximum/minimum measurement for
-* specified parameter.
-* The XADC device guarantees a 10 bit resolution for
-* the ADC converted data and data is the 10 MSB bits of the 16
-* data read from the device.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
-{
- u32 RegData;
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
- ((MeasurementType >= XADCPS_MIN_VCCPINT) &&
- (MeasurementType <= XADCPS_MIN_VCCPDRO)))
-
- /*
- * Read and return the specified Minimum/Maximum measurement.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_MAX_TEMP_OFFSET +
- MeasurementType));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of samples of averaging that is to be done for
-* all the channels in both the single channel mode and sequence mode of
-* operations.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Average is the number of samples of averaging programmed to the
-* Configuration Register 0. Use the XADCPS_AVG_* definitions defined
-* in xadcps.h file :
-* - XADCPS_AVG_0_SAMPLES for no averaging
-* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging
-* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging
-* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
-
- /*
- * Write the averaging value into the Configuration Register 0.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_AVG_VALID_MASK);
-
- RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegData);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the number of samples of averaging configured for all
-* the channels in the Configuration Register 0.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The averaging read from the Configuration Register 0 is
-* returned. Use the XADCPS_AVG_* bit definitions defined in
-* xadcps.h file to interpret the returned value :
-* - XADCPS_AVG_0_SAMPLES means no averaging
-* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
-* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
-* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
-{
- u32 Average;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the averaging value from the Configuration Register 0.
- */
- Average = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
-
-
- return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the given parameters in the Configuration Register 0 in
-* the single channel mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Channel is the channel number for the singel channel mode.
-* The valid channels are 0 to 6, 8, and 13 to 31.
-* If the external Mux is used then this specifies the channel
-* oonnected to the external Mux. Please read the Device Spec
-* to know which channels are valid.
-* @param IncreaseAcqCycles is a boolean parameter which specifies whether
-* the Acquisition time for the external channels has to be
-* increased to 10 ADCCLK cycles (specify TRUE) or remain at the
-* default 4 ADCCLK cycles (specify FALSE). This parameter is
-* only valid for the external channels.
-* @param IsDifferentialMode is a boolean parameter which specifies
-* unipolar(specify FALSE) or differential mode (specify TRUE) for
-* the analog inputs. The input mode is only valid for the
-* external channels.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the Configuration Register 0.
-* - XST_FAILURE if the channel sequencer is enabled or the input
-* parameters are not valid for the selected channel.
-*
-* @note
-* - The number of samples for the averaging for all the channels
-* is set by using the function XAdcPs_SetAvg.
-* - The calibration of the device is done by doing a ADC
-* conversion on the calibration channel(channel 8). The input
-* parameters IncreaseAcqCycles, IsDifferentialMode and
-* IsEventMode are not valid for this channel
-*
-*
-*****************************************************************************/
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
- (Channel == XADCPS_CH_ADC_CALIB) ||
- ((Channel >= XADCPS_CH_VCCPINT) &&
- (Channel <= XADCPS_CH_AUX_MAX)));
- Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
- (IncreaseAcqCycles == FALSE));
- Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
- Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
- (IsDifferentialMode == FALSE));
-
- /*
- * Check if the device is in single channel mode else return failure
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) !=
- XADCPS_SEQ_MODE_SINGCHAN)) {
- return XST_FAILURE;
- }
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- XADCPS_CFR0_AVG_VALID_MASK;
-
- /*
- * Select the number of acquisition cycles. The acquisition cycles is
- * only valid for the external channels.
- */
- if (IncreaseAcqCycles == TRUE) {
- if (((Channel >= XADCPS_CH_AUX_MIN) &&
- (Channel <= XADCPS_CH_AUX_MAX)) ||
- (Channel == XADCPS_CH_VPVN)){
- RegValue |= XADCPS_CFR0_ACQ_MASK;
- } else {
- return XST_FAILURE;
- }
-
- }
-
- /*
- * Select the input mode. The input mode is only valid for the
- * external channels.
- */
- if (IsDifferentialMode == TRUE) {
-
- if (((Channel >= XADCPS_CH_AUX_MIN) &&
- (Channel <= XADCPS_CH_AUX_MAX)) ||
- (Channel == XADCPS_CH_VPVN)){
- RegValue |= XADCPS_CFR0_DU_MASK;
- } else {
- return XST_FAILURE;
- }
- }
-
- /*
- * Select the ADC mode.
- */
- if (IsEventMode == TRUE) {
- RegValue |= XADCPS_CFR0_EC_MASK;
- }
-
- /*
- * Write the given values into the Configuration Register 0.
- */
- RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the alarm outputs for the specified alarms in the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-* in the Configuration Register 1.
-* Bit positions of 1 will be enabled. Bit positions of 0 will be
-* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
-* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note The implementation of the alarm enables in the Configuration
-* register 1 is such that the alarms for bit positions of 1 will
-* be disabled and alarms for bit positions of 0 will be enabled.
-* The alarm outputs specified by the AlmEnableMask are negated
-* before writing to the Configuration Register 1.
-*
-*
-*****************************************************************************/
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
-
- RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
- RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
-
- /*
- * Enable/disables the alarm enables for the specified alarm bits in the
- * Configuration Register 1.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of the alarm output enables in the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return This is the bit-mask of the enabled alarm outputs in the
-* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
-* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
-* returned value.
-* Bit positions of 1 indicate that the alarm output is enabled.
-* Bit positions of 0 indicate that the alarm output is disabled.
-*
-*
-* @note The implementation of the alarm enables in the Configuration
-* register 1 is such that alarms for the bit positions of 1 will
-* be disabled and alarms for bit positions of 0 will be enabled.
-* The enabled alarm outputs returned by this function is the
-* negated value of the the data read from the Configuration
-* Register 1.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the status of alarm output enables from the Configuration
- * Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
- return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified calibration in the Configuration
-* Register 1 :
-*
-* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
-* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
-* correction
-* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
-* offset correction
-* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
-* gain and offset correction
-* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Calibration is the Calibration to be applied.
-* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
-* Multiple calibrations can be enabled at a time by oring the
-* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
-* Calibration can be disabled by specifying
- XADCPS_CFR1_CAL_DISABLE_MASK;
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
- (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
- (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
-
- /*
- * Set the specified calibration in the Configuration Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET);
-
- RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
- RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the value of the calibration enables from the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The value of the calibration enables in the Configuration
-* Register 1 :
-* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
-* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
-* correction
-* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
-* correction
-* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
-* gain and offset correction
-* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the calibration enables from the Configuration Register 1.
- */
- return (u16) XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the specified Channel Sequencer Mode in the Configuration
-* Register 1 :
-* - Default safe mode (XADCPS_SEQ_MODE_SAFE)
-* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
-* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
-* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
-* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
-* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param SequencerMode is the sequencer mode to be set.
-* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
-* @return None.
-*
-* @note Only one of the modes can be enabled at a time. Please
-* read the Spec of the XADC for further information about the
-* sequencer modes.
-*
-*
-*****************************************************************************/
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
- (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
-
- /*
- * Set the specified sequencer mode in the Configuration Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET);
- RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
- RegValue |= ((SequencerMode << XADCPS_CFR1_SEQ_SHIFT) &
- XADCPS_CFR1_SEQ_VALID_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel sequencer mode from the Configuration
-* Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The channel sequencer mode :
-* - XADCPS_SEQ_MODE_SAFE : Default safe mode
-* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
-* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
-* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
-* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
-* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
-*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel sequencer mode from the Configuration Register 1.
- */
- return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
- XADCPS_CFR1_SEQ_SHIFT));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the frequency of the ADCCLK by configuring the DCLK to
-* ADCCLK ratio in the Configuration Register #2
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Divisor is clock divisor used to derive ADCCLK from DCLK.
-* Valid values of the divisor are
-* - 0 to 255. Values 0, 1, 2 are all mapped to 2.
-* Refer to the device specification for more details
-*
-* @return None.
-*
-* @note - The ADCCLK is an internal clock used by the ADC and is
-* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-* divided by the user selection in the Configuration Register 2.
-* - There is no Assert on the minimum value of the Divisor.
-*
-*****************************************************************************/
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write the divisor value into the Configuration Register #2.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
- Divisor << XADCPS_CFR2_CD_SHIFT);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function gets the ADCCLK divisor from the Configuration Register 2.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The divisor read from the Configuration Register 2.
-*
-* @note The ADCCLK is an internal clock used by the ADC and is
-* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-* divided by the user selection in the Configuration Register 2.
-*
-*****************************************************************************/
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
-{
- u16 Divisor;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the divisor value from the Configuration Register 2.
- */
- Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET);
-
- return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified channels in the ADC Channel Selection
-* Sequencer Registers. The sequencer must be disabled before writing to these
-* regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param ChEnableMask is the bit mask of all the channels to be enabled.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
-* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
-* be disabled.
-* The ChEnableMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Selection Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Selection Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Enable the specified channels in the ADC Channel Selection Sequencer
- * Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ00_OFFSET,
- (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ01_OFFSET,
- (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ01_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel enable bits status from the ADC Channel
-* Selection Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
-* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
-* are the channels that are enabled and bit mask of 0 are
-* the channels that are disabled.
-*
-* @return None
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
-{
- u32 RegValEnable;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel enable bits for all the channels from the ADC
- * Channel Selection Register.
- */
- RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ00_OFFSET) &
- XADCPS_SEQ00_CH_VALID_MASK;
- RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ01_OFFSET) &
- XADCPS_SEQ01_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
-
- return RegValEnable;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the averaging for the specified channels in the ADC
-* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AvgEnableChMask is the bit mask of all the channels for which
-* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
-* xadcps_hw.h to specify the Channel numbers. Averaging will be
-* enabled for bit masks of 1 and disabled for bit mask of 0.
-* The AvgEnableChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Averaging Enable Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Averaging Enables Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Enable/disable the averaging for the specified channels in the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ02_OFFSET,
- (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ03_OFFSET,
- (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ03_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the channels for which the averaging has been enabled
-* in the ADC Channel Averaging Enables Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The status of averaging (enabled/disabled) for all the channels.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* averaging is enabled and bit mask of 0 are the channels for
-* averaging is disabled
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
-{
- u32 RegValAvg;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the averaging enable status for all the channels from the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
- RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return RegValAvg;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Analog input mode for the specified channels in the ADC
-* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param InputModeChMask is the bit mask of all the channels for which
-* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
-* in xadcps_hw.h to specify the channel numbers. Differential
-* input mode will be set for bit masks of 1 and unipolar input
-* mode for bit masks of 0.
-* The InputModeChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Set the input mode for the specified channels in the ADC Channel
- * Analog-Input Mode Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ04_OFFSET,
- (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ05_OFFSET,
- (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ05_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Analog input mode for all the channels from
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The input mode for all the channels.
-* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* input mode is differential and bit mask of 0 are the channels
-* for which input mode is unipolar.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
-{
- u32 InputMode;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the input mode for all the channels from the ADC Channel
- * Analog-Input Mode Sequencer Registers.
- */
- InputMode = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ04_OFFSET) &
- XADCPS_SEQ04_CH_VALID_MASK;
- InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ05_OFFSET) &
- XADCPS_SEQ05_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return InputMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of Acquisition cycles in the ADC Channel
-* Acquisition Time Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AcqCyclesChMask is the bit mask of all the channels for which
-* the number of acquisition cycles is to be extended.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
-* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
-* for bit masks of 1 and will be the default 4 ADCCLK cycles for
-* bit masks of 0.
-* The AcqCyclesChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Acquisition Time Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the Channel Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None.
-*
-*****************************************************************************/
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) !=
- XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Set the Acquisition time for the specified channels in the
- * ADC Channel Acquisition Time Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ06_OFFSET,
- (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ07_OFFSET,
- (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ07_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of acquisition from the ADC Channel Acquisition
-* Time Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The acquisition time for all the channels.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* acquisition cycles are extended and bit mask of 0 are the
-* channels for which acquisition cycles are not extended.
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
-{
- u32 RegValAcq;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the Acquisition cycles for the specified channels from the ADC
- * Channel Acquisition Time Sequencer Registers.
- */
- RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ06_OFFSET) &
- XADCPS_SEQ06_CH_VALID_MASK;
- RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ07_OFFSET) &
- XADCPS_SEQ07_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return RegValAcq;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the contents of the given Alarm Threshold Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlarmThrReg is the index of an Alarm Threshold Register to
-* be set. Use XADCPS_ATR_* constants defined in xadcps.h to
-* specify the index.
-* @param Value is the 16-bit threshold value to write into the register.
-*
-* @return None.
-*
-* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper
-* threshold value.
-*
-*****************************************************************************/
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
-{
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
-
- /*
- * Write the value into the specified Alarm Threshold Register.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
- AlarmThrReg,Value);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the specified Alarm Threshold Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlarmThrReg is the index of an Alarm Threshold Register
-* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h
-* to specify the index.
-*
-* @return A 16-bit value representing the contents of the selected Alarm
-* Threshold Register.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
-{
- u32 RegData;
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
-
- /*
- * Read the specified Alarm Threshold Register and return
- * the value
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
-
- return (u16) RegData;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function enables programming of the powerdown temperature for the
-* OverTemp signal in the OT Powerdown register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
-{
- u16 OtUpper;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the OT upper Alarm Threshold Register.
- */
- OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET);
- OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
-
- /*
- * Preserve the powerdown value and write OT enable value the into the
- * OT Upper Alarm Threshold Register.
- */
- OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables programming of the powerdown temperature for the
-* OverTemp signal in the OT Powerdown register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
-{
- u16 OtUpper;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the OT Upper Alarm Threshold Register.
- */
- OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET);
- OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The function enables the Event mode or Continuous mode in the sequencer mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param IsEventMode is a boolean parameter that specifies continuous
-* sampling (specify FALSE) or event driven sampling mode (specify
-* TRUE) for the given channel.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_EC_MASK);
-
- /*
- * Set the ADC mode.
- */
- if (IsEventMode == TRUE) {
- RegValue |= XADCPS_CFR0_EC_MASK;
- } else {
- RegValue &= ~XADCPS_CFR0_EC_MASK;
- }
-
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function returns the sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The sampling mode
-* - 0 specifies continuous sampling
-* - 1 specifies event driven sampling mode
-*
-* @note None.
-*
-*****************************************************************************/
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
-{
- u32 Mode;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the sampling mode from the Configuration Register 0.
- */
- Mode = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- XADCPS_CFR0_EC_MASK;
- if (Mode) {
-
- return 1;
- }
-
- return (0);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sets the External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param MuxMode specifies whether External Mux is used
-* - FALSE specifies NO external MUX
-* - TRUE specifies External Mux is used
-* @param Channel specifies the channel to be used for the
-* external Mux. Please read the Device Spec for which
-* channels are valid for which mode.
-*
-* @return None.
-*
-* @note There is no Assert in this function for checking the channel
-* number if the external Mux is used. The user should provide a
-* valid channel number.
-*
-*****************************************************************************/
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_MUX_MASK);
- /*
- * Select the Mux mode and the channel to be used.
- */
- if (MuxMode == TRUE) {
- RegValue |= XADCPS_CFR0_MUX_MASK;
- RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
-
- }
-
- /*
- * Write the mux mode into the Configuration Register 0.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sets the Power Down mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mode specifies the Power Down Mode
-* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
-* ADC B are enabled)
-* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
-* - XADCPS_PD_MODE_XADC specifies the Power Down of
-* both ADC A and ADC B.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
-
-
- /*
- * Read the Configuration Register 2.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET) &
- (~XADCPS_CFR2_PD_MASK);
- /*
- * Select the Power Down mode.
- */
- RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
-
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
- RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Power Down mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Mode specifies the Power Down Mode
-* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
-* ADC B are enabled)
-* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
-* - XADCPS_PD_MODE_XADC specifies the Power Down of
-* both ADC A and ADC B.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Power Down Mode.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET) &
- (~XADCPS_CFR2_PD_MASK);
- /*
- * Return the Power Down mode.
- */
- return (RegValue >> XADCPS_CFR2_PD_SHIFT);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for writing to XADC Registers using the command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param RegOffset is the offset of the XADC register to be written.
-* @param Data is the data to be written.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
-{
- u32 RegData;
-
- /*
- * Write the Data into the FIFO Register.
- */
- RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
-
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Read the Read FIFO after any write since for each write
- * one location of Read FIFO gets updated
- */
- XAdcPs_ReadFifo(InstancePtr);
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function is used for reading from the XADC Registers using the Data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param RegOffset is the offset of the XADC register to be read.
-*
-* @return Data read from the FIFO
-*
-* @note None.
-*
-*
-*****************************************************************************/
-u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
-{
-
- u32 RegData;
-
- RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
-
- /* Read cmd to FIFO*/
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Do a Dummy read */
- RegData = XAdcPs_ReadFifo(InstancePtr);
-
- /* Do a Dummy write to get the actual read */
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Do the Actual read */
- RegData = XAdcPs_ReadFifo(InstancePtr);
-
- return RegData;
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
deleted file mode 100644
index 549bfff298f5c67a35b28b5231b1636dafd4396c..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps.h
-* @addtogroup xadcps_v2_2
-* @{
-* @details
-*
-* The XAdcPs driver supports the Xilinx XADC/ADC device.
-*
-* The XADC/ADC device has the following features:
-* - 10-bit, 200-KSPS (kilo samples per second)
-* Analog-to-Digital Converter (ADC)
-* - Monitoring of on-chip supply voltages and temperature
-* - 1 dedicated differential analog-input pair and
-* 16 auxiliary differential analog-input pairs
-* - Automatic alarms based on user defined limits for the on-chip
-* supply voltages and temperature
-* - Automatic Channel Sequencer, programmable averaging, programmable
-* acquisition time for the external inputs, unipolar or differential
-* input selection for the external inputs
-* - Inbuilt Calibration
-* - Optional interrupt request generation
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the XADC/ADC device.
-*
-*
-* <b> XADC Channel Sequencer Modes </b>
-*
-* The XADC Channel Sequencer supports the following operating modes:
-*
-* - <b> Default </b>: This is the default mode after power up.
-* In this mode of operation the XADC operates in
-* a sequence mode, monitoring the on chip sensors:
-* Temperature, VCCINT, and VCCAUX.
-* - <b> One pass through sequence </b>: In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers for a single pass and then stops.
-* - <b> Continuous cycling of sequence </b>: In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers continuously.
-* - <b> Single channel mode</b>: In this mode the XADC Channel
-* Sequencer is disabled and the XADC operates in a
-* Single Channel Mode.
-* The XADC can operate either in a Continuous or Event
-* driven sampling mode in the single channel mode.
-* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
-* Sequencer will automatically sequence through eight fixed pairs
-* of auxiliary analog input channels for simulataneous conversion.
-* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
-* is used to implement a fixed monitoring mode similar to the
-* default mode but the alarm fucntions ar eenabled.
-* The second ADC (B) is available to be used with external analog
-* input channels only.
-*
-* Read the XADC spec for more information about the sequencer modes.
-*
-* <b> Initialization and Configuration </b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the XADC/ADC device.
-*
-* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
-* device. The user needs to first call the XAdcPs_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAdcPs_CfgInitialize() API.
-*
-*
-* <b>Interrupts</b>
-*
-* The XADC/ADC device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* The interrupt mode is available only if hardware is configured to support
-* interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* <b> Virtual Memory </b>
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* <b> Threads </b>
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* <b> Asserts </b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* <b> Building the driver </b>
-*
-* The XAdcPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* <b> Limitations of the driver </b>
-*
-* XADC/ADC device can be accessed through the JTAG port and the PLB
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to care of this situation
-* in the user application code.
-*
-* <br><br>
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4 /**< VREFP */
-#define XADCPS_CH_VREFN 0x5 /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-
-u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
deleted file mode 100644
index ab17ec3f0758694622d106b1c03879dd6717feb3..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xadcps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_XADC_0_DEVICE_ID,
- XPAR_PS7_XADC_0_BASEADDR
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
deleted file mode 100644
index 55a47a440a6a9933952aa7d70ad73b5e198c689b..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_2
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-*
-* </pre>
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */
-#define XADCPS_CFR2_CD_SHIFT 8 /**<Num of shift on division */
-#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
-#define XADCPS_CFR2_CD_MAX 255 /**<Maximum value of divisor */
-
-#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
-#define XADCPS_CFR2_PD_MASK 0x0030 /**<Power Down Mask */
-#define XADCPS_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */
-#define XADCPS_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down ADC1 Mask */
-#define XADCPS_CFR2_PD_SHIFT 4 /**<Power Down Shift */
-/*@}*/
-
-/**
- * @name Sequence Register (SEQ) Bit Definitions
- * @{
- */
-#define XADCPS_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */
-#define XADCPS_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */
-#define XADCPS_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */
-#define XADCPS_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */
-#define XADCPS_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */
-#define XADCPS_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */
-#define XADCPS_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */
-#define XADCPS_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */
-#define XADCPS_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */
-#define XADCPS_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */
-#define XADCPS_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series */
-#define XADCPS_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */
-#define XADCPS_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */
-#define XADCPS_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */
-#define XADCPS_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */
-#define XADCPS_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */
-#define XADCPS_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */
-#define XADCPS_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */
-#define XADCPS_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */
-#define XADCPS_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */
-#define XADCPS_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */
-#define XADCPS_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */
-#define XADCPS_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */
-#define XADCPS_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */
-#define XADCPS_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */
-#define XADCPS_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */
-#define XADCPS_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */
-
-#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */
-#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */
-#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
-#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-#define XADCPS_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
-#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
-
-
-#define XADCPS_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */
-
-/*@}*/
-
-/**
- * @name OT Upper Alarm Threshold Register Bit Definitions
- * @{
- */
-
-#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */
-#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */
-#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */
-#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */
-#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */
-
-/*@}*/
-
-
-/**
- * @name JTAG DRP Bit Definitions
- * @{
- */
-#define XADCPS_JTAG_DATA_MASK 0x0000FFFF /**< Mask for the Data */
-#define XADCPS_JTAG_ADDR_MASK 0x03FF0000 /**< Mask for the Addr */
-#define XADCPS_JTAG_ADDR_SHIFT 16 /**< Shift for the Addr */
-#define XADCPS_JTAG_CMD_MASK 0x3C000000 /**< Mask for the Cmd */
-#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000 /**< Mask for CMD Write */
-#define XADCPS_JTAG_CMD_READ_MASK 0x04000000 /**< Mask for CMD Read */
-#define XADCPS_JTAG_CMD_SHIFT 26 /**< Shift for the Cmd */
-
-/*@}*/
-
-/** @name Unlock Register Definitions
- * @{
- */
- #define XADCPS_UNLK_OFFSET 0x034 /**< Unlock Register */
- #define XADCPS_UNLK_VALUE 0x757BDF0D /**< Unlock Value */
-
- /* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-*
-* Read a register of the XADC device. This macro provides register
-* access to all registers using the register offsets defined above.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset is the offset of the register to read.
-*
-* @return The contents of the register.
-*
-* @note C-style Signature:
-* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
-*
-******************************************************************************/
-#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-/*****************************************************************************/
-/**
-*
-* Write a register of the XADC device. This macro provides
-* register access to all registers using the register offsets defined above.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset is the offset of the register to write.
-* @param Data is the value to write to the register.
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XAdcPs_WriteReg(u32 BaseAddress,
-* u32 RegOffset,u32 Data)
-*
-******************************************************************************/
-#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Formats the data to be written to the the XADC registers.
-*
-* @param RegOffset is the offset of the Register
-* @param Data is the data to be written to the Register if it is
-* a write.
-* @param ReadWrite specifies whether it is a Read or a Write.
-* Use 0 for Read, 1 for Write.
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XAdcPs_FormatWriteData(u32 RegOffset,
-* u16 Data, int ReadWrite)
-*
-******************************************************************************/
-#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \
- ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
- ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
- (Data & XADCPS_JTAG_DATA_MASK))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
deleted file mode 100644
index 70a8697476baa4936baa7cdc16e3c9ca7b466b94..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xadcps_intr.c
-* @addtogroup xadcps_v2_2
-* @{
-*
-* This file contains interrupt handling API functions of the XADC
-* device.
-*
-* The device must be configured at hardware build time to support interrupt
-* for all the functions in this file to work.
-*
-* Refer to xadcps.h header file and device specification for more information.
-*
-* @note
-*
-* Calling the interrupt functions without including the interrupt component will
-* result in asserts if asserts are enabled, and will result in a unpredictable
-* behavior if the asserts are not enabled.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be enabled.
-* Bit positions of 1 will be enabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XADCPS_INTX_* bits defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the specified interrupts in the IPIER.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET);
- RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be disabled.
-* Bit positions of 1 will be disabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XADCPS_INTX_* bits defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Enable the specified interrupts in the IPIER.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET);
- RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET,
- RegValue);
-}
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Mask
-* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the I.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Enable Register.
- */
- return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the IPISR.
-*
-* @note The device must be configured at hardware build time to include
-* interrupt component for this function to work.
-*
-*****************************************************************************/
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Status register.
- */
- return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register (IPISR).
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be cleared.
-* Bit positions of 1 will be cleared. Bit positions of 0 will not
-* change the previous interrupt status. This mask is formed by
-* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Clear the specified interrupts in the Interrupt Status register.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_STS_OFFSET);
- RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
- RegValue);
-
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
deleted file mode 100644
index 7f171b416b5b576416d5d71f25ed4952fffcd0cf..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xadcps_selftest.c
-* @addtogroup xadcps_v2_2
-* @{
-*
-* This file contains a diagnostic self test function for the XAdcPs driver.
-* The self test function does a simple read/write test of the Alarm Threshold
-* Register.
-*
-* See xadcps.h for more information.
-*
-* @note None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-*
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constant defines the test value to be written
- * to the Alarm Threshold Register
- */
-#define XADCPS_ATR_TEST_VALUE 0x55
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. The test
-* - Resets the device,
-* - Writes a value into the Alarm Threshold register and reads it back
-* for comparison.
-* - Resets the device again.
-*
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - XST_SUCCESS if the value read from the Alarm Threshold
-* register is the same as the value written.
-* - XST_FAILURE Otherwise
-*
-* @note This is a destructive test in that resets of the device are
-* performed. Refer to the device specification for the
-* device status after the reset operation.
-*
-******************************************************************************/
-int XAdcPs_SelfTest(XAdcPs *InstancePtr)
-{
- int Status;
- u32 RegValue;
-
- /*
- * Assert the argument
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- /*
- * Reset the device to get it back to its default state
- */
- XAdcPs_Reset(InstancePtr);
-
- /*
- * Write a value into the Alarm Threshold registers, read it back, and
- * do the comparison
- */
- XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
- XADCPS_ATR_TEST_VALUE);
- RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
-
- if (RegValue == XADCPS_ATR_TEST_VALUE) {
- Status = XST_SUCCESS;
- } else {
- Status = XST_FAILURE;
- }
-
- /*
- * Reset the device again to its default state.
- */
- XAdcPs_Reset(InstancePtr);
- /*
- * Return the test result.
- */
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
deleted file mode 100644
index 5fb7cdeadfa46d0e590913dd89d81925ade784cf..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xadcps_sinit.c
-* @addtogroup xadcps_v2_2
-* @{
-*
-* This file contains the implementation of the XAdcPs driver's static
-* initialization functionality.
-*
-* @note None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xadcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XAdcPs_Config XAdcPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* This function looks up the device configuration based on the unique device ID.
-* The table XAdcPs_ConfigTable contains the configuration info for each device
-* in the system.
-*
-* @param DeviceId contains the ID of the device for which the
-* device configuration pointer is to be returned.
-*
-* @return
-* - A pointer to the configuration found.
-* - NULL if the specified device ID was not found.
-*
-* @note None.
-*
-******************************************************************************/
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
-{
- XAdcPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index=0; Index < 1; Index++) {
- if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XAdcPs_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/system.mss b/quad/xsdk_workspace_vivado/system_bsp/system.mss
deleted file mode 100644
index ecb14d2adb87bf499ef16182745346911cb91be6..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/system_bsp/system.mss
+++ /dev/null
@@ -1,334 +0,0 @@
-
- PARAMETER VERSION = 2.2.0
-
-
-BEGIN OS
- PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 6.7
- PARAMETER PROC_INSTANCE = ps7_cortexa9_0
- PARAMETER stdin = ps7_uart_0
- PARAMETER stdout = ps7_uart_0
-END
-
-
-BEGIN PROCESSOR
- PARAMETER DRIVER_NAME = cpu_cortexa9
- PARAMETER DRIVER_VER = 2.6
- PARAMETER HW_INSTANCE = ps7_cortexa9_0
-END
-
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_btns
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_leds
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_sws
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = tmrctr
- PARAMETER DRIVER_VER = 4.4
- PARAMETER HW_INSTANCE = axi_timer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.4
- PARAMETER HW_INSTANCE = ps7_coresight_comp_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = ddrps
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = ps7_ddr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ddrc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = devcfg
- PARAMETER DRIVER_VER = 3.5
- PARAMETER HW_INSTANCE = ps7_dev_cfg_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 2.3
- PARAMETER HW_INSTANCE = ps7_dma_ns
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 2.3
- PARAMETER HW_INSTANCE = ps7_dma_s
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.7
- PARAMETER HW_INSTANCE = ps7_ethernet_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_globaltimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpiops
- PARAMETER DRIVER_VER = 3.3
- PARAMETER HW_INSTANCE = ps7_gpio_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_gpv_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.7
- PARAMETER HW_INSTANCE = ps7_i2c_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.7
- PARAMETER HW_INSTANCE = ps7_i2c_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_intc_dist_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_l2cachec_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ocmc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_pl310_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_pmu_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = qspips
- PARAMETER DRIVER_VER = 3.4
- PARAMETER HW_INSTANCE = ps7_qspi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_qspi_linear_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ram_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ram_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_scuc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.9
- PARAMETER HW_INSTANCE = ps7_scugic_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scutimer
- PARAMETER DRIVER_VER = 2.1
- PARAMETER HW_INSTANCE = ps7_scutimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scuwdt
- PARAMETER DRIVER_VER = 2.1
- PARAMETER HW_INSTANCE = ps7_scuwdt_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 3.5
- PARAMETER HW_INSTANCE = ps7_sd_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_slcr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.6
- PARAMETER HW_INSTANCE = ps7_uart_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.6
- PARAMETER HW_INSTANCE = ps7_uart_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = usbps
- PARAMETER DRIVER_VER = 2.4
- PARAMETER HW_INSTANCE = ps7_usb_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = xadcps
- PARAMETER DRIVER_VER = 2.2
- PARAMETER HW_INSTANCE = ps7_xadc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_4
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_5
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_3
-END
-
-
-BEGIN LIBRARY
- PARAMETER LIBRARY_NAME = xilffs
- PARAMETER LIBRARY_VER = 3.9
- PARAMETER PROC_INSTANCE = ps7_cortexa9_0
-END
-
-