From 580829209a34d1bf96b879f7742473d280625c02 Mon Sep 17 00:00:00 2001
From: James Talbert <jtalbert@iastate.edu>
Date: Mon, 15 Oct 2018 16:21:58 -0500
Subject: [PATCH] Update Quad_Hardware_Platform_info.md
---
quad/doc/Quad_Hardware_Platform_info.md | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/quad/doc/Quad_Hardware_Platform_info.md b/quad/doc/Quad_Hardware_Platform_info.md
index b98d5bcc9..a85af44c8 100644
--- a/quad/doc/Quad_Hardware_Platform_info.md
+++ b/quad/doc/Quad_Hardware_Platform_info.md
@@ -7,7 +7,6 @@ The design includes:
- 1 Zynq Processing System block
- 6 PWM Recorder Blocks
- 4 PWM Generator Blocks
- - 1 AXI Timer block
- Any debugging GPIOs.
## Settings
@@ -37,6 +36,9 @@ Within the PS, we use both I2C controllers, a UART for the wifi bridge, and othe
- Enabled: true
- Frequency: 100 MHZ
+### AXI Bus Modules
+The axi bus modules do not require configuration.
+It is unlikely that the custom blocks will ever have useful configuration parameters as they are one-off and will be set for what the project needs.
## Unclarities
This section is for things that are in the design, but we don't know why (passed down over time and not yet investigated).
@@ -48,4 +50,6 @@ It is unclear if this is just a bug in XPS (seems likely) or if the interrupt is
### Clock Configuration
The clock configurations in the old XPS proejct are at slightly lower frequencies than the Vivado defaults.
This could mean that the old team has some problems running at max and backed it down some, or that Xilinx upped the default clock frequency between the Zybo part and the Zybo Z7020.
-E.g. The CPU clock is at 650 MHz in the old project, but the defaults in Vivado are 667 MHz.
\ No newline at end of file
+E.g. The CPU clock is at 650 MHz in the old project, but the defaults in Vivado are 667 MHz.
+
+Dr. Jones agrees that it is likely a default settings change and can be ignored.
\ No newline at end of file
--
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