From 4b837ad571a6ef4e06898b548e76905756910560 Mon Sep 17 00:00:00 2001
From: James Talbert <jtalbert@iastate.edu>
Date: Mon, 29 Oct 2018 17:50:32 -0500
Subject: [PATCH] Make the quad fly in manual mode! It turns out that the
motors and IMU were actually not flipped around, I had a naming bug in the
block design that made a bunch of things look wrong, and the direction plate
was flipped (velcro got removed and re-attached).
---
quad/vivado_workspace/quad_hw.tcl | 69 +++++++++----------
.../real_quad/src/hw_impl_zybo.h | 25 +++----
.../real_quad/src/hw_impl_zybo_imu.c | 4 +-
3 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/quad/vivado_workspace/quad_hw.tcl b/quad/vivado_workspace/quad_hw.tcl
index b51741d61..503789e45 100644
--- a/quad/vivado_workspace/quad_hw.tcl
+++ b/quad/vivado_workspace/quad_hw.tcl
@@ -3,7 +3,7 @@
#
# quad_hw.tcl: Tcl script for re-creating project 'quad_hw'
#
-# Generated by Vivado on Fri Oct 05 17:15:40 CDT 2018
+# Generated by Vivado on Mon Oct 29 17:47:47 CDT 2018
# IP Build 2289599 on Thu Jul 26 21:09:20 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -162,6 +162,7 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
+
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "design_1_wrapper" -objects $obj
@@ -296,34 +297,33 @@ proc cr_bd_design_1 { parentCell } {
set pwm_out_2 [ create_bd_port -dir O pwm_out_2 ]
set pwm_out_3 [ create_bd_port -dir O pwm_out_3 ]
-
- # Create instance: axi_gpio_0, and set properties
- set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ # Create instance: axi_gpio_3, and set properties
+ set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ]
set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {sws_4bits} \
+ CONFIG.GPIO_BOARD_INTERFACE {rgb_led} \
CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_0
+ ] $axi_gpio_3
- # Create instance: axi_gpio_1, and set properties
- set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ # Create instance: axi_gpio_btns, and set properties
+ set axi_gpio_btns [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_btns ]
set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {leds_4bits} \
+ CONFIG.GPIO_BOARD_INTERFACE {btns_4bits} \
CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_1
+ ] $axi_gpio_btns
- # Create instance: axi_gpio_2, and set properties
- set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
+ # Create instance: axi_gpio_leds, and set properties
+ set axi_gpio_leds [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_leds ]
set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {btns_4bits} \
+ CONFIG.GPIO_BOARD_INTERFACE {leds_4bits} \
CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_2
+ ] $axi_gpio_leds
- # Create instance: axi_gpio_3, and set properties
- set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ]
+ # Create instance: axi_gpio_sws, and set properties
+ set axi_gpio_sws [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sws ]
set_property -dict [ list \
- CONFIG.GPIO_BOARD_INTERFACE {rgb_led} \
+ CONFIG.GPIO_BOARD_INTERFACE {sws_4bits} \
CONFIG.USE_BOARD_FLOW {true} \
- ] $axi_gpio_3
+ ] $axi_gpio_sws
# Create instance: axi_timer_0, and set properties
set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
@@ -860,16 +860,16 @@ proc cr_bd_design_1 { parentCell } {
set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
# Create interface connections
- connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports sws_4bits] [get_bd_intf_pins axi_gpio_0/GPIO]
- connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports leds_4bits] [get_bd_intf_pins axi_gpio_1/GPIO]
- connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports btns_4bits] [get_bd_intf_pins axi_gpio_2/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports sws_4bits] [get_bd_intf_pins axi_gpio_sws/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports leds_4bits] [get_bd_intf_pins axi_gpio_leds/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports btns_4bits] [get_bd_intf_pins axi_gpio_btns/GPIO]
connect_bd_intf_net -intf_net axi_gpio_3_GPIO [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_3/GPIO]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_sws/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_leds/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_btns/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins ps7_0_axi_periph/M04_AXI] [get_bd_intf_pins pwm_recorder_0/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M05_AXI [get_bd_intf_pins ps7_0_axi_periph/M05_AXI] [get_bd_intf_pins pwm_recorder_1/S_AXI]
@@ -885,7 +885,7 @@ proc cr_bd_design_1 { parentCell } {
# Create port connections
connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins processing_system7_0/UART0_RX]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_btns/s_axi_aclk] [get_bd_pins axi_gpio_leds/s_axi_aclk] [get_bd_pins axi_gpio_sws/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
connect_bd_net -net processing_system7_0_UART0_TX [get_bd_ports UART0_TX_0] [get_bd_pins processing_system7_0/UART0_TX]
connect_bd_net -net pwm_in_master_0_1 [get_bd_ports pwm_in_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
@@ -894,17 +894,17 @@ proc cr_bd_design_1 { parentCell } {
connect_bd_net -net pwm_in_master_3_1 [get_bd_ports pwm_in_3] [get_bd_pins pwm_recorder_3/pwm_in_master]
connect_bd_net -net pwm_in_master_4_1 [get_bd_ports pwm_in_4] [get_bd_pins pwm_recorder_4/pwm_in_master]
connect_bd_net -net pwm_in_master_5_1 [get_bd_ports pwm_in_5] [get_bd_pins pwm_recorder_5/pwm_in_master]
- connect_bd_net -net pwm_signal_out_0_pwm_out_sm [get_bd_ports pwm_out_3] [get_bd_pins pwm_signal_out_0/pwm_out_sm]
- connect_bd_net -net pwm_signal_out_1_pwm_out_sm [get_bd_ports pwm_out_2] [get_bd_pins pwm_signal_out_1/pwm_out_sm]
- connect_bd_net -net pwm_signal_out_2_pwm_out_sm [get_bd_ports pwm_out_1] [get_bd_pins pwm_signal_out_2/pwm_out_sm]
- connect_bd_net -net pwm_signal_out_3_pwm_out_sm [get_bd_ports pwm_out_0] [get_bd_pins pwm_signal_out_3/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_0_pwm_out_sm [get_bd_ports pwm_out_0] [get_bd_pins pwm_signal_out_0/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_1_pwm_out_sm [get_bd_ports pwm_out_1] [get_bd_pins pwm_signal_out_1/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_2_pwm_out_sm [get_bd_ports pwm_out_2] [get_bd_pins pwm_signal_out_2/pwm_out_sm]
+ connect_bd_net -net pwm_signal_out_3_pwm_out_sm [get_bd_ports pwm_out_3] [get_bd_pins pwm_signal_out_3/pwm_out_sm]
connect_bd_net -net rst_ps7_0_50M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_50M/interconnect_aresetn]
- connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/M05_ARESETN] [get_bd_pins ps7_0_axi_periph/M06_ARESETN] [get_bd_pins ps7_0_axi_periph/M07_ARESETN] [get_bd_pins ps7_0_axi_periph/M08_ARESETN] [get_bd_pins ps7_0_axi_periph/M09_ARESETN] [get_bd_pins ps7_0_axi_periph/M10_ARESETN] [get_bd_pins ps7_0_axi_periph/M11_ARESETN] [get_bd_pins ps7_0_axi_periph/M12_ARESETN] [get_bd_pins ps7_0_axi_periph/M13_ARESETN] [get_bd_pins ps7_0_axi_periph/M14_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pwm_recorder_0/s_axi_aresetn] [get_bd_pins pwm_recorder_1/s_axi_aresetn] [get_bd_pins pwm_recorder_2/s_axi_aresetn] [get_bd_pins pwm_recorder_3/s_axi_aresetn] [get_bd_pins pwm_recorder_4/s_axi_aresetn] [get_bd_pins pwm_recorder_5/s_axi_aresetn] [get_bd_pins pwm_signal_out_0/s_axi_aresetn] [get_bd_pins pwm_signal_out_1/s_axi_aresetn] [get_bd_pins pwm_signal_out_2/s_axi_aresetn] [get_bd_pins pwm_signal_out_3/s_axi_aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
+ connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_btns/s_axi_aresetn] [get_bd_pins axi_gpio_leds/s_axi_aresetn] [get_bd_pins axi_gpio_sws/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/M05_ARESETN] [get_bd_pins ps7_0_axi_periph/M06_ARESETN] [get_bd_pins ps7_0_axi_periph/M07_ARESETN] [get_bd_pins ps7_0_axi_periph/M08_ARESETN] [get_bd_pins ps7_0_axi_periph/M09_ARESETN] [get_bd_pins ps7_0_axi_periph/M10_ARESETN] [get_bd_pins ps7_0_axi_periph/M11_ARESETN] [get_bd_pins ps7_0_axi_periph/M12_ARESETN] [get_bd_pins ps7_0_axi_periph/M13_ARESETN] [get_bd_pins ps7_0_axi_periph/M14_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pwm_recorder_0/s_axi_aresetn] [get_bd_pins pwm_recorder_1/s_axi_aresetn] [get_bd_pins pwm_recorder_2/s_axi_aresetn] [get_bd_pins pwm_recorder_3/s_axi_aresetn] [get_bd_pins pwm_recorder_4/s_axi_aresetn] [get_bd_pins pwm_recorder_5/s_axi_aresetn] [get_bd_pins pwm_signal_out_0/s_axi_aresetn] [get_bd_pins pwm_signal_out_1/s_axi_aresetn] [get_bd_pins pwm_signal_out_2/s_axi_aresetn] [get_bd_pins pwm_signal_out_3/s_axi_aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
# Create address segments
- create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_2/S_AXI/Reg] SEG_axi_gpio_2_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_sws/S_AXI/Reg] SEG_axi_gpio_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_leds/S_AXI/Reg] SEG_axi_gpio_1_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_btns/S_AXI/Reg] SEG_axi_gpio_2_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x42800000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x76EA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_0/S_AXI/S_AXI_reg] SEG_pwm_recorder_0_S_AXI_reg
@@ -1159,9 +1159,8 @@ set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
# set the current impl run
current_run -implementation [get_runs impl_1]
-puts "INFO: Project created:${_xil_proj_name_}"
-
make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
+puts "INFO: Project created:${_xil_proj_name_}"
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
index 08b654cfb..ab414f5c9 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
@@ -54,26 +54,27 @@
#if QUAD_NUM==1
-#define IMU_ACCX_SIGN -1
-#define IMU_ACCY_SIGN -1
+#define IMU_ACCX_SIGN 1
+#define IMU_ACCY_SIGN 1
#define IMU_ACCZ_SIGN 1
-#define IMU_GYRX_SIGN -1
+#define IMU_GYRX_SIGN 1
#define IMU_GYRY_SIGN 1
#define IMU_GYRZ_SIGN 1
-#define MOTOR_FRONTLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
-#define MOTOR_FRONTRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
-#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR
-#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR
-#define ACCEL_X_BIAS 0.023f
-#define ACCEL_Y_BIAS -0.104f
-#define ACCEL_Z_BIAS 0.0686f
+#define MOTOR_FRONTLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR
+#define MOTOR_FRONTRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR
+#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
+#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
+
+#define ACCEL_X_BIAS -0.028f
+#define ACCEL_Y_BIAS 0.109f
+#define ACCEL_Z_BIAS 0.0686f
#define GYRO_X_BIAS -0.001f
-#define GYRO_Y_BIAS 0.014f
-#define GYRO_Z_BIAS -0.033//0.0541f
+#define GYRO_Y_BIAS -0.0135f
+#define GYRO_Z_BIAS 0.035//0.0541f
#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
index 2b5abff25..287e6fe87 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
@@ -151,8 +151,8 @@ int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
//Get the number of degrees
//javey: converted to radians to following SI units
gam->gyro_xVel_p = IMU_GYRX_SIGN * ((gyro_x / GYRO_SENS) * DEG_TO_RAD) + GYRO_X_BIAS;
- gam->gyro_yVel_q = IMU_GYRX_SIGN * ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
- gam->gyro_zVel_r = IMU_GYRX_SIGN * ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
+ gam->gyro_yVel_q = IMU_GYRY_SIGN * ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
+ gam->gyro_zVel_r = IMU_GYRZ_SIGN * ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
// Magnometer
mpu9150_read_mag(self, gam);
--
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