diff --git a/quad/vivado_workspace/project_tcl/zybo_blank.tcl b/quad/vivado_workspace/project_tcl/zybo_blank.tcl
index 546073b0b6bc67ec8db975687abcbd7e885e1950..3591ade7b7008691b05e0fe81b6a5b8a2cc90c69 100644
--- a/quad/vivado_workspace/project_tcl/zybo_blank.tcl
+++ b/quad/vivado_workspace/project_tcl/zybo_blank.tcl
@@ -3,7 +3,7 @@
#
# zybo_blank.tcl: Tcl script for re-creating project 'zybo_blank'
#
-# Generated by Vivado on Thu Sep 20 14:27:22 CDT 2018
+# Generated by Vivado on Thu Sep 20 15:24:38 CDT 2018
# IP Build 2289599 on Thu Jul 26 21:09:20 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -97,10 +97,10 @@ if { $::argc > 0 } {
}
# Set the directory path for the original project from where this script was exported
-set orig_proj_dir "[file normalize "$origin_dir/../zybo_blank"]"
+set orig_proj_dir "[file normalize "$origin_dir/${_xil_proj_name_}"]"
# Create project
-create_project ${_xil_proj_name_} "zybo_blank" -part xc7z020clg400-1
+create_project ${_xil_proj_name_} ${_xil_proj_name_} -part xc7z020clg400-1 -force
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
@@ -154,7 +154,7 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
# Set IP repository paths
set obj [get_filesets sources_1]
-set_property "ip_repo_paths" "[file normalize "$origin_dir/../../ip_repo"]" $obj
+set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip_repo"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
@@ -162,8 +162,10 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
# Import local files from the original project
+exec mkdir -p "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/"
+exec cp "project_tcl/zybo_blank_wrapper.vhd" "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd"
set files [list \
- [file normalize "${origin_dir}/../zybo_blank/zybo_blank.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]\
+ [file normalize "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]\
]
set imported_files [import_files -fileset sources_1 $files]
@@ -189,7 +191,9 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
-set file "[file normalize ${origin_dir}/../zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc]"
+exec mkdir -p "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/constrs_1/imports/vivado_workspace/"
+exec cp "Zybo-Z7-Master.xdc" "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc"
+set file "[file normalize ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc]"
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "vivado_workspace/Zybo-Z7-Master.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
@@ -235,7 +239,6 @@ proc cr_bd_design_1 { parentCell } {
set list_check_ips "\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:processing_system7:5.5\
- user.org:user:pwm_recorder:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
"
@@ -297,7 +300,6 @@ proc cr_bd_design_1 { parentCell } {
set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ]
# Create ports
- set jb0 [ create_bd_port -dir I jb0 ]
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
@@ -806,9 +808,6 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.NUM_MI {5} \
] $ps7_0_axi_periph
- # Create instance: pwm_recorder_0, and set properties
- set pwm_recorder_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_0 ]
-
# Create instance: rst_ps7_0_50M, and set properties
set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
@@ -824,27 +823,27 @@ proc cr_bd_design_1 { parentCell } {
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins ps7_0_axi_periph/M04_AXI] [get_bd_intf_pins pwm_recorder_0/S_AXI]
# Create port connections
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
- connect_bd_net -net pwm_in_master_0_1 [get_bd_ports jb0] [get_bd_pins pwm_recorder_0/pwm_in_master]
connect_bd_net -net rst_ps7_0_50M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_50M/interconnect_aresetn]
- connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pwm_recorder_0/s_axi_aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
+ connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
# Create address segments
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_2/S_AXI/Reg] SEG_axi_gpio_2_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg
- create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_0/S_AXI/S_AXI_reg] SEG_pwm_recorder_0_S_AXI_reg
# Restore current instance
current_bd_instance $oldCurInst
+ regenerate_bd_layout
save_bd_design
+common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
+
close_bd_design $design_name
}
# End of cr_bd_design_1()
diff --git a/quad/vivado_workspace/project_tcl/zybo_blank_wrapper.vhd b/quad/vivado_workspace/project_tcl/zybo_blank_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e61ab941ae5493e6802af091726eede39428b0b9
--- /dev/null
+++ b/quad/vivado_workspace/project_tcl/zybo_blank_wrapper.vhd
@@ -0,0 +1,256 @@
+--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2018.2.1 (lin64) Build 2288692 Thu Jul 26 18:23:50 MDT 2018
+--Date : Thu Sep 20 14:07:28 2018
+--Host : co3050-12.ece.iastate.edu running 64-bit Red Hat Enterprise Linux Workstation release 6.6 (Santiago)
+--Command : generate_target design_1_wrapper.bd
+--Design : design_1_wrapper
+--Purpose : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1_wrapper is
+ port (
+ DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_cas_n : inout STD_LOGIC;
+ DDR_ck_n : inout STD_LOGIC;
+ DDR_ck_p : inout STD_LOGIC;
+ DDR_cke : inout STD_LOGIC;
+ DDR_cs_n : inout STD_LOGIC;
+ DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_odt : inout STD_LOGIC;
+ DDR_ras_n : inout STD_LOGIC;
+ DDR_reset_n : inout STD_LOGIC;
+ DDR_we_n : inout STD_LOGIC;
+ FIXED_IO_ddr_vrn : inout STD_LOGIC;
+ FIXED_IO_ddr_vrp : inout STD_LOGIC;
+ FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ FIXED_IO_ps_clk : inout STD_LOGIC;
+ FIXED_IO_ps_porb : inout STD_LOGIC;
+ FIXED_IO_ps_srstb : inout STD_LOGIC;
+ btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ jb0 : in STD_LOGIC;
+ leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ rgb_led_tri_io : inout STD_LOGIC_VECTOR ( 5 downto 0 );
+ sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+end design_1_wrapper;
+
+architecture STRUCTURE of design_1_wrapper is
+ component design_1 is
+ port (
+ DDR_cas_n : inout STD_LOGIC;
+ DDR_cke : inout STD_LOGIC;
+ DDR_ck_n : inout STD_LOGIC;
+ DDR_ck_p : inout STD_LOGIC;
+ DDR_cs_n : inout STD_LOGIC;
+ DDR_reset_n : inout STD_LOGIC;
+ DDR_odt : inout STD_LOGIC;
+ DDR_ras_n : inout STD_LOGIC;
+ DDR_we_n : inout STD_LOGIC;
+ DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ FIXED_IO_ddr_vrn : inout STD_LOGIC;
+ FIXED_IO_ddr_vrp : inout STD_LOGIC;
+ FIXED_IO_ps_srstb : inout STD_LOGIC;
+ FIXED_IO_ps_clk : inout STD_LOGIC;
+ FIXED_IO_ps_porb : inout STD_LOGIC;
+ sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rgb_led_tri_i : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ rgb_led_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ rgb_led_tri_t : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ jb0 : in STD_LOGIC
+ );
+ end component design_1;
+ component IOBUF is
+ port (
+ I : in STD_LOGIC;
+ O : out STD_LOGIC;
+ T : in STD_LOGIC;
+ IO : inout STD_LOGIC
+ );
+ end component IOBUF;
+ signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal rgb_led_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal rgb_led_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal rgb_led_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+begin
+design_1_i: component design_1
+ port map (
+ DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
+ DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
+ DDR_cas_n => DDR_cas_n,
+ DDR_ck_n => DDR_ck_n,
+ DDR_ck_p => DDR_ck_p,
+ DDR_cke => DDR_cke,
+ DDR_cs_n => DDR_cs_n,
+ DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
+ DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
+ DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
+ DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
+ DDR_odt => DDR_odt,
+ DDR_ras_n => DDR_ras_n,
+ DDR_reset_n => DDR_reset_n,
+ DDR_we_n => DDR_we_n,
+ FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+ FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+ FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
+ FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+ FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+ FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+ btns_4bits_tri_i(3 downto 0) => btns_4bits_tri_i(3 downto 0),
+ jb0 => jb0,
+ leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),
+ leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),
+ leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),
+ leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),
+ leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),
+ leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),
+ leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),
+ leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),
+ leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),
+ leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),
+ leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),
+ leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0),
+ rgb_led_tri_i(5) => rgb_led_tri_i_5(5),
+ rgb_led_tri_i(4) => rgb_led_tri_i_4(4),
+ rgb_led_tri_i(3) => rgb_led_tri_i_3(3),
+ rgb_led_tri_i(2) => rgb_led_tri_i_2(2),
+ rgb_led_tri_i(1) => rgb_led_tri_i_1(1),
+ rgb_led_tri_i(0) => rgb_led_tri_i_0(0),
+ rgb_led_tri_o(5) => rgb_led_tri_o_5(5),
+ rgb_led_tri_o(4) => rgb_led_tri_o_4(4),
+ rgb_led_tri_o(3) => rgb_led_tri_o_3(3),
+ rgb_led_tri_o(2) => rgb_led_tri_o_2(2),
+ rgb_led_tri_o(1) => rgb_led_tri_o_1(1),
+ rgb_led_tri_o(0) => rgb_led_tri_o_0(0),
+ rgb_led_tri_t(5) => rgb_led_tri_t_5(5),
+ rgb_led_tri_t(4) => rgb_led_tri_t_4(4),
+ rgb_led_tri_t(3) => rgb_led_tri_t_3(3),
+ rgb_led_tri_t(2) => rgb_led_tri_t_2(2),
+ rgb_led_tri_t(1) => rgb_led_tri_t_1(1),
+ rgb_led_tri_t(0) => rgb_led_tri_t_0(0),
+ sws_4bits_tri_i(3 downto 0) => sws_4bits_tri_i(3 downto 0)
+ );
+leds_4bits_tri_iobuf_0: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_0(0),
+ IO => leds_4bits_tri_io(0),
+ O => leds_4bits_tri_i_0(0),
+ T => leds_4bits_tri_t_0(0)
+ );
+leds_4bits_tri_iobuf_1: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_1(1),
+ IO => leds_4bits_tri_io(1),
+ O => leds_4bits_tri_i_1(1),
+ T => leds_4bits_tri_t_1(1)
+ );
+leds_4bits_tri_iobuf_2: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_2(2),
+ IO => leds_4bits_tri_io(2),
+ O => leds_4bits_tri_i_2(2),
+ T => leds_4bits_tri_t_2(2)
+ );
+leds_4bits_tri_iobuf_3: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_3(3),
+ IO => leds_4bits_tri_io(3),
+ O => leds_4bits_tri_i_3(3),
+ T => leds_4bits_tri_t_3(3)
+ );
+rgb_led_tri_iobuf_0: component IOBUF
+ port map (
+ I => rgb_led_tri_o_0(0),
+ IO => rgb_led_tri_io(0),
+ O => rgb_led_tri_i_0(0),
+ T => rgb_led_tri_t_0(0)
+ );
+rgb_led_tri_iobuf_1: component IOBUF
+ port map (
+ I => rgb_led_tri_o_1(1),
+ IO => rgb_led_tri_io(1),
+ O => rgb_led_tri_i_1(1),
+ T => rgb_led_tri_t_1(1)
+ );
+rgb_led_tri_iobuf_2: component IOBUF
+ port map (
+ I => rgb_led_tri_o_2(2),
+ IO => rgb_led_tri_io(2),
+ O => rgb_led_tri_i_2(2),
+ T => rgb_led_tri_t_2(2)
+ );
+rgb_led_tri_iobuf_3: component IOBUF
+ port map (
+ I => rgb_led_tri_o_3(3),
+ IO => rgb_led_tri_io(3),
+ O => rgb_led_tri_i_3(3),
+ T => rgb_led_tri_t_3(3)
+ );
+rgb_led_tri_iobuf_4: component IOBUF
+ port map (
+ I => rgb_led_tri_o_4(4),
+ IO => rgb_led_tri_io(4),
+ O => rgb_led_tri_i_4(4),
+ T => rgb_led_tri_t_4(4)
+ );
+rgb_led_tri_iobuf_5: component IOBUF
+ port map (
+ I => rgb_led_tri_o_5(5),
+ IO => rgb_led_tri_io(5),
+ O => rgb_led_tri_i_5(5),
+ T => rgb_led_tri_t_5(5)
+ );
+end STRUCTURE;