From 34d09737a50b4c0d30e3852615863beca6bfb7e0 Mon Sep 17 00:00:00 2001
From: 488_MP-4 <488_MP-4@iastate.edu>
Date: Thu, 11 Apr 2024 18:21:07 +0200
Subject: [PATCH] setting uboot folder correctly
---
.../ARM_CA72_64_BIT/port.c | 517 ++++++++++++++++++
.../ARM_CA72_64_BIT/portASM.S | 432 +++++++++++++++
.../ARM_CA72_64_BIT/portmacro.h | 211 +++++++
.../FreeRTOS_asm_vector.o | Bin 0 -> 9240 bytes
.../CORTEX_A72_64-bit_Raspberrypi4/Makefile | 87 ++-
.../bin/dep/list.o.d | 4 +-
.../bin/dep/tasks.o.d | 4 +-
.../CORTEX_A72_64-bit_Raspberrypi4/bin/list.o | Bin 585524 -> 587600 bytes
.../src/config/FreeRTOSConfig.h | 59 +-
.../CORTEX_A72_64-bit_Raspberrypi4/startup.o | Bin 0 -> 1592 bytes
10 files changed, 1294 insertions(+), 20 deletions(-)
create mode 100644 uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/port.c
create mode 100644 uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portASM.S
create mode 100644 uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portmacro.h
create mode 100644 uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/FreeRTOS_asm_vector.o
create mode 100644 uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/startup.o
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/port.c b/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/port.c
new file mode 100644
index 000000000..d2b964f01
--- /dev/null
+++ b/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/port.c
@@ -0,0 +1,517 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+ #define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portSP_ELx ( ( StackType_t ) 0x01 )
+#define portSP_EL0 ( ( StackType_t ) 0x00 )
+
+#if defined( GUEST )
+ #define portEL1 ( ( StackType_t ) 0x04 )
+ #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
+#else
+ #define portEL3 ( ( StackType_t ) 0x0c )
+ /* At the time of writing, the BSP only supports EL3. */
+ #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
+#endif
+
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK ( 0x0C )
+
+/* The I bit in the DAIF bits. */
+#define portDAIF_I ( 0x80 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ portDISABLE_INTERRUPTS(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB SY \n" \
+ "ISB SY \n" ); \
+ portENABLE_INTERRUPTS(); \
+}
+
+/* Hardware specifics used when sanity checking the configuration. */
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing. This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint64_t ullCriticalNesting = 9999ULL;
+
+/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
+then floating point context must be saved and restored for the task. */
+uint64_t ullPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint64_t ullPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+if the nesting depth is 0. */
+uint64_t ullPortInterruptNesting = 0;
+
+/* Used in the ASM code. */
+__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
+ pxTopOfStack--;
+
+ *pxTopOfStack = portINITIAL_PSTATE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
+ pxTopOfStack--;
+
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
+
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine how many priority bits are implemented in the GIC.
+
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to
+ all possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Shift to the least significant bits. */
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+ {
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+ }
+
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+ value. */
+
+ configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
+
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* conifgASSERT_DEFINED */
+
+
+ /* At the time of writing, the BSP only supports EL3. */
+ __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+
+#if defined( GUEST )
+ #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
+ configASSERT( ulAPSR == portEL1 );
+ if( ulAPSR == portEL1 )
+#else
+ configASSERT( ulAPSR == portEL3 );
+ if( ulAPSR == portEL3 )
+#endif
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Interrupts are turned off in the CPU itself to ensure a tick does
+ not execute while the scheduler is being started. Interrupts are
+ automatically turned back on in the CPU when the first task starts
+ executing. */
+ portDISABLE_INTERRUPTS();
+
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
+
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+ }
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ullCriticalNesting == 1000ULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ uxPortSetInterruptMask();
+
+ /* Now interrupts are disabled ullCriticalNesting can be accessed
+ directly. Increment ullCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ullCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ullCriticalNesting == 1ULL )
+ {
+ configASSERT( ullPortInterruptNesting == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ullCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ullCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ullCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+ /* Must be the lowest possible priority. */
+ #if !defined( QEMU )
+ {
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ }
+ #endif
+
+ /* Interrupts should not be enabled before this point. */
+ #if( configASSERT_DEFINED == 1 )
+ {
+ uint32_t ulMaskBits;
+
+ __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
+ configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. It is
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ updated. */
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb sy \n"
+ "isb sy \n" ::: "memory" );
+
+ /* Ok to enable interrupts after the interrupt source has been cleared. */
+ configCLEAR_TICK_INTERRUPT();
+ portENABLE_INTERRUPTS();
+
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ullPortYieldRequired = pdTRUE;
+ }
+
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ullPortTaskHasFPUContext = pdTRUE;
+
+ /* Consider initialising the FPSR here - but probably not necessary in
+ AArch64. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
+{
+ if( uxNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ updated. */
+ portDISABLE_INTERRUPTS();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb sy \n"
+ "isb sy \n" ::: "memory" );
+ }
+ portENABLE_INTERRUPTS();
+
+ return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible. */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portASM.S b/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portASM.S
new file mode 100644
index 000000000..f6aa78c95
--- /dev/null
+++ b/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portASM.S
@@ -0,0 +1,432 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ .text
+
+ /* Variables and functions. */
+ .extern ullMaxAPIPriorityMask
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vApplicationIRQHandler
+ .extern ullPortInterruptNesting
+ .extern ullPortTaskHasFPUContext
+ .extern ullCriticalNesting
+ .extern ullPortYieldRequired
+ .extern ullICCEOIR
+ .extern ullICCIAR
+ .extern _freertos_vector_table
+
+ .global FreeRTOS_IRQ_Handler
+ .global FreeRTOS_SWI_Handler
+ .global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+ /* Switch to use the EL0 stack pointer. */
+ MSR SPSEL, #0
+
+ /* Save the entire context. */
+ STP X0, X1, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
+ STP X4, X5, [SP, #-0x10]!
+ STP X6, X7, [SP, #-0x10]!
+ STP X8, X9, [SP, #-0x10]!
+ STP X10, X11, [SP, #-0x10]!
+ STP X12, X13, [SP, #-0x10]!
+ STP X14, X15, [SP, #-0x10]!
+ STP X16, X17, [SP, #-0x10]!
+ STP X18, X19, [SP, #-0x10]!
+ STP X20, X21, [SP, #-0x10]!
+ STP X22, X23, [SP, #-0x10]!
+ STP X24, X25, [SP, #-0x10]!
+ STP X26, X27, [SP, #-0x10]!
+ STP X28, X29, [SP, #-0x10]!
+ STP X30, XZR, [SP, #-0x10]!
+
+ /* Save the SPSR. */
+#if defined( GUEST )
+ MRS X3, SPSR_EL1
+ MRS X2, ELR_EL1
+#else
+# MRS X3, SPSR_EL3
+ /* Save the ELR. */
+# MRS X2, ELR_EL3
+#endif
+
+ STP X2, X3, [SP, #-0x10]!
+
+ /* Save the critical section nesting depth. */
+ LDR X0, ullCriticalNestingConst
+ LDR X3, [X0]
+
+ /* Save the FPU context indicator. */
+ LDR X0, ullPortTaskHasFPUContextConst
+ LDR X2, [X0]
+
+ /* Save the FPU context, if any (32 128-bit registers). */
+ CMP X2, #0
+ B.EQ 1f
+ STP Q0, Q1, [SP,#-0x20]!
+ STP Q2, Q3, [SP,#-0x20]!
+ STP Q4, Q5, [SP,#-0x20]!
+ STP Q6, Q7, [SP,#-0x20]!
+ STP Q8, Q9, [SP,#-0x20]!
+ STP Q10, Q11, [SP,#-0x20]!
+ STP Q12, Q13, [SP,#-0x20]!
+ STP Q14, Q15, [SP,#-0x20]!
+ STP Q16, Q17, [SP,#-0x20]!
+ STP Q18, Q19, [SP,#-0x20]!
+ STP Q20, Q21, [SP,#-0x20]!
+ STP Q22, Q23, [SP,#-0x20]!
+ STP Q24, Q25, [SP,#-0x20]!
+ STP Q26, Q27, [SP,#-0x20]!
+ STP Q28, Q29, [SP,#-0x20]!
+ STP Q30, Q31, [SP,#-0x20]!
+
+1:
+ /* Store the critical nesting count and FPU context indicator. */
+ STP X2, X3, [SP, #-0x10]!
+
+ LDR X0, pxCurrentTCBConst
+ LDR X1, [X0]
+ MOV X0, SP /* Move SP into X0 for saving. */
+ STR X0, [X1]
+
+ /* Switch to use the ELx stack pointer. */
+ MSR SPSEL, #1
+
+ .endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+ /* Switch to use the EL0 stack pointer. */
+ MSR SPSEL, #0
+
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR X0, pxCurrentTCBConst
+ LDR X1, [X0]
+ LDR X0, [X1]
+ MOV SP, X0
+
+ LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
+
+ /* Set the PMR register to be correct for the current critical nesting
+ depth. */
+ LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
+ MOV X1, #255 /* X1 holds the unmask value. */
+ LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
+ CMP X3, #0
+ LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
+ B.EQ 1f
+ LDR X6, ullMaxAPIPriorityMaskConst
+ LDR X1, [X6] /* X1 holds the mask value. */
+1:
+ STR W1, [X5] /* Write the mask value to ICCPMR. */
+ DSB SY /* _RB_Barriers probably not required here. */
+ ISB SY
+ STR X3, [X0] /* Restore the task's critical nesting count. */
+
+ /* Restore the FPU context indicator. */
+ LDR X0, ullPortTaskHasFPUContextConst
+ STR X2, [X0]
+
+ /* Restore the FPU context, if any. */
+ CMP X2, #0
+ B.EQ 1f
+ LDP Q30, Q31, [SP], #0x20
+ LDP Q28, Q29, [SP], #0x20
+ LDP Q26, Q27, [SP], #0x20
+ LDP Q24, Q25, [SP], #0x20
+ LDP Q22, Q23, [SP], #0x20
+ LDP Q20, Q21, [SP], #0x20
+ LDP Q18, Q19, [SP], #0x20
+ LDP Q16, Q17, [SP], #0x20
+ LDP Q14, Q15, [SP], #0x20
+ LDP Q12, Q13, [SP], #0x20
+ LDP Q10, Q11, [SP], #0x20
+ LDP Q8, Q9, [SP], #0x20
+ LDP Q6, Q7, [SP], #0x20
+ LDP Q4, Q5, [SP], #0x20
+ LDP Q2, Q3, [SP], #0x20
+ LDP Q0, Q1, [SP], #0x20
+1:
+ LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
+
+#if defined( GUEST )
+ /* Restore the SPSR. */
+ MSR SPSR_EL1, X3
+ /* Restore the ELR. */
+ MSR ELR_EL1, X2
+#else
+ /* Restore the SPSR. */
+# MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
+ /* Restore the ELR. */
+# MSR ELR_EL3, X2
+#endif
+
+ LDP X30, XZR, [SP], #0x10
+ LDP X28, X29, [SP], #0x10
+ LDP X26, X27, [SP], #0x10
+ LDP X24, X25, [SP], #0x10
+ LDP X22, X23, [SP], #0x10
+ LDP X20, X21, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
+
+ /* Switch to use the ELx stack pointer. _RB_ Might not be required. */
+ MSR SPSEL, #1
+
+ ERET
+
+ .endm
+
+
+/******************************************************************************
+ * FreeRTOS_SWI_Handler handler is used to perform a context switch.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+#if defined( GUEST )
+ MRS X0, ESR_EL1
+#else
+# MRS X0, ESR_EL3
+#endif
+
+ LSR X1, X0, #26
+
+#if defined( GUEST )
+ CMP X1, #0x15 /* 0x15 = SVC instruction. */
+#else
+# CMP X1, #0x17 /* 0x17 = SMC instruction. */
+#endif
+ B.NE FreeRTOS_Abort
+ BL vTaskSwitchContext
+
+ portRESTORE_CONTEXT
+
+FreeRTOS_Abort:
+ /* Full ESR is in X0, exception class code is in X1. */
+ B .
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 8
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+.set freertos_vector_base, _freertos_vector_table
+
+ /* Install the FreeRTOS interrupt handlers. */
+ LDR X1, =freertos_vector_base
+#if defined( GUEST )
+ MSR VBAR_EL1, X1
+#else
+# MSR VBAR_EL3, X1
+#endif
+ DSB SY
+ ISB SY
+
+ /* Start the first task. */
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * FreeRTOS_IRQ_Handler handles IRQ entry and exit.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+ /* Save volatile registers. */
+ STP X0, X1, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
+ STP X4, X5, [SP, #-0x10]!
+ STP X6, X7, [SP, #-0x10]!
+ STP X8, X9, [SP, #-0x10]!
+ STP X10, X11, [SP, #-0x10]!
+ STP X12, X13, [SP, #-0x10]!
+ STP X14, X15, [SP, #-0x10]!
+ STP X16, X17, [SP, #-0x10]!
+ STP X18, X19, [SP, #-0x10]!
+ STP X29, X30, [SP, #-0x10]!
+
+ /* Save the SPSR and ELR. */
+#if defined( GUEST )
+ MRS X3, SPSR_EL1
+ MRS X2, ELR_EL1
+#else
+# MRS X3, SPSR_EL3
+# MRS X2, ELR_EL3
+#endif
+ STP X2, X3, [SP, #-0x10]!
+
+ /* Increment the interrupt nesting counter. */
+ LDR X5, ullPortInterruptNestingConst
+ LDR X1, [X5] /* Old nesting count in X1. */
+ ADD X6, X1, #1
+ STR X6, [X5] /* Address of nesting count variable in X5. */
+
+ /* Maintain the interrupt nesting information across the function call. */
+ STP X1, X5, [SP, #-0x10]!
+
+ /* Read value from the interrupt acknowledge register, which is stored in W0
+ for future parameter and interrupt clearing use. */
+ LDR X2, ullICCIARConst
+ LDR X3, [X2]
+ LDR W0, [X3] /* ICCIAR in W0 as parameter. */
+
+ /* Maintain the ICCIAR value across the function call. */
+ STP X0, X1, [SP, #-0x10]!
+
+ /* Call the C handler. */
+ BL vApplicationIRQHandler
+
+ /* Disable interrupts. */
+ MSR DAIFSET, #2
+ DSB SY
+ ISB SY
+
+ /* Restore the ICCIAR value. */
+ LDP X0, X1, [SP], #0x10
+
+ /* End IRQ processing by writing ICCIAR to the EOI register. */
+ LDR X4, ullICCEOIRConst
+ LDR X4, [X4]
+ STR W0, [X4]
+
+ /* Restore the critical nesting count. */
+ LDP X1, X5, [SP], #0x10
+ STR X1, [X5]
+
+ /* Has interrupt nesting unwound? */
+ CMP X1, #0
+ B.NE Exit_IRQ_No_Context_Switch
+
+ /* Is a context switch required? */
+ LDR X0, ullPortYieldRequiredConst
+ LDR X1, [X0]
+ CMP X1, #0
+ B.EQ Exit_IRQ_No_Context_Switch
+
+ /* Reset ullPortYieldRequired to 0. */
+ MOV X2, #0
+ STR X2, [X0]
+
+ /* Restore volatile registers. */
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
+#if defined( GUEST )
+ MSR SPSR_EL1, X5
+ MSR ELR_EL1, X4
+#else
+# MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+# MSR ELR_EL3, X4
+#endif
+ DSB SY
+ ISB SY
+
+ LDP X29, X30, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
+
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ BL vTaskSwitchContext
+ portRESTORE_CONTEXT
+
+Exit_IRQ_No_Context_Switch:
+ /* Restore volatile registers. */
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
+#if defined( GUEST )
+ MSR SPSR_EL1, X5
+ MSR ELR_EL1, X4
+#else
+# MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+# MSR ELR_EL3, X4
+#endif
+ DSB SY
+ ISB SY
+
+ LDP X29, X30, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
+
+ ERET
+
+
+
+
+.align 8
+pxCurrentTCBConst: .dword pxCurrentTCB
+ullCriticalNestingConst: .dword ullCriticalNesting
+ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
+ullICCPMRConst: .dword ullICCPMR
+ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+
+.align 8
+ullPortInterruptNestingConst: .dword ullPortInterruptNesting
+ullPortYieldRequiredConst: .dword ullPortYieldRequired
+ullICCIARConst: .dword ullICCIAR
+ullICCEOIRConst: .dword ullICCEOIR
+
+
+
+.end
+
+
+
+
+
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portmacro.h b/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portmacro.h
new file mode 100644
index 000000000..c16449976
--- /dev/null
+++ b/uboot-compiler/bm_crazyflie_bitcraze/ARM_CA72_64_BIT/portmacro.h
@@ -0,0 +1,211 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE size_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef uint64_t UBaseType_t;
+
+typedef uint64_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 16
+#define portPOINTER_SIZE_TYPE uint64_t
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern uint64_t ullPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ullPortYieldRequired = pdTRUE; \
+ } \
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if defined( GUEST )
+ #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+#else
+ #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+#endif
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern UBaseType_t uxPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+#define portDISABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
+
+#define portENABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
+
+
+/* These macros do not globally disable/enable interrupts. They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+ } /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
+
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/FreeRTOS_asm_vector.o b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/FreeRTOS_asm_vector.o
new file mode 100644
index 0000000000000000000000000000000000000000..efba03d7f333ba6a058665d45dd597c85481ccde
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diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/Makefile b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/Makefile
index 2b8a2293a..af98a983e 100644
--- a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/Makefile
+++ b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/Makefile
@@ -55,7 +55,7 @@ UART2_LINK ?= 0
############### CPU-specific build configuration ################
ifeq ($(CPU), stm32f4)
-PORT = $(FREERTOS)/portable/GCC/ARM_CM4F
+PORT = $(FREERTOS)/portable/GCC/ARM_CA72_64_BIT
LINKER_DIR = $(CRAZYFLIE_BASE)/tools/make/F405/linker
ST_OBJ_DIR = $(CRAZYFLIE_BASE)/tools/make/F405
@@ -78,8 +78,8 @@ ST_OBJ += usb_core.o usb_dcd_int.o usb_dcd.o
# USB Device obj
ST_OBJ += usbd_ioreq.o usbd_req.o usbd_core.o
-PROCESSOR = -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
-CFLAGS += -fno-math-errno -DARM_MATH_CM4 -D__FPU_PRESENT=1 -mfp16-format=ieee
+PROCESSOR = -mcpu=cortex-a72 #-mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
+CFLAGS += -fno-math-errno -DARM_MATH_CM4 -D__FPU_PRESENT=1 #-mfp16-format=ieee
#Flags required by the ST library
CFLAGS += -DSTM32F4XX -DSTM32F40_41xxx -DHSE_VALUE=8000000 -DUSE_STDPERIPH_DRIVER
@@ -269,6 +269,37 @@ PROJ_OBJ += sleepus.o statsCnt.o rateSupervisor.o
PROJ_OBJ += lighthouse_core.o pulse_processor.o pulse_processor_v1.o pulse_processor_v2.o lighthouse_geometry.o ootx_decoder.o lighthouse_calibration.o lighthouse_deck_flasher.o lighthouse_position_est.o lighthouse_storage.o
PROJ_OBJ += kve_storage.o kve.o
+
+# From ./src
+PROJ_OBJ = startup.o
+PROJ_OBJ +=FreeRTOS_asm_vector.o
+PROJ_OBJ +=FreeRTOS_tick_config.o
+PROJ_OBJ +=interrupt.o
+PROJ_OBJ +=main.o
+PROJ_OBJ +=mmu_cfg.o
+PROJ_OBJ +=uart.o
+
+# From ../mmu
+PROJ_OBJ +=mmu.o
+
+# From ../cache
+PROJ_OBJ +=cache.o
+
+# From ../musl_libc
+PROJ_OBJ +=memset.o
+PROJ_OBJ +=memcpy.o
+
+# From ../../../Source/portable/GCC/ARM_CA72_64_BIT
+#PROJ_OBJ +=port.o
+#PROJ_OBJ +=portASM.o
+
+#PROJ_OBJ +=list.o
+#PROJ_OBJ +=queue.o
+#PROJ_OBJ +=tasks.o
+#PROJ_OBJ +=timers.o
+
+#PROJ_OBJ +=heap_1.o
+
ifeq ($(DEBUG_PRINT_ON_SEGGER_RTT), 1)
VPATH += $(LIB)/Segger_RTT/RTT
INCLUDES += -I$(LIB)/Segger_RTT/RTT
@@ -308,6 +339,11 @@ INCLUDES += -I$(LIB)/STM32_USB_Device_Library/Core/inc
INCLUDES += -I$(LIB)/STM32_USB_OTG_Driver/inc
INCLUDES += -I$(LIB)/STM32F4xx_StdPeriph_Driver/inc
INCLUDES += -I$(LIB)/vl53l1 -I$(LIB)/vl53l1/core/inc
+INCLUDES += -I$./src/uart/src
+INCLUDES += -I$./src/musl_libc
+INCLUDES += -I$./src/mmu
+#INCLUDES += -I$../../Source/include
+#INCLUDES += -I$../../Source/portable/GCC/ARM_CA72_64_BIT
CFLAGS += -g3
ifeq ($(DEBUG), 1)
@@ -343,6 +379,15 @@ CFLAGS += -ffunction-sections -fdata-sections
# Prevent promoting floats to doubles
CFLAGS += -Wdouble-promotion
+CFLAGS += -fpic \
+ -ffreestanding \
+ -std=gnu99 \
+ -O2 \
+ -Wall \
+ -Wextra \
+ -DGUEST \
+ -D__LINUX__
+
ASFLAGS = $(PROCESSOR) $(INCLUDES)
LDFLAGS += --specs=nosys.specs --specs=nano.specs $(PROCESSOR) -Wl,-Map=$(PROG).map,--cref,--gc-sections,--undefined=uxTopUsedPriority
@@ -394,8 +439,10 @@ ifeq ($(wildcard $(CRAZYFLIE_BASE)/vendor/*/*),)
endif
#################### Targets ###############################
+BUILTIN_OPS = -fno-builtin-memset
+ASMFLAGS = -mcpu=cortex-a72
-all: bin/ bin/dep bin/vendor check_submodules build
+all: bin/ bin/dep bin/vendor check_submodules build linker
build:
# Each target is in a different line, so they are executed one after the other even when the processor has multiple cores (when the -j option for the make command is > 1). See: https://www.gnu.org/software/make/manual/html_node/Parallel.html
@$(MAKE) --no-print-directory clean_version CRAZYFLIE_BASE=$(CRAZYFLIE_BASE)
@@ -404,6 +451,38 @@ build:
@$(MAKE) --no-print-directory size CRAZYFLIE_BASE=$(CRAZYFLIE_BASE)
compile: $(PROG).hex $(PROG).bin $(PROG).dfu
+linker : src/raspberrypi4.ld $(PROJ_OBJ)
+ $(CROSS)gcc -Wl,--build-id=none -std=gnu99 -T src/raspberrypi4.ld -o $@ -ffreestanding -nostdlib --specs=nosys.specs $(BUILTIN_OPS) $(PROJ_OBJ)
+ $(CROSS)objdump -d cf2.elf > cf2.list
+
+
+%.o : src/uart/src/%.S
+ $(CROSS)as $(ASMFLAGS) -c -o $@ $<
+
+%.o : src/uart/src/%.c
+ $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
+%.o : src/mmu/%.c
+ $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
+%.o : src/cache/%.S
+ $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
+%.o : src/musl_libc/%.c
+ $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
+#%.o : ../../Source/%.c
+# $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
+#%.o : ../../Source/portable/GCC/ARM_CA72_64_BIT/%.c
+# $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
+#%.o : ../../Source/portable/GCC/ARM_CA72_64_BIT/%.S
+# $(CROSS)as $(ASMFLAGS) -c -o $@ $<
+
+#%.o : ../../Source/portable/MemMang/%.c
+# $(CROSS)gcc $(CFLAGS) -c -o $@ $<
+
bin/:
mkdir -p bin
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/list.o.d b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/list.o.d
index 1e6318307..23833862a 100644
--- a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/list.o.d
+++ b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/list.o.d
@@ -53,7 +53,7 @@ list.o: vendor/FreeRTOS/list.c /usr/include/newlib/stdlib.h \
/usr/lib/gcc/arm-none-eabi/9.2.1/include/stdarg.h \
vendor/FreeRTOS/include/projdefs.h vendor/FreeRTOS/include/portable.h \
vendor/FreeRTOS/include/deprecated_definitions.h \
- vendor/FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h \
+ vendor/FreeRTOS/portable/GCC/ARM_CA72_64_BIT/portmacro.h \
vendor/FreeRTOS/include/mpu_wrappers.h vendor/FreeRTOS/include/list.h
/usr/include/newlib/stdlib.h:
@@ -192,7 +192,7 @@ vendor/FreeRTOS/include/portable.h:
vendor/FreeRTOS/include/deprecated_definitions.h:
-vendor/FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h:
+vendor/FreeRTOS/portable/GCC/ARM_CA72_64_BIT/portmacro.h:
vendor/FreeRTOS/include/mpu_wrappers.h:
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/tasks.o.d b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/tasks.o.d
index 99bf82091..586a0444c 100644
--- a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/tasks.o.d
+++ b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/dep/tasks.o.d
@@ -55,7 +55,7 @@ tasks.o: vendor/FreeRTOS/tasks.c /usr/include/newlib/stdlib.h \
/usr/lib/gcc/arm-none-eabi/9.2.1/include/stdarg.h \
vendor/FreeRTOS/include/projdefs.h vendor/FreeRTOS/include/portable.h \
vendor/FreeRTOS/include/deprecated_definitions.h \
- vendor/FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h \
+ vendor/FreeRTOS/portable/GCC/ARM_CA72_64_BIT/portmacro.h \
vendor/FreeRTOS/include/mpu_wrappers.h vendor/FreeRTOS/include/task.h \
vendor/FreeRTOS/include/list.h vendor/FreeRTOS/include/timers.h \
vendor/FreeRTOS/include/task.h vendor/FreeRTOS/include/stack_macros.h
@@ -204,7 +204,7 @@ vendor/FreeRTOS/include/portable.h:
vendor/FreeRTOS/include/deprecated_definitions.h:
-vendor/FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h:
+vendor/FreeRTOS/portable/GCC/ARM_CA72_64_BIT/portmacro.h:
vendor/FreeRTOS/include/mpu_wrappers.h:
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/list.o b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/bin/list.o
index ada96f33fd1c3ffe235469aa4a921cf141a5dfc3..e4956caae04af2468a7f27f7c60ee80846070a14 100644
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diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/src/config/FreeRTOSConfig.h b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/src/config/FreeRTOSConfig.h
index ad9af7c29..af4e8d8f9 100644
--- a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/src/config/FreeRTOSConfig.h
+++ b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/src/config/FreeRTOSConfig.h
@@ -70,17 +70,17 @@
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
-#define configUSE_PREEMPTION 1
-#define configUSE_IDLE_HOOK 1
-#define configUSE_TICK_HOOK 0
+// #define configUSE_PREEMPTION 1
+// #define configUSE_IDLE_HOOK 1
+// #define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) FREERTOS_MCU_CLOCK_HZ )
#define configTICK_RATE_HZ_RAW 1000
-#define configTICK_RATE_HZ ( ( portTickType ) configTICK_RATE_HZ_RAW )
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) FREERTOS_MIN_STACK_SIZE )
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( FREERTOS_HEAP_SIZE ) )
+//#define configTICK_RATE_HZ ( ( portTickType ) configTICK_RATE_HZ_RAW )
+//#define configMINIMAL_STACK_SIZE ( ( unsigned short ) FREERTOS_MIN_STACK_SIZE )
+//#define configTOTAL_HEAP_SIZE ( ( size_t ) ( FREERTOS_HEAP_SIZE ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_16_BIT_TICKS 0
-#define configIDLE_SHOULD_YIELD 0
+//#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 0
#ifdef DEBUG
#define configCHECK_FOR_STACK_OVERFLOW 1
@@ -88,12 +88,12 @@
#define configCHECK_FOR_STACK_OVERFLOW 0
#endif
#define configUSE_TIMERS 1
-#define configTIMER_TASK_PRIORITY 1
-#define configTIMER_QUEUE_LENGTH 20
+//#define configTIMER_TASK_PRIORITY 1
+//#define configTIMER_QUEUE_LENGTH 20
#define configUSE_MALLOC_FAILED_HOOK 1
-#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 4)
+//#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 4)
-#define configMAX_PRIORITIES ( 6 )
+//#define configMAX_PRIORITIES ( 6 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
@@ -118,7 +118,8 @@ to exclude the API function. */
//Map the port handler to the crt0 interruptions handlers
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler tickFreeRTOS
-#define vPortSVCHandler SVC_Handler
+#define vPortSVCHandler SVCne configUSE_PREEMPTION 1
+//#define configUSE_IDLE_HOOK 1_Handler
//Milliseconds to OS Ticks
#if configTICK_RATE_HZ_RAW != 1000
@@ -170,4 +171,38 @@ to exclude the API function. */
void qm_traceQUEUE_SEND_FAILED(void* xQueue);
#endif // DEBUG_QUEUE_MONITOR
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES ( 8 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 )
+#define configTOTAL_HEAP_SIZE ( 124 * 1024 )
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+
+#define configUSE_MUTEXES 1
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskDelay 1
+
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+
+void vConfigureTickInterrupt( void );
+#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
+void vClearTickInterrupt( void );
+#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt()
+
+#define configINTERRUPT_CONTROLLER_BASE_ADDRESS (0xFF841000U)
+#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET (0x1000U)
+#define configUNIQUE_INTERRUPT_PRIORITIES (16)
+#define configMAX_API_CALL_INTERRUPT_PRIORITY (14)
+
#endif /* FREERTOS_CONFIG_H */
diff --git a/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/startup.o b/uboot-compiler/bm_crazyflie_bitcraze/FreeRTOS/Demo/CORTEX_A72_64-bit_Raspberrypi4/startup.o
new file mode 100644
index 0000000000000000000000000000000000000000..3ff0c1abe7f60c886c96d1d23b5a18cb0f8378aa
GIT binary patch
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--
GitLab